Symposia on VLSI Technology and Circuits

A 0.4-1.6GHz Spur-Free Bang-Bang Digital PLL in 65nm with a D-Flip-Flop Based Frequency Subtractor Circuit

Bongjin Kim1, 2, Somnath Kundu1, and Chris H. Kim1

1University of Minnesota, Minneapolis, MN2Rambus Inc., Sunnyvale, CA

bkim@rambus.com

Outline• Motivation• Limit Cycle Issue in Bang-Bang Digital PLL• Proposed 65nm Bang-Bang Digital PLL

- Noise-Shaping DFF-based Frequency Subtractor- Spur-Free Bang-Bang Digital PLL Implementation

• Measurement Results• Summary

Slide 1

Bang-Bang Digital PLL vs. Other PLLs

Slide 2

• Digital PLL w/ 1b binary (bang-bang) phase detector• Pros: scalable, compact, supply insensitive, good PN• Cons: large spur-noise due to nonlinear BBPD

ɸREF

VCO

DLF DCO

Analog PLL

Digital PLL w/ TDC(i.e. TDC = multi-bit PD)

Digital PLL w/ BBPD(i.e. BBPD = 1-bit PD)

TDC

DLF DCO*BBPD

LFPD/CP

ɸFB

ɸREF

ɸFB

ɸREF

ɸFBPhase Difference

(∆ɸ=ɸREF-ɸFB)

PD O

utpu

t

∆ɸ=0

BBPD

TDCPD/CP0

*BBPD (Bang-Bang Phase Detector)

Limit Cycle Behavior in BBPLL

Slide 3

• Limit cycles in BBPLL loop due to a nonlinear BBPD- Leads to large spur noise in PLL output clock

• Large loop-gain & longer delay exacerbates problem

From M. Perrott tutorial slides

Delay DCOBBPD

ɸref(t)

ɸclk(t)

e(t) v(t)

Linearizing BBPD Gain by Introducing Jitter Noise

Slide 4

• Adding random jitter to input clock effectively linearizes BBPD gain thereby minimizing spur noise

∆ɸ ∆ɸ

BBPD output

BBPD output

CKREF

CKFB

CKFB jitter histogram

Probability of "down"

Probability of "up"

Ideal CKFB Noisy CKFB

J. Lee et. al., JSSC 2004

Slide 5

• Dithered reference from a variable delay line and a ∆Σ modulator provides a finite and linear BBPD gain

Existing Technique: Reference DitheringA. Rylyakov et. al., ISSCC 2009

Slide 6

• PLL feedback clock frequency down-conversion- Conventional: Asynchronous frequency divider- Proposed: Noise-shaping frequency subtractor(under-samples feedback clock with reference clock)

Proposed Technique: Freq. Subtractor

CKFB

CKREF

CKDIFF

➔ fDIFF : quantized & noise-shaped

(DFF quant. errors are used in next samples)

1fREF/4

1fREF/3

1fREF/4

1fREF/4

[e.g.] fREF/4 < fREF-fFB < fREF/3

1fDIFF

D QCKFB

CKREF

CKDIFF

Conventional BBPLL Circuit

Slide 7

• Conventional BBPLL with traditional freq. divider

BBPFD DLF

Locked condition: fFB=fREF·M/P

fREF /PDCO

/MfFB/M

fREF/P

fFB

Proposed BBPLL Circuit

Slide 8

• Proposed BBPLL with DFF-based freq. subtractor

BBPFD DLF

Locked condition: fFB=fREF·(P-1)/P

fREF /PDCO

fREF/P

DFFfDIFF=fREF-fFBfFB

D-Flip-Flop: Conv. Digital Sampler

Slide 9

• When fREF ≥ 2fFB (i.e. Nyquist sampling theorem)

CKREF

CKFB

D QCKFB

CKREF

CKOUT

Conventional Digital SamplerfREF ≥ 2fFB

D-Flip-Flop: Conv. Digital Sampler

Slide 10

• When fREF ≥ 2fFB (i.e. Nyquist sampling theorem)

CKREF

CKFB

CKOUT

1/fFB

D QCKFB

CKREF

CKOUT

Conventional Digital SamplerfREF ≥ 2fFB

D-Flip-Flop: Proposed Freq. Subtractor

Slide 11

• DFF works as a freq. subtractor when fFB ≤ fREF ≤ 2fFB

CKREF

CKFB

CKOUT

1/fFB

D QCKFB

CKREF

CKOUT

This Work: Freq. SubtractorConventional Digital SamplerfREF ≥ 2fFB fREF < 2fFB

D-Flip-Flop: Proposed Freq. Subtractor

Slide 12

• DFF works as a freq. subtractor when fFB ≤ fREF ≤ 2fFB

CKREF

CKFB

CKOUT

1/(fREF-fFB)1/fFB

D QCKFB

CKREF

CKOUT

This Work: Freq. SubtractorConventional Digital SamplerfREF ≥ 2fFB fREF < 2fFB

Noise-Shaping Behavior of DFF-Based Frequency Subtractor Circuit

Slide 13

• While quantizing CKFB with CKREF (freq. subtraction), the time residue is carried forward to next cycle

CKFB

CKREF

CKDIFF

➔ fDIFF : quantized & noise-shaped

(DFF quant. errors are used in next samples)

1fREF/4

1fREF/3

1fREF/4

1fREF/4

[e.g.] fREF/4 < fREF-fFB < fREF/3

1fDIFF

Implementation of 65nm Bang-Bang PLL

Slide 14

• DFF-based frequency subtractor (equivalent to /3)• Digital Loop-Filter with both coarse and fine gain ctrl.

/4KFF

−1+1UP

01

KFC KP

KI

Z-1

DLF (with fine/coarse gain ctrl)

KFF : Fine GainKFC : Coarse Gain

/8

BBPFD

D Q

fREF

10

Ring-DCO(10b cap. bank)

fPLL

fFB=fREFx3/4

fDIFF=fREF/4

Divider for high frequency gen.

fREF/4

4Coarse[3:0]

10b Digitally-Controlled Ring-Oscillator

Slide 15

• 10bit DCO with distributed fine-tuning cap. elements

N. August et. al., ISSCC 2012

1.6GHz BBPLL Test Configurations

Slide 16

BBPFD DLF

266.667MHz/4

DCO/366.667MHz

66.667MHz

200MHz/8

1.6GHz

BBPFD DLF

266.667MHz/4

DCO

66.667MHz

DFF

66.667MHz200MHz/8

1.6GHz

Conventional BBPLL

This Work

Replace /3 with

DFF

Measured PLL Output Spectrum

Slide 17

Conv. BBPLL

This Work

• Spur reduced by >20dB at PLL bandwidth (~6.5MHz)

Measured PLL Phase Noise

Slide 18

Conv. BBPLL

This Work

• In-band PN improvement is due to reduced div. ratio

Chip Micrograph and Summary

Slide 19

Comparison with Prior Bang-Bang PLLs

Slide 20

N. August et al.ISSCC'12

Proc.

D. Tasca et al.ISSCC'11

This Work

22nm

65nm

65nm

In-Band PN

-100dBc/Hz

-101dBc/Hz

-97dBc/Hz

IntegratedRMS Jitter

13.6ps@10k-500MHz

0.56ps@3k-30MHz

9.7ps@20k-40MHz

Area[mm2]

0.017

0.220

0.019

Z. Ru et al.VLSI'13 65nm -100dBc/Hz 0.215ps

@10k-20MHz0.150

DCO

Ring

LC

Ring

LC

Freq.

0.4GHz

3.3GHz

1.6GHz

11.8GHz

Power

0.8mW

4.5mW

2.7mW

6.0mW

J. Liu et al.ISSCC'14 20nm -90dBc/Hz 27.9ps

@20k-40MHz0.012Ring 1.23GHz 2.5mW

Summary

Slide 21

• Traditional frequency divider of BBPLL replaced by DFF based frequency subtractor circuit

• Noise-shaping behavior of DFF circuit suppresses spur noise due to limit cycle

• A 65nm BBPLL operating at 1.6 GHz has 9.7ps integrated RMS jitter from 20kHz to 40MHz while consuming 2.7mW