95% Efficiency, 10MHz Switching Rate and 30W, Fully

95% Efficiency, 10MHz Switching Rate and 30W, Fully Integrated Buck Converters Using E/D-mode

GaN HEMTs

Isabelle Telliez MaXentric Technologies, LLC

San Diego, CA 92037 Email: [email protected]

Toshifumi Nakatani MaXentric Technologies, LLC


Taoling Fu MaXentric Technologies, LLC


Yoann Tagro MaXentric Technologies, LLC


Cuong Vu MaXentric Technologies, LLC


Jeremy Fisher Wolfspeed, Cree Inc Durham, NC 27709

Email: [email protected]

Scott Sheppard Wolfspeed, Cree Inc Durham, NC 27709


Saptharishi Sriram Wolfspeed, Cree Inc Durham, NC 27709


Jennifer Gao Wolfspeed, Cree Inc Durham, NC 27709


Abstract— Highly efficient and fast power switches have been

demonstrated with GaN HEMT on SiC. With such devices, it is possible to increase the switching rate of a half bridge synchronous buck converter and therefore decrease the value of the inductance of the output filter. However a higher switching frequency increases the sensitivity of the gate driver connection to the switches. This paper reports two fully integrated buck converters with their gate drivers, using Wolfspeed enhanced/depleted mode GaN on SiC process. With a switching frequency of 10MHz, output powers from 10W to 30W have been delivered with a switcher efficiency ranging from 90% to 95%, and an overall efficiency of 87% to 95%, under an input voltage of 28V. The size of the circuits is less than 5.2mm2 .

Keywords— component, power management, buck converter, switched mode power supply, switching frequency, efficiency, GaN HEMT on SiC, logic

I. INTRODUCTION

Switched mode power supplies are widely used in a wide range of applications because they offer superior power efficiency compared to linear regulators. The half bridge buck converter is a frequently adopted topology due to its simplicity. Many commercial dc-dc converters use Silicon (Si) power devices for the switching stage, but the switching frequency is limited to a few hundred kilohertz. Size reduction, in particular reduction of passive components, increases the demand for higher switching frequency. On the other hand, as the switching frequency goes higher the losses associated with the output capacitance of the switching devices increases and lower the efficiency.

Recently, utilizing Gallium Nitride (GaN) devices as a

switching device has gained attraction. GaN on Si has demonstrated high efficiency at around 1MHz switching frequency, while enhanced mode GaN on SiC has reached the 5 to 10MHz frequency [1], [2], [3], [4]. Wideband GaN High Electron Mobility Transistors (HEMTs) present desirable features that help realize high efficiency, high switching frequency dc-dc converters. GaN HEMT on SiC can operate under low to medium voltage, and GaN HEMT present high breakdown voltage (>80V), high current and power density as well as a higher thermal conductivity compared to CMOS, or GaN on Si. This technology has been adopted for RF power amplifiers and demonstrated up to 40MHz for pulse width modulated (PWM) buck converters [3].

Furthermore, one of the main challenges of the half bridge topology is the implementation of the high side gate driver. The high side gate driver has to turn on and off efficiently while its source is switching under full input voltage swings. Any parasitic capacitance and inductance in the design of the half bridge and its drivers introduces additional losses and ringing because of the GaN HEMT high slew rate and switching frequency. To reduce the effects of the parasitic capacitances and inductances at high switching frequency, it is necessary to consider the power stage and its drivers in the same package or on the same die. Short propagation delay and good matching are necessary for half bridge topologies at high frequency.

Normally on or depletion mode, only GaN HEMT MMIC processes have enabled efficient power stage integrated with their drivers operating at switching frequency up to 200MHz [5], [6]. However these circuits either present a high driver DC consumption, or need various supplies. Normally off or enhanced mode power stage would be the preferred choice for a safe starting mode for the power stage, but the driver design is challenging with only enhanced mode (E-mode) transistors. This has been overcome by using CMOS drivers and by assembling the power stage and its driver in the same package

DISTRIBUTION STATEMENT A. (Approved for Public Release, Distribution Unlimited). Approval Date: January 16, 2019.

The views, opinions and/or findings expressed are those of the authors and should not be interpreted as representing the official views or policies of the Department of Defense or the U.S. Government.

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([1], [7], [8]). Although this realization achieves good performance, the switching frequency is limited to 10MHz and uses a bootstrap technique to connect the high side driver to the power stage.

This paper reports an alternative approach to the previous works: the half bridge power stage is realized with a standard 0.4µm gate width depletion mode (d-mode) GaN HEMT on SiC and integrated with its drivers using enhanced and depletion mode transistors.

II. OVERVIEW OF GAN PROCESS

The E/D mode logic circuits, along with MMICs in this work, were fabricated using a slight modification of Wolfspeed’s commercially available G28V3 foundry process which includes MIM capacitors, slot vias, and inductors. An important constraint in this development was to achieve monolithic integration of digital and microwave functions with minimal impact on the critical features (passivation, etc.) of the MMIC FETs while maintaining performance and reliability features. This objective was achieved by developing an insulated gate device for the E-mode FET. This device was formed by selectively removing the AlGaN layer of the GaN HEMT and then depositing an insulating layer in the gate region of the e-mode FET. E-mode gate metal was deposited on top of the insulator and extended slightly beyond the gate etch opening on both the source and drain sides. The source and drain ohmic contacts of the e-mode FET were fabricated at the same process step as the microwave FET ohmic contacts. The gate length (etched gate opening) was 0.4 µm, and the gate was placed in the middle of the source-drain gap. On this device there was no field plate. Typical turn-on voltage for the e-mode device was in the 1 to 1.5 V range. The drain current at Vg and Vd =5V was in the 200 to 250mA/mm range. The logic function was achieved by using the e-mode FET as the switch with a d-mode load FET in series with it. The standard GaN HEMT with a longer gate of 8 µm was used for the d-mode FET. The longer gate length was required to match the drive currents of e- and d-mode FETs. These devices are very reproducible and have been demonstrated in several lots. These characteristics were suitable for implementing the control drive, and digital functionality demonstrated in the buck converter circuits.

III. INTEGRATED GATE DRIVERS FOR

SYNCHRONOUS BUCK CONVERTER

A. Power stage

The power stage of the synchronous buck converter (Fig. 1) was implemented with the normally on (D-mode) standard RF power device of Wolfspeed G28V3 because of its high voltage handling and better figures of merit (RON, QG, COUT). After a trade space study of the different losses, the device’s total gate width was fixed to 12mm. The gate was composed of 2 transistors of 16 fingers which were 375µm long. As shown on Fig. 1, since the low side switcher device is referenced to ground, its gate control voltage needs to be referenced to a negative voltage and switched up to 0V. The negative supply was chosen to be (-5V).

Fig. 1: Synchronous buck converter configuration

B. Drivers

The E/D-mode GaN HEMTs on a single SiC wafer harks back to the early days of GaAs logic circuits in the 1970’s ([9], [10], [11]). Logic, power, driver, and control circuits can be efficiently implemented using this new process. This new process uses the same circuit topologies as 1970’s GaAs but at vastly better efficiency, power, and speed figures of merit ([12], [13]). The availability of normally off and normally on transistors in the same process enables logic circuit with only one supply, without level shifting diodes. Two types of basic logic cells can be used; a simple E/D inverter for Direct Coupled FET Logic (DCFL) and a Super Buffer FET Logic (SBFL) (Fig. 2). In the E/D mode HEMT inverter, the D mode HEMT is used as a load, and the E-mode transistor acts as a driver. In both cases, input voltages switch between the lowest supply (0V in Fig. 2) and the highest supply of the logic cell (Vdd in Fig. 2). Hence once properly scaled to drive the power stage devices, these two topologies are natural candidates for the driver chain. This applies mostly to the low side driver of a half bridge buck converter, since the high side driver faces a more challenging problem.

Fig. 2: Circuit schematic of: (a) DCFL (Direct Coupled FET Logic) inverter and (b) SBFL (Super Buffer FET Logic)

Once the power switch stage is sized properly, the major challenge is driving efficiently the high side power switch. The gate-source voltage of the high side switch has to switch from -5V to 0V to toggle from OFF state to ON state, while its source voltage varies from 0V to about 28V. Non-bootstrapped drivers using D-mode only transistors have proven to be efficient and functional over a wide range of frequencies [5]. We also adopted the direct connection to the switching node in our design. Our approach for the high side driver was to modify the E/D mode inverter where an additional D-mode device is stacked on top of the E-mode as shown in Fig. 3. This configuration keeps the E-mode device under safe operating voltages and balances the rise time and

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fall time of the output voltage by reducing the effect of the large output capacitance of the E-mode.

Fig. 3: E-stacked D/D-mode inverter (EDD) schematic

C. Integrated Buck converters

Fig. 4 shows the schematic of the synchronous buck converter integrated with its drivers (EDD version) and the external components. The high side driver is the E-stacked D/D mode inverter which has the supply node directly connected to the switching node. The low side driver is implemented with a super buffer configuration. When GH level is low (-5V), transistor QE1 is off, as well as QD1. Simultaneously, QD2 pulls the gate voltage GHT of the high side switcher QHS to its source voltage driving QHS on and the node SW to the input voltage Vin. When GH rises to 0V, QE1 turns on and subsequently QD1 turns on. The gate voltage is hence pulled down to VSH (-5V) turning off QHS.

Another version of this integrated synchronous buck converter (EDP) includes pre-drivers so that the high side input control voltage duty cycle is directly linked to the switcher duty cycle. The schematic of this version is presented in Fig. 5. The high side driver topology is the same as the one previously used in the EDD version, but it is now driven by a super buffer pre-driver. The low side driver is now an E/D inverter driven by a super buffer pre-driver. Although the super buffer topology presents lower consumption than an E/D chain, the overall efficiency is slightly impacted by the pre-drivers DC consumption.

The drivers and pre-drivers were simulated and their layout was performed with the digital models and rules, whereas the switcher was simulated and the layout was completed with the standard RF design kit. Fig. 6 shows the layout of the two fully integrated GaN HEMT buck converters. The die area is 2.67x1.92mm2. Most of the die area is occupied by the power switch devices. The buck converter chips include decoupling snubbers taking advantage of the MMIC process capabilities.

Fig. 4: Schematic of the synchronous buck converter integrated with its drivers (EDD version)

Fig. 5: Schematic of the integrated buck converter with drivers and pre-drivers (EDP version)

(a) (b)

Fig. 6: Layout of the two fully integrated GaN HEMT buck converters

IV. RESULTS

A. Test board and test set-up

The input waveforms were generated with the Tektronix Arbitrary Waveform Generator (AWG) 7082C. These waveforms were sampled at 8GHz with a switching frequency of 10MHz. The two layer test board included a dual current feedback Opamp with 2 GHz unity gain bandwidth (THS3202) to amplify the input signals generated by the AWG and applied complementary (-5V) to (0V) signals to the buck converter dies. A cut-out in the board allowed the dies to be eutectic bonded by directly attaching them to the heatsink. The dies were connected to the board with bonding wires as shown in Fig. 7. A catch diode was implemented as a dead band failsafe. We chose the magnetically shielded surface mount power

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inductor MSS1048-682 because it presented the best performance over a wide range of currents, the smallest DCR, and low losses. Unfortunately, MSS1048-682 did not the smallest volume (10.5x10.3x5.1mm3). The output filter also had two capacitors to ground of different values, in order to get a stable response over a wide range of loads [12-150 Ohm]. One of the capacitors was a Tantalum capacitor of ~100nF

Fig. 7: Photograph of the test board

B. Measurement results

The two buck converters were measured under the following conditions; 10MHz switching frequency, a load from 14 to 100 Ohm, a duty cycle from 20% to 80% by a step of 10%, and input DC voltages of 5V, 10V, 20V and 28V. Some additional DC input voltages of 15V and 25V were also applied to the EDP version. The switcher efficiency is defined as the ratio of the DC output power (Pout) over the DC input power. The overall efficiency was calculated as the ratio of the DC output power over the DC input power and the DC power consumption of the on-chip drivers. The measurement results are synthesized in Fig. 8 for the EDD version and in Fig. 9 for the EDP version.

For the EDD version, the switcher efficiency is over 90% and the overall efficiency higher than 89% for output powers over 10W. The waveforms applied are referred as the switcher duty cycle (and not 1-D) for the sake of comparisons with the other version. As expected the version with the pre-drivers EDP shows a slightly lower overall efficiency than EDD, but higher than 86%, for output powers over 10W.

The DC consumption of the driver is very well predicted. The simulated DC power was 0.217W and the measured DC power is 0.225W in the following conditions: 28V DC input voltage, a switching frequency of 10MHz, and a duty cycle of 50%.

Fig. 10 compares the integrated buck converter performance with previous other GaN HEMT buck converter realizations at 50% duty cycle. Our realizations exhibit high efficiency at 10W output power and pave the way to add the pulse width modulation circuitry as well, as demonstrated in [14].

(a)

(b)

Fig. 8: EDD version - Switcher efficiency (a) and overall efficiency (b) versus output power for a switching frequency of 10MHz

(a)

(b)

Fig. 9: EDP version - Switcher efficiency (a) and overall efficiency (b) versus output power at switching frequency of 10MHz

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Fig. 10: Total Efficiency versus DC Output Power of GaN DC-DC converters and their drivers for different switching frequencies

V. CONCLUSIONS

Two fully integrated buck converters with their drivers have been realized using a 0.4um E/D mode GaN HEMT on SiC process. Efficiencies over 90% have been demonstrated with output DC power ranging from 10 to 30W, over a wide range of duty cycles and output loads. The switching frequency could be increased to take full advantage of the integration.

ACKNOWLEDGMENT

This work was supported by DARPA under SBIR contract number D16PC00038.

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95% Efficiency, 10MHz Switching Rate and 30W, Fully