9/4/2012 - L6 Language Overview I Copyright 2006,2012 - Joanne DeGroat, ECE, OSU 1 Language Overview I The start of a grand tour of the language

9/4/2012 - L6 Language Overview I

Copyright 2006,2012 - Joanne DeGroat, ECE, OSU

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Language Overview IThe start of a grand tour of the language.



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Elements Covered in I Language overview lectures(I,II,III) do not cover all

aspects of the language, however, they do cover a large portion of it.

This Lecture: TYPES DECLARATIONS OPERATORS CONCURRENT STATEMENT

Component Instantiation Generate Statement



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DATA TYPES ENUMERATION TYPES

Initialize to the leftmost element Predefined types in Package Standard

type BIT is (‘0’,’1’); Will initialize to ‘0’ if not explicitly initialized.

type BOOLEAN is (FALSE, TRUE); Will initialize to what?

Usage SIGNAL mysig : BIT;

User defined examples type OPCODE is (OPAND, OPOR, OPADD, OPMOVE); type SWITCH_LVL is (‘0’,’1’,’X’);

SIGNAL proc_oper : OPCODE := OPOR; VARIABLE flag : BOOLEAN;



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DATA TYPES Integer Types

INTEGER Predefined type Integer type with range of at least -2147483647 to +2147483646

(a 2 complement range for a 32 bit integer) TYPE word_index IS RANGE 31 DOWNTO 0;

And integer with values >= 0 and <= 31 TYPE two_complement_integer IS RANGE -32768 TO 32767; use VARIABLE myintvar : INTEGER;

SIGNAL my_word :word_index;



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DATA TYPES Floating Point Type

REAL Predefined type with range >= -1E38 to +1E38

Character Type CHARACTER - a single alphanumeric character



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IMPORTANT:: A Type Issue VHDL IS STRONGLY TYPED

This means that the TYPE of the signal or variable on the left of the assignment operator must be the same as that type of the arguments on the right hand side.

Even if the definition of the type is identical, the signal or variable must reference back to the same TYPE declaration.



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DATA TYPES PHYSICAL TYPE

TYPE time IS RANGE 0 to 1E18 -- Predefined UNITS

FS; -- femtosecond PS = 1000 FS; -- picosecond NS = 1000 PS; -- nanosecond US = 1000 NS; -- microsecond MS = 1000 US; --millisecond SEC = 1000 MS; -- second MIN = 60 SEC; -- minute

END UNITS;



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DATA TYPES User defined physical type

TYPE distance IS RANGE 0 TO 1E16 UNITS

A; -- angstrom, base unit NM = 10A; -- nanometer MIL = 254000A; -- mil INCH = 1000 mil; -- inch

END UNITS; Usage

VARIABLE X : distance; VARIABLE Y : time; X := 5 A + 14 inch – 45 mil; Y := 3 ns + 5 min;

Any implementation allows for declaration of physical types with a range of -2147483647 to +2147483647



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More on TYPES - subtypes SUBTYPES

SUBTYPE POS_INT IS RANGE 1 TO integer’high; VARIABLE mri : POS_INT; “A subtype of type is also of the type”.

NOTE : VHDL CODE IS CASE INSENSITIVE!! Subtype pos_int IS RANGE 1 to INTEGER’High;

is the same as the declaration above



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Composite types ARRAYS

TYPE my_word IS ARRAY (0 to 31) of BIT; TYPE regs IS ARRAY (7 downto 0) of my_word;

Unconstrained ARRAYS TYPE memory IS ARRAY (INTEGER range <>)

of my-word; USE:

VARIABLE my_mem : MEMORY (0 to 65536);



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Predefined Arrays SUBTYPE positive IS INTEGER range 1 to

ITEGER’HIGH; INTEGER’HIGH is the largest integer for this

installation TYPE string IS ARRAY (POSITIVE RANGE <>)

of CHARACTER; SUBTYPE natural IS INTEGER range 0 to

ITEGER’HIGH; TYPE bit_vector IS ARRAY (NATURAL

range <>) of BIT;



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DATA TYPES EXAMPLES of use

VARIABLE message : STRING(1 to 17) := “THIS is a message”;

Text inside a string is case sensitive message (1 to 16) := “Modified Message”;

WHAT WOULD BE CONTAINED IN THE VARIABLE MESSAGE????

SIGNAL low_byte : BIT_VECTOR (0 to 7);

An interjected comment From prior years Comments on HW1 and PS1

BE SURE TO SUBMIT TO RIGHT DROPBOX

BE SURE FILES ARE THE RIGHT ONES AND ARE READABLE

For submission convert .ps files to .pdf Wave files as .pdf or .bmp Submit code and list files – text only



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DATA TYPES COMPOSITE TYPES RECORDS

TYPE month_name IS (Jan, Feb, Mar, Apr, May, Jun, Jul, Aug, Sep, Oct, Nov, Dec);

TYPE date IS RECORD

DAY : INTEGER range 1 to 31; MONTH : month_name; YEAR : INTEGER range 0 to 4000;

END RECORD;



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COMPOSITE TYPES ACCESS TYPES

Dynamic Records

FILE TYPES File of STRING File of NATURAL – defines a file that can

contain only non-negative integer values TYPE FT IS FILE OF STRING; We will use files I/O at the end of the course



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DECLARATIONS VARIABLES

For use in processes, procedures and functions Scope limited to the process, procedure, or function in

which declared. Cannot be declared in the declarative region of

architectures!!!! Have no time component Any assignment takes place immediately upon

assignment. VARIABLE my_var : BIT;



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DECLARATIONS SIGNALS

For use in entities, architectures, procedures, functions, and process.

Scope depends upon where declared – can be sort of global (scope of architecture)

Have a value and time component Assignments do-not take place immediately – assignment

of new values are scheduled Delaration in Entities, Architectures, Concurrent

Procedures SIGNAL my_sig : BIT :=‘1’; SIGNAL my_int : INTEGER := 45;



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DECLARATIONS ALIASES

SIGNAL real_num : BIT_VECTOR (0 TO 31); ALIAS sign : BIT is real_num(0); ALIAS exp : BIT_VECTOR(0 TO 7) is real_num

(1 TO 8); ALIAS fract : BIT_VECTOR (0 to 22) is

real_num (9 TO 31); Then in the design you can assign or use any

of the names real_num, sign, exp, fract.



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DECLARATIONS CONSTANTS

CONSTANT pi : REAL := 3.141592; CONSTANT cycle_time : TIME := 75 ns; Can be declared and used but cannot be assigned to

COMPONENT Declaration needed for hierarchical models COMPONENT local_component_name

PORT(port declarations from component’s entity) END COMPONENT; The easy way to do a component declaration is to copy the

ENTITY Declaration, change ENTITY TO COMPONENT, delete the IS and change END xxx to END COMPONENT.



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OPERATORS LOGICAL OPERATORS::

AND | OR | NAND | NOR | XOR | XNOR | NOT APPLY TO TYPES BIT AND BOOLEAN

RELATIONAL OPERATORS:: = | /= | < | <= | > | >=

Result of comparison with relational operators is BOOLEAN



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OPERATORS ADDING OPERATORS::

+ | - | & + and - work with REAL and INTEGER types & is the concatenation operator and works with types

BIT and BIT_VECTOR Result of & is concatenation of left + right

X <= “000”; Y <= “1111”; Z <= X & Y would now have value “0001111” scheduled for assignment



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Concatenation example VARIABLE r,x : BIT_VECTOR (31 downto 0); VARIABLE y : BIT_VECTOR (0 to 31); SIGNAL s, pval : BIT: SIGNAL Q76 : BIT_VECTOR( );

Using part of a vector is termed slicing R(15 downto 0) := x(31 downto 24) & y(0 to 7); r(31 downto 30) := s & pval; Q76 <= r & s & pval; How large does Q76 have

to be?



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Q76? The size of the concatenated vector MUST

match the size of the target. Q76

Could be 0 to 33 OR 33 downto 0;



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OPERATORS SIGN:: + | - MULTIPLYING:: * | / | MOD | REM

* and / can be used for integer and real MOD and REM are valid only for type integer

MISCELANOUS:: ** | ABS | NOT



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CONCURENT STATEMENTS Concurrent statements are those that can

appear between the BEGIN and END of an architecture.

With these statements you model the component or system to be modeled

These statements execute independent of the order in which they appear in the model.



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CONCURRENT STATEMENTS Component Instantiation Statement

Prior to use the component must be declared and configured in the declarative region of the architecture.

LABEL : component_name [generic_map_aspect] [port_map_aspect]



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Component Instantiation Consider that the following is already

analyzed and in your library ENTITY wigit IS

PORT(p1, p2 : IN BIT);

END wigit; ARCHITECTURE Y OF wigit IS …..; ARCHITECTURE Z OF wigit IS …..;



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Component Instantiation Then the declaration for use is ARCHITECTURE use_it OF xyz IS

COMPONENT wigit PORT(p1, p2 : IN BIT);

END COMPONENT; -- and the configuration is FOR C0 : wigit USE ENTITY work.wigit(y); FOR OTHERS : wigit USE ENTITY

work.wigit(Z);



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And use in the architecture SIGNAL A,B,C,D ; BIT;

BEGIN CO : wigit PORT MAP (A, B); C1 : wigit PORT MAP (p1 =>C, p2=>D);



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What about repetitive structures? When you have repetitive structures to build up with

instantiations GENERATE STATEMENT – automates the

instantiation of repetitive structures.

• • •

Leftmost Unit

Rightmost UnitInner Units



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Generate Example Consider the bit comparator ENTITY bit_comparator IS

PORT(a,b,gt,eq,lt : IN bit; a_gt_b, a_eq_b,a_lt_b : OUT bit);

END bit_comparator;

ARCHITECTURE bit_comp_arch OF bit_comparator IS BEGIN a_gt_b <= ‘1’ WHEN (a>b) OR ((a=b) AND gt) ELSE ‘0’; a_eq_b <= ‘1’ WHEN ((a=b) AND eq) ELSE ‘0’; a_lt_b <= ‘1’ WHEN ((a<b) OR ((a=b) AND lt) ELSE ‘0’; END bit_comp_arch;

BA

lt

eq

gt

a_lt_b

a_gt_b

a_eq_b



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Now make an 8 bit comparator ENTITY byte_comparator IS

PORT (a,b : IN bit_vector (7 downto 0); --a & b data gt,eq,lt: IN bit; --previous slice results a_gt_b, a_eq_b, a_lt_b : OUT bit); --outputs END byte_comparator;

Now we will look at three possible approaches to implementing this.

The first is of course 8 component instantiations



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The start of the architecture ARCHITECTURE iterative OF byte_comparator IS

--do component declaration and configuration COMPONENT bit_comparator

PORT (a,b,gt,eq,lt:IN bit;a_gt_b, a_eq_b, a_lt_b:OUT bit);

END COMPONENT; FOR ALL: bit_comparator USE ENTITY

WORK.bit_comparator(bit_comp_arch); --internal signal to connect bit positions SIGNAL igt,ieq,ilt : bit_vector (0 to 6);



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3 Possible approaches – 8 Instantiations very tedious BEGIN

C0 : bit_comparator PORT MAP (a(0),b(0),gt,eq,lt,igt(0),ieq(0),ilt(0)); C1 : bit_comparator PORT MAP

(a(1),b(1),igt(0),ieq(0),ilt(0),igt(1),ieq(1),ilt(1)); C2 : bit_comparator PORT MAP





(a(6),b(6),igt(5),ieq(5),ilt(5),igt(6),ieq(6),ilt(6)); C7 : bit_comparator PORT MAP (a(7),b(7),igt(6),ieq(6),ilt(6),a_gt_b,a_eq_b,

a_lt_b); END



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Generate version1 Use component instantiations to handle boundries BEGIN

--start with lsb where lsb is rightmost bit C0: bit_comparator PORT MAP(a(0),b(0),gt,eq,lt,igt(0),ieq(0),ilt(0)); C1to6: FOR i IN 1 to 6 GENERATE

C: bit_comparator PORT MAP (a(i),b(i),igt(i-1),ieq(i-1),ilt(i-1), igt(i),ieq(i),ilt(i));

END GENERATE; --end with msb where msb is leftmost bit C7: bit_comparator PORT MAP (a(7),b(7),igt(6),ieq(6),ilt(6),a_gt_b,a_eq_b,a_lt_b);

END iterative;



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GENERATE version 2 Nested Generate BEGIN

C_all: FOR i IN 0 to 7 GENERATE --handle lsb where lsb is rightmost bit lsb: IF i=0 GENERATE

least : bit_comparator PORT MAP (a(i),b(i),gt,eq,lt, igt(0),ieq(0),ilt(0)); END GENERATE; --handle msb where msb is leftmost bit msb: IF i=7 GENERATE

most : bit_comparator PORT MAP (a(i),b(i),igt(i-1),ieq(i-1),ilt(i-1), a_gt_b,a_eq_b,a_lt_b);

END GENERATE;



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And the middle slices --handle remaining bit slices mid: IF i>0 AND i<7 GENERATE

rest: bit_comparator PORT MAP (a(i),b(i),igt(i-1), ieq(i-1), ilt(i-1), igt(i),ieq(i),ilt(i));

END GENERATE;

END GENERATE; END iterative;

Documents

9/4/2012 - L6 Language Overview I Copyright 2006,2012 - Joanne DeGroat, ECE, OSU 1 Language Overview I The start of a grand tour of the language