9/16/2004 ACCESS ICLABaccess.ee.ntu.edu.tw/course/DSP_Lab/slides/w1 2004-09-15 DSP Out… · Lab handout and final project. ACCESS ICLAB Graduate Institute of Electronics Engineering,

ACCESS IC LAB

Graduate Institute of Electronics Engineering, NTU

/

9/16/2004

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

Overview of DSP Processor Current Status of NTU DSP Laboratory (E1-304)Course outline of Programmable DSP LabLab handout and final project


DSP processor is a specially designed microprocessor for multimedia/communication applications

Data path is configured for DSP algorithms (Inner product & convolutions)

Specialized (DSP-oriented) instruction sets (Single-cycle MAC, Hamming distance operations, Saturation operations, etc.)

Multiple memory banks and buses (Harvard architecture)

Specialized addressing modes (FFT bit reversal)

Specialized execution control (Loop control)

Specialized peripherals for DSP (ADC, DAC, A/V Codec)


Implementation Choices of DSP Implementation Choices of DSP SystemsSystems

DSP system can be implement through many approachesProgrammable DSP not only makes prototypingfast but also achieve great performance and powerefficiency.DSP processor costs less than ASIC/FPGA if it is selected carefully with application-specific analysis.





Two 16-bit MACs (Multiply-and Accumulator), two 40-bit ALUs, four 8-bit Video ALUs

Support for 8/16/32-bit integer and 16/32-bit fractional data types

Concurrent Fetch of One instruction and Two unique data elements

Two loop counters that allow for Nested Zero-overhead Looping

A Modified Harvard architecture



Compute Unit ArchitectureCompute Unit Architecture


A single, unified 4G byte address space using 32-bit addressesThe L1 memory system is the primary highest performance memory available to the core and is faster than L2 memory systemThe L2 memory system is off-chip and have longer access latencies


Parallel Peripheral Interface (PPI)Serial Ports (SPORTs)Serial Peripheral Interface (SPI)General-purpose timersUniversal Asynchronous Receiver Transmitter (UART)Real-Time Clock (RTC)Watchdog timerGeneral-purpose I/O (programmable flags)


ADSPADSP--BF535 EZBF535 EZ--KIT KIT LiteLite

Key features Attributes

ADSP-BF535 Blackfin Processor4M x 32-bit SDRAM272K x 16-bit FLASH memoryAD1885 48 kHz AC 97 SoundMax codecPower management capabilityJTAG ICE 14-pin headerEvaluation suite of VisualDSP++Three 90-pin connectors for analyzing andinterfacing with the processors peripheral interfaces CE Certified

System RequirementsPentium 166 MHz or higherMinimum of 32 MB of RAMWindows 98, Windows 2000, or Windows XPOne USB port


C2.4G 11 ( VLSI )

4 ( )

12 ( )

13 ( )

ADI Blackfin DSP tools 11 ( ADI donation)

TV-BOX 11 ( )

NTSC Camera 11 ( )

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Course Outline of NTU DSP LabCourse Outline of NTU DSP Lab(Fall 2004)(Fall 2004)

9/13~9/19 Course outline No Lab

9/20~9/26 DSP introduction No Lab

9/27~10/2 Blackfin architecture No Lab

10/4~10/10 Development tool Tool installation

10/11~10/17

BF533 peripherals Access peripherals

10/18~10/24

FIR (I) Audio sampling

10/25~10/31

FIR (II) Audio equalizer

11/1~11/7 Code optimization Previous Labs

11/8~11/14 VDK Previous Labs

11/15~11/21

DPCM/ADPCM ADPCM

11/22~11/28

Storage and FAT file system Access data from storage device

11/29~12/5 Digital Audio Recorder DAR

12/6~12/12 2D image compression (I) DCT & Quantizatizer

12/13~12/19

2D image compression (II) DVR ~

12/20~12/26

Term project

E2-144

E1-304


Course Outline of NTU DSP LabCourse Outline of NTU DSP Lab(Fall 2004) cont(Fall 2004) cont

1~3 2 1444~17 1 304

http://access.ee.ntu.edu.tw/course/DSP_Lab/Password : DSPprg

301~3

10



TA ([email protected])1 1 .zip

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8 final project proposalaudio/video

15~1718 8

60%40%

Documents

9/16/2004 ACCESS ICLABaccess.ee.ntu.edu.tw/course/DSP_Lab/slides/w1 2004-09-15 DSP Out… · Lab handout and final project. ACCESS ICLAB Graduate Institute of Electronics Engineering,