90nm RHBD ASIC Design Capability - NASA · 1 90nm RHBD ASIC Design Capability Tony Amort, Warren Snapp, John Evans, Jeremy Popp, Manuel Cabanas-Holmen, Ethan Cannon This work was

1

90nm RHBD ASIC Design Capability

Tony Amort, Warren Snapp, John Evans, Jeremy Popp, Manuel Cabanas-Holmen, Ethan Cannon

This work was sponsored in part by the Defense Threat Reduction Agency under contract #: HDTRA1-05-D-0001-0002. Opinions,

interpretations, conclusions, and recommendations are those of the author and are not necessarily endorsed by the United States Government.

ReSpace/MAPLD 2011

Engineering, Operations & Technology | Boeing Research & Technology Solid-State Electronics Development

2

RHBD with leading-edge commercial device technologies

provides a sustainable option which ensures the supply of

radiation-hardened components for future space systems.

• State-of-the-art performance

• Continuity of foundry access

• Leveraging the investment of

commercial foundries

including IP, EDA, QC

Motivation for RHBD on Commercial

Performance,

Power,

Complexity

2000 2005 2010 2015

Rad-Hard

Moore’s Law


Single Event

Errors

3

Commercial CMOS Hardness TrendsH

ard

ness

Technology Node (nm)

Spacecraft

Requirements

90130180250350500800

TID

Latch Up

65 45

Commercial process improvements reduce need for TID or Latchup Mitigations

Design methods to mitigate Single Event Errors are increasingly important

SOI


Single Event

Errors

4


ard

ness


Spacecraft

Requirements

90130180250350500800

TID

Latch Up

65 45

De

sig

n

Pro

ce

ss



SOI


Single Event

Errors

5


ard

ness


Spacecraft

Requirements

90130180250350500800

TID

Latch Up

65 45

De

sig

n

Pro

ce

ss

Pro

ce

ss

De

sig

n



SOI


Single Event

Errors

6


ard

ness


Spacecraft

Requirements

90130180250350500800

TID

Latch Up

65 45

De

sig

n

Pro

ce

ss

Pro

ce

ss

De

sig

n

De

sig

n



SOI


7

High Performance Communication Satellite DSPs Require Advanced ASICs

Parameter ICO Thuraya Spaceway Today’s

Capability

ASIC Technology 0.7µm

RHBP

0.25µm

Commercial

0.18µm

Commercial90nm

RHBD

Number of ASICs 2300 360 390 76

Performance (TOPS) 3.6 14 62 105

Mass (Kg) 270 190 124 90

Power (W) 2200 2300 2100 1575

RHBP RHBA RHBD

Switchover to commercial ASIC technologies enabled

major advances in functionality and performance

Next G

en 4

5nm

SO

I RH

BD


8

RHBD90 Development

Instrumentation

ARM

Cortex

Processor

Trace Memories

I/O

PLL

ARM

Cache

RH Cortex• ARM Cortex R4

• 22 million

transistors

• 430 MHz

MAESTRO• 49 core processor

• 10 Gbps SERDES

• 750 million

transistors

• 7,000 C4 Bumps

Digital Transistors

I/O Transistors

SET Spectrum

Technology

Characterization

Design

Enablement

Demonstrations


9

RHBD with Commercial 90nm CMOSTID Response

Digital Transistors

I/O Transistors

Logic Block

TID Hardness Demonstrated at Device, Circuit and SoC Levels

RH Cortex Processor

Phase-Locked Loop

0

0.5

1

1.5

2006 2007 2008 2009 2010

Fab A Fab B

TID

Hardness

(Mrad)

TID Lot-to-Lot

Compiled TD PLL Testing Results

1

10

100

1000

0 500 1000 1500 2000

Dose (Rad Si)

Cur

rent

(mA

)

1

10

100

1000

Freq

(GH

z) &

Gai

n (M

Hz/

V)Iq_V3_Bd1

Iq_V2_Bd1

Iq_V3_Bd2

Iq_V2_Bd2

VCOFreq_V3_Bd2

VCOFreq_V2_Bd2

VCOgain_V3_Bd2

VCOgain_V2_Bd2

VCOFreq_V3_Bd1

VCOFreq_V2_Bd1

VCOgain_V2_Bd1

VCOgain_V3_Bd1

SRAM

1.E+02

1.E+03

1.E+04

0 200 400 600 800 1000

Dose (Mrad[Si])C

urr

en

t (m

A)


10

SEU can be Mitigated Effectively

Soft FF

(8.4µm x 3.36µm)

DICE FF

(15.4µm x 3.36µm)

RHBD with Commercial 90nm CMOS

Single-Event Effects – Flip-Flop Upsets

FF

TypeSEU Rate(errors/bit-day)

Area Speed Power

Soft 10-6 1X 1X 1X

DICE 6x10-9 2X 1.5X 2X

TMR 10-12 (depends

on spacing)4X 1X 4X

Flip-Flop Options

• Classical methods of SEU rate analysis

are not applicable to redundant designs

• Pursued three analysis paths:• Boeing FastGT

• VU/ISDE MRED

• Robust Chip Monte-Carlo/Accuro

• Good agreement

among all 3 analysis methods

TxA TxB

New Analysis Methods Developed

Cross-section depends on incident angle


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Classical methods of SEU rate analysis (such as CREME96) are not

applicable to redundant designs

Use single sensitive volume

Neglects geometric effects

Angular effects must be accounted for• DICE is SEU Immune for ions with inclination at or less than 60

degrees

• Soft DICE SEU Rate > 1000 times greater than DICE

Cross Section Vs LET70 deg Tilt, 45 Deg Roll

Flip-Flop SEU Analysis


12

0102030405060708090

100

800 km,

45° GCR

800 km,

45° SAA

Adams

10%

GEO

Worst

Day

% o

f T

ota

l S

EU

Ra

te

LE proton HE Proton HI

SEU Mitigated for Heavy Ions, High and Low Energy Protons

Negligible Impact on Processor Performance


Single-Event Effects – SRAM Upsets

RHBD techniques include

• Bit spacing

• Scrubbing

• Error detection

• Bit cell design

• Peripheral ckt design

Commercial Cell

RHBD Cell B

RHBD Cell C

1.E-10

1.E-09

1.E-08

1.E-07

0.0 10.0 20.0 30.0 40.0 50.0 60.0 70.0

LET (MeV-cm2/mg)

SE

U C

ross S

ecti

on

(cm

2/b

it)

Commercial Cell RHBD Cell B RHBD Cell C

SEU Rate Components by Environment

Commercial CellHeavy Ion Cross

Section

Proton Cross Section


13


Single-Event Effects—Transients

• System-level error rate methodology

includes temporal and logical

masking• Characterized pulse spectra vs. LET

• Determined SET generation rate for

multiple environments

1.E-13

1.E-12

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

1X 2X 4X 8X 18X 30X

Inverter Drive Strength

SE

T G

en

era

tio

n R

ate

(e

ven

ts/d

evic

e-d

ay)

GEO

LEO

Buffer sizing for clock/reset trees Temporal filter reduces error rate

SETs leading to errors depend on timing and logical masking

RHBD Library

includes

temporal filter

elements

Variety of mitigation techniques allows design trades


RHBD Design Flow

• Proven design flow based on Synopsys Recommended

Methodology (RM) flow

• Radiation effects mitigation and analysis added


SEE Analysis Overview

SEE analysis in design loop allows performance vs. error-rate tradeoff

• Single-Event Effects drive radiation performance in

sub-100nm technology

• System effects differ on different circuits and

environments

• To solve this complex problem we developed an

algorithm and methodology to quantify system

effects


SEE Analysis Flow

• Inputs from• Radiation environment

• System error budget

• Design timing reports

• Calculate error-rate components• SRAM

• Clock/Reset trees

• SET

• Flip-flop/latch SEU

• Combine with derating for

top-level error rate


17

RHBD90 Demonstrations

RH Cortex• ARM Cortex R4

• 22 M Transistors

• 430 MHz

• Demonstrated• Hardening commercial IP

• Integration of RHBD library

with commercial EDA tool flow

• Successful operation to

specified performance

• System error rate prediction

MAESTRO• 49 core general-purpose processor

• 10 Gbps SERDES

• 750 million transistors

• 7,000 C4 Bumps

• Demonstrated

• Design flow supports large,

complex chips

Instrumentation

ARM

Cortex

Processor

Trace Memories

I/O

PLL

ARM

Cache


18

RH-ARM Cortex R4

• Successfully demonstrated:

• Performance, power, and area RHBD metrics

• Performance-optimized RH memory

• Transient hardening of clock and reset trees

• Radiation hardening of commercial IP

• Error rate prediction analysis

• Flip-chip Packaging

• Industry-Leading Processor for Embedded Control & Sensor Applications

• Optimized for High-Performance, Real-Time operation

• 370 MHz @ 1.0V

• 1,065K Drystones

• Integrated Floating Point Processor

• Fault-Tolerance Support

• Extensive Software Development & Debug Infrastructure

• Medical

• Digital Imaging

• Storage

• Microcontrollers

Cortex Applications

• TID Hard to 1MRad

• SEU Hardened• Clock and reset tree

hardening • FF & SRAM

hardening


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MAESTRO RH Multi-Core Processor

• Excellent performance

across processing

domains

• FIR filter – 5 GFLOPS

sustained performance

(26% peak)

• FFT – 4 GFLOPS

sustained performance

(21% peak).

• RHBD version of the Tilera 26480 processor:

• 300MHz, 44 GOPS, 22 GFLOPS

• 2D mesh of 49 cores with low latency networks

• Each core a general purpose processor with FPU

• High speed external serial interfaces (XAUI)

• DDR1 or 2

• 18W, 500 kRad TID

• Software development environment in place

• Autonomous operations

• Parallel Processing

• Sensor Fusion

• ALTAIR – Lunar Lander

• Europa – Deep Space


20

MAESTRO RH Multi-Core Processor

• Functional test complete

• MAESTRO Development Board

(MDB) system available for

software/hardware application

development

MDB system in use for software development


21

Demonstration Testing

• Error Rates predicted• Errors classified by type

– Uncorrectable SRAM errors

– Recoverable errors

– Un-recoverable errors

• Predictions were used in design

trades

• Heavy Ion testing performed• Scan chains

• Functional at-speed testing

• Variety of tilt and rotation angles

RHBD ARM Cortex™ R4

RHBD Single-Core Tilera


Reset Logic and SRAM Results

• Reset tree Single Event Transient (SET)

sensitivity of the RHBD ARM Cortex™

R4 processor

• Solid curves represent the predicted

cross section from logic gates in the

RESET tree, as identified in the bottom-

up analysis

• Uncorrectable error rate in SRAM test

array of the RHBD ARM Cortex™ R4

processor as a function of SRAM bit

upset rate

• The expected error rate is also shown

22

1E-4

1E-3

1E-2

1E-1

1E+0

1E+1

1E+2

1E-6 1E-5 1E-4 1E-3 1E-2

SR

AM

UE

Rate

(E

rro

r/s)

SRAM Bit Upset Rate (upset/bit-s)

SN29 SN33 SN34 Expected

Validated our approach of predicting

microprocessor sensitivity based on

testing dedicated test structures in

the same design environment


Functional Test Results – Recoverable Errors (SEFI)

• All RHBD Single-Core Tilera processor test

routines produced similar Recoverable Error

(SEFI) cross sections

• Predicted Recoverable Error Rate was within

35% of the rate calculated from measured

results

• Number of Recoverable Errors increased with

frequency as predicted

• Combined errors from logic SETs, clock tree SETs and

RESET tree SETs

• Errors from logic SETs dominated rate

23

Predicted Error Rate

(errors/processor-day)

Measured Error Rate

(errors/processor-day)

Add Hazard1 Hazard5

Recoverable

Errors 4.8E-05 3.2E-05 5.8E-05 5.7E-05

Recoverable Error Cross-Section


RHBD90 Library

• Boeing has distributed the library to several

government agencies and licensed it to several

companies

• Aeroflex Colorado Springs is working to productize

and qualify the RHBD90 ASIC design flow and library

to QML V

24


25

Conclusions

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RHBD on leading-edge commercial device

technologies provides needed performance and

integration density with assured access

Robust RHBD ASIC design environment in place at

Trusted Design Center

90nm Rad Hard by Design ASIC capability has been

demonstrated in multi-million gate SoCs

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Documents

90nm RHBD ASIC Design Capability - NASA · 1 90nm RHBD ASIC Design Capability Tony Amort, Warren Snapp, John Evans, Jeremy Popp, Manuel Cabanas-Holmen, Ethan Cannon This work was