89s52

89S52 Pin diagram

Important Pins (IO Ports)

One of the most useful features = 4 I/O ports (P0 - P3)• Port 0 :-P0 = (P0.0 - P0.7)

– 8-bit R/W - General Purpose I/O– low byte address and data bus for external memory

• Port 1 :- P1= (P1.0 - P1.7)– Only 8-bit R/W - General Purpose I/O

• Port 2 :- P2 = (P2.0 - P2.7)– 8-bit R/W - General Purpose I/O– high byte address for external memory

• Port 3:- P3 = (P3.0 - P3.7)– General Purpose I/O– Timers(T0,T1) – ext. int (INT0, INT1) – Serial (TXD, RXD)- RD,WR

Each port can be used as input or output (bi-direction)

Port 3 Alternate Functions

Hardware Structure of I/O Pin

D Q

Clk Q

Vcc

InternalPull-Up

Read latch

Read pin

Write to latch

Internal CPU bus

M1

P1.X pinP1.X

B1

B2

Hardware Structure of I/O Pin• Each pin of I/O ports

– Internally connected to CPU bus– A D latch store the value of this pin

• Write to latch ＝ 1 ： write data into the D latch

– 2 Tri-state buffer ：• B1: controlled by “Read pin”

– Read pin ＝ 1 ： really read the data present at the pin• B2: controlled by “Read latch”

– Read latch ＝ 1 ： read value from internal latch

– A transistor M1 gate• Gate=0: open• Gate=1: close

Writing “1” to Output Pin P1.X

D Q

Clk Q

Vcc

InternalPull-Up

Read latch

Read pin

Write to latch

Internal CPU bus

M1

P1.X pinP1.X

2. output pin is Vcc1. write a 1 to the pin

1

0 output 1

B1

B2

Writing “0” to Output Pin P1.X

D Q

Clk Q

Vcc

InternalPull-Up

Read latch

Read pin

Write to latch

Internal CPU bus

M1

P1.X pinP1.X

2. output pin is ground1. write a 0 to the pin

0

1 output 0

B1

B2

Reading “High” at Input Pin

D Q

Clk Q

Vcc

InternalPull-Up

Read latch

Read pin

Write to latch

Internal CPU bus

M1

P1.X pin

P1.X

2. MOV A,P1

external pin=High1. write a 1 to the pin

2. MOV P1,#0FFH

1

0

3. Read pin=1 Read latch=0

1

B1

B2

Reading “Low” at Input Pin

D Q

Clk Q

Vcc

InternalPull-Up

Read latch

Read pin

Write to latch

Internal CPU bus

M1

P1.X pin

P1.X

8051 IC

2. MOV A,P1

external pin=Low1. write a 1 to the pin

MOV P1,#0FFH

1

0

3. Read pin=1 Read latch=0

0

B1

B2

Important Pins • PSEN’ (out): Program Store Enable

– Read for External Code Memory (active low)

• ALE (out): Address Latch Enable

– to latch address outputs at Port0 and Port2

• EA’ (in): External Access Enable

– to access external program memory 0 to 4K (active low)

• RXD,TXD: UART pins for serial I/O on Port 3

• Vcc （ pin 40 ） : +5V (3~5V for 89LV51)

• GND （ pin 20 ） : ground

• XTAL1 , XTAL2 （ pins 19,18 ）

• RST （ pin 9 ）： reset (active high)

Types of Memory

ExternalDATA

Memory(up to 64KB)

RAM

ExternalCODE

Memory(up to 64KB)

ROM

8051 Chip

0000h

FFFFh

FFFFh

Internal RAM

SFRs

Internal code Memory

(EEPROM)0000h

Types of Memory • External Code Memory (64k)• External RAM Data Memory (64k)• Internal Code Memory

– 4k,8k,12k,20k– ROM, EPROM, EEPROM

• Internal RAM– First 128 bytes:

00h to 1Fh Register Banks20h to 2Fh Bit Addressable RAM

30 to 7Fh General Purpose RAM– Next 128 bytes:

80h to FFh Special Function Registers

Memory Arrays• RAM (Volatile)

– Read from and write to RAM– Used for Data and Program Storage

• ROM (Non volatile)– Only read from ROM– Used for Program Storage only

• Also store “Constant” data.– Special program stored in ROM

• “Boot” Program or “Loader” Program– This is the program that is executed when the microcontroller is

“reset”

Memory Arrays• Two major types

– Volatile• Data are lost when power is removed• E.g.

– SRAM – Static Random Access Memory– DRAM – Dynamic Random Access Memory

• Generically referred to as RAM (Random Access Memory)

– Although non-volatile RAM exists as well– Non-Volatile

• Data are retained when power is removed• E.g.

– EEPROM – Electrically Erasable Programmable Read Only Memory

– EPROM - Erasable Read Only Memory• Generically referred to as ROM (Read Only Memory)

External Memory Access• /EA （ pin 31 ）： external access

– /EA=‘0’ indicates that code is stored externally.– /PSEN ＆ ALE are used for external ROM.– For 8051 internal code, /EA pin is connected to Vcc.– “/” means active low.

• /PSEN （ pin 29 ）： program store enable– Output- connected to OE of ROM.– Read signal – fetch from ROM

• ALE （ pin 30 ） : address latch enable– It is an output pin and is active high– 8051 port 0 provides both address and data– The ALE pin is used for de-multiplexing the

address and data by connecting to the G pin of the 74LS373 latch.

Address Multiplexing for External Memory (code)

Accessing External Data RAM

On-Chip Memory Internal RAM

General Purpose Register

0706050403020100

R7R6R5R4R3R2R1R0

0F

08

17

10

1F

18

Bank 3

Bank 2

Bank 1

Bank 0

4 Register BanksEach bank has R0-R7Selectable by PSW.2,3

Bit Addressable Memory20h – 2Fh (16 locations 8-bits = 128 bits)

7F 78

1A

10

0F 08

07 06 05 04 03 02 01 00

27

26

25

24

23

22

21

20

2F

2E

2D

2C

2B

2A

29

28

Special Function Registers

DATA registers

CONTROL registersTimersSerial portsInterrupt systemAnalog to Digital converterDigital to Analog converterEtc.

Addresses 80h – FFh

Direct Addressing used to access SFRs

List of SFRs of 89s52

89S52 chip

• 8K bytes of Flash (ROM)• 256 bytes of RAM• 32 I/O lines (4 ports -8bits per port)• Three 16-bit timer/counters• Full duplex serial port

Machine cycleMachine Cycle Freq.=1/12 XTAL

• Find the machine cycle for(a) XTAL = 11.0592 MHz (for 89s52)

(b) XTAL = 16 MHz.

• Solution:(a) 11.0592 MHz / 12 = 921.6 kHz; machine cycle = 1 / 921.6 kHz = 1.085 s

(b) 16 MHz / 12 = 1.333 MHz; machine cycle = 1 / 1.333 MHz = 0.75 s

8051 instruction cycle

8051 Clock and Instruction Cycle In 8051, one instruction cycle consists of twelve (12) clock cycles. Instruction cycle is sometimes called as Machine cycle by some authors.

Power-On Reset

EA/VPPX1

X2RST

Vcc

10 uF

10 K

30 pF

9

31

at least 2 machine cycles

Registers Reset Value

0000DPTR07SP00PSW00B00ACC

0000PCReset ValueRegister

RAM are all zero and all ports are FF

Timer

TMOD SFR

TCON SFR