89s521

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89s52

89S52 Pin diagram

Important Pins (IO Ports)One of the most useful features = 4 I/O ports (P0 - P3) Port 0 :-P0 = (P0.0 - P0.7) 8-bit R/W - General Purpose I/O low byte address and data bus for external memory Port 1 :- P1= (P1.0 - P1.7) Only 8-bit R/W - General Purpose I/O Port 2 :- P2 = (P2.0 - P2.7) 8-bit R/W - General Purpose I/O high byte address for external memory Port 3:- P3 = (P3.0 - P3.7) General Purpose I/O Timers(T0,T1) ext. int (INT0, INT1) Serial (TXD, RXD)- RD,WR

Each port can be used as input or output (bi-direction)

Port 3 Alternate Functions

Hardware Structure of I/O PinRead latchVcc Internal Pull-Up Internal CPU bus Write to latchD Q

B2

P1.XClk Q

P1.X pin M1

B1 Read pin

Hardware Structure of I/O Pin Each pin of I/O ports Internally connected to CPU bus A D latch store the value of this pin Write to latch1write data into the D latch

2 Tri-state buffer B1: controlled by Read pin Read pin1really read the data present at the pin

B2: controlled by Read latch Read latch1read value from internal latch

A transistor M1 gate Gate=0: open Gate=1: close

Writing 1 to Output Pin P1.X

Read latch B2

Vcc Internal Pull-Up

1. write a 1 to the pinInternal CPU bus Write to latchD Q

2. output pin is VccP1.X pin

1 0M1

P1.XClk Q

output 1

B1 Read pin

Writing 0 to Output Pin P1.X

Read latch B2

Vcc Internal Pull-Up

1. write a 0 to the pinInternal CPU bus Write to latchD Q

2. output pin is groundP1.X pin

0 1M1

P1.XClk Q

output 0

B1 Read pin

Reading High at Input PinRead latch Vcc

1. 2.

write a 1 to the pin MOV P1,#0FFH

B2

Internal Pull-Up

2. MOV A,P1 external pin=High P1.X pin

Internal CPU bus

D

QP1.X 1 M1 1

ClkWrite to latch

Q0

B1 Read pin 3. Read pin=1 Read latch=0

Reading Low at Input PinRead latch 1. write a 1 to the pin MOV P1,#0FFH Internal CPU bus B2 Vcc 2. MOV A,P1

Internal Pull-Up D QP1.X 1 0

external pin=Low

P1.X pin

Write to latch

Clk

Q

0

M1

B1 Read pin 3. Read pin=1 Read latch=0 8051 IC

Important Pins PSEN (out): Program Store Enable

Read for External Code Memory (active low)

ALE (out): Address Latch Enable to latch address outputs at Port0 and Port2

EA (in): External Access Enable to access external program memory 0 to 4K (active low)

RXD,TXD: UART pins for serial I/O on Port 3 Vccpin 40: +5V (3~5V for 89LV51) GNDpin 20: ground XTAL1 , XTAL2pins 19,18 RSTpin 9reset (active high)

Types of MemoryFFFFh

ExternalDATA

8051 ChipInternal RAM

Memory (up to 64KB)RAM0000h

SFRsInternal code Memory(EEPROM)

FFFFh

ExternalCODE

Memory (up to 64KB)0000h

ROM

Types of Memory External Code Memory (64k) External RAM Data Memory (64k) Internal Code Memory 4k,8k,12k,20k ROM, EPROM, EEPROM Internal RAM First 128 bytes: 00h to 1Fh Register Banks 20h to 2Fh Bit Addressable RAM 30 to 7Fh General Purpose RAM Next 128 bytes: 80h to FFh Special Function Registers

Memory Arrays RAM (Volatile) Read from and write to RAM Used for Data and Program Storage ROM (Non volatile) Only read from ROM Used for Program Storage only Also store Constant data.

Special program stored in ROM Boot Program or Loader Program This is the program that is executed when the microcontroller is reset

Memory Arrays Two major types Volatile Data are lost when power is removed E.g. SRAM Static Random Access Memory DRAM Dynamic Random Access Memory Generically referred to as RAM (Random Access Memory) Although non-volatile RAM exists as well Non-Volatile Data are retained when power is removed E.g. EEPROM Electrically Erasable Programmable Read Only Memory EPROM - Erasable Read Only Memory Generically referred to as ROM (Read Only Memory)

External Memory Access /EApin 31external access /EA=0 indicates that code is stored externally. /PSEN ALE are used for external ROM. For 8051 internal code, /EA pin is connected to Vcc. / means active low.

/PSENpin 29program store enable Output- connected to OE of ROM. Read signal fetch from ROM

ALEpin 30: address latch enable It is an output pin and is active high 8051 port 0 provides both address and data

The ALE pin is used for de-multiplexing the address and data by connecting to the G pin of the 74LS373 latch.

Address Multiplexing for External Memory (code)

Accessing External Data RAM

On-Chip Memory Internal RAM

General Purpose Register1F

Bank 318 17

4 Register Banks Each bank has R0-R7 Selectable by PSW.2,3

Bank 210 0F

Bank 108 07 06 05 04 03 02 01 00 R7 R6 R5 R4 R3 R2 R1 R0

Bank 0

Bit Addressable Memory2F 2E 2D 7F 78

20h 2Fh (16 locations 8-bits = 128 bits)

2C2B 2A 29 28 27 26 25 24 23 22 21 20 0F 07 06 05 04 03 02 01 1A 10 08 00

Special Function RegistersDATA registers CONTROL registers Timers Serial ports Interrupt system Analog to Digital converter Digital to Analog converter Etc.

Addresses 80h FFhDirect Addressing used to access SFRs

List of SFRs of 89s52

89S52 chip 8K bytes of Flash (ROM) 256 bytes of RAM 32 I/O lines (4 ports -8bits per port) Three 16-bit timer/counters Full duplex serial port

Machine cycleMachine Cycle Freq.=1/12 XTAL Find the machine cycle for(a) XTAL = 11.0592 MHz (for 89s52)(b) XTAL = 16 MHz.

Solution:(a) 11.0592 MHz / 12 = 921.6 kHz; machine cycle = 1 / 921.6 kHz = 1.085 s(b) 16 MHz / 12 = 1.333 MHz; machine cycle = 1 / 1.333 MHz = 0.75 s

8051 instruction cycle

8051 Clock and Instruction Cycle In 8051, one instruction cycle consists of twelve (12) clock cycles. Instruction cycle is sometimes called as Machine cycle by some authors.

Power-On ResetVcc

31 10 uF 30 pF

EA/VPP X1

X2 RST 910 K

at least 2 machine cycles

Registers Reset ValueRegister PC ACC B PSW SP DPTR Reset Value 0000 00 00 00 07 0000

RAM are all zero and all ports are FF

Timer

TMOD SFR

TCON SFR