Upload
joan-bridges
View
214
Download
0
Embed Size (px)
Citation preview
8/9/2000 T.Matsumoto
RICH Front End
RICH FEE OverviewPMT to FEE signal connectionTrigger TileSummation of Current RICH LVL-1 Trigger Module1,2What is going to be built Connection of RICH FEE with MuID ROCSchedule
T.Matsumoto, CNSAug 9, 2000
8/9/2000 T.Matsumoto
RICH FEE Overview
Have you seen this in IR? Components 1 controller Module (center) 10 AMU/ADC Modules 2 Trigger Modules 2 Readout Modules
Input and Output / crate 640 PMT signal input 4 G-LINK output (2 initially) to DCM 2 G-LINK output for LVL-1Trigger
8/9/2000 T.Matsumoto
PMT to FEE signal connection
Figure shows an arm (2 side) of RICH PMT array 2560 PMT
640 PMT signals / crate8 RICH FEE crate is used to read out total 5120 PMT signals There are 2 arms !
RICH FEE Crates 16 PMT (Z)
80PM
T (p
hi)
PMT array
8/9/2000 T.Matsumoto
Trigger Tile
80 PMT (phi)5 PMT
4 PMT TriggerTile
…..preamps
These 16 Trigger Tiles are processed on aSame LVL-1 Trigger Module.
……16 PMT (z)
8/9/2000 T.Matsumoto
Summation of current
5 AMU/ADC Modules
•A RICH Chip on each AMU/ADC Module makes 2 pairs of 4PMT current sum.•Output of RICH Chip are summed up on the Back Plane, again .
Back Plane
RICH Chip
Itotal = i1+i2+i3+i4+i5
i1 i2 i3 i4 i5
4x5 PMT sum4PMT sum
8/9/2000 T.Matsumoto
RICH LVL-1 Trigger Module 1
There is working prototype Functions Current to voltage
conversion AD conversion
(BC =9.6 MHz; 3.5 BC latency)
Compare the signals with threshold in each clock
8/9/2000 T.Matsumoto
RICH LVL-1 Trigger Module 2
Configurations Input : 16 channel
/module 4x5 PMT current sum /
channel Comparison with
threshold Output : 1 G-LINK /module
(16 bits)
Total 256 bits of trigger information
8/9/2000 T.Matsumoto
What is going to be built ?
Final version of RICH LVL-1 Trigger Module We already have working prototype
G-LINK Receiver Board Design, test prototype Production of Final version
8/9/2000 T.Matsumoto
Connection of RICH LVL-1 Module and MuID ROC
Develop special G-LINK receiver board 4 G-LINK receiver deve
loped at BNL Connect with MuID ROC
using flat cable behind back plane
GND separation
8/9/2000 T.Matsumoto
ScheduleRICH LVL-1 Module(Final) by T.Matsumoto
Receiver board(prototype) by M.Tamai
Aug 2000
Sep
Oct
Nov
Dec
Jan 2001
Feb
Mar
Insall
DesignProduction
Test
Design
Production
Test
Receiver board(Final) by M.Tamai
Design
Production
Test
Insall
8/9/2000 T.Matsumoto
Some plot from prototype test
FADC output as a function of constant input current Typical pulse height distribution 5MHz rectangular curren
t pulse 10 MHz sampling Base line 2.8 mA Height 4.5 mA
8/9/2000 T.Matsumoto
Summary
There is already working prototype
We will make…. Final version of RICH LVL-1 Trigger Module Prototype and final version of G-LINK receiver
board
All these work will be done by next March