8282,8286,8284

8282 Latch, 8286 Transceiver, 8284 Clock Generator8288 Bus Controller

BTech-Comp Trim IV

Faculty: Prof. Sonia Relan

8282 Latch

12/08/10 Prof. Sonia Relan

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8282 Latch

Address/data bus on 8086/88 is multiplexed i.e. same bus is shared for address and data, this reduces no. of pins required.

The process of forming separate address and data bus from multiplexed bus is called demultiplexing. Thus demultiplexing is extracting separate information from the same bus.

Intel 8282 is a latch, which can be used to demultiplex address/data bus.

The 8282 is 8-bit latch, hence total three 8282 latches are required for 20-bit address.

As shown in fig. ALE (Address latch enable signal) of 8086 is connected to STB (Strobe) of 8282 latch.


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8282 Latch fig.


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8282 Latch contd.

When ALE goes high during earlier part of bus cycle the latch becomes transparent and Q output follows the input. The input is address bit at that time.

When ALE goes low, at the negative edge of the signal, latch stores the output (address bit) and it will hold this address till next ALE comes.

Thus A0-A15 is separated out from D0-D15 and A-16-A19 is separated out from S3-S6, using three 8282 latches. OE pin of 8282 is grounded to enable latch’s output.

The 8282 latch also provides buffering of address lines which increases output drive capability, but it introduces some time delay, so memory and I/O devices get less time to read or write data.

8286 Transceivers


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8286 Transceivers

If more than 10 unit loads are connected to any bus pin, the uP must be provided with buffers.

The demultiplexed address lines are buffered by 8282 latch. Intel 8286 transceiver provides buffering for data lines of 8086/8088. The 8286 transceiver contains eight receivers and eight drivers, so it

can be used for bidirectional data transfer. Total two 8286 are required for 16 data lines.

As shown in fig. OE pin of 8286 is connected to DEN pin of 8086. when uP is ready for data transfer it asserts DEN low, this will enable 8286 transceiver.

The direction of data transfer is decided by T pin of 8286, which is connected to DT/R pin of 8086. During the transmission of data, this pin is asserted high by 8086 and data is transferred from uP through transceiver to memory or I/O device.

When T pin of 8086 is driven high, A0-A7 lines act as input lines and B0-B7 lines act as output lines.


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Fig. 8286 Transceivers


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8286 Transceivers contd.

During reception of data DT/R pin is asserted low and data is transferred from memory or I/O device through transceiver to uP. When T pin is driven low, B0-B7 lines act as input lines and A0-A7 lines act as output lines.

This mechanism allows bidirectional data transfer through 8286 transceiver.

Intel 8287 transceiver functions in similar way as 8286 transceiver, but it inverts the input.

8284 Clock Generator


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8284 Clock Generator

The 8086 uP requires clock with following specifications.

1. Rise and Fall Time <10ns2. Logic 0: -0.5V to +0.6V3. Logic 1: 3.9V to 5.0V4. Duty cycle;33% Intel 8284 clock generator provides clock pulse train

with above specifications Other than this it also synchronizes READY signal

(which indicates peripheral is ready to complete data transfer) and RESET signal (which is used to initialize the system) with clock pulses.


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Pin Layout of 8284


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Generating the 8086 system clock and reset signals As shown in the block diagram clock source can be

crystal oscillator or external frequency input.1. If crystal oscillator is used as clock source, it should be

connected to X1 and X2. and F/C pin should be grounded.

2. If external frequency input is used as clock source then, it should be connected to EFI pin and F/C pin should be connected to +5V(Vcc).

The clock coming from any one of this source is given to divide by 3 counter through logic gate circuit. It provides 33% duty cycle


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Fig. Generating the 8086 system clock and reset signals


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8284 Clock Generator contd. As shown in dig. 8284 clock generator provides 3 clock signals as

output.1. CLK: it is output of divide by 3 counter, which is a clock pulse train

wit frequency equal to one third of crystal frequency and 33% duty cycle. This signal is passed through buffer.

2. PCLK: It is output of divide by 2 counter, which is a clock pulse train with frequency equal to one half of CLK frequency 50% duty cycle or on other words it has frequency equal to one sixth(1/6) of crystal frequency. This can be used to provide clock signal to peripheral equipment in the system

3. OSC: This oscillator output is TTL level signal with frequency equal to crystal frequency. This signal can be used to provide clock frequency to EFI pin of other 8284 clock Generators in multiprocessor systems.

The CSYNC (Clock Synchronization) input allows the system clock to be synchronized to an external event. It can also be used to synchronize more than one 8284s to provide clock signal that are in phase for multiprocessor systems. This pin must be grounded to set all the counters.


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8284 Clock Generator contd.

RDY1 and RDY2 two ready inputs are available, two peripherals can be connected to these pins.

AEN1 and AEN2 pins are used to enable RDY1 and RDY2 respectively. If these address enable pins are activated, then only ready signal will be of significance.

The RESET signal must be synchronized with clock pulse before it is given to 8086 RESET pin

8288 Bus Controller


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8288 Bus Controller

Used to provide the signals when the microprocessor 8086 operates in maximum mode.

Input signals:1. Status inputs:

S0, S1, S2 :connected to status output pins of 8086 mp.decoded to generate control signals for the system

2. Control Inputs:CLK: clock input provides internal timing and it must be

connected to CLK output pin of 8284 clock generator.


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Operating modes CEN, IOB and AEN: These three signals decides the operating mode as shown in table

Command Enable

I/O Bus mode IOB

Address Enable AEN

Operating mode

1 1 x I/O us mode, all control lines enabled

1 0 1 System bus mode, all control signals are disabled, Bus is busy

1 0 0 System bus mode, all control signals are enabled. Bus is free

0 x x All command outputs DEN and PDEN are disabled.


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8288 Bus Controller: Pin Layout


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Internal block diagram: 8288 bus controller


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Output signalsMultibus command signals MRDC: Memory Read control pin. It instructs memory to put data

form addressed memory location on the data bus. MWTC: Memory Write control pin. It instructs memory to accept

data form data bus and put the data in addressed memory location.

IOWC: I/O Write control pin. It instructs I/O to accept data from data bus and put the data in addressed I/O port.

IORC:I/O Read control pin. It instructs I/O to put data from addressed I/O port on the data bus.

AMWC: Advanced memory Write command. This output is enable one clock pulse earlier than normal write commands.

AIOWC: Advanced I/O Write command. This output is enable one clock pulse earlier than normal write commands.

INTA: interrupt acknowledge output. The output is generated in from of two negative pulses, in response to interrupt applied to the INTR pin.


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Output signals2. Address latch, Data Transceivers' and Interrupt control signals DEN DT/R ALE MCE/ PDEN: Master cascade enable/Peripheral

Data enable output signal. Has two different functions which depends on IOB pin 1st: if IOB pin is grounded, it functions as MCE pin to

select cascade operation for interrupt controller. 2nd: if IOB is connected to +5 V, it functions as PDEN to

enable I/O bus data transceivers. PDEN is identical to DEN, except that it is active only

during execution of I/O instructions.

Documents

8282,8286,8284