8282,8286,8284

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8282 Latch, 8286 Transceiver, 8284 Clock Generator 8288 Bus ControllerBTech-Comp Trim IV Faculty: Prof. Sonia Relan

8282 Latch

8282 Latch Address/data

bus on 8086/88 is multiplexed i.e. same bus is shared for address and data, this reduces no. of pins required. The process of forming separate address and data bus from multiplexed bus is called demultiplexing. Thus demultiplexing is extracting separate information from the same bus. Intel 8282 is a latch, which can be used to demultiplex address/data bus. The 8282 is 8-bit latch, hence total three 8282 latches are required for 20-bit address. As shown in fig. ALE (Address latch enable signal) of 8086 is connected to STB (Strobe) of 8282 latch.3

12/08/10

Prof. Sonia Relan

8282 Latch fig.

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8282 Latch contd.

When ALE goes high during earlier part of bus cycle the latch becomes transparent and Q output follows the input. The input is address bit at that time. When ALE goes low, at the negative edge of the signal, latch stores the output (address bit) and it will hold this address till next ALE comes. Thus A0-A15 is separated out from D0-D15 and A-16-A19 is separated out from S3-S6, using three 8282 latches. OE pin of 8282 is grounded to enable latchs output. The 8282 latch also provides buffering of address lines which increases output drive capability, but it introduces some time delay, so memory and I/O devices get less time to read or write data.5

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Prof. Sonia Relan

8286 Transceivers

8286 Transceivers

If more than 10 unit loads are connected to any bus pin, the uP must be provided with buffers. The demultiplexed address lines are buffered by 8282 latch. Intel 8286 transceiver provides buffering for data lines of 8086/8088. The 8286 transceiver contains eight receivers and eight drivers, so it can be used for bidirectional data transfer. Total two 8286 are required for 16 data lines. As shown in fig. OE pin of 8286 is connected to DEN pin of 8086. when uP is ready for data transfer it asserts DEN low, this will enable 8286 transceiver. The direction of data transfer is decided by T pin of 8286, which is connected to DT/R pin of 8086. During the transmission of data, this pin is asserted high by 8086 and data is transferred from uP through transceiver to memory or I/O device. When T pin of 8086 is driven high, A0-A7 lines act as input lines and B0-B7 lines act as output lines.7

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Prof. Sonia Relan

Fig. 8286 Transceivers

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8286 Transceivers contd. During

reception of data DT/R pin is asserted low and data is transferred from memory or I/O device through transceiver to uP. When T pin is driven low, B0-B7 lines act as input lines and A0A7 lines act as output lines. This mechanism allows bidirectional data transfer through 8286 transceiver. Intel 8287 transceiver functions in similar way as 8286 transceiver, but it inverts the input.9

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Prof. Sonia Relan

8284 Clock Generator

8284 Clock Generator 1. 2. 3. 4.

The 8086 uP requires clock with following specifications. Rise and Fall Time