Slide 1
8086 MicroprocessorIts a 40 pin IC (Integrated circuit)It has 20
address lines, so it can address 1 Mb memory locations8086 has 16
data line which is multiplexed with address line (AD0 to AD15)So it
is 16 bit MPIt can be operated in two modes1. Maximum mode2.
Minimum mode
8086 INTERNAL ARCHITECTURE
Divided into two units1 BIU - Bus interface unit It fetch the
instruction and data from the memory.2 EU -Execution unit It get
the instruction and data from BIU and executes it.1024 Byte = 1
kbyte1024 Kbyte= 1 MbyteEach segment contain 64 KyteSo 1 Mbyte can
be split into 16 segments
Bus Interfacing Unit(BIU)It supply the address to perform read
and write operation with the memoryIt fetch the instruction and
data from the memory and store it ,in the instruction queueFrom the
instruction queue , it will be supplied to the Execution UnitBIU
contain four segment register each 16 bit width 1. Code segment
Register, Data segment Register, Stack segment Register Extra
Segment Register and One Instruction pointerWith in 1 Mbyte of
memory MP can use four segments at a time.Size of each segment is
64 KbyteThe Segment register contain the starting address of the
respective segments
MEMORY ORGANIZATIONBy using 20 address line 8086 can access 1
Mbyte memory8086 can access four segment at a time 1 Code segment
contain program2 Data segment contain data3 Stack segment contain
stack data 4 Extra segment contain intermediate resultEach Segment
have 64 Kbyte locationsBase address is given by respective segment
register200002FFFF400004FFFF600006FFFF800008FFFF00000Code SegData
SegStack SegExtra SegFFFFF
5Address generationMP need to generate 20 bit address to access
memory if code segment = 2000And Instruction Pointer = 0050Then 20
bit address is generated asCode seg X 16 (H) = 20000 - - Base
addressIP = 0050 - - Effective address (Base add + Eff add) 20050 -
- Physical addressInstruction is fetched from the location
20050
Total 1 Mbyte is divided into two blocks Odd block and Even
block Size of Even block is 512 KbytesIt contain the locations with
even address onlyIt is enabled by the address line A0 Data bus D0
to D7 is connected with even bankSize of Odd block is 512 KbytesIt
contain the locations with odd address onlyIt is enabled by
signalData bus D8 to D15 is connected with odd bankAddress line A1
to A19 is connected with both the bankCSCSBHEA0A1---A19First
locFirst locSecond locSecond locD15 D8D0 D7ODD Bank512 KbEven
Bank512 Kb00000(H)00002(H)00001(H)00003(H)To read 8 bit data any
one of the bank is selected by BHE or A0 line and the address line
A1 to A15 select the any one location in the selected memory bankIf
the even bank is selected data is read/ write through D0 to D7, If
the odd bank is selected data is read/ write through D8 to D15, Due
to this arrangement 16 bit data can by read or write
simultaneouslyTo read 16 bit data both the bank is selected
simultaneously and data is read/write through D0 to
D15CSCSA0A1---A19Second locSecond locD15 D8ODD Bank512 KbEven
Bank512 KbBHED0 D7First locFirst
loc00001(H)00003(H)00000(H)00002(H)CSCSBHEA0A1---A1900000- 0000
0000 0000 0000 0000 BHE=1 ,A0=0 , first loc Even bank 00001- 0000
0000 0000 0000 0001 BHE=0,A0=1 , first loc Odd bank00002- 0000 0000
0000 0000 0010 BHE=1 ,A0=0 ,Second loc - Even00003 - 0000 0000 0000
0000 0011 BHE=0 ,A0=1, Second loc- oddA0A19First locFirst locSecond
locSecond locD15 D8D0 D7Upper Bank(ODD Bank)512 KbLower Bank(Even
Bank)512 Kb00000(H)00002(H)00001(H)00003(H)The Instruction Queue:
The BIU can fetches and store up to 6 instruction bytes. The BIU
stores these bytes in first-in-first-out register set called a
queue. When the EU is ready for its next instruction it simply
reads the instruction byte(s) from the queue in the BIU. This is
much faster then fetching single instruction and executing, then
fetching the next instruction Fetching the next instruction while
the current instruction executes is called pipelining
Execution UnitIt get the instruction and data from bus
interfacing unit(BIU) and executes it.It
containsRegistersArithmetic and Logic unitControl
Unit1.Registers(I)General Purpose registers
AX - the AccumulatorBX - the Base RegisterCX - the Count
RegisterDX - the Data Register Normally used for storing temporary
results Each of the registers is 16 bits wide (AX, BX, CX, DX)Can
be accessed as either 16 ( as AX,BX,CX,DX)or 8 bits (as
AL,AH,BL,BH,CL,CH,DL,DH)Each register have some special
purposeAXAccumulatorMust be used in Multiplication and Division
operationsMust be used in Input and Output operation
BXCalled as Base registerUsed as address registerCXCalled as
Counter registerUsed as a loop counterUsed in shift and rotate
operationDXCalled as Data registerUsed in Multiplication and
DivisionUsed in input and output operation
(II) Pointer and Index registerSP Stack PointerBP Base PointerSI
Source IndexDI Destination Index All are 16 bit registers cant be
used as 8 bit registersSP Stack pointer- Supply the address to
access the stack memoryBP base pointer- supply the address to
access the memorySI Source Index Used with the string instructionDI
destination Index- Used with String instruction
CarryParityAuxiliary CarryZeroOverflowDirectionInterrupt
enableTrapSign6 are conditional flags3 are control flagFlag
RegisterIt is 16 bit register But only 9 bits are used Types1.
Conditional Flag2. Control FlagConditional fagIt reflect the
condition of result of the previous operationCarry flag It will be
set when the carry is generated in the previous operation like
addition While performing Subtraction it will act as the borrow
flagParity FlagIt will set when the result contain even no of
onesAuxiliary Carry FlagIt will be set when the carry is generated
from the bit D3 to D4 ,while performing the arithmetic
operationZero FlagIt will be set when the result of the previous
operation is zeroSign FlagIt will be copy of the MSB of the
resultOver Flow flagIt will be set when the carry is generated from
Bit D14 to D15It is useful when the signed number system is
usedControl flagControl flags are set or reset deliberately to
control the operations of the execution unit.Trap Flag (TF): It is
used for single step control.When it is set , the user can execute
one instruction of a program at a time for debugging.
Interrupt Flag (IF): It is an interrupt enable/disable flag. If
it is set, the maskable interrupt of 8086 is enabled and if it is
reset, the interrupt is disabled. It can be set by executing
instruction STI and can be cleared by executing CLI
instruction.
Direction Flag (DF): It is used in string operation. If it is
set, string bytes are accessed from higher memory address to lower
memory address. When it is reset, the string bytes are accessed
from lower memory address to higher memory address.Control Unit ,
Arithmetic and Logical UnitThe execution unit (EU) of the 8086
tells the BIU from where to fetch instructions or Data.It decodes
instructions and executes instruction. A decoder in the EU
translates instructions into a series of actions which is carried
by EUThe EU is has a 16-bit ALU which can add, subtract, AND, OR,
XOR, increment, decrement, complement or shift binary numbers. The
EU contains control circuitry which directs internal
operations.Some Important Companion chips1. Clock generator 82842.
Bidirectional Bus Transceiver 8286/82873. 8 Bit Input/output Port
8282/82834. Bus controller 8288Clock generator 8284Functions of the
clock generator
1. It generates the clock and supply to 80862. It generate the
RESET signal, synchronized with clock signal, to reset 80863. It
generate READ signal used for wait state logic4. Pin
configuration
- (Input) External crystal is connected between this pinCrystal
frequency must be three times greater than required clock
frequencyEF1- (Input) Alternate clock inputF/ - (Input) Clock
source selectionIf it is high clock at EF1 is takenIf it is low
clock from crystal connected at X1 and X2 is takenCLK -(Out put) It
supply the clock to MPIt directly connected to 8086 MPOSC - (out
Put) Oscillator output running at crystal or EF1 frequencyPCLK
-(O/P) It is TTL level signal output for support circuitsCSYNC-
(I/P) it is used for clock synchronization When it is high it stops
the clock supplyWhen it become low it restart the clock supply
MINIMUM MODE SIGNALSALEAD0-AD15A16-A19BHEA0A1-A19LATCH8286
TRANSCEIVEROdd Bank 512 KbEven Bank512 KbCSCSDT/
RDEN8086D8-D15D0-D7WRWRWRRDRDRDMIN/MXVCCMemory Interface in minimum
mode RDY1 READY PCLK ALE 8086 8282STB STB8282 STB 8282 8284X1
X28286T8286TRESETCLKREADYRESET When the pin no 33 (MN/MX) is
connected to VCC 8086 will work in Minimum mode Address/data bus:
Address bus is 20 bit long (A0-A19), so 1 Mb memory can be
connectedAddress line A0-A15 are used to connect I/O devicesIt has
16 data lines (D0- D15)These data lines are multiplexed with the
address lines A0-A15Address lines A16-A19 are multiplexed with
status lines S3-S6Status signal8086 generate four status signalsS3
and S4 indicate which of the segment is used
S5 shows the status of internal interrupt enable flagS6=0
alwaysS3S4Segment-Register00ES01SS10CS11DS31Control signalsBHE/S7 -
BUS HIGH ENABLE/STATUSBHE signal is multiplexed with Status signal
S7BHE signal is used to enable the Odd address bank S7 become low
in interrupt acknowledgement cycleAddress latch enable (ALE)it is
used to demultiplex the address/data busIt is used to enable the
latch 8282.M/IO (memory/Io) it tells whether a memory or I/O
transfer is talking place.Logic 1 signals a memory operation and
logic 0 signals an I/O operation.
DT/R (data transmit/receive) It signals the direction of data
transfer over the bus. Logic 1 indicates that the bus is in the
transmit mode Logic 0 signals that the bus is in the receive modeIt
is connected with direction selection pin of 8286 WR (write)It
signal the write operation with memory or I/OInterrupt
Signals:(INTR) Interrupt requestUsed by an external device to get
the MP attention Sampled during the last clock of each instruction
A subroutine address is available in interrupt vector table
INTA Interrupt Acknowledgement When the MPU recognizes an
interrupt request, it send acknowledgement (INTA) signal.NMI
-nonmaskable interruptIt is interrupt request line It has highest
priority and cannot be masked by softwareRESET: Used to reset the
MPMP immediately terminate its present activity.This signal is
generated by 8284, when the manual reset switch is closedDMA
Interface Signals:HOLDIt is send by the DMA controller to request
address and data bus control HLDAWhen the MP relive the control of
the busses , it send HLDA signal to DMA controller
TEST: This input is examined by the ``Wait'' instruction. If the
TEST input is LOW execution continues, otherwise the processor
waits in an Idle state.
MAXIMUM MODE SIGNALSIn maximum mode 8086 MP produces signals for
multiprocessor and co-processor environment It produce status
signals S0,S1,S2. By using these status signal, Bus controller
produce all the control signals INTA- Interrupt Acknowledgement
signalIORC- used as I/O Read control signalIOWC, AIOWC- used as I/O
Write control signalMRDC- used as Memory Read control signalMWTC ,
AMWC used as Memory write control signal
The signals generated by bus controller 8288LOCKUsed in
multiprocessor systemUsed to lockout other processor from using
common busThe LOCK signal is activated by the ``LOCK'' prefix
instructionQS0,QS1- Queue statusIt specifies what operation is
performed in Instruction queue
RQ/GT0 RQ/GT1 : Request/ Grant signal Used for DMA accesses Each
signal is bidirectional , Receive the request signal and send the
Acknowledgement signal through the same pin RQ/GT0 have highest
priority
ALE
