Slide 1

EI 502Microprocessors & Microcontrollers

Part 5(16 bit 8086)Debasis Das1Mallabhum Institute of Technology Debasis DasSep-Oct 20111Intel 8086Sep-Oct 2011Mallabhum Institute of Technology Debasis Das2

2FeaturesDirect addressing of 1 MB memory space, 20 bit addressing bus16 bit data bus, Bit/ byte/block operationsMultiplexed busMultiprocessor features3Mallabhum Institute of Technology Debasis DasSep-Oct 20113Features8086 is designed to operate in two modes, Minimum and Maximum.

It can pre-fetch up to 6 instruction bytes from memory and queue them in order to speed up instruction execution.

Address ranges from 00000H to FFFFFH

Memory is byte addressable - Every byte has a separate addressSep-Oct 2011Mallabhum Institute of Technology Debasis Das448086 MicroprocessorBelongs to a popular microprocessor series 8086, 80186, 80286, 80386, 80486, PentiumINTEL launched 8086 in 1978Sep-Oct 20115Mallabhum Institute of Technology Debasis Das58086 Internal Architecture8086 CPU has two parts which operate independently (asynchronously) at the same timeBus Interface UnitExecution UnitCPU functionsFetch

DecodeExecute8086 CPUBus Interface Unit (BIU)Execution Unit(EU)Sep-Oct 20116Mallabhum Institute of Technology Debasis Das68088 MicroprocessorProcessor that drove the first PCIt is a 8 bit processorHandles 8 bit data, hence database is 8 bits.Otherwise most details are same as the 8086Sep-Oct 2011Mallabhum Institute of Technology Debasis Das77BIU & EU FeaturesBoth units operate asynchronously to give the 8086 an overlapping instruction fetch and execution mechanism which is called as Pipelining. This results in efficient use of the system bus and system performance.

BIU contains Instruction queue, Segment registers, Instruction pointer, Address adder.

EU contains Control circuitry, Instruction decoder, ALU, Pointer and Index register, Flag registerSep-Oct 2011Mallabhum Institute of Technology Debasis Das88Bus Interface UnitSends out addresses for memory locationsFetches Instructions from memoryReads/Writes data to memorySends out addresses for I/O portsReads/Writes data to Input / Output portsSep-Oct 20119Mallabhum Institute of Technology Debasis Das9Execution UnitTells BIU (addresses) where to fetch instructions or dataDecodes & Executes instructions

Dividing the work between BIU & EU speeds up processing

Sep-Oct 2011Mallabhum Institute of Technology Debasis Das10108086 Block DiagramSep-Oct 2011Mallabhum Institute of Technology Debasis Das11118086 ArchitectureSep-Oct 2011Mallabhum Institute of Technology Debasis Das12

12Min/Max Pin-out ModesSep-Oct 2011Mallabhum Institute of Technology Debasis Das13

13Logical SignalsSep-Oct 2011Mallabhum Institute of Technology Debasis Das14

148088 DetailsSep-Oct 2011Mallabhum Institute of Technology Debasis Das15

15Min/Max ModesMinimum and Maximum ModesThe minimum mode is selected by applying logic 1 to the MN / MX# input pin. This is a single microprocessor configuration.

The maximum mode is selected by applying logic 0 to the MN / MX# input pin. This is a multi micro processors configuration.Sep-Oct 2011Mallabhum Institute of Technology Debasis Das1616Signal Description-1Sep-Oct 2011Mallabhum Institute of Technology Debasis Das17

17Signal Description-2Sep-Oct 2011Mallabhum Institute of Technology Debasis Das18

18Signal DescriptionMax ModeSep-Oct 2011Mallabhum Institute of Technology Debasis Das19

19Execution UnitMain components areInstruction DecoderControl SystemArithmetic Logic UnitGeneral Purpose RegistersFlag RegisterPointer & Index registersSep-Oct 201120Mallabhum Institute of Technology Debasis Das20Instruction DecoderTranslates instructions fetched from memory into a series of actions which EU carries outControl SystemGenerates timing and control signals to perform the internal operations of the microprocessorArithmetic Logic UnitEU has a 16-bit ALU which can ADD, SUBTRACT, AND, OR, increment, decrement, complement or shift binary numbersSep-Oct 201121Mallabhum Institute of Technology Debasis Das21Memory OrganizationSep-Oct 2011Mallabhum Institute of Technology Debasis Das22

22General Purpose RegistersEU has 8 general purpose registersCan be individually used for storing 8-bit dataAL register is also called AccumulatorTwo registers can be combined to form a 16-bit registerThe valid register pairs are AX, BX, CX, and DXAHALBHBLCHCLDHDLAHALAXBHBLBXCHCLCXDHDLDXSep-Oct 201123Mallabhum Institute of Technology Debasis Das23Flag Register8086 has a 16-bit flag registerContains 9 active flagsThere are two types of flags in 8086Conditional flags six flags, set or reset by EU on the basis of results of some arithmetic operationsControl flags three flags, used to control certain operations of the processorSep-Oct 201124Mallabhum Institute of Technology Debasis Das24UUUUOFDFIFTFSFZFUAFUPFUCFFlag Register1.CFCARRY FLAGConditional Flags(Compatible with 8085, except OF)2.PFPARITY FLAG3.AFAUXILIARY CARRY4.ZFZERO FLAG5.SFSIGN FLAG6.OFOVERFLOW FLAG7.TFTRAP FLAGControl Flags8.IFINTERRUPT FLAG9.DFDIRECTION FLAGSep-Oct 201125Mallabhum Institute of Technology Debasis Das25Bus Interface UnitMain Components areInstruction QueueSegment RegistersInstruction PointerSep-Oct 201126Mallabhum Institute of Technology Debasis Das26Instruction Queue8086 employs overlapped processingWhen EU is busy decoding or executing current instruction, the system bus of 8086 may not be in use.At that time, BIU can use buses to fetch up to six instruction bytes of the instructions next in programBIU stores these pre-fetched bytes in a FIFO register called Instruction QueueWhen EU is ready for its next instruction, it simply reads the instruction from the queue in BIUSep-Oct 201127Mallabhum Institute of Technology Debasis Das27Instruction PipelineEU of 8086 does not have to wait for BIU to fetch next instruction byte from memoryThe presence of a queue in 8086 speeds up the processingFetching the next instruction while the current instruction executes is called Instruction look aheadSep-Oct 201128Mallabhum Institute of Technology Debasis Das28Instruction PipelineSep-Oct 2011Mallabhum Institute of Technology Debasis Das29

29Memory Segmentation8086 has a 20-bit address busSo it can address a maximum of 1MB of memory8086 works with four 64KB segments at a time within this 1MB range (can be overlapped in exactly the same space)These four memory segments are calledCode segmentStack segmentData segmentExtra segmentSep-Oct 201130Mallabhum Institute of Technology Debasis Das30Segment RegistersHolds the upper 16-bits of the starting address for each of the segmentsThe four segment registers areCS (Code Segment register)DS (Data Segment register)SS (Stack Segment register)ES (Extra Segment register)Sep-Oct 201131Mallabhum Institute of Technology Debasis Das31Memory Address GenerationSep-Oct 2011Mallabhum Institute of Technology Debasis Das32

32Code SegmentThat part of memory from where BIU is currently fetching instruction code bytesStack SegmentA section of memory set aside to store addresses and data while a subprogram executes, accommodates stacksData & Extra SegmentsUsed for storing data values to be used in the programSep-Oct 201133Mallabhum Institute of Technology Debasis Das33Reserved MemoryLocationsSep-Oct 2011Mallabhum Institute of Technology Debasis Das34

34Min Mode LogicalPin outSep-Oct 2011Mallabhum Institute of Technology Debasis Das35

35Min ModeInterface-1When the Minimum mode operation is selected, the 8086 provides all control signals needed to implement the memory and I/O interfaceThe minimum mode signal can be divided into the following basic groups: address/data bus, status, control, interrupt and DMA.Address/Data Bus : these lines serve two functions. As an address bus is 20 bits long and consists of signal lines A0 through A19. A19 represents the MSB and A0 LSB. A 20bit address gives the 8086 a 1Mbyte memory address space.Independent I/O address space which 64K bytes in lengthSep-Oct 2011Mallabhum Institute of Technology Debasis Das3636Min ModeInterface-2The 16 data bus lines D0 through D15 are actually multiplexed with address lines A0 through A15 respectively. The bus works as an address bus during first machine cycle and as a data bus during next machine cycles. D15 is the MSB and D0 LSB

When acting as a data bus, they carry read/write data for memory, input/output data for I/O devices, and interrupt type codes from an interrupt controllerSep-Oct 2011Mallabhum Institute of Technology Debasis Das3737Min ModeInterface-3Status signal : The four most significant address lines A19 through A16 are also multiplexed but in this case with status signals S6 through S3. These status bits are output on the bus at the same time that data are transferred over the other bus lines.Bit S4 and S3 together form a 2 bit binary code that identifies which of the 8086 internal segment registers are used to generate the physical address output on the address bus during the current bus cycleCode S4,S3 = 00 identifies a register known as extra segment register as the source of the segment addressSep-Oct 2011Mallabhum Institute of Technology Debasis Das3838Min ModeInterface-4Sep-Oct 2011Mallabhum Institute of Technology Debasis Das39

39Min ModeInterface-5Status line S5 reflects the status of another internal characteristic of the 8086. It is the logic level of the internal enable flag. The last status bit S6 is always at the logic 0 level

Control Signals : The control signals are provided to support the 8086 memory & I/O interfaces. They control functions such as when the bus is to carry a valid address, in which direction data are to be transferred over the bus, when valid write data are on the bus and when to put read data on the system busSep-Oct 2011Mallabhum Institute of Technology Debasis Das4040Min ModeInterface-6ALE is a pulse to logic 1 that signals external circuitry when a valid address word is on the bus. This address must be latched in external circuitry on the 1-to-0 edge of the pulse at ALE.Another control signal that is produced during the bus cycle is BHE bank high enable. Logic 0 on this used as a memory enable signal for the most significant byte half of the data bus D8 through D1. These line also serves a second function, which is as the S7 status lineUsing the M/IO and DT/R lines, the 8086 signals which type of bus cycle is in progress and in which direction data are to be transferred over the bus.Sep-Oct 2011Mallabhum Institute of Technology Debasis Das4141Min ModeInterface-7The logic level of M/IO tells external circuitry whether a memory or I/O transfer is taking place over the bus. Logic 1 at this output signals a memory operation and logic 0 an I/O operation.The direction of data transfer over the bus is signalled by the logic level output at DT/R. When this line is logic 1 during the data transfer part of a bus cycle, the bus is in the transmit mode. Therefore, data are either written intomemory or output to an I/O deviceOn the other hand, logic 0 at DT/R signals that the bus is in the receive mode. This corresponds to reading data from memory or input of data from an input portSep-Oct 2011Mallabhum Institute of Technology Debasis Das4242Min ModeInterface-8The signal read RD and write WR indicates that a read bus cycle or a write bus cycle is in progress. The 8086 switches WR to logic 0 to signal external device that valid write or output data are on the busOn the other hand, RD indicates that the 8086 is performing a read of data of the bus. During read operations, one other control signal is also supplied. This is DEN ( data enable) and it signals external devices when they should put data on the busThere is one other control signal that is involved with the memory and I/O interface. This is the READY signalSep-Oct 2011Mallabhum Institute of Technology Debasis Das4343Min ModeInterface-9READY signal is used to insert wait states into the bus cycle such that it is extended by a number of clock periods. This signal is provided by an external clock generator device and can be supplied by the memory or I/O subsystem to signal the 8086 when they are ready to permit the data transfer to be completed.Interrupt signals : The key interrupt interface signals are interrupt request (INTR) and interrupt acknowledge( INTA)INTR is an input to the 8086 that can be used by an external device to signal that it need to be servicedSep-Oct 2011Mallabhum Institute of Technology Debasis Das4444Min ModeInterface-10Logic 1 at INTR represents an active interrupt request. When an interrupt request has been recognized by the 8086, it indicates this fact to external circuit with pulse to logic 0 at the INTA outputThe TEST input is also related to the external interrupt interface. Execution of a WAIT instruction causes the 8086 to check the logic level at the TEST input If the logic 1 is found, the MPU suspends operation and goes into the idle state. The 8086 no longer executes instructions, instead it repeatedly checks the logic level of the TEST input waiting for its transition back to logic 0Sep-Oct 2011Mallabhum Institute of Technology Debasis Das4545Min ModeInterface-11As TEST switches to 0, execution resume with the next instruction in the program. This feature can be used to synchronize the operation of the 8086 to an event in external hardware.There are two more inputs in the interrupt interface: the non-maskable interrupt NMI and the reset interrupt RESETOn the 0-to-1 transition of NMI control is passed to a non-maskable interrupt service routine. The RESET input is used to provide a hardware reset for the 8086. Switching RESET to logic 0 initializes the internal register of the 8086 and initiates a reset service routineSep-Oct 2011Mallabhum Institute of Technology Debasis Das4646Min ModeInterface-12DMA Interface signals :The direct memory access DMA interface of the 8086 minimum mode consist of the HOLD and HLDA signalsWhen an external device wants to take control of the system bus, it signals to the 8086 by switching HOLD to the logic 1 level. At the completion of the current bus cycle, the 8086 enters the hold state. In the hold state, signal lines AD0 through AD15, A16/S3 through A19/S6, BHE, M/IO, DT/R, RD, WR, DEN and INTR are all in the high Z state. The 8086 signals external device that it is in this state by switching its HLDA output to logic 1 levelSep-Oct 2011Mallabhum Institute of Technology Debasis Das4747Max ModeBlock DiagramSep-Oct 2011Mallabhum Institute of Technology Debasis Das48

48Max ModeInterface-1When the 8086 is set for the maximum-mode configuration, it provides signals for implementing a multiprocessor / coprocessor system environmentBy multiprocessor environment we mean that one microprocessor exists in the system and that each processor is executing its own programUsually in this type of system environment, there are some system resources that are common to all processorsThey are called as global resources. There are also other resources that are assigned to specific processors. These are known as local or private resourcesSep-Oct 2011Mallabhum Institute of Technology Debasis Das4949Max ModeInterface-2In multiple processor situation a second processor is in the system. Both processors do not access the bus at the same timeOne passes the control of the system bus to the other and then may suspend its operationIn the maximum-mode 8086 system, facilities are provided for implementing allocation of global resources and passing bus control to other microprocessor or coprocessor.Sep-Oct 2011Mallabhum Institute of Technology Debasis Das5050Max ModeInterface-28288 Bus Controller Bus Command and Control Signals: 8086 does not directly provide all the signals that are required to control the memory, I/O and interrupt interfacesSpecially the WR, M/IO, DT/R, DEN, ALE and INTA, signals are no longer produced by the 8086. Instead it outputs three status signals S0, S1, S2 prior to the initiation of each bus cycle. This 3- bit bus status code identifies which type of bus cycle is to followS2,S1,S0 are input to the external bus controller device, the bus controller generates the appropriately timed command and control signalsSep-Oct 2011Mallabhum Institute of Technology Debasis Das5151Max ConfigurationUsing 8288 Bus ControllerSep-Oct 2011Mallabhum Institute of Technology Debasis Das52

528288 Pin outSep-Oct 2011Mallabhum Institute of Technology Debasis Das53

53Max ModeInterface-3Sep-Oct 2011Mallabhum Institute of Technology Debasis Das54

54Max ModeInterface-4The 8288 produces one or two of these eight command signals for each bus cycles. For instance, when the 8086 outputs the code S2S1S0 equals 001, it indicates that an I/O read cycle is to be performedIf the code 111 is output by the 8086, it is signalling that no bus activity is to take placeThe control outputs produced by the 8288 are DEN, DT/R and ALE. These 3 signals provide the same functions as those described for the minimum system mode. This set of bus commands and control signals is compatible with the Multibus (an industry standard) for interfacing microprocessor systems.Sep-Oct 2011Mallabhum Institute of Technology Debasis Das5555Max ModeInterface-58289 Bus Arbiter Bus Arbitration and Lock Signals : This device permits processors to reside on the system bus. It does this by implementing the Multibus arbitration protocol in an 8086-based systemAddition of the 8288 bus controller and 8289 bus arbiter frees a number of the 8086 pins for use to produce control signals that are needed to support multiple processorsBus priority lock ( LOCK) is one of these signals. It is input to the bus arbiter together with status signals S0 through S2.Sep-Oct 2011Mallabhum Institute of Technology Debasis Das56568289 Block DiagramSep-Oct 2011Mallabhum Institute of Technology Debasis Das57

578289 Pin OutSep-Oct 2011Mallabhum Institute of Technology Debasis Das58

58Max ModeInterface-6The output of 8289 are bus arbitration signals: bus busy (BUSY), common bus request (CBRQ), bus priority out (BPRO), bus priority in (BPRN), bus request (BREQ) and bus clock (BCLK).They correspond to the bus exchange signals of the Multibus and are used to lock other processor off the system bus during the execution of an instruction by the 8086In this way the processor can be assured of uninterrupted access to common system resources such as global memory.Sep-Oct 2011Mallabhum Institute of Technology Debasis Das5959Max ModeInterface-7Queue Status Signals : Two new signals that are produced by the 8086 in the maximum-mode system are queue status outputs QS0 and QS1. Together they form a 2-bit queue status code, QS1QS0Following table shows the four different queue status

Sep-Oct 2011Mallabhum Institute of Technology Debasis Das60

60Max ModeInterface-8Local Bus Control Signal Request / Grant Signals: In a maximum mode configuration, the minimum mode HOLD, HLDA interface is also changed. These two are replaced by request/grant lines RQ/ GT0 and RQ/ GT1, respectively. They provide a prioritized bus access mechanism for accessing the local bus.Sep-Oct 2011Mallabhum Institute of Technology Debasis Das6161Instruction Pointer (IP) RegisterA 16-bit registerHolds 16-bit offset, of the next instruction byte in the code segment BIU uses IP and CS registers to generate the 20-bit address of the instruction to be fetched from memory

Sep-Oct 201162Mallabhum Institute of Technology Debasis Das62Stack Segment (SS) Register Stack Pointer (SP) RegisterUpper 16-bits of the starting address of stack segment is stored in SS registerIt is located in BIUSP register holds a 16-bit offset from the start of stack segment to the top of the stackIt is located in EU

Sep-Oct 201163Mallabhum Institute of Technology Debasis Das63Other Pointer & Index RegistersBase Pointer (BP) registerSource Index (SI) registerDestination Index (DI) registerCan be used for temporary storage of dataMain use is to hold a 16-bit offset of a data word in one of the segmentsSep-Oct 201164Mallabhum Institute of Technology Debasis Das64Memory SpaceSep-Oct 2011Mallabhum Institute of Technology Debasis Das65

658086 System RelatedChips Sep-Oct 2011Mallabhum Institute of Technology Debasis Das66668286/7 OctalTransceiversSep-Oct 2011Mallabhum Institute of Technology Debasis Das67

678 Bit I/O Ports8282/8283Sep-Oct 2011Mallabhum Institute of Technology Debasis Das68

688284A Clock generatorSep-Oct 2011Mallabhum Institute of Technology Debasis Das69

69Instruction SetSep-Oct 2011Mallabhum Institute of Technology Debasis Das7070Instruction FormatSep-Oct 2011Mallabhum Institute of Technology Debasis Das71

71Addressing ModesAddressing mode indicates a way of locating data or operands Depending upon the data types used in the instruction and the memory addressing modes, any instruction may belong to one or more addressing modes, or some instruction may not belong to any of the addressing modes Addressing modes describe the types of operands and the way they are accessed for executing an instruction. Instructions may be categorized as Sequential control flow instructions and Control transfer instructionsSep-Oct 2011Mallabhum Institute of Technology Debasis Das7272Instruction Type ModesSequential control flow instructions are the instructions, which after execution, transfer control to the next instruction appearing immediately after it (in sequence) in the program For example, the arithmetic, logical, data transfer and processor control instructions are sequential control flow instructions The control transfer instructions, on the other hand, transfer control to some predefined address somehow specified in the instruction after their execution. For example, INT, CALL, RET and JUMP instructions fall under this categorySep-Oct 2011Mallabhum Institute of Technology Debasis Das7373Sequential Control Flow ModesSep-Oct 2011Mallabhum Institute of Technology Debasis Das7474Immediate ModeIn this type of addressing, immediate data is a part of instruction, and appears in the form of successive byte or bytes.Example: MOV AX, 0005H

In the above example, 0005H is the immediate data. The immediate data may be 8-bit or 16-bit in size

Sep-Oct 2011Mallabhum Institute of Technology Debasis Das7575Direct ModeIn the direct addressing mode, a 16-bit memory address (offset) is directly specified in the instruction as a part of it.Example: MOV AX, [5000H]

Here, data resides in a memory location in the data segment, whose effective address may be computed using 5000H as the offset address and content of DS as segment address. The effective address, here, is 10H*DS+5000HSep-Oct 2011Mallabhum Institute of Technology Debasis Das7676Register ModeIn register addressing mode, the data is stored in a register and it is referred using the particular register. All the registers, except IP, may be used in this mode.

Example: MOV BX, AXSep-Oct 2011Mallabhum Institute of Technology Debasis Das7777Register IndirectSometimes, the address of the memory location, which contains data or operand, is determined in an indirect way, using the offset registers. This mode of addressing is known as register indirect mode. In this addressing mode, the offset address of data is in either BX or SI or DI registers. The default segment is either DS or ES. The data is supposed to be available at the address pointed to by the content of any of the above registers in the default data segment.Example: MOV AX, [BX]

Here, data is present in a memory location in DS whose offset address is in BX. The effective address of the data is given as 10H*DS+ [BX]Sep-Oct 2011Mallabhum Institute of Technology Debasis Das7878IndexedIn this addressing mode, offset of the operand is stored in one of the index registers. DS and ES are the default segments for index registers SI and DI respectively. This mode is a special case of the above discussed register indirect addressing mode.Example: MOV AX, [SI]

Here, data is available at an offset address stored in SI and DS. The effective address, in this case, is computed as 10H*DS+ [SI]Sep-Oct 2011Mallabhum Institute of Technology Debasis Das7979Register RelativeIn this addressing mode, the data is available at an effective address formed by adding an 8-bit or 16-bit displacement with the content of any one of the registers BX, BP, SI and DI in the default (either DS or ES) segment. The example given before explains this mode. Example: MOV Ax, 50H [BX]

Here, effective address is given as 10H*DS+50H+ [BX]Sep-Oct 2011Mallabhum Institute of Technology Debasis Das8080Based IndexedThe effective address of data is formed, in this addressing mode, by adding content of a base register (any one of BX or BP) to the content of an index register (any one of SI or DI). The default segment register may be ES or DS.Example: MOV AX, [BX] [SI]

Here, BX is the base register and SI is the index register. The effective address is computed as 10H*DS+ [BX] + [SI]Sep-Oct 2011Mallabhum Institute of Technology Debasis Das8181Relative Based IndexedThe effective address is formed by adding an 8-bit or 16-bit displacement with the sum of contents of any one of the bases registers (BX or BP) and any one of the index registers, in a default segment. Example: MOV AX, 50H [BX] [SI]

Here, 50H is an immediate displacement, BX is a base register and SI is an index register. The effective address of data is computed as 160H*DS+ [BX] + [SI] + 50HSep-Oct 2011Mallabhum Institute of Technology Debasis Das8282Control TransferModesSep-Oct 2011Mallabhum Institute of Technology Debasis Das8383Basis of ModesFor the control transfer instructions, the addressing modes depend upon whether the destination location is within the same segment or a different one. It also depends upon the method of passing the destination address to the processor. Basically, there are two addressing modes for the control transfer instructions, viz. inter-segment and intra-segment addressing modes.

If the location to which the control is to be transferred lies in a different segment other than the current one, the mode is called inter-segment mode. If the destination location lies in the same segment, the mode is called intra-segment.

Sep-Oct 2011Mallabhum Institute of Technology Debasis Das8484Control Transfer ModesModesInter segmentInter segment directInter segment indirectIntra segmentIntra segment directIntra segment indirectSep-Oct 2011Mallabhum Institute of Technology Debasis Das8585Instruction CategoriesCategoriesCategoriesData TransferArithmeticStringLogicalShiftRotateProgram Execution TransferInterruptHLL SupportProcessor ControlBit ManipulationIteration Control

Sep-Oct 2011Mallabhum Institute of Technology Debasis Das8686Data Transfer-1MOV destination, sourcePUSH sourcePUSH / PUSHADPOP destinationPOPA / POPADXCHG destination, sourceXLATSep-Oct 2011Mallabhum Institute of Technology Debasis Das8787Data Transfer-2MOXZX destination, sourceMOVSZ destination, sourceCBWCDWCWDECDQSep-Oct 2011Mallabhum Institute of Technology Debasis Das8888Data Transfer-3LEA register, sourceLDS register, sourceLSS register, sourceLES register, sourceLGS register, sourceLFS register, source89Mallabhum Institute of Technology Debasis DasSep-Oct 201189Data Transfer-4LAHFSAHFPUSHFPOPFPUSHFDPOPFDSTCCLCCMCSTDCLDCLTSSep-Oct 2011Mallabhum Institute of Technology Debasis Das9090Data Transfer-5IN accumulator, port numberOUT port number, accumulatorSep-Oct 2011Mallabhum Institute of Technology Debasis Das9191Arithmetic-1ADD destination, sourceADC destination, sourceINC destinationAAADAASUB destination, sourceSBB destination, sourceDEC destinationSep-Oct 2011Mallabhum Institute of Technology Debasis Das9292Arithmetic-2NEG registerCMP destination, sourceAASDASMUL sourceAAMDIV sourceIDIV sourceAADSep-Oct 2011Mallabhum Institute of Technology Debasis Das9393Logical-1NOT destinationAND destination, sourceOR destination, sourceXOR destination, sourceTEST destination, source94Mallabhum Institute of Technology Debasis DasSep-Oct 201194Logical-2Sep-Oct 2011Mallabhum Institute of Technology Debasis Das95SAL / SHL Destination, CountSAL BX, 01SAL BP, CLMOV CL, 04HSAL AL, CL

95Logical-3SHR Destination, CountSHR BP, 01SHR AL, CLSep-Oct 2011Mallabhum Institute of Technology Debasis Das96

96Logical-4SAR Destination, CountSAR DI, 1SAR AL, 0197Mallabhum Institute of Technology Debasis DasSep-Oct 2011

97Logical-5ROL Destination, CountROL AX, 1ROL BL, CL98Mallabhum Institute of Technology Debasis DasSep-Oct 2011

98Logical-6RCL Destination, CountRCL AX, 1RCL BL, CLSep-Oct 2011Mallabhum Institute of Technology Debasis Das99

99Logical-7ROR Destination, CountROR BL, 01ROR AL, CLSep-Oct 2011Mallabhum Institute of Technology Debasis Das100

100Logical-8RCR Destination, CountRCR BL, 01RCR AL, CLSep-Oct 2011Mallabhum Institute of Technology Debasis Das101

101Program Execution TransferCall ProcedureCALL SQRTCALL BXCALL WORD PTR(BX)RETSep-Oct 2011Mallabhum Institute of Technology Debasis Das102102Jump Instructions-1JMP labelSep-Oct 2011Mallabhum Institute of Technology Debasis Das103

103Jump Instructions-2Sep-Oct 2011Mallabhum Institute of Technology Debasis Das104

104Jump Instructions-3Sep-Oct 2011Mallabhum Institute of Technology Debasis Das105

105Iteration Control InstructionsSep-Oct 2011Mallabhum Institute of Technology Debasis Das106

106InterruptSTICLIINT typeINTOIRETSep-Oct 2011Mallabhum Institute of Technology Debasis Das107107Bit ManipulationBT Bit test and put specified bit in carry flag. E.g. BT ECX, 4BTSBTRBTCBSF BSF BX, CXBSRSep-Oct 2011Mallabhum Institute of Technology Debasis Das108108String InstructionsMOVS / MOVSB / MOVSW / MOVSDINS / INSB / INSWOUTS / OUTSB / OUTSWCMPS / CMPSB / CMPSW / CMPSDSCAS / SCASB / SCABW / SCASDLODS / LODSB / LODSW / LODSDSTOS / STOSB / STOSW / STOSDREP / REPE / REPZ / REPNE / REPNZSep-Oct 2011Mallabhum Institute of Technology Debasis Das109109Processor ControlHLTWAITESCLOCKNOPSep-Oct 2011Mallabhum Institute of Technology Debasis Das110110