8051 Intro to Hardware

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Why do we need to learn Microprocessors/controllers?

• The microprocessor is the core of computer systems.

• Nowadays many communication, digital entertainment, portable devices, are controlled by them.

• A designer should know what types of components he needs, ways to reduce production costs and product reliable.

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Different aspects of a microprocessor/controller

• Hardware :Interface to the real world

• Software :order how to deal with inputs

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The necessary tools for a microprocessor/controller

• CPU: Central Processing Unit• I/O: Input /Output• Bus: Address bus & Data bus• Memory: RAM & ROM• Timer• Interrupt• Serial Port• Parallel Port

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CPU

General-Purpose Micro-processor

RAM ROM I/O Port

TimerSerial COM Port

Data Bus

Address Bus

General-Purpose Microprocessor System

Microprocessors:

• CPU for Computers• No RAM, ROM, I/O on CPU chip itself• Example：Intel’s x86, Motorola’s 680x0

Many chips on mother’s board

General-purpose microprocessor

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RAM ROM

I/O Port

TimerSerial COM Port

Microcontroller

CPU

• A smaller computer• On-chip RAM, ROM, I/O ports...• Example：Motorola’s 6811, Intel’s 8051, Zilog’s Z8 and PIC 16X

A single chip

Microcontroller :

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Microprocessor• CPU is stand-alone, RAM,

ROM, I/O, timer are separate• designer can decide on the

amount of ROM, RAM and I/O ports.

• expansive• versatility • general-purpose

Microcontroller• CPU, RAM, ROM, I/O and

timer are all on a single chip• fix amount of on-chip ROM,

RAM, I/O ports• for applications in which cost,

power and space are critical• single-purpose

Microprocessor vs. Microcontroller

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• Embedded system means the processor is embedded into that application.• An embedded product uses a microprocessor or microcontroller to do one

task only.• In an embedded system, there is only one application software that is

typically burned into ROM.• Example：printer, keyboard, video game player

Embedded System

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1. meeting the computing needs of the task efficiently and cost effectively• speed, the amount of ROM and RAM, the number of I/O ports and

timers, size, packaging, power consumption• easy to upgrade• cost per unit

2. availability of software development tools• assemblers, debuggers, C compilers, emulator, simulator, technical

support3. wide availability and reliable sources of the microcontrollers.

Three criteria in Choosing a Microcontroller

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Block Diagram

CPU

On-chip RAM

On-chip ROM for program code

4 I/O Ports

Timer 0

Serial PortOSC

Interrupt Control

External interrupts

Timer 1

Timer/Counter

Bus Control

TxD RxDP0 P1 P2 P3

Address/Data

Counter Inputs

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Pin Description of the 8051

1234567891011121314151617181920

4039383736353433323130292827262524232221

P1.0P1.1P1.2P1.3P1.4P1.5P1.6P1.7RST

(RXD)P3.0(TXD)P3.1

(T0)P3.4(T1)P3.5

XTAL2XTAL1

GND

(INT0)P3.2(INT1)P3.3

(RD)P3.7(WR)P3.6

VccP0.0(AD0)P0.1(AD1)P0.2(AD2)P0.3(AD3)P0.4(AD4)P0.5(AD5)P0.6(AD6)P0.7(AD7)EA/VPPALE/PROGPSENP2.7(A15)P2.6(A14)P2.5(A13)P2.4(A12)P2.3(A11)P2.2(A10)P2.1(A9)P2.0(A8)

8051(8031)

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Packing Types of 8051

• The 8051 family members come in different packages, such as DIP（dual in-line package）,QFP（quad flat package）and LLC（leadless chip carrier）.– See Appendix H（Pages 427-429）

• They all have 40 pins.• Figure 4-1. 8051 Pin Diagram

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8051 Pin DiagramPDIP/Cerdip

1234567891011121314151617181920

4039383736353433323130292827262524232221

P1.0P1.1P1.2P1.3P1.4P1.5P1.6P1.7RST

(RXD)P3.0(TXD)P3.1

(T0)P3.4(T1)P3.5

XTAL2XTAL1

GND

(INT0)P3.2(INT1)P3.3

(RD)P3.7(WR)P3.6

VccP0.0(AD0)P0.1(AD1)P0.2(AD2)P0.3(AD3)P0.4(AD4)P0.5(AD5)P0.6(AD6)P0.7(AD7)EA/VPPALE/PROGPSENP2.7(A15)P2.6(A14)P2.5(A13)P2.4(A12)P2.3(A11)P2.2(A10)P2.1(A9)P2.0(A8)

8051(8031)

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Pins of 8051（1/4）

• Vcc（pin 40）：

– Vcc provides supply voltage to the chip. – The voltage source is +5V.

• GND（pin 20）：ground• XTAL1 and XTAL2（pins 19,18）：

– These 2 pins provide external clock.– Way 1：using a quartz crystal oscillator – Way 2：using a TTL oscillator – Example 4-1 shows the relationship between XTAL and

the machine cycle.

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Pins of 8051（2/4）

• RST（pin 9）：reset– It is an input pin and is active high（normally low）.

• The high pulse must be high at least 2 machine cycles.

– It is a power-on reset.• Upon applying a high pulse to RST, the microcontroller will reset

and all values in registers will be lost.• Reset values of some 8051 registers

– Way 1：Power-on reset circuit – Way 2：Power-on reset with debounce

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Pins of 8051（3/4）

• /EA（pin 31）：external access– There is no on-chip ROM in 8031 and 8032 .– The /EA pin is connected to GND to indicate the code is

stored externally.– /PSEN ＆ ALE are used for external ROM.– For 8051, /EA pin is connected to Vcc.– “/” means active low.

• /PSEN（pin 29）：program store enable– This is an output pin and is connected to the OE pin of the

ROM.– See Chapter 14.

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Pins of 8051（4/4）

• ALE（pin 30）：address latch enable– It is an output pin and is active high.– 8051 port 0 provides both address and data.– The ALE pin is used for de-multiplexing the address and

data by connecting to the G pin of the 74LS373 latch.

• I/O port pins– The four ports P0, P1, P2, and P3.– Each port uses 8 pins.– All I/O pins are bi-directional.

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Figure 4-2 (a). XTAL Connection to 8051

C2

30pF

C1

30pF

XTAL2

XTAL1

GND

• Using a quartz crystal oscillator• We can observe the frequency on the XTAL2 pin.

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Figure 4-2 (b). XTAL Connection to an External Clock Source

NC

EXTERNALOSCILLATORSIGNAL

XTAL2

XTAL1

GND

• Using a TTL oscillator• XTAL2 is unconnected.

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Example 4-1

Find the machine cycle for(a) XTAL = 11.0592 MHz (b) XTAL = 16 MHz.

Solution:

(a) 11.0592 MHz / 12 = 921.6 kHz;machine cycle = 1 / 921.6 kHz = 1.085 µs

(b) 16 MHz / 12 = 1.333 MHz;machine cycle = 1 / 1.333 MHz = 0.75 µs

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Table 4-1: RESET Value of Some 8051 Registers

0000DPTR

0007SP

0000PSW

0000B

0000ACC

0000PC

Reset ValueRegister

RAM are all zero.⌦

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Figure 4-3 (a). Power-On RESET Circuit

30 pF

30 pF

8.2 K

10 uF

+

Vcc

11.0592 MHz

EA/VPPX1

X2

RST

31

19

18

9

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Figure 4-3 (b). Power-On RESET with Debounce

EA/VPPX1

X2RST

Vcc

10 uF

8.2 K

30 pF

9

31

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Pins of I/O Port

• The 8051 has four I/O ports– Port 0 （pins 32-39）：P0（P0.0〜P0.7）– Port 1（pins 1-8）：P1（P1.0〜P1.7）– Port 2（pins 21-28）：P2（P2.0〜P2.7）– Port 3（pins 10-17）：P3（P3.0〜P3.7）– Each port has 8 pins.

• Named P0.X （X=0,1,...,7）, P1.X, P2.X, P3.X• Ex：P0.0 is the bit 0（LSB）of P0 • Ex：P0.7 is the bit 7（MSB）of P0• These 8 bits form a byte.

• Each port can be used as input or output (bi-direction).

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Port 1（pins 1-8）

• Port 1 is denoted by P1.– P1.0 ~ P1.7

• We use P1 as examples to show the operations on ports.– P1 as an output port (i.e., write CPU data to the external pin)– P1 as an input port (i.e., read pin data into CPU bus)

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A Pin of Port 1

8051 IC

D Q

Clk Q

Vcc

Load(L1)

Read latch

Read pin

Write to latch

Internal CPU bus

M1

P1.X pinP1.X

TB1

TB2

⌦P0.x

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Hardware Structure of I/O Pin

• Each pin of I/O ports– Internal CPU bus：communicate with CPU– A D latch store the value of this pin

• D latch is controlled by “Write to latch”– Write to latch＝1：write data into the D latch

– 2 Tri-state buffer：• TB1: controlled by “Read pin”

– Read pin＝1：really read the data present at the pin• TB2: controlled by “Read latch”

– Read latch＝1：read value from internal latch

– A transistor M1 gate• Gate=0: open• Gate=1: close

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Figure C-9. Tri-state Buffer

Output Input

Tri-state control (active high)

L H Low

Highimpedance (open-circuit)

HH

L H

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Writing “1” to Output Pin P1.X

D Q

Clk Q

Vcc

Load(L1)

Read latch

Read pin

Write to latch

Internal CPU bus

M1

P1.X pinP1.X

8051 IC

2. output pin is Vcc1. write a 1 to the pin

1

0 output 1

TB1

TB2

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Writing “0” to Output Pin P1.X

D Q

Clk Q

Vcc

Load(L1)

Read latch

Read pin

Write to latch

Internal CPU bus

M1

P1.X pinP1.X

8051 IC

2. output pin is ground1. write a 0 to the pin

0

1 output 0

TB1

TB2

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Port 1 as Output（Write to a Port）

• Send data to Port 1：MOV A,#55H

BACK: MOV P1,A ACALL DELAYCPL ASJMP BACK

– Let P1 toggle.– You can write to P1 directly.

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Reading Input v.s. Port Latch

• When reading ports, there are two possibilities：– Read the status of the input pin. （from external pin

value）• MOV A, PX• JNB P2.1, TARGET ; jump if P2.1 is not set• JB P2.1, TARGET ; jump if P2.1 is set• Figures C-11, C-12

– Read the internal latch of the output port.• ANL P1, A ; P1 ← P1 AND A• ORL P1, A ; P1 ← P1 OR A• INC P1 ; increase P1• Figure C-17 • Table C-6 Read-Modify-Write Instruction (or Table 8-5)

S S ti 8 3

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Figure C-11. Reading “High” at Input Pin

D Q

Clk Q

Vcc

Load(L1)

Read latch

Read pin

Write to latch

Internal CPU bus

M1

P1.X pinP1.X

8051 IC

2. MOV A,P1

external pin=High

1. write a 1 to the pin MOV P1,#0FFH

1

0

3. Read pin=1 Read latch=0

Write to latch=1

1

TB1

TB2

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Figure C-12. Reading “Low” at Input Pin

D Q

Clk Q

Vcc

Load(L1)

Read latch

Read pin

Write to latch

Internal CPU bus

M1

P1.X pinP1.X

8051 IC

2. MOV A,P1

external pin=Low

1. write a 1 to the pin

MOV P1,#0FFH 1

0

3. Read pin=1 Read latch=0

Write to latch=1

0

TB1

TB2

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Port 1 as Input（Read from Port）

• In order to make P1 an input, the port must be programmed by writing 1 to all the bit.

MOV A,#0FFH ;A=11111111BMOV P1,A ;make P1 an input port

BACK: MOV A,P1 ;get data from P0MOV P2,A ;send data to P2SJMP BACK

– To be an input port, P0, P1, P2 and P3 have similar methods.

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Table 8-4: Instructions For Reading an Input Port

Copy status of pin P2.4 to CY

MOV C,P2.4MOV C,PX.Y

Jump if pin P1.3 is highJB P1.3,TARGETJB PX.Y,..

Jump if pin P2.1 is lowJNB P2.1,TARGETJNB PX.Y,..

Bring into A the data at P2 pins

MOV A,P2MOV A,PX

DescriptionExamplesMnemonics

• Following are instructions for reading external pins of ports:

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Figure C-17. Reading the Latch

D Q

Clk Q

Vcc

Load(L1)

Read latch

Read pin

Write to latch

Internal CPU bus

M1

P1.X pinP1.X

8051 IC

4. P1.X=12. CPU compute P1.X OR 1 0

0

1. Read pin=0 Read latch=1 Write to latch=0 (Assume

P1.X=0 initially)

1

TB1

TB2

3. write result to latch Read pin=0

Read latch=0 Write to latch=1

1

0

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Reading Latch

• Exclusive-or the Port 1：MOV P1,#55H ;P1=01010101ORL P1,#0F0H ;P1=11110101

1. The read latch activates TB2 and bring the data from the Q latch into CPU.

• Read P1.0=0

2. CPU performs an operation.• This data is ORed with bit 1 of register A. Get 1.

3. The latch is modified.• D latch of P1.0 has value 1.

4. The result is written to the external pin.• External pin (pin 1: P1.0) has value 1.

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Read-modify-write Feature

• Read-modify-write Instructions– Table C-6

• This features combines 3 actions in a single instruction：1. CPU reads the latch of the port2. CPU perform the operation3. Modifying the latch4. Writing to the pin– Note that 8 pins of P1 work independently.

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Port 1 as Input（Read from latch）

• Exclusive-or the Port 1：MOV P1,#55H ;P1=01010101

AGAIN: XOR P1,#0FFH ;complement ACALL DELAY SJMP AGAIN

– Note that the XOR of 55H and FFH gives AAH.– XOR of AAH and FFH gives 55H.– The instruction read the data in the latch (not from the pin).– The instruction result will put into the latch and the pin.– P1 is configured as an output port.

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Table C-6：Read-Modify-Write InstructionsExampleMnemonics

SETB P1.4SETB PX.Y

CLR P1.3CLR PX.Y

MOV P1.2,CMOV PX.Y,C

DJNZ P1,TARGETDJNZ PX, TARGET

INC P1INC

CPL P1.2CPL

JBC P1.1, TARGETJBC PX.Y, TARGET

XRL P1,AXRL

ORL P1,AORL

ANL P1,AANL

DEC P1DEC

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Questions

• How to write the data to a pin？• How to read the data from the pin？

– Read the value present at the external pin.• Why we need to set the pin first？

– Read the value come from the latch（not from the external pin）.

• Why the instruction is called read-modify write?

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Other Pins

• P1, P2, and P3 have internal pull-up resisters.– P1, P2, and P3 are not open drain.

• P0 has no internal pull-up resistors and does not connects to Vcc inside the 8051.– P0 is open drain.– Compare the figures of P1.X and P0.X.

• However, for a programmer, it is the same to program P0, P1, P2 and P3.

• All the ports upon RESET are configured as output.

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A Pin of Port 0

8051 IC

D Q

Clk Q

Read latch

Read pin

Write to latch

Internal CPU bus

M1

P0.X pinP1.X

TB1

TB2

⌦P1.x

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• P0 is an open drain.– Open drain is a term used for MOS chips in the same way

that open collector is used for TTL chips.

• When P0 is used for simple data I/O we must connect it to external pull-up resistors.– Each pin of P0 must be connected externally to a 10K ohm

pull-up resistor.– With external pull-up resistors connected upon reset, port 0

is configured as an output port.

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Figure 4-4. Port 0 with Pull-Up Resistors

P0.0P0.1P0.2P0.3P0.4P0.5P0.6P0.7

DS500087518951

Vcc10 K

Port

0

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Dual Role of Port 0

• When connecting an 8051/8031 to an external memory, the 8051 uses ports to send addresses and read instructions.– 8031 is capable of accessing 64K bytes of external memory.– 16-bit address：P0 provides both address A0-A7, P2

provides address A8-A15.– Also, P0 provides data lines D0-D7.

• When P0 is used for address/data multiplexing, it is connected to the 74LS373 to latch the address.– There is no need for external pull-up resistors as shown in

Chapter 14.

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Figure 14-9 74LS373

D

74LS373ALE

P0.0

P0.7

PSEN

A0

A7

D0

D7

P2.0

P2.7

A8

A15

OEOC

EA

G

8051 ROM

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Reading ROM (1/2)

D

74LS373ALE

P0.0

P0.7

PSEN

A0

A7

D0

D7

P2.0

P2.7

A8

A12

OEOC

EA

G

8051 ROM

1. Send address to ROM

2. 74373 latches the address and

send to ROM

Address

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Reading ROM (2/2)

D

74LS373ALE

P0.0

P0.7

PSEN

A0

A7

D0

D7

P2.0

P2.7

A8

A12

OEOC

EA

G

8051 ROM

2. 74373 latches the address and

send to ROM

Address

3. ROM send the instruction back

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ALE Pin

• The ALE pin is used for de-multiplexing the address and data by connecting to the G pin of the 74LS373 latch.– When ALE=0, P0 provides data D0-D7.– When ALE=1, P0 provides address A0-A7.– The reason is to allow P0 to multiplex address and data.

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• Port 2 does not need any pull-up resistors since it already has pull-up resistors internally.

• In an 8031-based system, P2 are used to provide address A8-A15.

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• Port 3 does not need any pull-up resistors since it already has pull-up resistors internally.

• Although port 3 is configured as an output port upon reset, this is not the way it is most commonly used.

• Port 3 has the additional function of providing signals.– Serial communications signal：RxD, TxD（Chapter 10）– External interrupt：/INT0, /INT1（Chapter 11）– Timer/counter：T0, T1（Chapter 9）– External memory accesses in 8031-based system：/WR,

/RD（Chapter 14）

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Table 4-2: Port 3 Alternate Functions

17RDP3.7

16WRP3.6

15T1P3.5

14T0P3.4

13INT1P3.3

12INT0P3.2

11TxDP3.1

10RxDP3.0

PinFunctionP3 Bit

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I/O Programming; Bit Manipulation

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I/O Programming

• To toggle every bit of P1 continuously.• 3 ways：Way 1, Way 2, and Way 3.

– Which one is better？

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Way 1

• Send data to Port 1 through ACC：BACK: MOV A,#55H ;A=01010101B

MOV P1,AACALL DELAYMOV A,#0AAH ;A=10101010B MOV P1,A ACALL DELAYSJMP BACK

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Way 2

• Access Port 1 directly：BACK: MOV P1,#55H ;P1=01010101B

ACALL DELAYMOV P1,#0AAH ;P1=10101010B ACALL DELAYSJMP BACK

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Way 3

• Read-modify-write feature：MOV P1,#55H ;P1=01010101B

AGAIN: XRL P1,#0FFHACALL DELAYSJMP AGAIN

– The instruction XRL P1,#0FFH do EX-OR P1 and FFH （That is, to toggle P1.）

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Bit Manipulation

• Sometimes we need to access only 1 or 2 bits of the port instead of the entire 8 bits.

• Table 4-3 shows how to name each pin for each I/O port.

• Example 4-2 • See Section 8.1 single-bit instruction programming

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Table 4-3: Single-Bit Addressability of Ports

D7P3.7P2.7P1.7P0.7

D6P3.6P2.6P1.6P0.6

D5P3.5P2.5P1.5P0.5

D4P3.4P2.4P1.4P0.4

D3P3.3P2.3P1.3P0.3

D2P3.2P2.2P1.2P0.2

D1P3.1P2.1P1.1P0.1

D0P3.0P2.0P1.0P0.0

Port BitP3P2P1P0

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Example 4-2Write a program to perform the following.(a) Keep monitoring the P1.2 bit until it becomes high,(b) When P1.2 becomes high, write value 45H to port 0, and(c) Send a high-to-low (H-to-L) pulse to P2.3.Solution:

SETB P1.2 ;make P1.2 an inputMOV A,#45H ;A=45H

AGAIN:JNB P1.2,AGAIN;get out when P.2=1MOV P0,A ;issue A to P0SETB P2.3 ;make P2.3 highCLR P2.3 ;make P2.3 low for H-to-L

Note：1. JNB: jump if no bit（jump if P1.2 = 0 ）2. a H-to-L pulse by the sequence of instructions SETB and CLR.

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8051 Intro to Hardware