8 7 6 5 4 3 2 1 SCHEM,MLB-PRQ,M59...Yukon Power P.39 P.57-64,69 P.56 Fan SMBus x5 TSB83AA22 FireWire P.43 PHY Power Controller Yukon Gig-E P.39 P.37-38 Controller Connectors SMBus

TABLE_TABLEOFCONTENTS_ITEM























ANGLES

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

DATE

APPDENG

DATE

APPDCK

ECNZONEREV

DO NOT SCALE DRAWING

X.XXX

X.XX

XX

DIMENSIONS ARE IN MILLIMETERS

THIRD ANGLE PROJECTIOND

SIZE

APPLICABLENOTED AS

MATERIAL/FINISH

NONE

SCALE

DESIGNER

MFG APPD

DESIGN CK

RELEASE

QA APPD

ENG APPD

DRAFTER

METRIC

OFSHT

DRAWING NUMBER

TITLE

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PARTII NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

Apple Computer Inc.

12345678

12345678

B

C

D

A

B

C

D

A

REV.

DESCRIPTION OF CHANGE

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEMTABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD

DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL

DRAWING





























































Schematic / PCB #’s

SCHEM,MLB-PRQ,M5902/12/2007

BOM Update for Post Ramp Qualifications

486797

SCHEM,MLB-PRQ,M59

1 105

02/12/07B PRODUCTION RELEASED

B051-7270

SyncContentsDate

Page(.csa)

(MASTER)FW PHY Power Supply44

42(MASTER)

1N/A

N/ATable of Contents1

Page Sync(.csa) Date

Contents

SCH CRITICAL1 SCHEM,MLB-PRQ,M59051-7270

LAST_MODIFIED=Mon Feb 12 10:35:04 2007

ABBREV=DRAWING

TITLE=M59_MLB

PCB820-2054 1 PCBF,MLB,M59 CRITICAL

(MASTER)FireWire Port Power45

43(MASTER)

(MASTER)FireWire Ports46

44(MASTER)

(MASTER)Camera Connector49

45(MASTER)

(MASTER)External USB Connector52

46(MASTER)

(MASTER)Left I/O Board Connector55

47(MASTER)

(MASTER)PCI-E Connections57

48(MASTER)

(MASTER)SMC58

49(MASTER)

(MASTER)SMC Support59

50(MASTER)

(MASTER)LPC+ Debug Connector60

51(MASTER)

(MASTER)Thermal Sensors61

52(MASTER)

(MASTER)Current & Voltage Sensing62

53(MASTER)

(MASTER)SPI BOOTROM63

54(MASTER)

(MASTER)ALS Support64

55(MASTER)

(MASTER)Fan Connectors65

56(MASTER)

(MASTER)Sudden Motion Sensor (SMS)66

57(MASTER)

(MASTER)TPM67

58(MASTER)

(MASTER)IMVP6 CPU VCore Regulator75

59(MASTER)

(MASTER)5V / 1.5V Power Supply76

60(MASTER)

M59_MG2.5V & 1.2V Regulators77

6105/07/2006

M59_MG1.8V Supply78

6205/07/2006

M59_MG3.3V / 1.05V Power Supplies79

6305/07/2006

M59_MG3.3V G3Hot Supply & Power Control80

6408/01/2006

M59_MGPower Aliases81

6505/07/2006

(MASTER)PBus-In,Batt. & 3G Pwr Connectors82

66(MASTER)

(MASTER)ATI M56 PCI-E84

67(MASTER)

(MASTER)GPU (M56) Core Supplies85

68(MASTER)

(MASTER)ATI M56 Core Power86

69(MASTER)

(MASTER)ATI M56 Frame Buffer I/F87

70(MASTER)

M59_MGGPU Straps88

7107/25/2006

(MASTER)GDDR3 Frame Buffer A89

72(MASTER)

(MASTER)GDDR3 Frame Buffer B90

73(MASTER)

(MASTER)ATI M56 GPIO/DVO/Misc91

74(MASTER)

(MASTER)ATI M56 Video Interfaces93

75(MASTER)

M59_MGInternal Display Connectors94

7607/25/2006

M59_MGExternal Display Connector97

7707/25/2006

(MASTER)M59 Specific Connectors98

78(MASTER)

M59_MGLVDS Interface Pull-downs99

7908/01/2006

N/ARevision History100

80N/A

(MASTER)Napa Platform Constraints101

81(MASTER)

(MASTER)More System Constraints102

82(MASTER)

(MASTER)M59 Spacing & Physical Constraints103

83(MASTER)

(MASTER)M59 Net Properties104

84(MASTER)

N/A22uF Capacitor BOM Configuration105

85N/A

2N/A

N/ASystem Block Diagram2

3N/A

N/APower Block Diagram3

4N/A

N/ABOM Configuration4

5N/A

N/AFunctional / ICT Test5

6N/A

N/ASignal Aliases/Misc Comps6

7(MASTER)

(MASTER)CPU 1 OF 2-FSB7

8(MASTER)

(MASTER)CPU 2 OF 2-PWR/GND8

9(MASTER)

(MASTER)CPU Decoupling & VID9

10(MASTER)

(MASTER)CPU MISC1-TEMP SENSOR10

11(MASTER)

(MASTER)CPU ITP700FLEX DEBUG11

12(MASTER)

(MASTER)NB CPU Interface12

13(MASTER)

(MASTER)NB PEG / Video Interfaces13

14(MASTER)

(MASTER)NB Misc Interfaces14

15(MASTER)

(MASTER)NB DDR2 Interfaces15

16(MASTER)

(MASTER)NB Power 116

17(MASTER)

(MASTER)NB Power 217

18(MASTER)

(MASTER)NB Grounds18

1907/25/2006

M59_MGNB (GM) Decoupling19

20(MASTER)

(MASTER)NB Config Straps20

21(MASTER)

(MASTER)SB: 1 OF 421

22(MASTER)

(MASTER)SB: 2 of 422

2307/25/2006

M59_MGSB: 3 OF 423

24(MASTER)

(MASTER)SB: 4 OF 424

25(MASTER)

(MASTER)SB Decoupling25

26(MASTER)

(MASTER)SB Misc26

27(MASTER)

(MASTER)M1 SMBus Connections27

28(MASTER)

(MASTER)DDR2 SO-DIMM Connector A28

29(MASTER)

(MASTER)DDR2 SO-DIMM Connector B29

30(MASTER)

(MASTER)Memory Active Termination30

31(MASTER)

(MASTER)Memory Vtt Supply31

32(MASTER)

(MASTER)DDR2 VRef32

33(MASTER)

(MASTER)CLOCKS33

3405/07/2006

M59_MGClock Termination34

35(MASTER)

(MASTER)Mobile Clocking37

36(MASTER)

(MASTER)PATA Connector38

37(MASTER)

(MASTER)FireWire Link (TSB83AA22)39

38(MASTER)

(MASTER)FireWire PHY (TSB83AA22)40

39(MASTER)

(MASTER)ETHERNET CONTROLLER41

40(MASTER)

(MASTER)Ethernet Connector42

41(MASTER)

(MASTER)Yukon Power Control43

DSIZE

OFSHT

DRAWING NUMBER



III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT


12345678

12345678

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.SCALE

NONE

CH.B

Connector

P.78

PATA

SATA

USB x2

DDR2 SO-DIMM B

DDR2 SO-DIMM A"Expansion Slot" Connector

Geyser KB/TP/BT

Connector

MUX

Dual-Channel LVDS

LVDS Graphics

P.99

Dual-Channel TMDS

S-Video/Composite

P.67-71,74-75

ATI M56P

GPU

Yukon Power

P.39

P.57-64,69

P.56

Fan

SMBus x5

TSB83AA22 FireWire

P.43

PHY Power

Controller

Yukon Gig-E

P.39

P.37-38

Controller

Connectors

SMBus

BootROM

PWM/Tach

P.54

SPI

SMC

H8S/2116

P.49-50

LPC 33MHZ

TPM

P.58

PCI

PCIe x1

609 BGA

P.21-26

SB

P.12-20

ICH7-M

DMI x4

P.72-73

GDDR3

128MB/256MB

Frame Buffer

PCIe x16

SENSOR

P.10

THERMAL

CPU

P.7-9

NB

1466UFCBGA

945GM

FSB

(Merom)

479 BGA

SMS

Analog

Sensors

Connector

LPC

Debug

ALS

USB

USB

P.51

P.55,78

P.57

P.53

PCIe x1

PCIe x1

CH.A

P.11

Power

Supplies

Azalia (HD-Audio)

BUFFER

DDR2 VREF

P.32

P.47

Connector

Audio Board

Left I/O &

P.30-31

CPU Debug

ITP700FLEX

Connector

J2900

J2800

P.28

P.29

DDR2 VTT

& REGULATOR

P.27

SB SMBus

SMC SMBus

P.27

16BITS

66MHZ

P.43

Port Power

P.40

P.44

Sensors

Temperature

FW

ENET

DVI-I/DL Connector

w/TV-Out Support

LCD Panel

ODDConnector

Connector

Controller

CK410 Clock

P.33-34

Battery SMBus

Connector

RJ45 (Ethernet)

Connector

Right USB 2.0

Connector

1394a/b (FireWire)

P.46

P.78

P.45

P.36

P.52

P.66

P.76,79

P.77

Connectors

PWMConnectorInverter

P.76

Camera

USB x2

USBHDD/IR/SIL

USB

"Factory Slot" Connector

(Lower/Outer)

(Upper/Inner)

Core 2 Duo

SYNC_DATE=N/ASYNC_MASTER=N/A

051-7270

1052

B

System Block Diagram

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

Connector

LIO Power

PPVCORE_D3C_GPUD3C

=GPUVCORE_EN_L

FW_PWRCTRL_GATE2_1/2FW_PWRCTRL_GATE1

PM_SLP_S3_LS5V

Q4501Q4500

PPBUS_S5_FWPORT

12.6V - 9V

P3V3D3C_EN_L

PP3V3_D3C

Q7948

3.3V

PP3V3_S0

3.3V

Q7947

PP1V8_D3C

P1V8D3C_EN

P1V2R2V5D3C_EN_LS5V

PP1V2_D3C

P1V2R2V5D3C_EN_LS5V

PP2V5_D3C

Q7721

PP2V5_S0

PM_SLP_S3_LS5V_L

2.5V

Q7720

2.5V

(TPS62510)

2.5V

3.3V

PP3V3_S5

1.1V - 0.95V

Q7945

Q7845

Q7770

Q7615

Q7610

U7530

PM_SLP_S3BATT

PM_SLP_S3BATT

NC

PM_SLP_S3BATT

Q4300

3.3V

PP3V3_S3AC

ODD_PWR_EN_L (SB GPIO14)

PP5V_S0_IDE_ODD

5V

Q3820

J8200

PPBUS_G3H

U7900

PM_SLP_S4_L

Connector

LIO Flex

J5500

PPDCIN_G3H

18.5V - 9V

12.6V - 9V

ENABLE

3.425

G3Hot

(LT3470)

PP3V42_G3H

3.425V

U8000

5.0V

1.8V

1.2V

0.9V

PP0V9_S0S0

0.9V (Vtt)

U3100

PM_SLP_S3_L

PGOOD

ENABLE

S3

U7800

1.8V

NC

1.8V

PP1V8_S3

Inverter

Connector

J5500

ENABLE

ENABLE

PM_SLP_S4_LS5V

PM_SLP_S3_LS5V

PM_SLP_S4_LS5V

IMVP_PWRGD_IN/ALL_SYS_PWRGD

S0

RSMRST_PWRGD

IMVP_VR_ON

IMVP_PWRGD_IN

ENABLES

CPU VCore

S0

"IMVP6"

VR_PWRGOOD_DELAY

PGOOD

SMC_PM_G2_ENABLE

PM_SLP_S3_L

1.5V

5V

U7600ENABLES

PGOOD

S5/S0

(LTC3728)

NC

SMC_PM_G2_ENABLE

PP5V_S5

5.0V

PP1V5_S0

PP5V_S3

5.0V

PP5V_S0

PP3V3_S3

3.3V

U7700ENABLE

PGOOD

S3

2.5VPP2V5_S3

PP1V2_S3

1.2V

U7750ENABLE

1.2V

PGOOD

S3

(LTC3412)

NC

ENABLE

GPU VCore

PGOOD

U7950

1.05V

PGOOD

PP1V05_S0

1.05V

PPVCORE_S0_CPU

ENABLE

3.3V

S5

PGOOD

1.5V

NC

U8500

PM_SLP_S3_L

5V/1.5V

1.25V - 0.8V(ISL9504)

(TPS51117)

(TPS51100)

(ISL6269B)

(ISL6269B)

(ISL6269B)

Power Block DiagramSYNC_MASTER=N/A SYNC_DATE=N/A

B051-7270

3 105

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

BOM OPTIONSBOM NAMEBOM NUMBERTABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM


TABLE_BOMGROUP_ITEM


TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM


TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_ALT_ITEM

BOM OPTIONSBOM GROUPTABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

TABLE_ALT_ITEM

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM


Alternate Parts

Bar Code Label / EEE #’s

BOMOPTION Groups

extra TPM options:

for option definitionssee page 85 (csa page 105)

SMC_TPM_PPSMC_TPM_GPIO1SMC_TPM_GPIO2

Qimonda (Infineon) VRAM BOMs

Mixed Cap BOMs

Original Production BOMs (SS VRAM, All SS/MU Caps)

Module Parts

[EEE:XBX]1826-4393 LBL,P/N LABEL,PCB,28MM X 6 MM CRITICAL EEE_XBX

33uF,16V,D2ALL128S0093 128S0092

1 CRITICALU7530IC,ISL9504,SYNC REG CTRL,QFN48353S1461

333S0376 IC,SGRAM,GDDR3,8MX32,700MHZ,136 FBGA CRITICAL4 U8900,U8950,U9000,U9050 VRAM_128_INFINEON

IC,SGRAM,GDDR3,16MX32,600MHZ,136 FBGA U8900,U8950,U9000,U9050 CRITICAL4 VRAM_256_INFINEON333S0377

IC,MDC,B2,PRQ,2.16G,34W,667M,4M,479BGA337S3391 U07001 CRITICAL CPU_2_16GHZ

IC,MDC,B2,PRQ,2.33G,34W,667M,4M,479BGA CPU_2_33GHZU07001 CRITICAL337S3393

BOOTROM_DEVELU6301 CRITICAL1341S1922 IC,EFI,BOOTROM DEVELOPMENT (UNLOCKED),M59

U6301 CRITICAL1 IC,EFI,BOOTROM FINAL (LOCKED),M59 BOOTROM_FINAL341S2006

CRITICALIC,SMC,HS8/2116 U5800 SMC_BLANK1338S0274

VRAM_256_HYNIXU8900,U8950,U9000,U9050333S0351 CRITICAL4 IC,SGRAM,GDDR3,16MX32,700MHZ,136 FBGA

M59_TPM TPM

CAP22UF_SAM,CAP22UF_SAM_CRITCAP22UF_ALLSAM

CAP22UF_MURA,CAP22UF_MURA_CRITCAP22UF_ALLMURA

CAP22UF_TAIYO,CAP22UF_SAM_CRITCAP22UF_MIXSAM

CAP22UF_TAIYO,CAP22UF_MURA_CRITCAP22UF_MIXMURA

VRAM_128_SAMSUNGIC,SGRAM,GDDR3,8MX32,700MHZ,136 FBGA CRITICALU8900,U8950,U9000,U90504333S0354

IC,SGRAM,GDDR3,16MX32,700MHZ,136 FBGA4 CRITICAL VRAM_256_SAMSUNG333S0350 U8900,U8950,U9000,U9050

U12001 CRITICALIC,945GM,NORTHBRIDGE338S0269

341S1929 SMC_PRGRM1 U5800 CRITICALIC,PRGRM,SMC (NEW),M59

GPU_MEM_256M,VRAM_256_SAMSUNGVRAM_SAM256

GPU_MEM_256M,GPU_MEM_NOT_SAM,VRAM_256_INFINEONVRAM_INF256

VRAM_SAM128 VRAM_128_SAMSUNG

ITP,KBDLED_HAS,LPCPLUS,LVDS_PD,MEMVREF_S3M59_COMMON2

M59_COMMON3 MEMVTT_EN_PU,RTUSB_ESD,SMC_PRGRM,USB_C_OC_PU,USB_D_OC_PU,USB_E_OC_PU

GPU_MEM_NOT_SAM,VRAM_128_INFINEONVRAM_INF128

630-7920 PCBA,2.33,256VR-SS,MUR-CAP,M59,MBP15 EEE_X35,M59_COMMON,CPU_2_33GHZ,VRAM_SAM256,CAP22UF_ALLMURA,ODD_NONLOCK_CONN

630-7851 PCBA,2.33,256VR-SS,SAM-CAP,M59,MBP15 EEE_WTG,M59_COMMON,CPU_2_33GHZ,VRAM_SAM256,CAP22UF_ALLSAM,ODD_NONLOCK_CONN

PCBA,2.16,128VR-SS,SAM-CAP,M59,MBP15630-7849 EEE_WTE,M59_COMMON,CPU_2_16GHZ,VRAM_SAM128,CAP22UF_ALLSAM,ODD_NONLOCK_CONN

PCBA,2.16,128VR-SS,MUR-CAP,M59,MBP15630-7919 EEE_X34,M59_COMMON,CPU_2_16GHZ,VRAM_SAM128,CAP22UF_ALLMURA,ODD_NONLOCK_CONN

630-7967 PCBA,2.33,256VR-SS,MUR_TYO-CAP,M59,MBP15 EEE_XAF,M59_COMMON,CPU_2_33GHZ,VRAM_SAM256,CAP22UF_MIXMURA,ODD_NONLOCK_CONN

CRITICALLBL,P/N LABEL,PCB,28MM X 6 MM1826-4393 EEE_WTG[EEE:WTG]

EEE_X34CRITICAL[EEE:X34]826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM

EEE_X35[EEE:X35]826-4393 CRITICAL1 LBL,P/N LABEL,PCB,28MM X 6 MM

PCBA,2.16,128VR-QM,SS_TY-CAP,M59,MBP15 EEE_XBY,M59_COMMON,CPU_2_16GHZ,VRAM_INF128,CAP22UF_MIXSAM,ODD_NONLOCK_CONN630-7986

PCBA,2.16,128VR-QM,MU_TY-CAP,M59,MBP15630-7987 EEE_XBZ,M59_COMMON,CPU_2_16GHZ,VRAM_INF128,CAP22UF_MIXMURA,ODD_NONLOCK_CONN

PCBA,2.33,256VR-QM,SS_TY-CAP,M59,MBP15 EEE_XC0,M59_COMMON,CPU_2_33GHZ,VRAM_INF256,CAP22UF_MIXSAM,ODD_NONLOCK_CONN630-7988

PCBA,2.33,256VR-QM,MU-CAP,M59,MBP15630-7985 EEE_XBX,M59_COMMON,CPU_2_33GHZ,VRAM_INF256,CAP22UF_ALLMURA,ODD_NONLOCK_CONN

EEE_XBU,M59_COMMON,CPU_2_16GHZ,VRAM_INF128,CAP22UF_ALLSAM,ODD_NONLOCK_CONN630-7982 PCBA,2.16,128VR-QM,SS-CAP,M59,MBP15

CRITICALLBL,P/N LABEL,PCB,28MM X 6 MM [EEE:WTE] EEE_WTE1826-4393

LBL,P/N LABEL,PCB,28MM X 6 MM1 CRITICAL826-4393 [EEE:XC0] EEE_XC0

TPMU6700 CRITICALIC, TPM, 28-PIN TSSOP1341S1789

IC,ICH7M,BGA1 CRITICALU2100343S0385

333S0358 VRAM_128_HYNIX4 CRITICALIC,SGRAM,GDDR3,8MX32,700MHZ,136 FBGA U8900,U8950,U9000,U9050

IC,EEPROM,SERIAL IIC,8KBIT,SO81 U4102 CRITICAL341S1797

M59_COMMON1 BOOTROM_FINAL,ENET_LOWPWR_EN,ENETPWR_S3AC,GPU_BB_CTL,D3CPGOOD_3V3

M59_COMMON ALTERNATE,COMMON,M59_COMMON1,M59_COMMON2,M59_COMMON3

353S1461 Screened ISL6262 for ISL9504ALL353S1465

PCBA,2.33,256VR-SS,SAM_TYO-CAP,M59,MBP15630-7966 EEE_XAE,M59_COMMON,CPU_2_33GHZ,VRAM_SAM256,CAP22UF_MIXSAM,ODD_NONLOCK_CONN

128S0060 330uF,2V,9MOHM,D2128S0094 ALL

PCBA,2.33,256VR-QM,SS-CAP,M59,MBP15630-7984 EEE_XBW,M59_COMMON,CPU_2_33GHZ,VRAM_INF256,CAP22UF_ALLSAM,ODD_NONLOCK_CONN

ALL128S0095 330uF,2V,6MOHM,D2128S0060

105

SYNC_DATE=N/ASYNC_MASTER=N/A

051-7270

BOM Configuration

B

4

PCBA,2.16,128VR-SS,SAM_TYO-CAP,M59,MBP15630-7964 EEE_XAC,M59_COMMON,CPU_2_16GHZ,VRAM_SAM128,CAP22UF_MIXSAM,ODD_NONLOCK_CONN

EEE_XAD,M59_COMMON,CPU_2_16GHZ,VRAM_SAM128,CAP22UF_MIXMURA,ODD_NONLOCK_CONN630-7965 PCBA,2.16,128VR-SS,MUR_TYO-CAP,M59,MBP15

PCBA,2.16,128VR-QM,MU-CAP,M59,MBP15 EEE_XBV,M59_COMMON,CPU_2_16GHZ,VRAM_INF128,CAP22UF_ALLMURA,ODD_NONLOCK_CONN630-7983

PCBA,2.33,256VR-QM,MU_TY-CAP,M59,MBP15630-7989 EEE_XC1,M59_COMMON,CPU_2_33GHZ,VRAM_INF256,CAP22UF_MIXMURA,ODD_NONLOCK_CONN

IC,88E8053,GIGABIT ENET XCVR,64P QFN, NO CRITICALU41011338S0270

IC,ATI,M56L-LLP,GRPHXCRTL,LF 880BGA U84001 CRITICAL338S0368

LOW POWER CLOCK SYNTHESIZER, 68PIN1 CRITICALU3301359S0109

[EEE:XC1]1 CRITICALLBL,P/N LABEL,PCB,28MM X 6 MM826-4393 EEE_XC1

LBL,P/N LABEL,PCB,28MM X 6 MM [EEE:XBZ]1 CRITICAL826-4393 EEE_XBZ

LBL,P/N LABEL,PCB,28MM X 6 MM [EEE:XBY]1826-4393 CRITICAL EEE_XBY

[EEE:XBW]1826-4393 LBL,P/N LABEL,PCB,28MM X 6 MM CRITICAL EEE_XBW

LBL,P/N LABEL,PCB,28MM X 6 MM EEE_XBV[EEE:XBV]826-4393 CRITICAL1

CRITICAL[EEE:XAC] EEE_XAC826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM

EEE_XAD826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM CRITICAL[EEE:XAD]

[EEE:XAE] EEE_XAE826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM CRITICAL

[EEE:XAF]LBL,P/N LABEL,PCB,28MM X 6 MM EEE_XAF1 CRITICAL826-4393

LBL,P/N LABEL,PCB,28MM X 6 MM EEE_XBU[EEE:XBU]826-4393 CRITICAL1

128S0061128S0081 ALL 150uF,6.3V,25MOHM,C2

376S0445 ALL Si7806ADN for FDM6296376S0448

152S0435 ALL152S0287 Alternates for Coilcraft MSS5131

TDK Ethernet XFMR for E&EALL157S0011157S0030

ALL353S1278353S1381 ISL60002 for REF3133 SMC AVREF Supply

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

Power Supply NO_TESTsEXPOSED_VIANO_TEST

FUNC_TEST

FUNC_TEST

FUNC_TESTFUNC_TEST

FUNC_TEST

LPC+ Debug Connector

Fan Connectors

Left I/O Data Connector

Functional Test Points

Battery Digital Connector

Left ALS Connector

Left I/O Power Connector

Request for at least 10 GND test points

called out separately in these notes.

NOTE: 10 additional GND test points are

FUNC_TEST

should have a via with 10-mil soldermask

EXPOSED_VIA property indicates that the net

Misc EXPOSED_VIA Nets

opening for use as engineering probe point.

EXPOSED_VIA

EXPOSED_VIA

CPU FSB NO_TESTsNO_TEST

2 TPs per

FUNC_TEST

8 TPs, 2 with each of above TP pairs

FUNC_TEST

Thermal Diode Connectors

Current Sense Calibration

FUNC_TEST

Other Func Test Points

RTC Battery ConnectorFUNC_TEST

Camera ConnectorFUNC_TEST

FUNC_TEST

Inverter Connector

Functional / ICT TestSYNC_DATE=N/ASYNC_MASTER=N/A

5 105

B051-7270

TRUE GND_CHASSIS_INVERTER

INVERTER_PWMTRUE

GND_INVERTERTRUE

PP5V_INVERTER_SWTRUE

PPBUS_S0_INVERTERTRUE

=USB2_CAMERA_N

=USB2_CAMERA_P

=PP5V_S3_CAMERATRUEGNDTRUE

PPVBATT_G3C_RTCTRUE

LTALS_OUTTRUE

SMC_ONOFF_LTRUE

PM_SYSRST_LTRUE

=PP1V05_S0_REGTRUE

HSTHMSNS_DX_PTRUE

TRUE HSTHMSNS_DX_N

RSFSTHMSNS_D_PTRUERSFSTHMSNS_D_NTRUE

TRUE ISENSE_CAL_EN

=PP5V_S0_ISENSECALTRUE

=PP1V8_S3_REGTRUE=PP1V5_S0_REGTRUE

TRUE PPVCORE_S0_GPU

TRUE PPVCORE_S0_CPU

TRUE GND

TRUE SMC_TRST_L

FSB_LOCK_LTRUEFSB_REQ_L<4..0>TRUE

FSB_HIT_LTRUEFSB_HITM_LTRUE

FSB_DSTBP_L<3..0>TRUE TRUE

TRUE FSB_DSTBN_L<3..0>TRUE

TRUE FSB_DRDY_L

FSB_DINV_L<3..0>TRUE TRUE

FSB_DBSY_LTRUE

FSB_D_L<63..0>TRUE

FSB_BNR_LTRUEFSB_BREQ0_LTRUE

TRUE FSB_ADSTB_L<1..0>TRUE

TRUE FSB_ADS_L

FSB_A_L<31..3>TRUE

TRUE CK410_XTAL_IN

P3V3S5_UGTRUE

P3V3S5_FSETTRUE

P3V3S5_ISENTRUE

P3V3S5_LGTRUE

P3V3S5_FB_RCTRUE

P3V3S5_COMPTRUE

P3V3S5_COMP_RTRUE

P3V3S5_FBTRUE

P1V5S0_RUNSSTRUE

P3V3S5_BOOTTRUE

P3V3S5_BOOT_RTRUE

P1V05S0_PHASETRUE

P1V05S0_LGTRUE

P1V05S0_UGTRUE

P1V05S0_ISENTRUE

P1V05S0_FB_RCTRUE

P1V05S0_FBTRUE

P1V05S0_FSETTRUE

P1V05S0_COMPTRUE

P1V05S0_BOOT_RTRUE

P1V05S0_COMP_RTRUE

P1V05S0_BOOTTRUE

IMVP6_VDIFFTRUE

IMVP6_OCSETTRUE

IMVP6_VDIFF_RCTRUE

IMVP6_DFBTRUE

IMVP6_COMP_RCTRUE

IMVP6_FBTRUE

GPUVCORE_UGTRUE

GPUVCORE_PHASETRUE

GPUVCORE_ISENTRUE

GPUVCORE_LGTRUE

GPUBBN_FBTRUE

GPUVCORE_FBTRUE

GPUVCORE_FB_RCTRUE

GPUBBP_ADJTRUE

TRUE GPUVCORE_FSETTRUE GPUVCORE_COMP

TRUE P3V42G3H_FB

TRUE P1V05S0_COMP

TRUE P1V05S0_FSET

TRUE P3V3S5_FSETTRUE P3V3S5_COMP

TRUE P1V2S3_RT

TRUE P1V2S3_RUNSS

TRUE SB_CLK100M_SATA_NTRUE SB_CLK100M_SATA_PTRUE DMI_N2S_N<1..0>TRUE DMI_N2S_P<1..0>

TRUE EXCARD_CLKREQ_L

TRUE =PPBUS_G3H_LIO_CONN

TRUE GND

PCIE_WAKE_LTRUE

=SMBUS_LIO_SB_SDATRUE

=SMBUS_LIO_SB_SCLTRUE

=SMBUS_LIO_SMC_SDATRUE

PCIE_CLK100M_MINI_NTRUE=SMBUS_LIO_SMC_SCLTRUE

PCIE_CLK100M_MINI_PTRUE

=PCIE_MINI_D2R_NTRUE=PCIE_MINI_D2R_PTRUE

=PCIE_MINI_R2D_PTRUE

TRUE =PCIE_MINI_R2D_N

TRUE SYS_ONEWIRE

TRUE LIO_P3V3S0_EN_L

TRUE SMC_BATT_ISET

EXCARD_OC_LTRUE

ACZ_RST_LTRUE

LTUSB_OC_LTRUE

TRUE GND_BATT

TRUE GND

ALS_GAINTRUE

=PP3V3_S3_LTALSTRUE

TRUE FWH_INIT_L

TRUE PM_SUS_STAT_L

TRUE SMC_TCK

TRUE SMC_NMI

TRUE SV_SET_UP

TRUE =PCIE_EXCARD_R2D_N

TRUE SMC_TDI

TRUE INT_SERIRQ

TRUE LPC_AD<2>TRUE PCI_CLK_PORT80_LPC

LPC_AD<3>TRUE

=PP5V_S0_FAN_LTTRUE

FAN_RT_PWMTRUE

FAN_LT_TACHTRUE

FAN_LT_PWMTRUE

FAN_RT_TACHTRUE

TRUE PCIE_CLK100M_EXCARD_P

ACZ_BITCLKTRUE

TRUE SMC_TMS

TRUE LPC_AD<0>

TRUE LPC_FRAME_L

TRUE PM_CLKRUN_L

TRUE BOOT_LPC_SPI_L

TRUE DEBUG_RST_L

TRUE =PP5V_S0_LPCPLUS

ACZ_SDATAIN<0>TRUE

TRUE LPC_AD<1>

TRUE SMC_TX_L

TRUE SMC_RST_L

TRUE SMC_RX_L

GND_AUDIOTRUE

GND_AUDIO_PWRTRUE

TRUE =PP3V42_G3H_LIO

TRUE PP5V_S0_AUDIO_PWR

TRUE SMC_MD1

SMC_TDOTRUE

TRUE SMC_SYS_ISETTRUE LIO_BATT_ISENSE

LIO_DCIN_ISENSETRUE

TRUE LIO_P3V3S3_EN

TRUE SMC_BATT_TRICKLE_EN_L

TRUE MINI_CLKREQ_L

TRUE SMC_EXCARD_CP

LIO_PLT_RESET_LTRUE

TRUE SMC_EXCARD_PWR_EN

TRUE ACZ_SYNC

TRUE =USB2_LT_PTRUE =USB2_LT_N

TRUE =USB2_EXCARD_PTRUE =USB2_EXCARD_N

=PCIE_EXCARD_R2D_PTRUE

=PCIE_EXCARD_D2R_PTRUE

TRUE SMC_ADAPTER_EN

TRUE =SMBUS_BATT_SDA

TRUE SMC_BS_ALRT_L

TRUE =SMBUS_BATT_SCL

=PCIE_EXCARD_D2R_NTRUE

TRUE PCIE_CLK100M_EXCARD_N

TRUE PP5V_S0_AUDIO

=PP5V_S5_LIOTRUE

TRUE =PPDCIN_G3H_LIO

=PP1V5_S0_LIOTRUE

TRUE SMC_BC_ACOKTRUE SMC_BATT_CHG_EN

ACZ_SDATAOUTTRUE

TRUE =PP3V3_S5_LPCPLUS

IMVP6_RBIASTRUEIMVP6_COMPTRUE

P5VS5_RUNSSTRUEP1V5S0_RUNSSTRUE

84D6 12D6

84D6

84D6

84D6

12C6

12B4

12B4

12B4

12B6

84D6

58C6

51B4

51B5

78C2

84D6

7C4

7C4

7C4

7C4

84C6

12D4

51B5

58C6

58C6

58C6

58C6

58C6

58C6

58C6

50B3

50B3

50A2

50C6

49B7

65D8

84D6

12B4

84D6

84D6

7C3

7C3

84D6

7C3

84D6

7C3

84D6

84D6

12C4

84D6

12C4

64C6

47C3

50B2

50B3

84B4

78C6

51C5

50A2

51B5

51B5

51B5

51C5

51C5

51C5

84B4

51B4

51C4

51C4

51C4

51B4 84B4

51C4

50B2

51B5

50B2

51B4

50A2

50A2

84B4

49D5

66B5

50A2

50A2

84B4

64C6

45C3

45B3

65B1

78C6

50B2

26C5

63A2

53A8

65A1

65B8

65C8

51B4

12B4

12A4

12B4

12B4

7B4

7B4

12B4

7B4

12B4

7B4

12C4

12C4

7D8

12C4

7D8

63D6

63C6

60C4

63B7

63A7

63A7

63B7

63D6

63C6

61B7

34C3

34C3

22D2

22D2

47C6

66C4

39C6

47C3

47C3

47C3

47C3

47C3

47C3

48C6

48C6

48C6

48C6

49B7

64C6

49B5

47C6

47B3

47C6

49B5

78C5

50D3

49C5

50B2

51B5

23C3

48C6

50B2

49C7

49C7

51C5

49C7

65A1

47B3

47B6

50B2

49D7

49C7

49C5

49C7

51B4

65A1

47B6

49D7

49C7

50D6

49C7

65D3

51B4

50B2

49B5

53C3

53C5

64A6

49D7

47C6

49B7

47C6

49B7

47B6

47C3

47C3

47C3

47C3

48C6

48C6

47C6

66B5

50B2

66B5

48B6

47B3

65B1

65A8

65C6

49C5

49D7

47B6

65D3

64A6

60C4

6A8

76A5

76A5

76B5

76B5

6C3

6D3

45C3 26D6

55C7

49C5

23C5

53A4

52C5

52C5

52D5

52C5

49B7

53A8

62C1

60C1

65D1

49C1

7D6

7D8

7D6

7D6

7B3

7B3

7D6

7B3

7D6

7B3

7D6

7D6

7C8

7D6

7C8

33C6

63D4

5D7

63C4

63C4

63C2

5D7

63C6

63C6

5D7

63D4

63D4

63B5

63A5

63B5

63A5

63A3

63A7

5D7

5D7

63B5

63A7

63B5

59C7

59C6

59B8

59B6

59B8

59B7

68D5

68C5

68C5

68C5

68A3

68C7

68C3

68B7

68C7

68C7

64C3

5C7

5B7

5B7

5B7

61B6

41C4

21B6

21B6

14B4

14B4

34A3

65C3

23C8

27B6

27B6

27D1

34D4

27D1

34D4

47C3

47C3

47B3

47B3

47C6

47B6

47B6

6C3

21C7

6D3

66B5

6D5

65C3

21C4

23C5

49C5

49C1

23B6

47B3

49B5

23C8

21D4

34D6

21D4

56C7

56B3

56B6

56B6

56B3

34C3

21C7

49B5

21D4

21C5

23C8

22B3

26B1

51C4

21C7

21D4

46B5

49C3

46B5

47A4

47A4

47D6

47D4

49C1

49B5

47C6

47C6

47B6

47B6

47B6

34A3

47B6

26C1

47B6

21C7

6D3

6D3

6C3

6C3

47B3

47B3

43B7

27C1

49C5

27C1

47B3

34B3

47C4

47C6

47C6

47D6

47B6

47C6

21C7

51C4

59C7

59B7

60C5

5B7

IN OUT

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

USB Port "H" = Reserved

Frame holes

Left CPU TM Hole

Top CPU TM Hole

Right CPU TM Hole

Add 2 blind vias per hole per side to GND

Bottom Left GPU TM Hole

Top GPU Right TM Hole

Thermal Module Holes

"ENET_LOWPWR_EN" are mutually-exclusive.

Chassis connection to be made at the mounting hole east of the LVDS connector

USB Port "G" = Bluetooth (M13L)

USB Port "E" = ExpressCard

USB Port "F" = IR Receiver

USB Port "C" = Left USB 2.0 Port

NOTE: NB_CFG<13..12> require test access

USB Port "B" = Trackpad (Geyser)

USB Port "A" (Debug Port) = Right USB 2.0 Port

USB Port "D" = Camera

FireWire Aliases

RAM door (Torx) holes

Chassis GNDs

LVDS pulldown aliases

Ethernet Power Management Support

Inverter PWM Reset Alias

NOTE: BOM options "USB_G_OC_PU" and

ZT0602

1HOLE-VIA-P5RP25

R06001 2

ENET_LOWPWR_EN

5%1/16W

402

0

MF-LF

C06301

2

0.01UF10%50VX7R402

ZT0630

1HOLE-VIA-P5RP25

C06311

2

0.01UF10%50VX7R402

ZT0631

1HOLE-VIA-P5RP25

C06101

2402X7R50V10%0.01UF

ZT0610

1HOLE-VIA-P5RP25

C06111

2

0.01UF10%50VX7R402

ZT0611

1HOLE-VIA-P5RP25 C06121

2402X7R50V10%0.01UF

ZT0612

1HOLE-VIA-P5RP25

C0602 1

2402X7R50V10%

0.01UF

C0600 1

2402X7R50V10%

0.01UF

ZT0615

1HOLE-VIA-P5RP25

ZT0614

1HOLE-VIA-P5RP25

ZT0613

1HOLE-VIA-P5RP25

C06131

2402X7R50V10%0.01UF

C06141

2402X7R50V10%0.01UF

C06151

2402X7R50V10%0.01UF

SH06001

2

3SHLD-SM-LF

OG-503040

R06011

2

05%1/16WMF-LF402

Signal Aliases/Misc Comps

6 105

B051-7270

SYNC_MASTER=N/A SYNC_DATE=N/A

M59_INVERTER_PLT_RST_L =INVERTER_PWM_PLT_RST_L

ENET_CTRL25MAKE_BASE=TRUENO_TEST=TRUE

NC_ENET_CTRL25

=LVDS_PD_L_DATA_N<2> LVDS_L_DATA_CONN_N<2>MAKE_BASE=TRUE

=LVDS_PD_L_DATA_P<2> LVDS_L_DATA_CONN_P<2>MAKE_BASE=TRUE





=LVDS_PD_L_CLK_P LVDS_L_CLK_CONN_PMAKE_BASE=TRUE

=LVDS_PD_U_DATA_N<2> LVDS_U_DATA_CONN_N<2>MAKE_BASE=TRUE

=LVDS_PD_L_CLK_N LVDS_L_CLK_CONN_NMAKE_BASE=TRUE

=LVDS_PD_U_DATA_P<2> LVDS_U_DATA_CONN_P<2>MAKE_BASE=TRUE





=LVDS_PD_U_CLK_PMAKE_BASE=TRUELVDS_U_CLK_CONN_P

=LVDS_PD_U_CLK_NMAKE_BASE=TRUELVDS_U_CLK_CONN_N

MAKE_BASE=TRUEVOLTAGE=0VMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mmGND_CHASSIS_ENET

MIN_NECK_WIDTH=0.25 mm

GND_CHASSIS_DVI_BOT

VOLTAGE=0VMAKE_BASE=TRUE

MIN_LINE_WIDTH=0.5 mm

=GND_CHASSIS_FW_PORT2U

=GND_CHASSIS_FW_PORT1

=GND_CHASSIS_ENET

=GND_CHASSIS_DVI5

=GND_CHASSIS_DVI1

=GND_CHASSIS_DVI3

GND_CHASSIS_DVI_TOP


MAKE_BASE=TRUEVOLTAGE=0V


=GND_CHASSIS_DVI4

=GND_CHASSIS_DVI2

=GND_CHASSIS_FW_EMI_R

=GND_CHASSIS_RTUSB

=GND_CHASSIS_FW_PORT2L

GND_CHASSIS_RTUSBMIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mmVOLTAGE=0VMAKE_BASE=TRUE

GND_CHASSIS_LIOFLEX_HOLE

VOLTAGE=0VMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mm

GND_CHASSIS_BATTCONN_HOLE


GND_CHASSIS_RAMDOOR_HOLE_0MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mmVOLTAGE=0V

=GND_CHASSIS_CAMERA

=PP3V3_FWPHY_CORE TP_USB_H_NMAKE_BASE=TRUE

TP_USB_H_N

USB_G_P

USB_G_NUSB_BT_NMAKE_BASE=TRUE

MAKE_BASE=TRUEUSB_BT_P=USB_BT_P

=USB_BT_N

MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mmVOLTAGE=0V

GND_CHASSIS_LNDACARD_HOLE

VOLTAGE=0V

GND_CHASSIS_LVDS

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mm


GND_CHASSIS_RAMDOOR_HOLE_1

=PP1V95_FWPHY_CORE_LDO

PCI_REQ3_LMAKE_BASE=TRUE

=FW_PCI_REQ_LMAKE_BASE=TRUE

PCI_GNT3_L =FW_PCI_GNT_LMAKE_BASE=TRUE

PCI_AD<19> =FW_PCI_IDSELMAKE_BASE=TRUE

SMC_RSTGATE_L =SMC_FWRSTGATE_L

=PP1V8_FWPHY_OSC

=PP1V95_FWPHY

=PP3V3_FWPHY_REG

=PP3V3_FWLATEVG_ACTIVE

=PP3V3_FWPHY

MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.38 mm

PP1V95_FWPHYVOLTAGE=1.95V

MAKE_BASE=TRUE

USB_F_N

USB_B_P

MAKE_BASE=TRUETP_NB_CFG<8>

LTUSB_OC_LMAKE_BASE=TRUE

USB_F_P

=USB2_LT_N

=USB2_EXCARD_N

USB2_EXCARD_PMAKE_BASE=TRUE

MAKE_BASE=TRUEUSB2_CAMERA_N

USB2_CAMERA_PMAKE_BASE=TRUE

USB_E_N

USB_E_OC_L

USB_D_N

=USB2_LT_P

USB_TRACKPAD_NMAKE_BASE=TRUE

USB_TRACKPAD_PMAKE_BASE=TRUE

=RTUSB_OC_LMAKE_BASE=TRUERTUSB_OC_L

USB_C_N

USB_C_OC_L

USB_C_P

UNUSED_USB_B_OC_LMAKE_BASE=TRUE

USB_B_OC_L

USB_B_N

USB_A_OC_L

USB_A_N

USB_A_P

=USB2_RT_N

=USB2_RT_PMAKE_BASE=TRUEUSB2_RT_P

USB2_RT_NMAKE_BASE=TRUE

NC_CPU_A32_L

NO_TEST=TRUEMAKE_BASE=TRUE

NC_CPU_A33_L


NC_CPU_A34_L


NC_CPU_A35_L


NC_CPU_A37_L


NC_CPU_A38_L


NC_CPU_A39_L


NC_CPU_HFPLL


NC_CPU_SPARE0


NC_CPU_SPARE2


NC_CPU_SPARE1MAKE_BASE=TRUENO_TEST=TRUE

NC_CPU_SPARE4MAKE_BASE=TRUENO_TEST=TRUE

TP_CPU_A32_L

TP_CPU_A33_L

TP_CPU_A34_L

TP_CPU_A37_L

TP_CPU_A36_L

TP_CPU_A38_L

TP_CPU_A39_L

TP_CPU_APM1_L

TP_CPU_EXTBREF

TP_CPU_SPARE0

TP_CPU_SPARE2

TP_CPU_SPARE1

TP_CPU_SPARE4

USB_D_P

=USB_TRACKPAD_P

MAKE_BASE=TRUEUSB2_LT_P

USB2_LT_NMAKE_BASE=TRUE

NC_CPU_EXTBREF


TP_CPU_HFPLL

NC_CPU_APM0_LMAKE_BASE=TRUENO_TEST=TRUE

NC_CPU_APM1_L


NC_CPU_A36_L


=USB2_CAMERA_PTP_CPU_APM0_L

MEM_A_A<15..14>MAKE_BASE=TRUENO_TEST=TRUE

NC_MEM_A_A<15..14>

MEM_B_A<15..14>MAKE_BASE=TRUENO_TEST=TRUE

NC_MEM_B_A<15..14>

NB_CFG<4..3>MAKE_BASE=TRUE

TP_NB_CFG<4..3>

NB_CFG<6>MAKE_BASE=TRUE

TP_NB_CFG<6>

NB_CFG<8>


TP_NB_CFG<11..10>


TP_NB_CFG<15..14>

NB_CFG<17>MAKE_BASE=TRUE

TP_NB_CFG<17>


TP_NB_CFG<13..12>

SUS_CLK_SBMAKE_BASE=TRUE

TP_SB_SUS_CLK

TP_SB_XOR_T5


NC_SB_XOR_T5

TP_SB_XOR_V3


NC_SB_XOR_V3

TP_SB_XOR_U5


NC_SB_XOR_U5

TP_SB_XOR_W3


NC_SB_XOR_W3

TP_SB_XOR_V4


NC_SB_XOR_V4

SMC_RSTGATE_LMAKE_BASE=TRUE

TP_SMC_RSTGATE_L

=RTALS_GAINMAKE_BASE=TRUE

ALS_GAIN

ENET_CTRL12


NC_ENET_CTRL12

=USB_TRACKPAD_N

EXCARD_OC_LMAKE_BASE=TRUE

=USB_IR_N USB_IR_NMAKE_BASE=TRUE

USB_E_P

USB_D_OC_L

MAKE_BASE=TRUEUSB_IR_P=USB_IR_P

=USB2_EXCARD_P

=GND_CHASSIS_INVERTER

=GND_CHASSIS_LCD3

=GND_CHASSIS_LCD4

=GND_CHASSIS_LCD2

=GND_CHASSIS_LCD1

UNUSED_USB_D_OC_LMAKE_BASE=TRUE

MAKE_BASE=TRUEUSB2_EXCARD_N

=USB2_CAMERA_N

TP_CPU_A35_L

ENET_LOWPWR_ENSB_GPIO30


GND_CHASSIS_DIMM_NOTCH


GND_CHASSIS_RIGHT_FAN_NOTCH

GND_CHASSIS_RIGHT_FAN_HOLE


=PP3V3_FWLATEVGMIN_LINE_WIDTH=0.38 mm

MAKE_BASE=TRUEMIN_NECK_WIDTH=0.25 mm

VOLTAGE=3.3VPP3V3_FWPHY


GND_CHASSIS_INVERTER

MAKE_BASE=TRUE

TP_USB_H_PMAKE_BASE=TRUE

TP_USB_H_P

79C1

79C1

79C1

79C1

79C1

79C1

79C1

79D1

79C1

79C1

79C1

79C1

79D1

79D1

79C1

79C1

78C6

50B3

76D7

76D7

76D7

76D7

76D7

76D7

76D7

76D7

76D7

76D7

76D7

76D7

76D7

76D7

76D7

76D7

45C5

22C2 22C2

26D2

37C6

49D7

44B8

47C6

47C3

47C3

22D8

47C3

22D8

22D8

22D8

45B3

49D7

49B5

47C6

22D8

47C3

45C3

22D8

22C2 22C2

26C1 76A8

39C8

79C8 76C2

79C8 76C2

79C8 76C2

79D8 76C2

79D8 76C2

79D8 76C2

79C8 76C2

79B8 76C2

79C8 76C2

79B8 76B2

79B8 76C2

79B8 76C2

79C8 76C2

79C8 76C2

79B8 76B2

79B8 76B2

44A1

44C1

40B2

77A2

77B5

77A2

77A3

77A5

44A3

46B2

44A1

45B5

42C4 6C1 6C2

22C2

22C2

78C2

78C2

42C1

22B6 37D3

22B6 37D3

22A7 37B7

6D4 37A8

38B2

38D5

42C4

43A7

38D7

22C2

22C2

5C1

22C2

5B1

5B1 22C2

22C4

22C2

5B1

46C5

22C2

22C4

22C2

22C4

22C2

22C4

22C2

22C2

46B5

46B5

7C8

7B8

7B8

7B8

7B8

7B8

7B8

7B8

7B6

7B6

7B6

7B6

7B6

22C2

78C3

7B8

5A4 7B8

28C3

29C3

14C6

14C6

14C6

14C6

14C6

14C6

14C6

23C3

21C6

21C6

21C6

21C6

21C6

6B7

55C4 5B2

39C8

78C3

5C1

78B4

22C2

22C4

78B4

5B1

76A6

76C3

76B2

76D3

76D2

5A4

7B8

39B8 22C4

44A8

5A4

6C1 6C2

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IN

IN

IN

IN

IN

IN

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

OUT

OUT

OUT

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

IN

IN

IN

IN

IN

IN

IN

IN

OUT

A7*

RSVD14

RSVD15

BCLK1

BCLK0

RSVD20

RSVD17

RSVD18

RSVD19

RSVD16

RSVD13

RSVD12

THERMTRIP*

THERMDC

THERMDA

PROCHOT*

DBR*

TRST*

TMS

TDO

TDI

TCK

PREQ*

PRDY*

BPM3*

BPM1*

BPM2*

BPM0*

HITM*

HIT*

TRDY*

RS2*

RS1*

RS0*

RESET*

LOCK*

INIT*

IERR*

BR0*

DBSY*

DRDY*

DEFER*

BPRI*

BNR*

ADS*

RSVD11

RSVD6

RSVD7

RSVD8

RSVD1

RSVD2

RSVD3

RSVD4

RSVD5

RSVD9

RSVD10

SMI*

LINT0

LINT1

STPCLK*

IGNNE*

FERR*

A20M*

ADSTB1*

A30*

A31*

A27*

A28*

A29*

A26*

A25*

A24*

A22*

A23*

A21*

A20*

A19*

A18*

A17*

REQ4*

REQ3*

REQ1*

REQ0*

REQ2*

ADSTB0*

A14*

A15*

A16*

A13*

A12*

A11*

A10*

A9*

A8*

A6*

A5*

A4*

A3*

(1 OF 4)

THERM

HCLK

RESERVED

ADDR GROUP1

ADDR GROUP0

CONTROL

XDP/ITP SIGNALS

PSI*

SLP*

PWRGOOD

DPRSTP*

DPSLP*

DPWR*

COMP2

COMP3

COMP1

COMP0

DSTBP3*

DSTBN3*

DINV3*

D63*

D62*

D61*

D60*

D59*

D58*

D57*

D56*

D55*

D54*

D52*

D53*

D51*

D50*

D49*

D48*

DINV2*

DSTBN2*

D47*

DSTBP2*

D45*

D46*

D44*

D43*

D42*

D41*

D40*

D39*

D38*

D37*

D36*

D35*

D34*

D33*

D32*

BSEL2

DSTBN1*

BSEL0

BSEL1

TEST2

TEST1

DINV1*

DSTBP1*

D31*

D30*

D29*

D26*

D27*

D28*

D24*

D25*

D23*

D21*

D22*

D20*

D19*

D18*

D16*

D17*

DINV0*

DSTBP0*

DSTBN0*

D15*

D14*

D13*

D12*

D11*

D10*

D9*

D8*

D7*

D6*

D5*

D4*

D3*

D2*

D1*

D0*

GTLREF

NC

(2 OF 4)

MISC

DATA GRP0

DATA GRP2

DATA GRP1

DATA GRP3

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

0.1" AWAY

ROUTE TO TP VIA AND

SPARE[7-0],HFPLL:

STUB)

PM_THRMTRIP#

SHOULD CONNECT TO

CPU_PROCHOT_L TO SMC

COMP1,3 CONNECT WITH ZO=55OHM, MAKE

LAYOUT NOTE:

COMP0,2 CONNECT WITH ZO=27.4OHM, MAKE

TRACE LENGTH SHORTER THAN 0.5".

TRACE LENGTH SHORTER THAN 0.5".

ICH7-M AND GMCH

LAYOUT NOTE: 0.5" MAX LENGTH

PLACE TESTPOINT ON

FSB_IERR_L WITH A GND

PLACE GND VIA W/IN 1000 MILS

TCK PULL DOWN THROUGH 54.9 OHM(FOLLOW UP XDP DESIGN REFERENCE)SO THE TDI PULL UP THROUGH 54.9 OHM,TMS PULL UP THROUGH 54.9 OHM WE THROUGH THE ITP700FLEX CONNECTOR CONNECT TO PDB XDP BUFFER BOARD--ECM*50

CHANGE THE PULLS RESISTOR VALUE PER NAPA PLATFORM DG REV 0.9

WITHOUT T-ING (NO

AND CPU VR TO INFORM

CPU IS HOT

R07021

2

1%54.9

MF-LF402

1/16W

R07041

2

681/16W5%

402MF-LF

R07051

2

1K

MF-LF402

1%1/16W

R07061

2

2.0K

MF-LF402

1%1/16W

R07191 2

1%402

54.9

R07181 227.4

R07171 2

1% 402

54.9

R07161 227.4

402

R07301 2

NOSTUFF

402

0

R07071

2

1/16W5%

402MF-LF

1K

NOSTUFFR07121

2

511/16W5%

402MF-LF

R07031

2 402MF-LF1/16W1%54.9

R07201 2

1%402

54.9

R07211 254.9

4021%

R07221 2

1%402

54.9

U0700YONAH-BST1

CPUBGA

OMIT

U0700

CPUBGA

YONAH-BST1

OMIT

CPU 1 OF 2-FSB

7

B051-7270

105

SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)

=PP1V05_S0_CPU

=PP1V05_S0_CPU

=PP1V05_S0_CPU

=PP1V05_S0_CPU

XDP_TMS

XDP_TDI

XDP_TCK

FSB_A_L<3>FSB_A_L<4>FSB_A_L<5>FSB_A_L<6>

FSB_A_L<8>FSB_A_L<9>FSB_A_L<10>FSB_A_L<11>FSB_A_L<12>FSB_A_L<13>

FSB_A_L<16>FSB_A_L<15>FSB_A_L<14>

FSB_ADSTB_L<0>

FSB_REQ_L<0>FSB_REQ_L<1>

FSB_REQ_L<3>FSB_REQ_L<4>

FSB_A_L<17>FSB_A_L<18>FSB_A_L<19>FSB_A_L<20>FSB_A_L<21>

FSB_A_L<23>FSB_A_L<22>



FSB_A_L<31>FSB_A_L<30>

FSB_ADSTB_L<1>

CPU_A20M_LCPU_FERR_LCPU_IGNNE_L

CPU_STPCLK_L

CPU_NMICPU_INTR

CPU_SMI_L

TP_CPU_APM1_LTP_CPU_APM0_L

TP_CPU_A36_LTP_CPU_A35_LTP_CPU_A34_LTP_CPU_A33_LTP_CPU_A32_L

TP_CPU_A39_LTP_CPU_A38_LTP_CPU_A37_L

TP_CPU_HFPLL

FSB_ADS_LFSB_BNR_LFSB_BPRI_L

FSB_DEFER_LFSB_DRDY_LFSB_DBSY_L

FSB_BREQ0_L

FSB_IERR_L

FSB_LOCK_L

FSB_CPURST_LFSB_RS_L<0>FSB_RS_L<1>FSB_RS_L<2>FSB_TRDY_L

FSB_HITM_L

XDP_BPM_L<0>

XDP_BPM_L<2>XDP_BPM_L<1>

XDP_BPM_L<3>XDP_BPM_L<4>XDP_BPM_L<5>XDP_TCKXDP_TDIXDP_TDOXDP_TMSXDP_TRST_LXDP_DBRESET_L

CPU_PROCHOT_LCPU_THERMD_PCPU_THERMD_N

PM_THRMTRIP_L

TP_CPU_EXTBREF

TP_CPU_SPARE0

TP_CPU_SPARE3

TP_CPU_SPARE6TP_CPU_SPARE5TP_CPU_SPARE4

TP_CPU_SPARE7

FSB_CLK_CPU_PFSB_CLK_CPU_N

TP_CPU_SPARE2TP_CPU_SPARE1

FSB_A_L<7>

FSB_REQ_L<2> FSB_HIT_L

CPU_GTLREF

FSB_D_L<0>FSB_D_L<1>FSB_D_L<2>FSB_D_L<3>FSB_D_L<4>FSB_D_L<5>FSB_D_L<6>FSB_D_L<7>FSB_D_L<8>FSB_D_L<9>FSB_D_L<10>FSB_D_L<11>FSB_D_L<12>FSB_D_L<13>FSB_D_L<14>FSB_D_L<15>FSB_DSTBN_L<0>FSB_DSTBP_L<0>FSB_DINV_L<0>

FSB_D_L<17>FSB_D_L<16>

FSB_D_L<18>FSB_D_L<19>FSB_D_L<20>


FSB_D_L<23>




FSB_DSTBP_L<1>FSB_DINV_L<1>

CPU_TEST1

CPU_TEST2

CPU_BSEL<1>CPU_BSEL<0>

FSB_DSTBN_L<1>

CPU_BSEL<2>

FSB_D_L<32>FSB_D_L<33>FSB_D_L<34>FSB_D_L<35>FSB_D_L<36>FSB_D_L<37>FSB_D_L<38>FSB_D_L<39>FSB_D_L<40>FSB_D_L<41>FSB_D_L<42>FSB_D_L<43>FSB_D_L<44>


FSB_DSTBP_L<2>

FSB_D_L<47>FSB_DSTBN_L<2>

FSB_DINV_L<2>

FSB_D_L<48>FSB_D_L<49>FSB_D_L<50>FSB_D_L<51>


FSB_D_L<54>FSB_D_L<55>FSB_D_L<56>FSB_D_L<57>FSB_D_L<58>FSB_D_L<59>FSB_D_L<60>FSB_D_L<61>FSB_D_L<62>FSB_D_L<63>

FSB_DINV_L<3>

FSB_DSTBN_L<3>FSB_DSTBP_L<3>

CPU_COMP<0>CPU_COMP<1>

CPU_COMP<3>CPU_COMP<2>

FSB_DPWR_LCPU_DPSLP_LCPU_DPRSTP_L

CPU_PWRGDFSB_SLPCPU_LCPU_PSI_L

CPU_INIT_L

65D6

65D6

11C5

65D6

65D6

11C5

11B3

11C5

11C5

11B3

9B7

11B3

11B3

9B7

8C7

9B7

9B7

8C7

7D5

8C7

8C7

7D5 84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84C6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84C6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

50C1

84D6

84D6 84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

7B6

7D5

7D5

7B6

11B3

11B3

11B3

12D4

12D4

12D4

12D4

12D4

12D4

12D4

12D4

12D4

12D4

12C4

12D4

12D4

12C4

12B4

12B4

12A4

12A4

12C4

12C4

12C4

12C4

12C4

12C4

12C4

12C4

12C4

12C4

12C4

12C4

12C4

12C4

12C4

12C4

84C6

84C6

84C6

84C6

84C6

84C6

12C4

12C4

84D6

84D6

12B4

12B4

12C4

12B4

12C4

84D6

84D6

84D6

84D6

12B4

84C6

84C6

84C6

84C6

84C6

84C6

11B3

11B3

11B3

26C6

50D3

21C2

12D4

12A4 12B4

12D6

12D6

12D6

12D6

12D6

12D6

12D6

12D6

12D6

12D6

12D6

12D6

12D6

12C6

12C6

12C6

12B4

12B4

12B4

12C6

12C6

12C6

12C6

12C6

12C6

12C6

12C6

12C6

12C6

12C6

12C6

12C6

12C6

12C6

12C6

12B4

12B4

12B4

12C6

12C6

12C6

12C6

12C6

12C6

12C6

12B6

12B6

12B6

12B6

12B6

12B6

12B6

12B6

12B4

12B6

12B4

12B4

12B6

12B6

12B6

12B6

12B6

12B6

12B6

12B6

12B6

12B6

12B6

12B6

12B6

12B6

12B6

12B6

12B4

12B4

12B4

84D6

84C6

59C7

84C6

84C6

7B5

7B5

7B6

7B5

7C6

7C6

7C6

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

21C4

21C2

21C4

21C4

21C4

21C4

21C4

6C7

6D7

6D7

6D7

6D7

6D7

6D7

6D7

6D7

6D7

6C7

5D5

5D5

12C4

12B4

5D5

5D5

5D5

84C6

5D5

11B5

12A4

12A4

12A4

12A4

5D5

11B3

11B3

11B3

11B3

11B3

11B3

7A8

7B8

11B5

7B8

11B3

11B4

50C1

10B6

10B6

14B6

6C7

6C7

6C7

34D3

34D3

6C7

6C7

5D5

5D5 5D5

84C6

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

34B6

34C6

5D5

34B6

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

84C6

84C6

84C6

84C6

12B4

21C4

21C4

21C4

12A4

59C7

21C4

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

VSS_82

VSS_83

VSS_84

VSS_85

VSS_87

VSS_86

VSS_88

VSS_89

VSS_90

VSS_92

VSS_91

VSS_93

VSS_94

VSS_95

VSS_97

VSS_96

VSS_100

VSS_98

VSS_99

VSS_102

VSS_101

VSS_105

VSS_103

VSS_104

VSS_106

VSS_107

VSS_110

VSS_109

VSS_108

VSS_111

VSS_112

VSS_115

VSS_114

VSS_113

VSS_116

VSS_117

VSS_118

VSS_120

VSS_119

VSS_123

VSS_121

VSS_122

VSS_124

VSS_125

VSS_128

VSS_126

VSS_127

VSS_129

VSS_130

VSS_133

VSS_131

VSS_132

VSS_134

VSS_135

VSS_138

VSS_136

VSS_137

VSS_139

VSS_140

VSS_141

VSS_143

VSS_142

VSS_146

VSS_144

VSS_145

VSS_147

VSS_148

VSS_151

VSS_150

VSS_149

VSS_152

VSS_153

VSS_156

VSS_155

VSS_154

VSS_157

VSS_158

VSS_159

VSS_161

VSS_160

VSS_162

VSS_1

VSS_2

VSS_3

VSS_5

VSS_4

VSS_6

VSS_7

VSS_8

VSS_10

VSS_9

VSS_11

VSS_12

VSS_15

VSS_13

VSS_14

VSS_16

VSS_17

VSS_18

VSS_19

VSS_20

VSS_23

VSS_22

VSS_21

VSS_24

VSS_25

VSS_28

VSS_27

VSS_26

VSS_29

VSS_30

VSS_33

VSS_32

VSS_31

VSS_34

VSS_35

VSS_38

VSS_37

VSS_36

VSS_39

VSS_40

VSS_41

VSS_42

VSS_43

VSS_46

VSS_44

VSS_45

VSS_47

VSS_48

VSS_51

VSS_49

VSS_50

VSS_52

VSS_53

VSS_56

VSS_54

VSS_55

VSS_57

VSS_58

VSS_59

VSS_60

VSS_61

VSS_63

VSS_62

VSS_64

VSS_65

VSS_66

VSS_69

VSS_68

VSS_67

VSS_70

VSS_71

VSS_74

VSS_73

VSS_72

VSS_75

VSS_76

VSS_79

VSS_78

VSS_77

VSS_80

VSS_81

(4 OF 4)

VCC_67

VCC_64

VCC_66

VCC_65

VCC_63

VCC_62

VCC_61

VCC_59

VCC_60

VCC_58

VCC_57

VCC_56

VCC_54

VCC_55

VCC_53

VCC_51

VCC_52

VCC_49

VCC_50

VCC_48

VCC_47

VCC_46

VCC_44

VCC_45

VCC_43

VCC_41

VCC_42

VCC_40

VCC_39

VCC_38

VCC_36

VCC_37

VCC_33

VCC_35

VCC_34

VCC_31

VCC_32

VCC_29

VCC_30

VCC_28

VCC_26

VCC_27

VCC_23

VCC_25

VCC_24

VCC_22

VCC_21

VCC_20

VCC_18

VCC_19

VCC_17

VCC_16

VCC_15

VCC_13

VCC_14

VCC_12

VCC_10

VCC_11

VCC_8

VCC_9

VCC_7

VCC_6

VCC_5

VCC_3

VCC_4

VCC_2

VCC_1 VCC_68

VCC_69

VCC_71

VCC_70

VCC_72

VCC_74

VCC_76

VCC_75

VCC_78

VCC_77

VCC_79

VCC_81

VCC_80

VCC_84

VCC_82

VCC_83

VCC_86

VCC_85

VCC_87

VCC_89

VCC_88

VCC_90

VCC_91

VCC_92

VCC_94

VCC_93

VCC_95

VCC_96

VCC_97

VCC_99

VCC_98

VCC_100

VCCP_1

VCCP_2

VCCP_3

VCCP_4

VCCP_5

VCCP_6

VCCP_7

VCCP_9

VCCP_8

VCCP_11

VCCP_10

VCCP_12

VCCP_13

VCCP_14

VCCP_16

VCCP_15

VCCA

VID0

VID1

VID2

VID3

VID4

VID5

VID6

VSSSENSE

VCCSENSE

VCC_73(3 OF 4)

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

VCCA=1.5 ONLY

LAYOUT NOTE: CONNECT R0803

PULL-DOWN

IF NO USE, NEED PULL-UP OR

VID FOR CPU POWER SUPPLY

TRANSMISSION LINE

RESISTORS TERMINATE THE 55 OHM

LAYOUT NOTE:

(CPU CORE POWER)

(CPU IO POWER 1.05V)

STUB.

LAYOUT NOTE:

VCCSENSE AND VSSSENSE LINES

SHOULD BE OF EQUAL LENGTH

LOCATION WHERE THE TWO 54.9 OHM

BETWEEN VCCSENSE AND VSSSENSE AT THE

TO CONNECT A DIFFERENCTIAL PROBE

PROVIDE A TEST POINT (WITH NO STUB)

LAYOUT NOTE:

TO TP_VSSSENSE WITH NO

(CPU INTERNAL PLL POWER 1.5V)

ZO=27.4 OHM DIFFERNTIAL TRACE ROUTING.

CPU_VCCSENSE_P/CPU_VCCSENSE_N USE

9C2 84B6

9C2 84B6

9C2 84B6

9C2 84B6

9C2 84B6

9C2 84B6

R08031

2

100

MF-LF402

1%1/16W

9C2 84B6

59A1 84B6

59B1 84B6

R08021

2

1/16W1%

402MF-LF

100

U0700

OMIT

YONAH-BST1

BGACPU

U0700

OMIT

YONAH-BST1

BGACPU

SYNC_DATE=(MASTER)SYNC_MASTER=(MASTER)

1058

B051-7270

CPU 2 OF 2-PWR/GND

=PPVCORE_S0_CPU

=PP1V05_S0_CPU

=PP1V5_S0_CPU

CPU_VID<0>CPU_VID<1>CPU_VID<2>CPU_VID<3>CPU_VID<4>CPU_VID<5>CPU_VID<6>

CPU_VCCSENSE_N

CPU_VCCSENSE_P

=PPVCORE_S0_CPU

65D6 11C5

65D1

11B3

65D1

53D7

9B7

53D7

53A6

7D5

53A6

9D7

7B6

65C6

9D7

8B5

7B5

9B7

8D7

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

CPU VCORE HF AND BULK DECOUPLING

4x 330uF. 20x 22uF 0805

VCCA (CPU AVdd) Decoupling

1x 470uF, 6x 0.1uF 0402

between CPU and NB

1x 10uF, 1x 0.01uF

Resistors to allow for override of CPU VID

Will probably be removed before production

VCCP (CPU I/O) Decoupling

NOTE: This cap is shared

NCNC

CPU VCORE VID ConnectionsC09061

26.3V20%

CERM805

22UF

OMIT

C09041

26.3V20%

CERM

22UF

805

OMIT

C09161

26.3V20%

CERM

22UF

805

OMIT

C09141

26.3V20%

CERM

22UF

805

OMIT

C09081

26.3V20%

CERM

22UF

805

OMIT

C09031

26.3V20%

CERM

22UF

805

OMIT

C09071

26.3V20%

CERM

22UF

805

OMIT

C09021

26.3V20%

CERM

22UF

805

OMIT

C09011

2

22UF

805CERM

20%6.3V

OMIT

C09131

26.3V20%

CERM805

22UF

OMIT

C09121

2

805

22UF

CERM

20%6.3V

OMIT

C09111

2

805

22UF

CERM

20%6.3V

OMIT

C09191

26.3V20%

CERM

22UF

805

OMIT

C09361

2

0.1UF

CERM402

20%10V

C0935 1

2 3

470uF

CRITICALD2T

TANT2.5V20%

C09051

26.3V20%

CERM

22UF

805

OMIT

C09091

26.3V20%

CERM

22UF

805

OMIT

C09151

2

20%

CERM

22UF

6.3V

805

OMIT

C09171

26.3V20%

CERM

22UF

805

OMIT

C09371

2

0.1UF

CERM402

20%10V

C09381

2

0.1UF

CERM402

20%10V

C09391

2

0.1UF

CERM402

20%10V

C09401

2

0.1UF

CERM402

20%10V

C09411

2

0.1UF

CERM402

20%10V

C09181

2

22UF

CERM

20%6.3V

805

OMIT

C09811

216V

0.01UF

CERM402

20%

C0980 1

2X5R

10uF20%

6.3V

603

RP0990

1

2

3

4

8

7

6

5

SM-LF1/16W

5%

0

RP0991

1

2

3

4

8

7

6

5

SM-LF1/16W

5%

0C09501

23

330UF20%2.5VPOLYD2T

CRITICAL

C09521

23

CRITICAL

D2TPOLY2.5V20%330UF

C09531

23

330UF20%2.5VPOLYD2T

CRITICAL

C09541

23

CRITICAL

D2TPOLY2.5V20%330UF

C09101

2805

22UF

CERM

20%6.3V

OMIT

C09001

2 6.3V20%

CERM805

22UF

OMIT

CPU Decoupling & VID

051-7270


B

9 105

IMVP6_VID<6>

IMVP6_VID<5>

IMVP6_VID<4>

CPU_VID<6>

CPU_VID<5>

CPU_VID<4>

IMVP6_VID<3>

IMVP6_VID<2>

IMVP6_VID<1>

IMVP6_VID<0>

CPU_VID<3>

CPU_VID<2>

CPU_VID<1>

CPU_VID<0>

=PP1V05_S0_CPU

=PP1V5_S0_CPU

=PPVCORE_S0_CPU

65D6 11C5 11B3

65D1

8C7

53D7

7D5

53A6

84B6

84B6

84B6

84B6

84B6

84B6

84B6

7B6

65C6

8D7

59C7

59C7

59C7

8B7

8B7

8B7

59C7

59C7

59C7

59C7

8B7

8B7

8B7

8B7

7B5

8B7

8B5

IO

IO

IN

OUT

GND

VDD

SDATA

SCLK

THM*

ALERT*/

D+

D-

THM2*

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

PLACE U1001 NEAR THE U1200

CPU ZONE THERMAL SENSOR

ADD GND GUARD TRACE

FOR CPU_THERMD_P AND

CPU_THERMD_N

LAYOUT NOTE:

10 MIL SPACING

LAYOUT NOTE:

10 MIL TRACE

LAYER.

CPU_THERMD_N ON SAME

ROUTE CPU_THERMD_P AND

(TO CPU INTERNAL THERMAL DIODE)

(TC0D)C10011

2

0.001UF10%

402CERM50V

C1002 1

2

0.1UF

X5R16V10%

402

U10016

3

2

5

8

7

4

1

CRITICAL

TMP401MSOP

R10051

2MF-LF402

1/16W5%10K

R10061

2

1/16W5%

402

10K

MF-LF

R10011 2

499

1%1/16WMF-LF402

R10021 2

499

402MF-LF1/16W1%


051-7270 B

10 105

CPU MISC1-TEMP SENSOR

THRM_ALERT_L

THRM_ALERTSMB_THRM_CLK

SMB_THRM_DATA

THRM_CPU_DX_N

CPU_THERMD_N

THRM_CPU_DX_PCPU_THERMD_P

=PP3V3_S0_THRM_SNR

27D1

27D1

7C6

7C6

65B3

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IO

IO

IO

IO

IO

IO

OUT

IN

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

and to provide better feeding of the 1.5V NB rail through its current sense resistor

Note: This connection to 1V5_S0 is to steal this mounting pad to add to the 1.5V S0 shape

ROUTE THE TCK SIGNAL FROM ITP700FLEX CONNECTOR’S TCK PIN TO CPU’STCK PIN AND THEN FORK BACK FROM CPU TCK PIN AND ROUTE BACK TO ITP700FLEX

INDICATE THAT ITP IS USING TAP I/F, NC IN 945GM CHIPSET SYSTEM.

(FROM CK410M HOST 133/167MHZ)

(DEBUG PORT RESET)(AND WITH RESET BUTTON) TO ICH7M SYS_RST*, AND WITH SYSTEM RESET LOGIC

NC

NC

NC

(DBA#)

(DBR#)

(DEBUG PORT ACTIVE)

CPU ITP700FLEX DEBUG SUPPORT

(FBO)

(TCK)

518S0320

CONNECTOR’S FBO PIN.

ITP TCK SIGNAL LAYOUT NOTE:

R11001 2

MF-LF

22.6

1%1/16W

402

ITP

R11021 2

ITP

402

1%

22.6

1/16WMF-LF

R11031

2

54.91/16W1%

402MF-LF

ITP

C11001

2402X5R16V10%0.1UF

R11041

2

1/16W

240

402MF-LF

5%

J1101

1

10

11

12

13

14

15

16

17

18

19

2

20

21

22

23

24

25

26

27

28

29

3

30

4

5

6

7

8

9

F-RT-SM52435-2872

CRITICAL

ITPCONN

R11011

2

1/16W

402

54.91%

MF-LF

R11061

2MF-LF

680

402

5%1/16W


CPU ITP700FLEX DEBUG

051-7270 B

11 105

=PP1V05_S0_CPU

FSB_CPURST_L

XDP_BPM_L<0>

XDP_TCK

XDP_TDI

XDP_TDO

=PP3V3_S5_SB_PM

=PP1V05_S0_CPU

XDP_TMS

CPU_XDP_CLK_N

XDP_TRST_L

XDP_BPM_L<1>

XDP_BPM_L<2>

XDP_BPM_L<3>

XDP_BPM_L<4>

XDP_BPM_L<5>

XDP_TCK

CPU_XDP_CLK_P

ITP_TDO

XDP_DBRESET_L

ITPRESET_L

=PP1V5_S0_ITPMOUNT

65D6

65D6

11C5

11B3

9B7

9B7

8C7

8C7

7D5

84D6

11B3

65D3

7D5

11B3

7B6

12C4

84C6

7C6

7C6

26C5

7B6

7C6

84C6

84C6

84C6

84C6

84C6

84C6

7C6

84C6

26C6

7B5

7D6

7C6

7A8

7B8

7C6

23D1

7B5

7B8

34D3

7C6

7C6

7C6

7C6

7C6

7C6

7A8

34D3

7C6

84C6

65C6

IO

IO

IO

OUT

OUT

OUT

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

OUT

IO

OUT

OUT

OUT

OUT

IO

IO

IO

IO

IO

IN

IO

IN

IO

IO

HD4*

HD6*

HD16*

HTRDY*

HSLPCPU*

HRS1*

HRS0*

HHITM*

HLOCK*

HHIT*

HDSTBP2*

HDTSBP3*

HDSTBP1*

HDSTBP0*

HDSTBN3*

HDSTBN1*

HDSTBN2*

HDSTBN0*

HDINV2*

HDINV3*

HDINV1*

HDINV0*

HDVREF

HDRDY*

HDPWR*

HDEFER*

HDBSY*

HCPURST*

HBREQ0*

HBPRI*

HBNR*

HAVREF

HCLKIN*

HCLKIN

HYSWING

HYRCOMP

HYSCOMP

HXSWING

HXSCOMP

HXRCOMP

HA13*

HADS*

HADSTB0*

HD3*

HD2*

HD1*

HD0*

HD63*

HD62*

HD61*

HD60*

HD59*

HD58*

HD57*

HD56*

HD55*

HD54*

HD53*

HD52*

HD51*

HD50*

HD49*

HD48*

HD47*

HD46*

HD45*

HD44*

HD43*

HD42*

HD41*

HD40*

HD39*

HD38*

HD37*

HD36*

HD35*

HD34*

HD33*

HD32*

HD31*

HD29*

HD28*

HD27*

HD26*

HD25*

HD24*

HD23*

HD22*

HD21*

HD20*

HD19*

HD18*

HD17*

HD15*

HD10*

HD11*

HD12*

HD13*

HD14*

HD5*

HD7*

HD8*

HD9*

HA30*

HA29*

HA28*

HA27*

HA26*

HA25*

HA24*

HA23*

HA31*

HA20*

HA19*

HA18*

HA16*

HA15*

HA14*

HA21*

HA22*

HA17*

HA9*

HA8*

HA7*

HA6*

HA5*

HA4*

HA3*

HA10*

HA11*

HA12*

HADSTB1*

HREQ0*

HREQ1*

HREQ2*

HREQ3*

HD30*

HREQ4*

HRS2*

(1 OF 10)

HOST

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

C1211 1

2

402X5R16V10%

0.1uF

R12111

2

2001%1/16WMF-LF402

R12101

2

1001%1/16WMF-LF402

R12201

2

54.91%

1/16WMF-LF402

R12211

2402

MF-LF1/16W

1%24.9

R12251

2

2211%1/16WMF-LF402

R12261

2

1%1/16WMF-LF402

100C12261

2

0.1uF

402X5R16V10%

C12361

2

402X5R16V10%0.1uF

R12351

2

2211%1/16WMF-LF402

R12301

2

54.91%

1/16WMF-LF402

R12361

2

1%1/16WMF-LF402

100R12311

2402

MF-LF1/16W

1%24.9

U1200

H11

J12

G14

D9

J14

H13

J15

F14

D12

A11

C11

A12

A13

E13

G13

F12

B12

B14

C12

A14

H9

C14

D14

C9

E11

G11

F11

G12

F9

E8

B9

C13

J13

C6

F6

C7

AG2

AG1

B7

F1

J1

K7

J8

H4

J3

K11

G4

T10

W11

T3

U7

H1

U9

U11

T11

W9

T1

T8

T4

W7

U5

T9

J6

W6

T5

AB7

AA9

W4

W3

Y3

Y7

W5

Y10

H3

AB8

W2

AA4

AA7

AA2

AA6

AA10

Y8

AA1

AB4

K2

AC9

AB11

AC11

AB3

AC2

AD1

AD9

AC1

AD7

AC6

G1

AB5

AD10

AD4

AC8

G2

K9

K1

A7

C3

J7

W8

U3

AB10

J9

H8

K4

T7

Y5

AC4

K3

T6

AA5

AC5

K13

D3

D4

B3

D8

G8

B8

F8

A8

B4

E6

D6

E3

E7

E1

E2

E4

Y1

U1

W1

BGA

NB

945GM

OMIT


NB CPU Interface

B

12 105

051-7270

FSB_D_L<17>

FSB_DSTBN_L<2>

FSB_DSTBN_L<3>

FSB_DSTBP_L<1>

FSB_DSTBP_L<2>

FSB_DSTBP_L<3>

FSB_DINV_L<0>

FSB_DSTBN_L<0>

FSB_DINV_L<1>

FSB_DINV_L<2>

NB_FSB_VREF

FSB_D_L<1>

FSB_D_L<2>

FSB_D_L<4>

FSB_D_L<5>

FSB_D_L<6>

FSB_D_L<10>

FSB_D_L<9>

FSB_D_L<8>

FSB_D_L<7>

FSB_D_L<3>

FSB_D_L<0>

FSB_D_L<16>

FSB_TRDY_L

FSB_SLPCPU_L

FSB_RS_L<1>

FSB_RS_L<0>

FSB_HITM_L

FSB_LOCK_L

FSB_HIT_L

FSB_DSTBP_L<0>

FSB_DSTBN_L<1>

FSB_DINV_L<3>

FSB_DRDY_L

FSB_DPWR_L

FSB_DEFER_L

FSB_DBSY_L

FSB_CPURST_L

FSB_BREQ0_L

FSB_BPRI_L

FSB_BNR_L

FSB_CLK_NB_N

FSB_CLK_NB_P

NB_FSB_YSWING

NB_FSB_YRCOMP

NB_FSB_YSCOMP

NB_FSB_XSWING

NB_FSB_XSCOMP

FSB_A_L<13>

FSB_ADS_L

FSB_ADSTB_L<0>

FSB_D_L<63>

FSB_D_L<62>

FSB_D_L<61>

FSB_D_L<60>

FSB_D_L<59>

FSB_D_L<58>

FSB_D_L<57>

FSB_D_L<56>

FSB_D_L<55>

FSB_D_L<54>

FSB_D_L<53>

FSB_D_L<52>

FSB_D_L<51>

FSB_D_L<50>

FSB_D_L<49>

FSB_D_L<48>

FSB_D_L<47>

FSB_D_L<46>

FSB_D_L<45>

FSB_D_L<44>

FSB_D_L<43>

FSB_D_L<42>

FSB_D_L<41>

FSB_D_L<40>

FSB_D_L<39>

FSB_D_L<38>

FSB_D_L<37>

FSB_D_L<36>

FSB_D_L<35>

FSB_D_L<34>

FSB_D_L<33>

FSB_D_L<32>

FSB_D_L<31>

FSB_D_L<29>

FSB_D_L<28>

FSB_D_L<27>

FSB_D_L<26>

FSB_D_L<25>

FSB_D_L<24>

FSB_D_L<23>

FSB_D_L<22>

FSB_D_L<21>

FSB_D_L<20>

FSB_D_L<19>

FSB_D_L<18>

FSB_D_L<15>

FSB_D_L<11>

FSB_D_L<12>

FSB_D_L<13>

FSB_D_L<14>

FSB_A_L<30>

FSB_A_L<29>

FSB_A_L<28>

FSB_A_L<27>

FSB_A_L<26>

FSB_A_L<25>

FSB_A_L<24>

FSB_A_L<23>

FSB_A_L<31>

FSB_A_L<20>

FSB_A_L<19>

FSB_A_L<18>

FSB_A_L<16>

FSB_A_L<15>

FSB_A_L<14>

FSB_A_L<21>

FSB_A_L<22>

FSB_A_L<17>

FSB_A_L<9>

FSB_A_L<8>

FSB_A_L<7>

FSB_A_L<6>

FSB_A_L<5>

FSB_A_L<4>

FSB_A_L<3>

FSB_A_L<10>

FSB_A_L<11>

FSB_A_L<12>

FSB_ADSTB_L<1>

FSB_REQ_L<0>

FSB_REQ_L<1>

FSB_REQ_L<2>

FSB_REQ_L<3>

FSB_D_L<30>

FSB_REQ_L<4>

FSB_RS_L<2>

=PP1V05_S0_FSB_NB

=PP1V05_S0_FSB_NB

=PP1V05_S0_FSB_NB

NB_FSB_XRCOMP

65D6

65D6

65D6

34C8

34C8

34C8

34C6

34C6

34C6

34B8

34B8

34B8

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84C6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84D6

84C6

84D6

84D6

84D6

84D6

84D6

84D6

19D7

19D7

19D7

7C4

7C3

7B3

7B4

7C3

7B3

7C4

7C4

7B4

7C3

7C4

7C4

7C4

7C4

7C4

7C4

7C4

7C4

7C4

7C4

7C4

7C4

7D6

7D6

7D6

7C4

7B4

7B3

84D6

7D8

7D6

7D8

7B3

7B3

7B3

7B3

7B3

7B3

7B3

7B3

7B3

7B3

7B3

7B3

7B3

7B3

7C3

7C3

7C3

7C3

7C3

7C3

7C3

7C3

7C3

7C3

7C3

7C3

7C3

7C3

7C3

7C3

7C3

7C3

7B4

7B4

7B4

7B4

7B4

7B4

7B4

7B4

7B4

7B4

7B4

7B4

7B4

7C4

7C4

7C4

7C4

7C4

7C8

7C8

7C8

7C8

7C8

7C8

7C8

7C8

7C8

7C8

7C8

7C8

7D8

7D8

7D8

7C8

7C8

7C8

7D8

7D8

7D8

7D8

7D8

7D8

7D8

7D8

7D8

7D8

7C8

7D8

7D8

7D8

7D8

7B4

7D8

12C2

12C2

12B7

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

7A3

5D5

5D5

5D5

5D5

5D5

5D5

7B3

34D3

34D3

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

5D5

12A7

12B7

12A7

CRT_BLUE*

CRT_BLUE

CRT_GREEN*

CRT_GREEN

CRT_RED

CRT_DDC_CLK

CRT_RED*

HSYNC

CRT_DDC_DATA

CRT_VSYNC

CRT_IREF

TV_IRTNC

TV_IRTNB

TV_IREF

TV_IRTNA

TV_DACB_OUT

TV_DACC_OUT

TV_DACA_OUT

LB_DATA2

LB_DATA1

LB_DATA0

LB_DATA2*

LB_DATA1*

LB_DATA0*

LA_DATA2

LA_DATA1

LA_DATA0

LA_DATA2*

LA_DATA1*

LA_DATA0*

LB_CLK

LB_CLK*

LA_CLK

LA_CLK*

L_VDDEN

L_VREFL

L_VREFH

L_VBG

L_IBG

L_DDC_CLK

L_DDC_DATA

EXP_A_COMPI

EXP_A_COMPO

EXP_A_RXN0

EXP_A_RXN1

EXP_A_RXN2

EXP_A_RXN3

EXP_A_RXN4

EXP_A_RXN5

EXP_A_RXN6

EXP_A_RXN7

EXP_A_RXN8

EXP_A_RXN9

EXP_A_RXN10

EXP_A_RXN11

EXP_A_RXN12

EXP_A_RXN13

EXP_A_RXN15

EXP_A_RXN14

EXP_A_RXP0

EXP_A_RXP1

EXP_A_RXP2

EXP_A_RXP4

EXP_A_RXP3

EXP_A_RXP5

EXP_A_RXP6

EXP_A_RXP7

EXP_A_RXP10

EXP_A_RXP9

EXP_A_RXP8

EXP_A_RXP11

EXP_A_RXP12

EXP_A_RXP14

EXP_A_RXP13

EXP_A_RXP15

EXP_A_TXN1

EXP_A_TXN0

EXP_A_TXN3

EXP_A_TXN2

EXP_A_TXN6

EXP_A_TXN5

EXP_A_TXN4

EXP_A_TXN7

EXP_A_TXN8

EXP_A_TXN9

EXP_A_TXN10

EXP_A_TXN11

EXP_A_TXN12

EXP_A_TXN14

EXP_A_TXN13

EXP_A_TXN15

EXP_A_TXP0

EXP_A_TXP2

EXP_A_TXP1

EXP_A_TXP3

EXP_A_TXP4

EXP_A_TXP5

EXP_A_TXP7

EXP_A_TXP6

EXP_A_TXP8

EXP_A_TXP9

EXP_A_TXP10

EXP_A_TXP12

EXP_A_TXP11

EXP_A_TXP13

EXP_A_TXP14

EXP_A_TXP15

L_CLKCTLB

L_BKLTEN

L_CLKCTLA

L_BKLTCTL

(3 OF 10)

LVDS

TV

VGA

PCI-EXPRESS GRAPHICS

IN

IN

OUT

IN

OUT

OUT

OUT

OUT

IN

IN

OUT

OUT

OUT

OUT

IN

OUT

OUT

IO

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IO

IO

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

IO

IO

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

SDVO_FLDSTALL#

SDVO Alternate Function

SDVO_TVCLKIN#

SDVO_INT#

SDVO_TVCLKIN

SDVO_INT

SDVO_FLDSTALL

SDVOB_GREEN

SDVOB_RED

SDVOC_CLKN

SDVOC_BLUE#

SDVOC_GREEN#

SDVOC_RED#

SDVOB_CLKN

SDVOB_BLUE#

SDVOB_GREEN#

SDVOB_RED#

SDVOB_CLKP

SDVOB_BLUE

SDVOC_RED

SDVOC_GREEN

SDVOC_BLUE

SDVOC_CLKP

Otherwise, tie VCCD_LVDS to GND also.

LVDS Disable

VCCD_LVDS must remain powered with proper decoupling.

Tie R/R#/G/G#/B/B# and IREF to VCC Core rail, tie

filtering components. Unused DAC outputs should

Tie DACx_OUT, IRTNx, and IREF to 1.5V power rail.

VCCA_TVBG to 1.5V power rail. Tie VSSA_TVBG to GND.

rail, and tie VSSA_CRTDAC and VCC_SYNC to GND.

Component: DACA, DACB & DACC

Tie VCCD_TVDAC, VCCD_QTVDAC, VCCA_TVDACx, and

connect to GND through 75-ohm resistors.

S-Video: DACB & DACC only

Unused DAC outputs must remain powered, but can omit

HSYNC and VSYNC to GND. Tie VCCA_CRTDAC to VCC Core

TV-Out Signal Usage:

Composite: DACA only

TV-Out Disable

CRT Disable

Can leave all signals NC if LVDS is not implemented

Tie VCC_TXLVDS and VCCA_LVDS to GND. If SDVO is used

U1200

E23

D23

C26

C25

C22

B22

J22

A21

B21

H23

D40

D38

F34

G38

V34

W38

Y34

AA38

AB34

AC38

H34

J38

L34

M38

N34

P38

R34

T38

D34

F38

T34

V38

W34

Y38

AA34

AB38

G34

H38

J34

L38

M34

N38

P34

R38

F36

G40

V36

W40

Y36

AA40

AB36

AC40

H36

J40

L36

M40

N36

P40

R36

T40

D36

F40

T36

V40

W36

Y40

AA36

AB40

G36

H40

J36

L40

M36

N40

P36

R40

G23

D32

J30

H30

H29

G26

G25

B38

C35

F32

C33

C32

A32

A33

B37

C37

B34

B35

A36

A37

E26

E27

F30

G30

D29

D30

F28

F29

A16

C18

A19

J20

B16

B18

B19

OMIT

945GMNBBGA

R13101

2

24.91%1/16WMF-LF402

NB PEG / Video InterfacesSYNC_DATE=(MASTER)SYNC_MASTER=(MASTER)

13 105

B051-7270

TV_DACA_OUT

TV_DACB_OUT

TV_DACC_OUT

TV_IREF

TV_IRTNA

TV_IRTNB

TV_IRTNC

PEG_D2R_N<7>

PEG_D2R_N<9>

PEG_D2R_N<15>

CRT_BLUE_L

CRT_BLUE

CRT_GREEN_L

CRT_GREEN

CRT_RED

CRT_DDC_CLK

CRT_RED_L

CRT_DDC_DATA

CRT_IREF

LVDS_B_DATA_P<2>

LVDS_B_DATA_P<1>

LVDS_B_DATA_P<0>

LVDS_B_DATA_N<2>

LVDS_B_DATA_N<1>

LVDS_B_DATA_N<0>

LVDS_A_DATA_P<2>

LVDS_A_DATA_P<1>

LVDS_A_DATA_P<0>

LVDS_A_DATA_N<2>

LVDS_A_DATA_N<1>

LVDS_A_DATA_N<0>

LVDS_B_CLK_P

LVDS_B_CLK_N

LVDS_A_CLK_P

LVDS_A_CLK_N

LVDS_VDDEN

LVDS_VREFL

LVDS_VREFH

TP_LVDS_VBG

LVDS_IBG

LVDS_DDC_CLK

LVDS_DDC_DATA

PEG_COMP

PEG_D2R_N<0>

PEG_D2R_N<1>

PEG_D2R_N<2>

PEG_D2R_N<3>

PEG_D2R_N<4>

PEG_D2R_N<5>

PEG_D2R_N<6>

PEG_D2R_N<8>

PEG_D2R_N<10>

PEG_D2R_N<11>

PEG_D2R_N<12>

PEG_D2R_N<13>

PEG_D2R_N<14>

PEG_D2R_P<0>

PEG_D2R_P<1>

PEG_D2R_P<2>

PEG_D2R_P<4>

PEG_D2R_P<3>

PEG_D2R_P<5>

PEG_D2R_P<6>

PEG_D2R_P<7>

PEG_D2R_P<10>

PEG_D2R_P<9>

PEG_D2R_P<8>

PEG_D2R_P<11>

PEG_D2R_P<12>

PEG_D2R_P<14>

PEG_D2R_P<13>

PEG_D2R_P<15>

PEG_R2D_C_N<1>

PEG_R2D_C_N<0>

PEG_R2D_C_N<3>

PEG_R2D_C_N<2>

PEG_R2D_C_N<6>

PEG_R2D_C_N<5>

PEG_R2D_C_N<4>

PEG_R2D_C_N<7>

PEG_R2D_C_N<8>

PEG_R2D_C_N<9>

PEG_R2D_C_N<10>

PEG_R2D_C_N<11>

PEG_R2D_C_N<12>

PEG_R2D_C_N<14>

PEG_R2D_C_N<13>

PEG_R2D_C_N<15>

PEG_R2D_C_P<0>

PEG_R2D_C_P<2>

PEG_R2D_C_P<1>

PEG_R2D_C_P<3>

PEG_R2D_C_P<4>

PEG_R2D_C_P<5>

PEG_R2D_C_P<7>

PEG_R2D_C_P<6>

PEG_R2D_C_P<8>

PEG_R2D_C_P<9>

PEG_R2D_C_P<10>

PEG_R2D_C_P<12>

PEG_R2D_C_P<11>

PEG_R2D_C_P<13>

PEG_R2D_C_P<14>

PEG_R2D_C_P<15>

LVDS_BKLTEN

LVDS_CLKCTLA

LVDS_BKLTCTL

=PP1V5_S0_NB_PCIE

LVDS_CLKCTLB

CRT_VSYNC_R

CRT_HSYNC_R

65C6

19D5

19D5

19D5

19D5

19D5

19C5

19C5

67C1

67C1

67B1

19D5

19D5

19D5

19D5

19D5

19D5

19D5

19D5

19D5

79C3

79C3

79D3

79D3

79C3

79D3

79D3

79D3

79D3

79D3

79D3

79D3

79C3

79C3

79D3

79D3

79A4

19D3

19D3

19D3

79A7

79A7

67D1

67D1

67D1

67D1

67C1

67C1

67C1

67C1

67B1

67B1

67B1

67B1

67B1

67D1

67D1

67D1

67D1

67D1

67C1

67C1

67C1

67C1

67C1

67C1

67B1

67B1

67B1

67B1

67B1

67D5

67D5

67D5

67D5

67C5

67C5

67C5

67C5

67C5

67C5

67B5

67B5

67B5

67B5

67B5

67B5

67D5

67D5

67D5

67D5

67D5

67C5

67C5

67C5

67C5

67C5

67B5

67B5

67B5

67B5

67B5

67B5

79A4

19D3

79A4

19D7

19D3

19D5

19D5

SM_CS0*RSVD15

RSVD14

SM_CKE2

RSVD2

RSVD3

RSVD6

RSVD4

RSVD5

RSVD8

RSVD7

RSVD9

RSVD1

RSVD10

RSVD11

RSVD12

RSVD13

CFG1

CFG0

CFG2

CFG3

CFG4

CFG6

CFG5

CFG7

CFG8

CFG9

CFG10

CFG11

CFG12

CFG13

CFG14

CFG17

CFG16

CFG15

CFG18

CFG19

CFG20

PM_BM_BUSY*

PM_EXTTS0*

PM_EXTTS1*

PW_THRMTRIP*

PWROK

RSTIN*

SDVO_CTRLCLK

SDVO_CTRLDATA

ICH_SYNC*

CLK_REQ*

NC2

NC3

NC4

NC5

NC6

NC7

NC8

NC9

NC0

NC1

NC13

NC12

NC11

NC10

NC18

NC17

NC16

NC15

NC14

SM_CK0

SM_CK1

SM_CK2

SM_CK0*

SM_CK3

SM_CK1*

SM_CK2*

SM_CK3*

SM_CKE0

SM_CKE1

SM_CKE3

SM_CS1*

SM_CS2*

SM_CS3*

SMOCDCOMP0

SMOCDCOMP1

SM_ODT1

SM_ODT0

SM_ODT2

SMRCOMP*

SM_ODT3

SMRCOMP

SMVREF0

SMVREF1

G_CLKIN*

G_CLKIN

D_REFCLKIN*

D_REFCLKIN

D_REFSSCLKIN*

D_REFSSCLKIN

DMI_RXN0

DMI_RXN1

DMI_RXN2

DMI_RXN3

DMI_RXP0

DMI_RXP1

DMI_RXP2

DMI_RXP3

DMI_TXN0

DMI_TXN1

DMI_TXN2

DMI_TXN3

DMI_TXP0

DMI_TXP2

DMI_TXP1

DMI_TXP3

DDR MUXING

CFG

NC

PM

CLK

DMI

MISC

(2 OF 10)

RSVD

IN

IN

IN

IN

IN

OUT

OUT

IN

IN

IN

IO

IO

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

NC

NC

NC

IPU

IPU

NC

NCIPU

IPU

IPU

IPU

IPU

IPU

IPU

IPU

IPU

IPU

IPU

IPU

IPD

IPU

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC(D_PLLMON1#)

(VSS_MCHDETECT)

(H_PCREQ#)

(H_PLLMON1#)

(H_PLLMON1)

(TV_DCONSEL1)

(TV_DCONSEL0)

(TESTIN#)

(H_PROCHOT#)

(D_PLLMON1)

(H_EDRDY#)

(LB_DATAP3)

(LB_DATAN3)

(LA_DATAP3)

(LA_DATAN3)

IPD

IPD

NC

NC

U1200

K16

K18

E16

D15

G15

K15

C15

H16

G18

H15

J25

K27

J18

J26

F18

E15

F15

E18

D19

D16

G16

H32

A26

A27

D41

C40

AE35

AF39

AG35

AH39

AC35

AE39

AF35

AG39

AE37

AF41

AG37

AH41

AC37

AE41

AF37

AG41

AG33

AF33

K28

D1

C41

B2

AY41

AY1

AW41

AW1

A40

A4

A39

A3

C1

BA41

BA40

BA39

BA3

BA2

BA1

B41

G28

F25

H26

G6

AH33

AH34

T32

J29

A41

A35

A34

D28

D27

R32

F3

F7

AG11

AF11

H7

J19

K30

H28

H27

AY35

AW35

AR1

AT1

AW7

AY7

AW40

AY40

AU20

AT20

BA29

AY29

AW13

AW12

AY21

AW21

BA13

BA12

AY20

AU21

AL20

AF10

AT9

AV9

AK1

AK41

OMIT

945GMNBBGA

R14301 2

100

5%1/16WMF-LF402

R14411

2

1/16WMF-LF

5%

402

10KR14401

2

MF-LF1/16W

5%

402

10K

C14161

2

20%10VCERM402

0.1uFC1415 1

2

20%10VCERM402

0.1uF

R14101

2

80.6

MF-LF402

1%1/16W

R14111

2

80.6

MF-LF402

1%1/16W

R14201

2

10K

MF-LF402

5%1/16W

14 105

B051-7270


NB Misc Interfaces

PM_EXTTS_L

NB_RST_IN_L_R

CLK_NB_OE_L

NB_CLK_DREFCLKIN_N

NB_CLK_DREFCLKIN_P

NB_CLK_DREFSSCLKIN_N

NB_CLK_DREFSSCLKIN_P

=PP3V3_S0_NB

NB_TV_DCONSEL1

NB_TV_DCONSEL0

TP_NB_XOR_LVDS_A35

TP_NB_TESTIN_L

PM_DPRSLPVR

=PP3V3_S0_NB

NB_CFG<18>

NB_CFG<13>

NB_CFG<11>

NB_CFG<8>

NB_RST_IN_L

DMI_N2S_P<3>

DMI_N2S_P<1>

DMI_N2S_P<2>

DMI_N2S_P<0>

DMI_N2S_N<3>

DMI_N2S_N<2>

DMI_N2S_N<1>

DMI_N2S_N<0>

DMI_S2N_P<3>

DMI_S2N_P<2>

DMI_S2N_P<1>

DMI_S2N_P<0>

DMI_S2N_N<3>

DMI_S2N_N<2>

DMI_S2N_N<1>

DMI_S2N_N<0>

NB_CLK100M_GCLKIN_P

NB_CLK100M_GCLKIN_N

MEM_ODT<3>

MEM_ODT<0>

MEM_CKE<3>

MEM_CKE<1>

MEM_CKE<0>

MEM_CLK_N<3>

MEM_CLK_N<2>

MEM_CLK_N<1>

MEM_CLK_P<3>

MEM_CLK_N<0>

MEM_CLK_P<2>

MEM_CLK_P<1>

MEM_CLK_P<0>

NB_SB_SYNC_L

SDVO_CTRLDATA

SDVO_CTRLCLK

VR_PWRGOOD_DELAY

PM_THRMTRIP_L

PM_BMBUSY_L

NB_CFG<20>

NB_CFG<19>

NB_CFG<15>

NB_CFG<16>

NB_CFG<17>

NB_CFG<14>

NB_CFG<10>

NB_CFG<9>

NB_CFG<7>

NB_CFG<5>

NB_CFG<6>

NB_CFG<4>

NB_CFG<3>

NB_BSEL<2>

NB_BSEL<0>

NB_BSEL<1>

MEM_CS_L<0>

NB_CFG<12>

MEM_ODT<2>

MEM_ODT<1>

MEM_CS_L<3>

MEM_CS_L<2>

MEM_CS_L<1>

MEM_CKE<2>

=PP1V8_S3_MEM_NB

MEM_RCOMP_L

MEM_RCOMP

MEM_VREF_NB_0

MEM_VREF_NB_1

TP_NB_XOR_LVDS_A34

TP_NB_XOR_LVDS_D28

TP_NB_XOR_LVDS_D27

TP_NB_XOR_FSB2_H7

65B3

65B3

20B4

20B4

20A4

84C6

20A4

50C1

65B6

50D5

34B4

34B4

19C7

59C8

19C7

30C6

30C6

30D6

30D6

30D6

59C7

21C2

30D6

30C6

30C6

30D6

30D6

30D6

30D6

19D7

49B7

33B4

34B2

34B2

34B4

34B4

14C7

19D3

23C3

14D6

20B5

6C6

6D6

6D6

26C1

22D2

22D2

22D2

22D2

22D2

22D2

22D2

22D2

22D2

22D2

22D2

22D2

34C4

34C4

29B6

28B3

29C3

28C3

28C6

29D3

29A3

28A3

29D3

28D3

29A3

28A3

28D3

22A6

19D3

19D3

26B5

7C6

23C5

20A5

20B5

6D6

20C5

6D6

6D6

6D6

20B7

20C7

20C7

6D6

6D6

6D6

34B7

34C7

34B7

28B3

6C6

29B3

28B6

29B6

29B3

28B6

29C6

16B6

32B3

32B3

19D3

19D3

19D3

SA_DQ1

SA_DQ0

SA_DQ2

SA_DQ3

SA_DQ4

SA_DQ5

SA_DQ6

SA_DQ7

SA_DQ8

SA_DQ9

SA_DQ10

SA_DQ12

SA_DQ11

SA_DQ13

SA_DQ14

SA_DQ15

SA_DQ16

SA_DQ17

SA_DQ18

SA_DQ19

SA_DQ20

SA_DQ21

SA_DQ22

SA_DQ23

SA_DQ24

SA_DQ25

SA_DQ26

SA_DQ27

SA_DQ29

SA_DQ28

SA_DQ30

SA_DQ31

SA_DQ32

SA_DQ33

SA_DQ35

SA_DQ34

SA_DQ36

SA_DQ37

SA_DQ38

SA_DQ39

SA_DQ40

SA_DQ41

SA_DQ42

SA_DQ43

SA_DQ44

SA_DQ46

SA_DQ45

SA_DQ47

SA_DQ48

SA_DQ49

SA_DQ50

SA_DQ51

SA_DQ52

SA_DQ53

SA_DQ54

SA_DQ55

SA_DQ56

SA_DQ57

SA_DQ58

SA_DQ59

SA_DQ60

SA_DQ61

SA_DQ62

SA_DQ63

SA_BS1

SA_BS0

SA_BS2

SA_CAS*

SA_DM0

SA_DM1

SA_DM2

SA_DM3

SA_DM5

SA_DM4

SA_DM7

SA_DM6

SA_DQS0

SA_DQS2

SA_DQS1

SA_DQS3

SA_DQS5

SA_DQS4

SA_DQS6

SA_DQS7

SA_DQS3*

SA_DQS2*

SA_DQS4*

SA_DQS5*

SA_DQS6*

SA_DQS7*

SA_MA1

SA_MA0

SA_MA2

SA_MA3

SA_MA5

SA_MA4

SA_MA6

SA_MA7

SA_MA9

SA_MA8

SA_MA10

SA_MA11

SA_MA12

SA_MA13

SA_RAS*

SA_RCVENIN*

SA_RCVENOUT*

SA_WE*

SA_DQS1*

SA_DQS0*

(4 OF 10)

DDR SYSTEM MEMORY A

IO

IO

IO

IO

IO

IO

OUT

OUT

OUT

OUT

OUT

IO

OUT

OUT

IO

IO

IO

IO

IO

IO

IO

IO

IO IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

SB_DQ1

SB_DQ0

SB_DQ2

SB_DQ3

SB_DQ4

SB_DQ5

SB_DQ6

SB_DQ7

SB_DQ8

SB_DQ9

SB_DQ10

SB_DQ12

SB_DQ11

SB_DQ13

SB_DQ14

SB_DQ15

SB_DQ16

SB_DQ17

SB_DQ18

SB_DQ19

SB_DQ20

SB_DQ21

SB_DQ22

SB_DQ23

SB_DQ24

SB_DQ25

SB_DQ26

SB_DQ27

SB_DQ29

SB_DQ28

SB_DQ30

SB_DQ31

SB_DQ32

SB_DQ33

SB_DQ35

SB_DQ34

SB_DQ36

SB_DQ37

SB_DQ38

SB_DQ39

SB_DQ40

SB_DQ41

SB_DQ42

SB_DQ43

SB_DQ44

SB_DQ46

SB_DQ45

SB_DQ47

SB_DQ48

SB_DQ49

SB_DQ50

SB_DQ51

SB_DQ52

SB_DQ53

SB_DQ54

SB_DQ55

SB_DQ56

SB_DQ57

SB_DQ58

SB_DQ59

SB_DQ60

SB_DQ61

SB_DQ62

SB_DQ63

SB_BS1

SB_BS0

SB_BS2

SB_CAS*

SB_DM0

SB_DM1

SB_DM2

SB_DM3

SB_DM5

SB_DM4

SB_DM7

SB_DM6

SB_DQS0

SB_DQS2

SB_DQS1

SB_DQS3

SB_DQS5

SB_DQS4

SB_DQS6

SB_DQS7

SB_DQS3*

SB_DQS2*

SB_DQS4*

SB_DQS5*

SB_DQS6*

SB_DQS7*

SB_MA1

SB_MA0

SB_MA2

SB_MA3

SB_MA5

SB_MA4

SB_MA6

SB_MA7

SB_MA9

SB_MA8

SB_MA10

SB_MA11

SB_MA12

SB_MA13

SB_RAS*

SB_RCVENIN*

SB_RCVENOUT*

SB_WE*

SB_DQS1*

SB_DQS0*

(5 OF 10)

DDR SYSTEM MEMORY B

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

OUT

OUT

OUT

IO

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IO

OUT

OUT

OUT

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

OUT

IO

IO

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IO

OUT

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

OUT

OUT

OUT

IO

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IO

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

NC

NC

NC

NC

U1200AU12

AV14

BA20

AY13

AJ33

AM35

AL26

AN22

AM14

AL9

AR3

AH4

AJ35

AJ34

AR31

AP31

AN38

AM36

AM34

AN33

AK26

AL27

AM26

AN24

AM31

AK28

AL28

AM24

AP26

AP23

AL22

AP21

AN20

AL23

AP24

AM33

AP20

AT21

AR12

AR14

AP13

AP12

AT13

AT12

AL14

AL12

AJ36

AK9

AN7

AK8

AK7

AP9

AN9

AT5

AL5

AY2

AW2

AK35

AP1

AN2

AV2

AT3

AN1

AL2

AG7

AF9

AG4

AF6

AJ32

AG9

AH6

AF4

AF8

AH31

AN35

AP33

AK33

AK32

AT33

AU33

AN28

AN27

AM22

AM21

AN12

AM12

AN8

AL8

AP3

AN3

AG5

AH5

AY16

AU14

AU13

AT17

AV20

AV12

AW16

BA16

BA17

AU16

AV17

AU17

AW17

AT16

AW14

AK23

AK24

AY14

OMIT

NB945GM

BGA

U1200AT24

AV23

AY28

AR24

AK36

AR38

AT36

BA31

AL17

AH8

BA5

AN4

AK39

AJ37

AU38

AV38

AP38

AR40

AW38

AY38

BA38

AV36

AR36

AP36

AP39

BA36

AU36

AP35

AP34

AY33

BA33

AT31

AU29

AU31

AW31

AR41

AV29

AW29

AM19

AL19

AP14

AN14

AN17

AM16

AP15

AL15

AJ38

AJ11

AH10

AJ9

AN10

AK13

AH11

AK10

AJ8

BA10

AW10

AK38

BA4

AW4

AY10

AY9

AW5

AY5

AV4

AR5

AK4

AK3

AN41

AT4

AK5

AJ5

AJ3

AP41

AT40

AV41

AM39

AM40

AT39

AU39

AU35

AT35

AR29

AP29

AR16

AP16

AR10

AT10

AR7

AT7

AN5

AP5

AY23

AW24

AV24

BA27

AY27

AR23

AY24

AR28

AT27

AT28

AU27

AV28

AV27

AW27

AU23

AK16

AK18

AR27

OMIT

NB945GM

BGA

15 105

B051-7270

NB DDR2 InterfacesSYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)

MEM_B_DQ<1>

MEM_B_DQ<0>

MEM_B_DQ<2>

MEM_B_DQ<3>

MEM_B_DQ<4>

MEM_B_DQ<5>

MEM_B_DQ<6>

MEM_B_DQ<7>

MEM_B_DQ<8>

MEM_B_DQ<9>

MEM_B_DQ<10>

MEM_B_DQ<12>

MEM_B_DQ<11>

MEM_B_DQ<13>

MEM_B_DQ<14>

MEM_B_DQ<15>

MEM_B_DQ<16>

MEM_B_DQ<17>

MEM_B_DQ<18>

MEM_B_DQ<19>

MEM_B_DQ<20>

MEM_B_DQ<21>

MEM_B_DQ<22>

MEM_B_DQ<23>

MEM_B_DQ<24>

MEM_B_DQ<25>

MEM_B_DQ<26>

MEM_B_DQ<27>

MEM_B_DQ<29>

MEM_B_DQ<28>

MEM_B_DQ<30>

MEM_B_DQ<31>

MEM_B_DQ<32>

MEM_B_DQ<33>

MEM_B_DQ<35>

MEM_B_DQ<34>

MEM_B_DQ<36>

MEM_B_DQ<37>

MEM_B_DQ<38>

MEM_B_DQ<39>

MEM_B_DQ<40>

MEM_B_DQ<41>

MEM_B_DQ<42>

MEM_B_DQ<43>

MEM_B_DQ<44>

MEM_B_DQ<46>

MEM_B_DQ<45>

MEM_B_DQ<47>

MEM_B_DQ<48>

MEM_B_DQ<49>

MEM_B_DQ<50>

MEM_B_DQ<51>

MEM_B_DQ<52>

MEM_B_DQ<53>

MEM_B_DQ<54>

MEM_B_DQ<55>

MEM_B_DQ<56>

MEM_B_DQ<57>

MEM_B_DQ<58>

MEM_B_DQ<59>

MEM_B_DQ<60>

MEM_B_DQ<61>

MEM_B_DQ<62>

MEM_B_DQ<63>

MEM_B_BS<1>

MEM_B_BS<0>

MEM_B_BS<2>

MEM_B_CAS_L

MEM_B_DM<0>

MEM_B_DM<1>

MEM_B_DM<2>

MEM_B_DM<3>

MEM_B_DM<5>

MEM_B_DM<4>

MEM_B_DM<7>

MEM_B_DM<6>

MEM_B_DQS_P<0>

MEM_B_DQS_P<2>

MEM_B_DQS_P<1>

MEM_B_DQS_P<3>

MEM_B_DQS_P<5>

MEM_B_DQS_P<4>

MEM_B_DQS_P<6>

MEM_B_DQS_P<7>

MEM_B_DQS_N<3>

MEM_B_DQS_N<2>

MEM_B_DQS_N<4>

MEM_B_DQS_N<5>

MEM_B_DQS_N<6>

MEM_B_DQS_N<7>

MEM_B_A<1>

MEM_B_A<0>

MEM_B_A<2>

MEM_B_A<3>

MEM_B_A<5>

MEM_B_A<4>

MEM_B_A<6>

MEM_B_A<7>

MEM_B_A<9>

MEM_B_A<8>

MEM_B_A<10>

MEM_B_A<11>

MEM_B_A<12>

MEM_B_A<13>

MEM_B_RAS_L

MEM_B_WE_L

MEM_B_DQS_N<1>

MEM_B_DQS_N<0>

MEM_A_DQ<1>

MEM_A_DQ<0>

MEM_A_DQ<2>

MEM_A_DQ<3>

MEM_A_DQ<4>

MEM_A_DQ<6>

MEM_A_DQ<7>

MEM_A_DQ<8>

MEM_A_DQ<9>

MEM_A_DQ<10>

MEM_A_DQ<12>

MEM_A_DQ<11>

MEM_A_DQ<13>

MEM_A_DQ<14>

MEM_A_DQ<15>

MEM_A_DQ<16>

MEM_A_DQ<17>

MEM_A_DQ<18>

MEM_A_DQ<19>

MEM_A_DQ<20>

MEM_A_DQ<21>

MEM_A_DQ<22>

MEM_A_DQ<23>

MEM_A_DQ<24>

MEM_A_DQ<25>

MEM_A_DQ<26>

MEM_A_DQ<27>

MEM_A_DQ<29>

MEM_A_DQ<28>

MEM_A_DQ<30>

MEM_A_DQ<31>

MEM_A_DQ<32>

MEM_A_DQ<33>

MEM_A_DQ<35>

MEM_A_DQ<34>

MEM_A_DQ<36>

MEM_A_DQ<37>

MEM_A_DQ<38>

MEM_A_DQ<39>

MEM_A_DQ<40>

MEM_A_DQ<41>

MEM_A_DQ<42>

MEM_A_DQ<43>

MEM_A_DQ<44>

MEM_A_DQ<46>

MEM_A_DQ<45>

MEM_A_DQ<47>

MEM_A_DQ<48>

MEM_A_DQ<49>

MEM_A_DQ<50>

MEM_A_DQ<51>

MEM_A_DQ<52>

MEM_A_DQ<53>

MEM_A_DQ<54>

MEM_A_DQ<55>

MEM_A_DQ<56>

MEM_A_DQ<57>

MEM_A_DQ<58>

MEM_A_DQ<59>

MEM_A_DQ<60>

MEM_A_DQ<61>

MEM_A_DQ<62>

MEM_A_DQ<63>

MEM_A_BS<1>

MEM_A_BS<0>

MEM_A_BS<2>

MEM_A_CAS_L

MEM_A_DM<0>

MEM_A_DM<1>

MEM_A_DM<2>

MEM_A_DM<3>

MEM_A_DM<5>

MEM_A_DM<4>

MEM_A_DM<7>

MEM_A_DM<6>

MEM_A_DQS_P<0>

MEM_A_DQS_P<2>

MEM_A_DQS_P<1>

MEM_A_DQS_P<3>

MEM_A_DQS_P<5>

MEM_A_DQS_P<4>

MEM_A_DQS_P<6>

MEM_A_DQS_P<7>

MEM_A_DQS_N<3>

MEM_A_DQS_N<2>

MEM_A_DQS_N<4>

MEM_A_DQS_N<5>

MEM_A_DQS_N<6>

MEM_A_DQS_N<7>

MEM_A_A<1>

MEM_A_A<0>

MEM_A_A<2>

MEM_A_A<3>

MEM_A_A<5>

MEM_A_A<4>

MEM_A_A<6>

MEM_A_A<7>

MEM_A_A<9>

MEM_A_A<8>

MEM_A_A<10>

MEM_A_A<11>

MEM_A_A<12>

MEM_A_A<13>

MEM_A_RAS_L

MEM_A_WE_L

MEM_A_DQS_N<1>

MEM_A_DQS_N<0>

MEM_A_DQ<5>

30A6

30A6

30A6

30A6

30B6

30B6

30B6

30B6

30B6

30B6

30B6

30B6

30B6

30B6

30B6

30B6

30B6

30B6

30A6

30A6

30B6

30B6

30B6

30B6

30C6

30C6

30C6

30C6

30C6

30C6

30C6

30C6

30C6

30C6

30C6

30C6

30C6

30C6

30B6

30B6

29D6

29D3

29D6

29D3

29D6

29D3

29D3

29D6

29D3

29D3

29D6

29D3

29D3

29D6

29D6

29D6

29C3

29C3

29C3

29C6

29C6

29C6

29C3

29C6

29C6

29C6

29C3

29C6

29C6

29C3

29C3

29C3

29B3

29B6

29B6

29B6

29B6

29B3

29B3

29B3

29B6

29B6

29A6

29A6

29B3

29A3

29B3

29A3

29A3

29A6

29A3

29A6

29A6

29A3

29A6

29A3

29A3

29A3

29A3

29A6

29A6

29A6

29A6

29A3

29B3

29B6

29C6

29B6

29D3

29D3

29C3

29C6

29A6

29B3

29A3

29A6

29D6

29C6

29D6

29C3

29A3

29B6

29A3

29A6

29C3

29C6

29B6

29B3

29A3

29A6

29B6

29B3

29B3

29B6

29B6

29B3

29C3

29C3

29C6

29C6

29B6

29C3

29C6

29B3

29B3

29B6

29D6

29D6

28D3

28D3

28D3

28D3

28D6

28D6

28D6

28D3

28D3

28D6

28D3

28D6

28D6

28D6

28D3

28C6

28C3

28C6

28C6

28C6

28C3

28C3

28C3

28C3

28C6

28C3

28C6

28C3

28C6

28C6

28C3

28B3

28B6

28B6

28B3

28B3

28B6

28B3

28B6

28A3

28A6

28A3

28A6

28A3

28A6

28A6

28A3

28A6

28A3

28A6

28A6

28A3

28A6

28A3

28A3

28A3

28B3

28A6

28B6

28B6

28A6

28A3

28B3

28B3

28B6

28C6

28B6

28D3

28D3

28C3

28C6

28A3

28B3

28A6

28A6

28D6

28C6

28D6

28C3

28A6

28B6

28A3

28A3

28C3

28C6

28B6

28A6

28A3

28B3

28B6

28B3

28B3

28B6

28B6

28B3

28C3

28C3

28C6

28C6

28B6

28C3

28C6

28B3

28B3

28B6

28D6

28D6

28D6

VCC_SM19

VCC_SM107

VCC_SM105

VCC_SM106

VCC_SM102

VCC_SM104

VCC_SM103

VCC_SM100

VCC_SM101

VCC_SM98

VCC_SM99

VCC_SM97

VCC_SM95

VCC_SM96

VCC_SM93

VCC_SM94

VCC_SM92

VCC_SM91

VCC_SM90

VCC_SM89

VCC_SM88

VCC_SM86

VCC_SM87

VCC_SM85

VCC_SM84

VCC_SM83

VCC_SM81

VCC_SM80

VCC_SM82

VCC_SM79

VCC_SM78

VCC_SM77

VCC_SM74

VCC_SM75

VCC_SM76

VCC_SM73

VCC_SM72

VCC_SM70

VCC_SM71

VCC_SM68

VCC_SM67

VCC_SM69

VCC_SM65

VCC_SM66

VCC_SM64

VCC_SM63

VCC_SM62

VCC_SM61

VCC_SM60

VCC_SM59

VCC_SM58

VCC_SM56

VCC_SM57

VCC_SM55

VCC_SM53

VCC_SM54

VCC_SM52

VCC_SM50

VCC_SM51

VCC_SM49

VCC_SM48

VCC_SM46

VCC_SM47

VCC_SM44

VCC_SM45

VCC_SM43

VCC_SM41

VCC_SM42

VCC_SM40

VCC_SM39

VCC_SM37

VCC_SM38

VCC_SM36

VCC_SM34

VCC_SM35

VCC_SM32

VCC_SM33

VCC_SM30

VCC_SM31

VCC_SM28

VCC_SM29

VCC_SM27

VCC_SM26

VCC_SM25

VCC_SM23

VCC_SM24

VCC_SM22

VCC_SM21

VCC_SM20

VCC_SM18

VCC_SM16

VCC_SM17

VCC_SM15

VCC_SM13

VCC_SM14

VCC_SM11

VCC_SM12

VCC_SM10

VCC_SM9

VCC_SM8

VCC_SM7

VCC_SM6

VCC_SM5

VCC_SM4

VCC_SM3

VCC_SM0

VCC_SM1

VCC_SM2

VCC_110

VCC_109

VCC_108

VCC_105

VCC_106

VCC_107

VCC_104

VCC_103

VCC_101

VCC_100

VCC_102

VCC_98

VCC_99

VCC_96

VCC_97

VCC_95

VCC_94

VCC_93

VCC_92

VCC_91

VCC_90

VCC_88

VCC_89

VCC_87

VCC_86

VCC_85

VCC_83

VCC_84

VCC_82

VCC_80

VCC_81

VCC_79

VCC_78

VCC_76

VCC_77

VCC_74

VCC_73

VCC_75

VCC_72

VCC_71

VCC_70

VCC_69

VCC_68

VCC_67

VCC_66

VCC_65

VCC_64

VCC_62

VCC_63

VCC_61

VCC_60

VCC_59

VCC_57

VCC_58

VCC_55

VCC_56

VCC_53

VCC_54

VCC_52

VCC_50

VCC_51

VCC_49

VCC_46

VCC_47

VCC_48

VCC_44

VCC_45

VCC_43

VCC_42

VCC_41

VCC_40

VCC_39

VCC_38

VCC_37

VCC_36

VCC_34

VCC_35

VCC_33

VCC_32

VCC_31

VCC_30

VCC_28

VCC_29

VCC_25

VCC_26

VCC_27

VCC_24

VCC_23

VCC_21

VCC_20

VCC_22

VCC_13

VCC_14

VCC_12

VCC_16

VCC_15

VCC_17

VCC_18

VCC_19

VCC_11

VCC_10

VCC_9

VCC_8

VCC_7

VCC_4

VCC_5

VCC_6

VCC_2

VCC_3

VCC_0

VCC_1

(6 OF 10)

VCC

VCCAUX_NCTF57

VCCAUX_NCTF56

VCCAUX_NCTF55

VCCAUX_NCTF54

VCCAUX_NCTF53

VCCAUX_NCTF52

VCCAUX_NCTF51

VCCAUX_NCTF50

VCCAUX_NCTF49

VCCAUX_NCTF47

VCCAUX_NCTF48

VCCAUX_NCTF45

VCCAUX_NCTF44

VCCAUX_NCTF46

VCCAUX_NCTF40

VCCAUX_NCTF39

VCCAUX_NCTF37

VCCAUX_NCTF38

VCCAUX_NCTF36

VCCAUX_NCTF34

VCCAUX_NCTF35

VCCAUX_NCTF32

VCCAUX_NCTF33

VCCAUX_NCTF31

VCCAUX_NCTF30

VCCAUX_NCTF29

VCCAUX_NCTF27

VCCAUX_NCTF28

VCCAUX_NCTF26

VCCAUX_NCTF24

VCCAUX_NCTF25

VCCAUX_NCTF22

VCCAUX_NCTF21

VCCAUX_NCTF23

VCCAUX_NCTF42

VCCAUX_NCTF43

VCCAUX_NCTF41

VCCAUX_NCTF19

VCCAUX_NCTF20

VCCAUX_NCTF18

VCCAUX_NCTF17

VCCAUX_NCTF16

VCCAUX_NCTF14

VCCAUX_NCTF15

VCCAUX_NCTF13

VCCAUX_NCTF12

VCCAUX_NCTF11

VCCAUX_NCTF9

VCCAUX_NCTF10

VCCAUX_NCTF8

VCCAUX_NCTF7

VCCAUX_NCTF6

VCCAUX_NCTF5

VCCAUX_NCTF4

VCCAUX_NCTF3

VCCAUX_NCTF1

VCCAUX_NCTF0

VCCAUX_NCTF2

VSS_NCTF12

VSS_NCTF11

VSS_NCTF10

VSS_NCTF9

VSS_NCTF7

VSS_NCTF8

VSS_NCTF5

VSS_NCTF6

VSS_NCTF4

VSS_NCTF2

VSS_NCTF3

VSS_NCTF0

VSS_NCTF1

VCC_NCTF72

VCC_NCTF71

VCC_NCTF70

VCC_NCTF69

VCC_NCTF68

VCC_NCTF67

VCC_NCTF66

VCC_NCTF65

VCC_NCTF64

VCC_NCTF61

VCC_NCTF62

VCC_NCTF63

VCC_NCTF60

VCC_NCTF57

VCC_NCTF58

VCC_NCTF59

VCC_NCTF56

VCC_NCTF55

VCC_NCTF53

VCC_NCTF54

VCC_NCTF52

VCC_NCTF50

VCC_NCTF51

VCC_NCTF49

VCC_NCTF48

VCC_NCTF46

VCC_NCTF47

VCC_NCTF45

VCC_NCTF44

VCC_NCTF43

VCC_NCTF41

VCC_NCTF40

VCC_NCTF42

VCC_NCTF38

VCC_NCTF39

VCC_NCTF36

VCC_NCTF37

VCC_NCTF34

VCC_NCTF35

VCC_NCTF33

VCC_NCTF31

VCC_NCTF32

VCC_NCTF30

VCC_NCTF29

VCC_NCTF28

VCC_NCTF27

VCC_NCTF26

VCC_NCTF25

VCC_NCTF24

VCC_NCTF23

VCC_NCTF22

VCC_NCTF21

VCC_NCTF20

VCC_NCTF18

VCC_NCTF19

VCC_NCTF17

VCC_NCTF16

VCC_NCTF15

VCC_NCTF13

VCC_NCTF14

VCC_NCTF11

VCC_NCTF12

VCC_NCTF10

VCC_NCTF8

VCC_NCTF9

VCC_NCTF7

VCC_NCTF6

VCC_NCTF5

VCC_NCTF4

VCC_NCTF3

VCC_NCTF2

VCC_NCTF0

VCC_NCTF1

(7 OF 10)

NCTF

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

1.8V Max Current

Speed 1 Channel 2 Channel

400MTs 1300mA 2400mA

533MTs 1500mA 2800mA

667MTs 1700mA 3200mA

1.05V, Internal Graphics: 3500mA Max

1.5V, Internal Graphics: 5500mA Max

1.05V, External Graphics: 1500mA Max

1.05V or 1.5V

Place in cavity

Layout Note:

Layout Note:

Place near pin BA15

Place near pin BA23

Layout Note:

impacting part performance.

These connections can break without

NCTF balls are Not Critical To Function

U1200

AA33

W33

P32

M19

L19

N18

M18

L18

P17

N17

M17

N16

M16

N32

L16

M32

L32

J32

AA31

W31

V31

T31

R31

P33

P31

N31

M31

AA30

Y30

W30

V30

U30

T30

R30

N33

P30

N30

M30

L30

AA29

Y29

W29

V29

U29

R29

L33

P29

M29

L29

AB28

AA28

Y28

V28

U28

T28

R28

J33

P28

N28

M28

L28

P27

N27

M27

L27

P26

N26

AA32

L26

N25

M25

L25

P24

N24

M24

AB23

AA23

Y23

Y32

P23

N23

M23

L23

AC22

AB22

Y22

W22

P22

N22

W32

M22

L22

AC21

AA21

W21

N21

M21

L21

AC20

AB20

V32

Y20

W20

P20

N20

M20

L20

AB19

AA19

Y19

N19

AU41

AT41

AR34

AR6

AP6

AN6

AL6

AK6

AJ6

AV1

AJ1

BA30

AY30

AW30

AV30

AU30

AT30

AR30

AP30

AN30

AM41

AM30

AM29

AL29

AK29

AJ29

AH29

AJ28

AH28

AJ27

AH27

AU40

BA26

AY26

AW26

AV26

AU26

AT26

AR26

AJ26

AH26

AJ25

BA34

AH25

AJ24

AH24

BA23

AJ23

BA22

AY22

AW22

AV22

AU22

AY34

AT22

AR22

AP22

AK22

AJ22

AK21

AK20

BA19

AY19

AW19

AW34

AV19

AU19

AT19

AR19

AP19

AK19

AJ19

AJ18

AJ17

AH17

AV34

AJ16

AH16

BA15

AY15

AW15

AV15

AU15

AT15

AR15

AJ15

AU34

AJ14

AJ13

AH13

AK12

AJ12

AH12

AG12

AK11

BA8

AY8

AT34

AW8

AV8

AT8

AR8

AP8

BA6

AY6

AW6

AV6

AT6

BGA

NB

945GM

OMIT

C16101

2 CERM-X5R6.3V

402

0.47UF10%

C16211

2

603

20%

X5R6.3V

10uFC1620 1

2

10uF

6.3VX5R

20%

603

U1200AD27

AC27

AD26

AC26

AB26

AA26

Y26

W26

V26

U26

T26

R26

AB27

AD25

AC25

AB25

AA25

Y25

W25

V25

U25

T25

R25

AA27

AD24

AC24

AB24

AA24

Y24

W24

V24

U24

T24

R24

Y27

AD23

V23

U23

T23

R23

AD22

V22

U22

T22

R22

W27

AD21

V21

U21

T21

R21

AD20

V20

U20

T20

R20

V27

AD19

V19

U19

T19

AD18

AC18

AB18

AA18

Y18

W18

U27

V18

U18

T18

T27

R27

AG27

AF27

AG22

AF22

AG21

AF21

AG20

AF20

AG19

AF19

R19

AG18

AG26

AF18

R18

AG17

AF17

AE17

AD17

AB17

AA17

W17

V17

AF26

T17

R17

AG16

AF16

AE16

AD16

AC16

AB16

AA16

Y16

AG25

W16

V16

U16

T16

R16

AG15

AF15

AE15

AD15

AC15

AF25

AB15

AA15

Y15

W15

V15

U15

T15

R15

AG24

AF24

AG23

AF23

AE27

AE26

AC17

Y17

U17

AE25

AE24

AE23

AE22

AE21

AE20

AE19

AE18

945GMNBBGA

OMIT

C16111

2

10%0.47UF

402

6.3VCERM-X5R

C1612 1

2CERM-X5R6.3V

402

0.47UF10%

C16131

2 CERM-X5R6.3V

402

0.47UF10%

C1614 1

2CERM-X5R6.3V

402

0.47UF10%

C16151

2 CERM-X5R6.3V

402

0.47UF10%

NB Power 1SYNC_DATE=(MASTER)SYNC_MASTER=(MASTER)

051-7270 B

10516

=PP1V5_S0_NB_VCCAUX

=PPVCORE_S0_NB

=PPVCORE_S0_NB

NB_VCCSM_LF4

NB_VCCSM_LF5

NB_VCCSM_LF2

NB_VCCSM_LF1

=PP1V8_S3_MEM_NB

65D6

65D6

65B6

19D7

19D7

19D7

19D2

19D2

65B6

19C4

19C8

19C8

19D7

17B6

16C8

16D3

14C2

VTT0

VTT1

VTT2

VTT3

VTT4

VTT5

VTT6

VTT7

VTT8

VTT9

VTT10

VTT11

VTT12

VTT13

VTT15

VTT14

VTT16

VTT18

VTT17

VTT19

VTT20

VTT21

VTT22

VTT23

VTT24

VTT25

VTT27

VTT26

VTT28

VTT29

VTT31

VTT30

VTT32

VTT34

VTT33

VTT35

VTT36

VTT37

VTT39

VTT38

VTT40

VTT41

VTT42

VTT43

VTT44

VTT45

VTT48

VTT46

VTT47

VTT49

VTT50

VTT52

VTT51

VTT53

VTT55

VTT54

VTT57

VTT56

VTT58

VTT59

VTT60

VTT61

VTT62

VTT64

VTT63

VTT65

VTT66

VTT67

VTT69

VTT68

VTT70

VTT71

VTT73

VTT72

VTT74

VTT76

VTT75

VCCSYNC

VCC_TXLVDS0

VCC_TXLVDS1

VCC_TXLVDS2

VCC3G0

VCC3G1

VCC3G3

VCC3G2

VCC3G4

VCC3G6

VCC3G5

VCCA_3GPLL

VCCA_3GBG

VSSA_3GBG

VCCA_CRTDAC0

VCCA_CRTDAC1

VSSA_CRTDAC

VCCA_DPLLB

VCCA_DPLLA

VCCA_HPLL

VSSA_LVDS

VCCA_LVDS

VCCA_MPLL

VCCA_TVBG

VSSA_TVBG

VCCA_TVDACC0

VCCA_TVDACC1

VCCA_TVDACB0

VCCA_TVDACB1

VCCA_TVDACA0

VCCA_TVDACA1

VCCD_HMPLL0

VCCD_HMPLL1

VCCD_LVDS2

VCCD_LVDS0

VCCD_LVDS1

VCCD_TVDAC

VCC_HV1

VCC_HV2

VCC_HV0

VCCD_QTVDAC

VCCAUX19

VCCAUX18

VCCAUX17

VCCAUX16

VCCAUX14

VCCAUX15

VCCAUX13

VCCAUX12

VCCAUX11

VCCAUX10

VCCAUX0

VCCAUX1

VCCAUX2

VCCAUX3

VCCAUX4

VCCAUX6

VCCAUX5

VCCAUX9

VCCAUX8

VCCAUX7

VCCAUX21

VCCAUX20

VCCAUX23

VCCAUX24

VCCAUX22

VCCAUX25

VCCAUX26

VCCAUX29

VCCAUX28

VCCAUX27

VCCAUX30

VCCAUX31

VCCAUX33

VCCAUX32

VCCAUX34

VCCAUX35

VCCAUX36

VCCAUX38

VCCAUX37

VCCAUX39

VCCAUX40

POWER

(8 OF 10)

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

1500mA Max VCC3G/3GPLL

800mA Max

2mA Max

70mA Max VCCA_CRTDAC/VCCSYNC

20mA Max

24mA Max

10mA Max

50mA Max

50mA Max

45mA Max

45mA Max

120mA Max

150mA Max

See VCCSYNC

40mA Max

1900mA Max

60mA Max

U1200

AJ41

AB41

Y41

V41

R41

N41

L41

A23

B23

B25

C30

B30

A30

G41

AC33

F21

E21

B26

C39

AF1

A38

AF2

H20

E19

F19

C20

D20

E20

F20

AK31

AF31

AE30

AD30

AC30

AG29

AF29

AE29

AD29

AC29

AG28

AF28

AE31

AE28

AH22

AJ21

AH21

AJ20

AH20

AH19

P19

P16

AH15

AC31

P15

AH14

AG14

AF14

AE14

Y14

AF13

AE13

AF12

AE12

AL30

AD12

AK30

AJ30

AH30

AG30

AF30

AH1

AH2

A28

B28

C28

H19

D21

H22

H41

G21

B39

G20

AC14

AB14

AD13

AC13

AB13

AA13

Y13

W13

V13

U13

T13

R13

W14

N13

M13

L13

AB12

AA12

Y12

W12

V12

U12

T12

V14

R12

P12

N12

M12

L12

R11

P11

N11

M11

R10

T14

P10

N10

M10

P9

N9

M9

R8

P8

N8

M8

R14

P7

N7

M7

R6

P6

M6

A6

R5

P5

N5

P14

M5

P4

N4

M4

R3

P3

N3

M3

R2

P2

N14

M2

D2

AB1

R1

P1

N1

M1

M14

L14

945GMNBBGA

OMIT

C1711 1

2

402CERM-X5R

6.3V

0.47UF10%

C17121

2 X5R402

6.3V

0.22uF20%

C1713 1

2

402

6.3VCERM-X5R

0.47UF10%

17 105

B051-7270

NB Power 2SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)

=PP1V5_S0_NB_VCCD_LVDS

PP1V5_S0_NB_VCCD_TVDAC

=PP1V05_S0_NB_VTT

NB_VTTLF_CAP3

NB_VTTLF_CAP2

NB_VTTLF_CAP1

=PP2V5_S0_NB_VCCSYNC

=PP2V5_S0_NB_VCC_TXLVDS

PP1V5_S0_NB_VCC3G

PP1V5_S0_NB_VCCA_3GPLL

=PP2V5_S0_NB_VCCA_3GBG

GND_NB_VSSA_3GBG

GND_NB_VSSA_CRTDAC

PP1V5_S0_NB_VCCA_DPLLB

PP1V5_S0_NB_VCCA_DPLLA

PP1V5_S0_NB_VCCA_HPLL

GND_NB_VSSA_LVDS

=PP2V5_S0_NB_VCCA_LVDS

PP1V5_S0_NB_VCCA_MPLL

PP3V3_S0_NB_VCCA_TVBG

GND_NB_VSSA_TVBG

PP3V3_S0_NB_VCCA_TVDACC

PP3V3_S0_NB_VCCA_TVDACB

PP3V3_S0_NB_VCCA_TVDACA

=PP1V5_S0_NB_VCCD_HMPLL

=PP3V3_S0_NB_VCC_HV

PP1V5_S0_NB_VCCD_QTVDAC

=PP1V5_S0_NB_VCCAUX

PP2V5_S0_NB_VCCA_CRTDAC

65B6

65D6

65A6

65A6

65B3

19D7

65B6

19D7

19D7

19D7

19D7

34B2

65A6

65B6

19C7

19C4

19A5

19D1

19C8

19D1

19A6

19B3

19B3

19C5

19A3

19D1

19A6

19A6

19B6

19A3

19A4

19B6

19C1

19C1

19C1

19D1

19D1

19D7

19C6

19D1

16D1

19D1

VSS_1

VSS_0

VSS_2

VSS_3

VSS_4

VSS_5

VSS_6

VSS_7

VSS_9

VSS_8

VSS_10

VSS_11

VSS_12

VSS_13

VSS_14

VSS_15

VSS_16

VSS_17

VSS_19

VSS_18

VSS_20

VSS_21

VSS_22

VSS_23

VSS_24

VSS_25

VSS_26

VSS_28

VSS_27

VSS_29

VSS_30

VSS_31

VSS_32

VSS_33

VSS_34

VSS_35

VSS_37

VSS_36

VSS_39

VSS_38

VSS_40

VSS_41

VSS_42

VSS_43

VSS_44

VSS_45

VSS_46

VSS_47

VSS_49

VSS_48

VSS_50

VSS_51

VSS_52

VSS_53

VSS_54

VSS_55

VSS_57

VSS_56

VSS_59

VSS_58

VSS_61

VSS_60

VSS_64

VSS_63

VSS_62

VSS_65

VSS_66

VSS_67

VSS_68

VSS_69

VSS_70

VSS_71

VSS_73

VSS_72

VSS_74

VSS_75

VSS_76

VSS_77

VSS_78

VSS_79

VSS_82

VSS_80

VSS_81

VSS_84

VSS_83

VSS_85

VSS_87

VSS_86

VSS_89

VSS_88

VSS_91

VSS_90

VSS_92

VSS_93

VSS_94

VSS_96

VSS_95

VSS_97

VSS_98

VSS_99

VSS_100

VSS_101

VSS_102

VSS_103

VSS_104

VSS_105

VSS_106

VSS_107

VSS_108

VSS_109

VSS_110

VSS_111

VSS_112

VSS_114

VSS_113

VSS_115

VSS_117

VSS_116

VSS_118

VSS_119

VSS_120

VSS_121

VSS_122

VSS_123

VSS_124

VSS_125

VSS_127

VSS_126

VSS_128

VSS_129

VSS_130

VSS_131

VSS_132

VSS_133

VSS_134

VSS_135

VSS_137

VSS_136

VSS_138

VSS_139

VSS_140

VSS_141

VSS_143

VSS_142

VSS_144

VSS_145

VSS_146

VSS_147

VSS_148

VSS_149

VSS_150

VSS_151

VSS_152

VSS_153

VSS_154

VSS_155

VSS_156

VSS_158

VSS_157

VSS_159

VSS_160

VSS_161

VSS_162

VSS_164

VSS_163

VSS_165

VSS_166

VSS_167

VSS_168

VSS_169

VSS_170

VSS_172

VSS_171

VSS_173

VSS_174

VSS_175

VSS_176

VSS_177

VSS_178

VSS_179

VSS

(9 OF 10)

VSS_272

VSS_271

VSS_269

VSS_270

VSS_268

VSS_266

VSS_267

VSS_265

VSS_264

VSS_263

VSS_261

VSS_262

VSS_260

VSS_259

VSS_258

VSS_256

VSS_257

VSS_255

VSS_254

VSS_253

VSS_251

VSS_252

VSS_250

VSS_248

VSS_249

VSS_247

VSS_246

VSS_245

VSS_243

VSS_244

VSS_242

VSS_241

VSS_240

VSS_238

VSS_239

VSS_237

VSS_236

VSS_235

VSS_233

VSS_234

VSS_232

VSS_231

VSS_230

VSS_228

VSS_229

VSS_227

VSS_225

VSS_226

VSS_224

VSS_223

VSS_222

VSS_220

VSS_221

VSS_219

VSS_218

VSS_217

VSS_215

VSS_216

VSS_214

VSS_213

VSS_212

VSS_210

VSS_211

VSS_209

VSS_207

VSS_208

VSS_205

VSS_206

VSS_204

VSS_202

VSS_203

VSS_201

VSS_200

VSS_199

VSS_197

VSS_198

VSS_196

VSS_195

VSS_194

VSS_192

VSS_193

VSS_191

VSS_190

VSS_189

VSS_187

VSS_188

VSS_186

VSS_184

VSS_185

VSS_183

VSS_182

VSS_180

VSS_181

VSS_273

VSS_274

VSS_276

VSS_275

VSS_277

VSS_279

VSS_278

VSS_281

VSS_280

VSS_282

VSS_283

VSS_284

VSS_286

VSS_285

VSS_287

VSS_288

VSS_289

VSS_291

VSS_290

VSS_293

VSS_292

VSS_294

VSS_296

VSS_295

VSS_297

VSS_299

VSS_298

VSS_301

VSS_302

VSS_300

VSS_304

VSS_303

VSS_305

VSS_306

VSS_307

VSS_309

VSS_308

VSS_311

VSS_310

VSS_312

VSS_313

VSS_314

VSS_315

VSS_317

VSS_316

VSS_318

VSS_319

VSS_320

VSS_322

VSS_321

VSS_323

VSS_324

VSS_325

VSS_327

VSS_326

VSS_328

VSS_329

VSS_330

VSS_332

VSS_331

VSS_334

VSS_333

VSS_335

VSS_337

VSS_336

VSS_338

VSS_339

VSS_340

VSS_342

VSS_343

VSS_341

VSS_345

VSS_344

VSS_346

VSS_347

VSS_348

VSS_350

VSS_349

VSS_352

VSS_351

VSS_353

VSS_354

VSS_355

VSS_356

VSS_357

VSS_358

VSS_359

VSS_360

VSS

(10 OF 10)

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

U1200AC41

AA41

AN40

AE34

AC34

C34

AW33

AV33

AR33

AE33

AB33

Y33

V33

AK40

T33

R33

M33

H33

G33

F33

D33

B33

AH32

AG32

AJ40

AF32

AE32

AC32

AB32

G32

B32

AY31

AV31

AN31

AJ31

AH40

AG31

AB31

Y31

AB30

E30

AT29

AN29

AB29

T29

N29

AG40

K29

G29

E29

C29

B29

A29

BA28

AW28

AU28

AP28

AF40

AM28

AD28

AC28

W28

J28

E28

AP27

AM27

AK27

J27

AE40

G27

F27

C27

B27

AN26

M26

K26

F26

D26

AK25

B40

P25

K25

H25

E25

D25

A25

BA24

AU24

AL24

AW23

AY39

AW39

W41

AV39

AR39

AN39

AJ39

AC39

AB39

AA39

Y39

W39

V39

T41

T39

R39

P39

N39

M39

L39

J39

H39

G39

F39

P41

D39

AT38

AM38

AH38

AG38

AF38

AE38

C38

AK37

AH37

M41

AB37

AA37

Y37

W37

V37

T37

R37

P37

N37

M37

J41

L37

J37

H37

G37

F37

D37

AY36

AW36

AN36

AH36

F41

AG36

AF36

AE36

AC36

C36

B36

BA35

AV35

AR35

AH35

AV40

AB35

AA35

Y35

W35

V35

T35

R35

P35

N35

M35

AP40

L35

J35

H35

G35

F35

D35

AN34

AK34

AG34

AF34

NB

945GM

BGA

OMIT

U1200AT23

AN23

AM23

AH23

AC23

W23

K23

J23

F23

C23

AA22

K22

G22

F22

E22

D22

A22

BA21

AV21

AR21

AN21

AL21

AB21

Y21

P21

K21

J21

H21

C21

AW20

AR20

AM20

AA20

K20

B20

A20

AN19

AC19

W19

K19

G19

C19

AH18

P18

H18

D18

A18

AY17

AR17

AP17

AM17

AK17

AV16

AN16

AL16

J16

F16

C16

AN15

AM15

AK15

N15

M15

L15

B15

A15

BA14

AT14

AK14

AD14

AA14

U14

K14

H14

E14

AV13

AR13

AN13

AM13

AL13

AG13

P13

F13

D13

B13

AY12

AC12

K12

H12

E12

AD11

AA11

Y11

J11

D11

B11

AV10

AP10

AL10

AJ10

AG10

AC10

W10

U10

BA9

AW9

AR9

AH9

AB9

Y9

R9

G9

E9

A9

AG8

AD8

AA8

U8

K8

C8

BA7

AV7

AP7

AL7

AJ7

AH7

AF7

AC7

R7

G7

D7

AG6

AD6

AB6

Y6

U6

N6

K6

H6

B6

AV5

AF5

AD5

AY4

AR4

AP4

AL4

AJ4

Y4

U4

R4

J4

F4

C4

AY3

AW3

AV3

AL3

AH3

AG3

AF3

AD3

AC3

AA3

G3

AT2

AR2

AP2

AK2

AJ2

AD2

AB2

Y2

U2

T2

N2

J2

H2

F2

C2

AL1

NB945GM

BGA

OMIT


NB Grounds

051-7270 B

10518

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

NR/FBINEN

OUT

GND

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

800mA Max

These are the power signals that leave the NB "block"

Power Interface

40mA Max

MCH VCC_HV BYPASS

(MCH HV BUFFER 3.3V PWR)

Layout Note: Route to caps, then GND

(MCH MEMORY PLL 1.5V PWR)

1500mA Max

1500mA Max

10mA Max?

GMCH CORE PWR 1.05V BYPASS

1900mA Max

3200mA Max

(MCH TVDAC DEDICATED PWR 1.5V)

(MCH TVDAC DIGITAL QUIET 1.5V PWR)

(MCH TV OUT CHANNEL A 3.3V PWR)

(MCH TV OUT CHANNEL B 3.3V PWR)

(MCH TV DAC BAND GAP 3.3V PWR)

(MCH TV OUT CHANNEL C 3.3V PWR)

(MCH CRTDAC ANALOG 2.5V PWR)

(MCH H/V SYNC 2.5V PWR)

Rail Totals:

2310mA Max?

?mA Max

?mA Max

100mA Max

800mA Max

3674mA Max

40mA Max 40mA Max?

2mA Max

150mA Max

3200mA Max

1500mA Max

24mA Max

70mA Max

?mA Max

Layout Note: Route to caps, then GND

10MA MAX

(MCH LVDS ANALOG 2.5V PWR)

MCH VCCA_LVDS BYPASS

132mA Max

?mA Max

60mA Max

GMCH VCC3G FILTER

(PCI-E/DMI ANALOG 1.5V PWR)

1500mA Max

(3GIO PLL 1.5V PWR)

GMCH VCCA_3GPLL FILTER

Layout Note:

be close to MCH

10uF caps should

on opposite side.

(MCH DDR DLL&IO, FSB HSIO&IO PWR 1.5V)

GMCH VCCAUX FILTER

1900mA Max

(MCH PCIE/DMI BAND GAP 2.5V PWR)

2mA Max

MCH VCCA_3GBG BYPASS

be placed in cavity

3GPLL 10uF cap should

Layout Note:

Layout Note:

Place L and C

close to MCH

Place on the edge

Layout Note:

(SHARE C0940 470UF)

45mA Max

45mA Max

GMCH VCCA_HPLL FILTER

(HOST PLL 1.5V PWR)

GMCH VCCA_MPLL FILTER

MCH VTT BYPASS

(MCH FSB 1.05V PWR)

Layout Note:

Place in cavity

100mA Max

(MCH LVDS DIGITAL 1.5V PWR)

MCH VCCD_LVDS BYPASS

20MA MAX

GMCH VCCA_DPLLA FILTER

50MA MAX

50MA MAX

(CRT/TVOUT PLL 1.5V PWR)

GMCH VCCA_DPLLB FILTER

(LVDS PLL 1.5V PWR)

1500mA Max

60MA MAX

(MCH LVDS TRANSMITTER 2.5V PWR)

MCH VCC_TXLVDS BYPASS

C19071

2

0.22uF

X5R6.3V20%

402

C19721

2 X5R603

20%6.3V

10uF

C19671

2

0.22uF

X5R402

20%6.3V

C19661

2 CERM1

20%2.2uF

603

6.3V

C19651

2

4.7uF

CERM603

20%6.3V

C19001

23

CRITICAL

470uF

D2TTANT2.5V20%

L1970

1 2

91nH

1210

C1916 1

2CERM10V20%

402

0.1uF

C19061

26.3V20%

402X5R

0.22uF

C19911

210V20%

402CERM

0.1uFC1990 1

2CERM603

20%6.3V

4.7UFC19931

2

0.1uF

CERM402

20%10V

C1992 1

26.3V20%

603X5R

10uFC19951

210V20%

402CERM

0.1uFC1994 1

2

0.01UF

402CERM16V20%C19521

2

603X5R6.3V

10uF20%

R19901

2

1.5K1%1/16WMF-LF402

U1900

3

2

1

4

5

CRITICAL

TPS73115SOT23-5

C1950 1

26.3V10%1uF

CERM402

C1951 1

216V10%

0.01uF

CERM402

R19541 2

0

5%1/16WMF-LF402

R19531 2

NO STUFF

0

5%1/16WMF-LF402

C1953 1

2CERM

NO STUFF

20%10V

402

0.1uF

C19151

2

0.1uF

CERM402

20%10V

C19541

2

20%10VCERM402

0.1uF

C19701

2POLY2.5V20%220UF

CASE-B2

C1914 1

2

10uF

X5R603

6.3V20%

C19051

26.3V20%

X5R

0.22uF

402

C19351

2

0.1uF

CERM402

10V20%

L1934

1 2

0603

FERR-120-OHM-0.2A

C19371

210V

0.1uF20%

CERM402

C19041

2

402

6.3V

1uF

CERM

10%

L1936

1 2

FERR-120-OHM-0.2A

0603

C1934 1

26.3V20%

805CERM

22UF

OMIT

C1936 1

26.3V20%

805CERM

22UF

OMIT

C19031

26.3VX5R

20%10uF

603

C19021

2 X5R6.3V20%

603

10uF

C1918 1

2CERM402

20%10V

0.1uF

C19761

210V20%

402CERM

0.1uF

L1975

1 2

1.0UH-220MA-0.12-OHM

0805

C1975 1

26.3V20%

603X5R

10uF

R19751 2

MF-LF402

0.51

1/16W1%

C19711

2

10uF

X5R603

20%6.3V

NB (GM) DecouplingSYNC_DATE=07/25/2006SYNC_MASTER=M59_MG

051-7270 B

10519

VOLTAGE=1.5V

PP1V5_S0_NB_VCC3GMIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mm

=PP2V5_S0_NB_DPLL

TPS73115_NR

PP1V5_S0_NB_VCCA_DPLLB


VOLTAGE=1.5V

=PP2V5_S0_NB_VCC_TXLVDSVOLTAGE=1.5V


PP1V5_S0_NB_DPLL


VOLTAGE=1.5VMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.38 mm



VOLTAGE=1.5V

PP1V5_S0_NB_3GPLL_FMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.4 mm

MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.38 mmPP1V5_S0_NB_VCCA_MPLL

VOLTAGE=1.5V


VOLTAGE=1.5V

PP1V5_S0_NB_VCCA_HPLL

PP1V5_S0_NB_VCCA_3GPLL

VOLTAGE=1.5V


=PP1V5_S0_NB_3G

=PP1V5_S0_NB_VCCAUX

=PP1V05_S0_FSB_NB


GND_NB_VSSA_LVDS

LVDS_VREFL

LVDS_VREFH

LVDS_IBG

CRT_HSYNC_R

CRT_DDC_DATA

MAKE_BASE=TRUETP_SDVO_CTRLDATA SDVO_CTRLDATAMAKE_BASE=TRUE

TP_SDVO_CTRLCLK SDVO_CTRLCLK

NO_TEST=TRUEMAKE_BASE=TRUENC_NB_XOR_LVDS_D28 TP_NB_XOR_LVDS_D28

NO_TEST=TRUEMAKE_BASE=TRUENC_NB_XOR_LVDS_D27 TP_NB_XOR_LVDS_D27

NO_TEST=TRUEMAKE_BASE=TRUENC_NB_XOR_LVDS_A34 TP_NB_XOR_LVDS_A34

NO_TEST=TRUEMAKE_BASE=TRUENC_NB_XOR_LVDS_A35 TP_NB_XOR_LVDS_A35

MAKE_BASE=TRUETP_LVDS_CLKCTLB LVDS_CLKCTLBMAKE_BASE=TRUE

TP_LVDS_CLKCTLA LVDS_CLKCTLA

TV_DACA_OUT

TV_DACB_OUT

=PP1V5_S0_NB_TVDAC

=PP1V05_S0_NB_CRT

=PP1V5_S0_NB

=PP1V05_S0_NB_VTT

=PP3V3_S0_NB

=PP3V3_S0_NB_VCC_HV


MAKE_BASE=TRUETP_CRT_DDC_CLK CRT_DDC_CLK

CRT_IREF

CRT_BLUE_L

CRT_GREEN_L

CRT_RED_L

CRT_BLUE

CRT_GREEN

CRT_RED

=PP1V05_S0_NB_CRT

TV_IREF

TV_IRTNC

TV_IRTNB

CRT_VSYNC_R

=PP1V5_S0_NB_PCIE

=PPVCORE_S0_NB

=PP1V5_S0_NB_TVDAC

GND_NB_VSSA_CRTDAC

PP2V5_S0_NB_VCCA_CRTDAC


PP1V5_S0_NB_VCCD_TVDAC

PP1V5_S0_NB_VCCD_QTVDAC

PP3V3_S0_NB_VCCA_TVDACA

PP3V3_S0_NB_VCCA_TVDACB

PP3V3_S0_NB_VCCA_TVDACC

PP3V3_S0_NB_VCCA_TVBG

GND_NB_VSSA_TVBG

=PP1V5_S0_NB_3G

TV_IRTNA

TV_DACC_OUT

MAKE_BASE=TRUETP_CRT_DDC_DATA

=PP1V5_S0_NB_VCCAUX

=PP1V5_S0_NB_3GPLL

=PP1V5_S0_NB_PLL

GND_NB_VSSA_3GBG

=PP3V3_S0_NB_VCC_HV

=PPVCORE_S0_NB




=PP1V8_S3_MEM_NB

=PP1V5_S0_NB_3GPLL

=PPVCORE_S0_NB

=PP1V5_S0_NB_TVDAC

=PP1V5_S0_NB_PLL

=PP1V05_S0_NB_VTT

65D6 34C8 34C6

65B3

65D6

65D6

65D6

65B6

34B8

20B4

19D7

65B6

19D7

19D2

65A6

65A6 19D7

12C2

65B6

65C8

65D6

20A4

65B3

19C8

65B6

19C4

65B3

19D2

65A6

65A6

65B6

19C8

65B6

65D6

19D7

34B2

19D7

65B6

65C6

17B6

12B7

65A6

19D7

65D6

65C6

19C8

14D6

19C6

65B6

65D6

65C6

16D3

19D7

19D7

65C6

17B6

65C6

65B6

19C7

16D3

19C5

19A6

19D1

16B6

65C6

16D3

19D6

65B6

19D7

17D6

65A6 17C6 17D6

17C6

17D6

17C6

17C6

17C6

17D6

19D7

16D1

12A7

17C6

17C6

13D5

13D5

13D5

13B5

13B5

14B6

14B6

14C6

14C6

14C6

14C6

13D5

13C5

13C5

19D2

19D6

60A7

17D3

14C7

17C6

17C6

13B5

13B5

13B5

13B5

13B5

13B5

13B5

13B5

19D7

13C5

13C5

13C5

13B5

13D2

16C8

19D6

17D6

17D6

17D6

17C6

17B6

17C6

17C6

17C6

17C6

17C6

19B5

13C5

13C5

16D1

19D7

19D7

17D6

17C6

16C8

17D6

17D6

17D6

14C2

19B5

16C8

19D2

19B8

17D3

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

PCIe Backward

Interop. Mode

VCC Select

Reversal

DMI Lane

High = Reversed

Low = Normal

High = 1.5V

Low = 1.05V

Internal pull-down

Internal pull-down

Internal pull-down

945 External Design Spec says reserved

High = Both active

Low = Only SDVO

or PCIe x1

ODT

FSB Dynamic

RESERVED

Low = Disabled

High = Enabled

RESERVED

Internal pull-up

RESERVED

00 = Partial Clock Gating Disable

01 = XOR Mode Enabled

10 = All-Z Mode Enabled

11 = Normal Operation

Internal pull-up

Low = Reversed

RESERVED

CPU Strap

RESERVED

PCIE Graphics

High = Normal

Low = RESERVED

High = DMIx4

Low = DMIx2

NB_CFG<20>

NB_CFG<19>NB_CFG<9>

NB_CFG<8>NB_CFG<18>

NB_CFG<17>

NB_CFG<6>NB_CFG<16>

NB_CFG<15>NB_CFG<5>

NB_CFG<14>

NB_CFG<13:12>

RESERVED

NB_CFG<3>

NB_CFG<4>

Lane Reversal

PROBABLY NOT NEEDED

PROBABLY NOT NEEDED

DMI x2 Select

Internal pull-up

RESERVED

NB_CFG<7> High = Mobile CPU

NB_CFG<10>

NB_CFG<11>

RESERVED

RESERVED

Internal pull-up

Internal pull-ups

R20751

2402

5%2.2K

1/16WMF-LF

NBCFG_DMI_X2

R20851

2

5%2.2K

1/16WMF-LF402

NBCFG_DYN_ODT_DISABLE

R20581

2402

1/16W5%2.2K

NBCFG_VCC_1V5

MF-LF

R20591

2402MF-LF1/16W5%2.2K

NBCFG_DMI_REVERSE

R20601

2

NBCFG_SDVO_AND_PCIE

402MF-LF1/16W5%2.2K

R20771

2

NO STUFF

2.2K5%1/16WMF-LF402

R20791

2402MF-LF1/16W5%2.2K

NBCFG_PEG_REVERSE

20 105

B051-7270

NB Config StrapsSYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)

NB_CFG<7>

NB_CFG<9>

NB_CFG<5>

NB_CFG<16>

NB_CFG<20>

NB_CFG<19>

NB_CFG<18>

=PP3V3_S0_NB

=PP3V3_S0_NB

=PP3V3_S0_NB

65B3

65B3

65B3

20B4

20B4

20B4

20A4

20A4

19C7

19C7

19C7

14D6

14D6

14D6

14C6

14C6

14C6

14C6

14B6

14C6

14C6

14C7

14C7

14C7

IO

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IO

IO

IO

IO

IN

IO

DDACK*

SATARBIASN

SATARBIASP

SATA_CLKN

SATA_CLKP

SATA_2TXP

SATA_2TXN

SATA_2RXN

SATA_2RXP

SATA_0TXP

SATA_0TXN

SATA_0RXP

SATA_0RXN

SATALED*

ACZ_SDOUT

ACZ_SDIN1

ACZ_SDIN2

ACZ_SDIN0

ACZ_SYNC

ACZ_BIT_CLK

LAN_TXD2

LAN_TXD0

LAN_TXD1

LAN_RXD1

LAN_RXD2

LAN_RSTSYNC

LAN_RXD0

LAN_CLK

EE_SHCLK

EE_CS

INTVRMEN

INTRUDER*

RTCRST*

RTCX2

RTCX1

THRMTRIP*

STPCLK*

NMI

SMI*

RCIN*

INTR

INIT*

INIT3_3V*

IGNNE*

GPIO49/CPUPWRGD

FERR*

TP1/DPRSTP*

TP2/DPSLP*

A20M*

CPUSPL*

A20GATE

LFRAME*

LDRQ1*/GPIO23

LDRQ0*

LAD3

LAD2

LAD0

LAD1

EE_DOUT

EE_DIN

ACZ_RST*

DIOR*

IDEIRQ

DIOW*

IORDY

DDREQ

DD0

DD1

DD3

DD2

DD5

DD4

DD6

DD7

DD8

DD11

DD9

DD10

DD12

DD13

DD14

DD15

DA0

DA1

DA2

DCS3*

DCS1*

AC-97/

AZALIA

RTC

LPC

LAN

CPU

IDE

SATA

(1 OF 6)

OUT

OUT

OUT

IN

OUT

IN

IN

IN

IN

OUT

OUT

OUT

OUT

IN

IN

OUT

OUT

OUT

IN

IN

IN OUT

OUT

OUT

OUT

OUT

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

NOTE: EE_CS HAS INTERNAL PD, ONLY ENABLED WHEN LAN_RST#=L

(INT PU)

(INT PU)

(WEAK INT PD)

NOTE: R2108=56 IN CV.

BOM CONSOLIDATION

CHANGED TO 54.9 FOR

NOTE: R2110=56 IN CV. NOTE: PULLED UP PER INTEL

NOTE: LDRQ<0-1># HAVE INTERNAL 20K PU

INTEL CONFIRMS OK TO LEAVE PINS AS NC

- BOTH FUNCTION 2 & 3 OF DEVICE 30 ARE DISABLED

INTO RESET STATE TO SAVE PWR.

NOTE:

POR IS SMC WILL PUT LAN INT’F

NOTE: KEYBOARD CONTROLLER RESET CPU

NOTE: RISING-EDGE TRIGGERED AT CPUBOM CONSOLIDATION

< 2 IN OF SB

LAYOUT NOTE: R2107 TO BE

CHANGED TO 54.9 FOR

LAYOUT NOTE: R2108 TO BE

< 2 IN OF R2107 W/O STUB

(DSTROBE)

20K PD

20K PD

20K PD

(STOP)

(HSTROBE)

NOTE: DD<7> HAS INTERNAL 11.5K PD

NOTE: ENABLE INTERNAL 1.05V SUSPEND REG

INTERNAL 20K PD ONLY ENABLED IN S3COLD

INTERNAL 20K PD

NONE

- LSO BIT IN AC’97 GLOBAL CONTROL REG = 1; OR

INTERNAL 20K PD ENABLED WHEN

INTERNAL 20K PD

INTERNAL 20K PD ENABLED DURING RESET AND WHEN





AC ’07

INTERNAL 20K PD

INTERNAL 20K PD ENABLED WHEN

ACZ_SDIN[0-2]

ACZ_RST#

ACZ_BIT_CLK

ACZ_SYNC

ACZ_SDOUT

INTEL HIGH DEFINITION AUDIO

NOTE: LAD<0-3> HAVE INTERNAL 20K PU

NOTE: DDREQ HAS INTERNAL 11.5K PD

LAYOUT NOTE: PLACE R2101 & R2194 WHERE ACCESSIBLE

NOTE: ALL IDE PINS HAVE INTERNAL 33-OHM SERIES R’S

(WEAK INT PU)

R21001 2

4025%

0

MF-LF1/16W

NOSTUFF

R21011 2

MF-LF1/16W5%

2.2K

402

NOSTUFF

R2195 1 2

1/16W

40239

5%

MF-LF

R2198 1 2 39

R2197 1 2 39

R2196 1 2 39

R21991

2MF-LF1/16W5%10K

402

U2100

AE22

AH28

U1

R5

T2

T3

T1

T4

R6

AG27

AH17

AE17

AF17

AE16

AD16

AB15

AE14

AB13

AC14

AF14

AH13

AH14

AC15

AG13

AF13

AD14

AC13

AD12

AC12

AE12

AF12

AF16

AE15

AF15

AH15

W1

W3

Y2

Y1

AG26

AG24

AH16

AG22

AF22

AG21

AF25

Y5

W4

AG16

AA6

AB5

AC4

Y6

V3

U3

U5

V4

T5

U7

V6

V7

AC3

AA5

AB3

AH24

AG23

AA3

AB1

AB2

AF3

AE3

AG2

AH2

AF7

AE7

AG6

AH6

AF1

AE1

AF18

AH10

AG10

AF23

AH22

AF26

AF24

AH25

OMIT

ICH7-MSBBGA

R21941

2MF-LF1/16W5%10K

402

R2105

1

2

MF-LF1/16W 1%402332K

R21071 2

4021%1/16W

MF-LF

24.9

R2108

1

2

54.91%1/16W

MF-LF 402

R2110

12

1%

54.9402

1/16WMF-LF


SB: 1 OF 4

051-7270

10521

B

IDE_PDD<3>

IDE_PDD<2>

TP_SB_XOR_V3

TP_SB_XOR_W3

TP_SB_XOR_T5

TP_SB_XOR_V4

TP_SB_XOR_U5

TP_SB_XOR_U3

PP3V3_S5_SB_RTC

ACZ_RST_L

ACZ_BITCLK

SB_RTC_RST_L

SB_RTC_X2

LPC_FRAME_L

TP_SB_GPIO23

TP_SB_DRQ0_L

LPC_AD<3>

LPC_AD<2>

LPC_AD<1>

LPC_AD<0>

=PP3V3_S0_SB_GPIO

=PP3V3_S0_SB_GPIO

IDE_PDD<6>

ACZ_SDATAOUTPM_THRMTRIP_L

=PP1V05_S0_SB_CPU_IO

SMC_RCIN_LACZ_SYNC

IDE_PDCS1_L

IDE_PDCS3_L

IDE_PDA<2>

IDE_PDA<1>

IDE_PDA<0>

IDE_PDD<15>

IDE_PDD<14>

IDE_PDD<13>

IDE_PDD<12>

IDE_PDD<10>

IDE_PDD<9>

IDE_PDD<11>

IDE_PDD<8>

IDE_PDD<7>

IDE_PDD<4>

IDE_PDD<5>

IDE_PDD<1>

IDE_PDD<0>

IDE_PDDREQ

IDE_PDIORDY

IDE_PDIOW_L

IDE_IRQ14

IDE_PDIOR_L

SB_ACZ_RST_L

TP_CPU_CPUSLP_L

CPU_A20M_L

CPU_DPSLP_L

CPU_DPRSTP_L

CPU_PWRGD

CPU_IGNNE_L

FWH_INIT_L

CPU_INIT_L

CPU_INTR

CPU_SMI_L

CPU_NMI

CPU_STPCLK_L

CPU_THERMTRIP_R

SB_RTC_X1

SB_SM_INTRUDER_L

SB_ACZ_BITCLK

SB_ACZ_SYNC

ACZ_SDATAIN<0>

TP_SB_ACZ_SDIN2

TP_SB_ACZ_SDIN1

SB_ACZ_SDATAOUT

TP_SB_SATALED_L

SATA_A_D2R_N

SATA_A_D2R_P

SATA_A_R2D_C_N

SATA_A_R2D_C_P

SATA_C_D2R_N

SATA_C_R2D_C_N

SATA_C_R2D_C_P

SB_CLK100M_SATA_P

SB_CLK100M_SATA_N

SATA_RBIAS_P

SATA_RBIAS_N

IDE_PDDACK_L

SATA_C_D2R_P

CPU_RCIN_L

SB_A20GATE

CPU_FERR_L


SB_INTVRMEN

TP_SB_XOR_W1

TP_SB_XOR_Y1

TP_SB_XOR_Y2

TP_SB_XOR_U7

TP_SB_XOR_V6

TP_SB_XOR_V7

58C6

58C6

58C6

65B3

65B3 65D6

65D6

26D3

84B4

84B4

51C4

51C5

51C4

23D5

23D5

84B4

50C1

25C4

84B4

51C5

84B4

25C4

25A4

47B3

47B6

49C7

49C7

49D7

23B3

23B3

47B6 14B6

24C3

47B6

84C6

84C6

59C7

84C6

84C6

50D3

84C6

84C6

84C6

84C6

84C6

47B6

34C3

34C3

24C3

36C5

36C5

6C6

6C6

6C6

6C6

6C6

24B3

5C1

5C1

26D4

26C8

5C2

79A4

5C2

5D2

21C3

21D3

36C5

5C1 7C6

21C1

49C7 5C1

36C5

36C4

36C5

36C5

36C4

36C4

36C4

36C4

36C4

36C4

36C4

36C4

36D4

36C5

36C5

36C5

36C5

36C5

36C4

36C4

36C5

36C4

36C5

84B4

7C8

7B3

7B3

7B3

7C8

5C2

7D6

7C8

7C8

7C8

7C8

26C8

26D4

84B4

84B4

5C1

84B4

36A5

36A5

36A5

36A5

78B7

78B2

78B2

5A7

5A7

36A5

36A5

36C5

78B7

7C8

21C1

IN

IO

IO

IO

IO

IO

IO

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IO

IO

IO

IO

IN

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IN

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IO

DMI_ZCOMP

DMI_CLKP

DMI_IRCOMP

USBRBIAS*

USBRBIAS

DMI0RXN

DMI0RXP

DMI0TXN

DMI0TXP

DMI2TXN

DMI2TXP

DMI3RXN

DMI3TXP

DMI3TXN

DMI3RXP

USBP0N

USBP0P

USBP1N

USBP1P

USBP2N

USBP2P

USBP3N

USBP3P

USBP4P

USBP5N

USBP5P

USBP6N

USBP6P

USBP7N

USBP7P

USBP4N

OC0*

OC1*

OC2*

OC3*

OC4*

OC6*/GPIO30

OC5*/GPIO29

SPI_CLK

SPI_CS*

SPI_MOSI

SPI_MISO

SPI_ARB

DMI_CLKN

DMI2RXP

DMI2RXN

DMI1TXP

DMI1TXN

DMI1RXN

DMI1RXP

PERN1

PERP1

PETN1

PETP1

PERN2

PERP2

PETN2

PETP2

PERN3

PERP3

PETN3

PETP3

PERN4

PERP4

PETN4

PETP4

PERN5

PERP5

PETN5

PETP5

PERN6

PERP6

PETN6

PETP6

OC7*/GPIO31

PCI-EXP

(3 OF 6)

DMI

SPI

USB

REQ4*/GPIO22

REQ0*

MCH_SYNC*

RSVD8

RSVD7

RSVD6

RSVD5

RSVD4

GPIO5/PIRQH*

GPIO4/PIRQG*

GPIO3/PIRQF*

GPIO2/PIRQE*

GPIO17/GNT5*

GPIO1/REQ5*

GNT4*/GPIO48

C/BE0*

C/BE1*

DEVSEL*

PERR*

STOP*

PCIRST*

PME*

PLTRST*

TRDY*

FRAME*

IRDY*

PCICLK

PAR

PLOCK*

SERR*

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

AD8

AD9

AD10

AD11

AD12

AD13

AD14

AD15

AD16

AD17

AD18

AD19

AD20

AD21

AD22

AD23

AD24

AD25

AD26

AD27

AD28

AD29

AD30

AD31

C/BE2*

C/BE3*

GNT0*

REQ1*

GNT1*

REQ2*

GNT2*

REQ3*

GNT3*

PIRQA*

PIRQB*

PIRQC*

PIRQD*

RSVD0

RSVD1

RSVD2

RSVD3

MISC

INT I/F

PCI

(2 OF 6)

IO

OUT

OUT

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IN

IO

IO

IO

IO

OUT

IO

IO

IO

IO

IO

IO

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

NOTE: USBP[0-7]P/N HAVE INTERNAL 15K PD

NO STUFF - DEFAULT

GNT[0-3]# HAVE INT 20K PU

(INT 20K PU)

(AKA TP3, INTERNAL 20K PU)

SB: 2 OF 4

ENABLED ONLY WHEN PCIRST#=0

R2211

NOTE: FWH_WP_L NOT USED

GNT5# HAS INT PU (NOMINAL=20K, SIMULATION=15K-35K)

(INT PD)

(INT PD)

GNT4# HAS INT PU; ENABLED ONLY WHEN PCIRST#=0 AND PWROK=H

PLACE R2204 < 1/2 IN FROM SB

LAYOUT NOTE:

PLACE R2203 < 1/2 IN FROM SB

LAYOUT NOTE:

NOTE:

LPC (DEFAULT)

PCI

SPI UNSTUFF

STUFF

UNSTUFFUNSTUFF

UNSTUFF

STUFF01

10

11

STRAP R2210

NOTE: CHANGE SYMBOL

TO RSVD[1-9]

GNT5# GNT4#

SB BOOT BIOS SELECT

TARGETING FWH BIOS SPACE)IE SB INVERTS A16 FOR ALL CYCLES(STRAPPED TO TOP-BLOCK SWAP MODE

STUFF - A16 SWAP OVERRIDE

NOTE:

EXTERNAL 0

EXTERNAL 1

EXTERNAL 2

BOM NOTE FOR PD ON PCI_GNT3_L:

NOTE: R2210 WAS PD ON PIN A14 = FWH_TBL_L

AND PWROK=H

IR

CAMERA

TRACKPAD (GEYSER)

BLUETOOTH

R22031 2

1/16W 402

24.9

MF-LF 1%

R22221

2

10K1/16WMF-LF

5%

402

USB_G_OC_PU

R22041 2

402

22.6

1%1/16WMF-LF

R22231

2

1/16W5%10K

MF-LF402

R22251

2

10K5%1/16WMF-LF402

R22261

2 402MF-LF1/16W

10K5%

R22991

2

10K5%1/16WMF-LF402

U2100V26

V25

U28

U27

Y26

Y25

W28

W27

AB26

AB25

AA28

AA27

AD25

AD24

AC28

AC27

AE28

AE27

D25

C25

D3

C4

D5

D4

E5

C3

A2

B3

F26

H26

K26

M26

P26

T25

F25

H25

K25

M25

P25

T24

E28

G28

J28

L28

N28

R28

E27

G27

J27

L27

N27

R27

P1

R2

P6

P2

P5

F1

F2

G4

G3

H1

H2

J4

J3

K1

K2

L4

L5

M1

M2

N4

N3

D1

D2

OMIT

BGASB

ICH7-M

U2100E18

C18

E14

D14

B12

C13

G15

G13

E12

C11

D11

A11

A16

A10

F11

F10

E9

D9

B9

A8

A6

C7

B6

F18

E6

D6

E16

A18

E17

A17

A15

C14

B15

C12

D12

C15

A12

F16

E7

D16

D17

F13

A14

C8

D8

G8

F7

F8

G7

A7

AH20

E10

A9

B18

C9

A3

B4

C5

B5

E11

C26

B19

D7

C16

C17

E13

A13

AE5

AD5

AG4

AH4

AD9

AE9

AG8

AH8

F21

B10

F15

F14

SBBGA

ICH7-M

OMIT

R22001

2MF-LF1/16W5%10K

402

R22501

2402MF-LF1/16W5%10K

USB_C_OC_PU

R22511

2

10K5%1/16WMF-LF402

USB_E_OC_PU

R22551

2

USB_D_OC_PU

MF-LF1/16W5%10K

402

R22981

2MF-LF402

1/16W5%10K

R2205

1

2

MF-LF

402 5%

10K

1/16W

R2206

1

2

402

10KMF-LF

5%1/16W

NOSTUFF

R2207

1

2

MF-LF1/16W

10K

402 5%

VOLTAGE=0V

R22111

2

1/16WMF-LF

5%1K

402

051-7270

10522

B

SB_GPIO31

TP_PCI_GNT4_L

PCI_GNT3_L

TP_PCI_GNT2_L

TP_PCI_GNT0_L

TP_PCI_GNT1_L

=PP3V3_S5_SB_USB

USB_D_OC_L

USB_B_OC_L

USB_E_OC_L

USB_A_OC_L

NB_SB_SYNC_L

TP_SB_RSVD9

ODD_PWR_EN_L

SB_GPIO4

SB_GPIO3

SB_GPIO2

PCI_C_BE_L<0>

PCI_C_BE_L<1>

PCI_DEVSEL_L

PCI_PERR_L

PCI_RST_L

TP_PCI_PME_L

PLT_RST_L

PCI_TRDY_L

PCI_FRAME_L

PCI_IRDY_L

PCI_CLK_SB

PCI_PAR

PCI_LOCK_L

PCI_SERR_L

PCI_AD<0>

PCI_AD<2>

PCI_AD<3>

PCI_AD<4>

PCI_AD<5>

PCI_AD<7>

PCI_AD<8>

PCI_AD<9>

PCI_AD<10>

PCI_AD<11>

PCI_AD<12>

PCI_AD<13>

PCI_AD<14>

PCI_AD<15>

PCI_AD<16>

PCI_AD<17>

PCI_AD<18>

PCI_AD<19>

PCI_AD<20>

PCI_AD<21>

PCI_AD<22>

PCI_AD<23>

PCI_AD<24>

PCI_AD<25>

PCI_AD<26>

PCI_AD<27>

PCI_AD<28>

PCI_AD<29>

PCI_AD<30>

PCI_AD<31>

PCI_C_BE_L<3>

INT_PIRQA_L

INT_PIRQB_L

INT_PIRQC_L

DMI_IRCOMP_R

SB_CLK100M_DMI_P

USB_RBIAS_PN

DMI_N2S_N<0>

DMI_N2S_P<0>

DMI_S2N_N<0>

DMI_S2N_P<0>

DMI_S2N_N<2>

DMI_S2N_P<2>

DMI_N2S_N<3>

DMI_S2N_P<3>

DMI_S2N_N<3>

DMI_N2S_P<3>

USB_A_N

USB_A_P

USB_B_N

USB_B_P

USB_C_N

USB_C_P

USB_D_N

USB_D_P

USB_E_P

USB_F_N

USB_F_P

USB_G_N

USB_G_P

TP_USB_H_N

USB_E_N

SB_GPIO30

SB_GPIO29

SB_CLK100M_DMI_N

DMI_N2S_P<2>

DMI_N2S_N<2>

DMI_S2N_P<1>

DMI_S2N_N<1>

DMI_N2S_N<1>

DMI_N2S_P<1>

PCIE_A_D2R_N

PCIE_A_D2R_P

PCIE_A_R2D_C_N

PCIE_A_R2D_C_P

PCIE_B_D2R_N

PCIE_B_D2R_P

PCIE_B_R2D_C_N

PCIE_B_R2D_C_P

PCIE_C_D2R_N

PCIE_C_D2R_P

PCIE_C_R2D_C_N

PCIE_C_R2D_C_P

PCIE_D_D2R_N

PCIE_D_D2R_P

PCIE_D_R2D_C_N

PCIE_D_R2D_C_P

PCIE_E_D2R_N

PCIE_E_D2R_P

PCIE_E_R2D_C_N

PCIE_E_R2D_C_P

PCIE_F_D2R_N

PCIE_F_D2R_P

PCIE_F_R2D_C_N

PCIE_F_R2D_C_P

SB_GPIO31

PP1V5_S0_SB_VCC1_5_B=PP3V3_S5_SB_IO

USB_C_OC_L

USB_A_OC_L

USB_B_OC_L

USB_D_OC_L

USB_C_OC_L

SPI_ARB

SPI_SO

TP_USB_H_P

INT_PIRQD_L

TP_SB_XOR_AD5

TP_SB_XOR_AG4

TP_SB_XOR_AH4

TP_SB_XOR_AD9

TP_SB_XOR_AE5

TP_SB_XOR_AH8

SB_CRT_TVOUT_MUX

TP_SB_XOR_AG8

TP_SB_XOR_AE9

SB_GPIO29

USB_E_OC_L

PCI_AD<6>

PCI_AD<1>

PCI_REQ0_L

PCI_REQ1_L

PCI_REQ3_L

PCI_STOP_L

SPI_SCLK

PCI_C_BE_L<2>

BOOT_LPC_SPI_L

PCI_REQ2_L

SB_GPIO30

SPI_CE_L

SPI_SI

=PP3V3_S0_SB

PCI_PME_FW_L

51B4

22D8

22D8

22D8

22D8

37D3

37D3

79A4

37C3

37D3

37D3

37C3

37C6

14B4

14B4

6C2

22D8

14B4

14B4

25B6

22D8

22C4

22C4

22C4

22C4

54C1

6C2

37D3

22C4

37C3

54C7

49C7

22C4

54C7

54C1

65B3

22C4

6B7

65C3

6C1

6D1

6C1

6D1

14B6

36C7

77A1

26C2

26D2

37C6

37B6

26D2

26D2

37C2

26C3

26D2

26D2

26D2

34D6

37B6

26D2

26D2

37D6

37D6

37D6

37D6

37D6

37D6

37C6

37C6

37C6

37C6

37C6

37C6

37C6

37C6

37C6

37C6

37C6

6B7

37C6

37C6

37C6

37C6

37C6

37C6

37C6

37C6

37C6

37C6

37C6

37C6

37B6

26D2

26D2

26D2

34C3

5A7

5A7

14B4

14B4

14B4

14B4

14B4

14B4

14B4

14B4

6D1

6D1

6D1

6D1

6D1

6D1

6C1

6D1

6C1

6C1

6C1

6C1

6C1

6C1

6C1

6C5

22D8

34C3

14B4

14B4

14B4

14B4

5A7

5A7

39D5

39D5

39C5

39C5

48C3

48C3

48C3

48C3

48B3

48C3

48C3

48C3

48B3

48B3

48B3

48B3

48B3

48B3

48B3

48B3

48A3

48B3

48B3

48B3

22D8

24D5 65D3

6D1

6D1

6D1

6C1

6D1

49D5

49D5

6C1

26D2

22C4

6C1

37D6

37D6

26D2

26D2

26D2

49D5

37B6

5C2

26D2

6C5

49B5

49D5

25D8

37D3

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

IN

IN

IO

IO

OUT

OUT

OUT

IN

IN

IO

IN

IN

IO

IN

IN

IN

IN

IO

IO

IN

OUT

IN

OUT

IN

OUT

GPIO19/SATA1GP

GPIO21/SATA0GP

GPIO36/SATA2GP

CLK48

GPIO37/SATA3GP

CLK14

SUSCLK

SLP_S3*

SLP_S4*

SLP_S5*

PWROK

TP0/BATLOW*

GPIO16/DPRSLPVR

PWRBTN*

LAN_RST*

RSMRST*

GPIO10

GPIO9

GPIO12

GPIO14

GPIO13

GPIO24

GPIO15

GPIO25

GPIO35

GPIO38

GPIO39

SMBCLK

SMBDATA

LINKALERT*

SMLINK1

SMLINK0

RI*

SYS_RST*

SPKR

SUS_STAT*

GPIO0/BM_BUSY*

GPIO18/STPPCI*

GPIO11/SMBALERT*

GPIO20/STPCPU*

GPIO26

GPIO28

GPIO27

GPIO32/CLKRUN*

GPIO33/AZ_DOCK_EN*

WAKE*

GPIO34/AZ_DOCK_RST*

SERIRQ

THRM*

GPIO7

GPIO6

VRMPWRGD

GPIO8

(4 OF 6)

SMB

GPIO

PWR MNGT

SYS GPIO

CLKS

SATA GPIO

IN

IN

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

(INT 20K PU)

PLACE R2306-14 WHERE PHYSICALLY ACCESSIBLE

NOTE FOR R2323 (DEF=NOSTUFF)

SB WILL DISABLE TCO TIMERSTRAPPING @ PWROK RISING:

SYSTEM REBOOT FEATURE

NOT USED

NOTE: RESERVED FOR FUTURE

LAYOUT NOTE:

NOTE FOR GPIO25:

OD

DEF=GPI

IN RESET STATE TO SAVE PWRSMC WILL DRIVE 0-1-0 TO KEEP LAN INT’FNOTE:

NOTE:

SV_SET_UP IS LINDACARD DETECT

LO = NOT PRESENT

HI = PRESENT

(INT WEAK PD)

NOTE: DPRSLPVR HAS INT 20K PD, ENABLED AT BOOT/RESET FOR STRAPPING FCN

DEF=GPI

- CAN NOT BE LOW FOR 35US AFTER RSMRST# ON BOOT (DMI AC COUPLING MODE STRAP)- HAS INTERNAL 20K PU, ENABLED DURING RSMRST# AND DISABLED WITHIN 100MS AFTER RSMRST# DEASSERTS

DEF=GPI

R23021 2100R23031 2100

R23051 2100

R23061

2

10K1/16W

MF-LF5%

402

NOSTUFF

R23071

21/16W

MF-LF5%

402

10K

R23081

2

10K

5%MF-LF

1/16W402

R23091

2

NOSTUFF

402

01/16W

MF-LF5%

R23101

2

10K1/16W

MF-LF5%

402

R23111

2

10K

402

NOSTUFF

5%MF-LF

1/16W

R23131

2 402

5%MF-LF

1/16W10K

R23141

25%MF-LF

1/16W0

NOSTUFF

402

R2316

1

25%MF-LF

1/16W10K

402

R2317

1

25%

1/16W10K

402MF-LF

R2318

1

25%MF-LF

1/16W402

10K

R23191

2402

5%MF-LF

1/16W10K

R2320

1

2

10K1/16W

MF-LF5%

402

RP2300

1 2 3 4

8 7 6 5

SM-LF

10K5%1/16W

R23991 2

100K

1/16WMF-LF402

5%

R2398

1

2

1K

402

5%MF-LF

1/16W

R2397

1

21/16W402

8.2K

MF-LF5%

R2396

1

2402

10K1/16W

5%MF-LF

R2395

1

25%

402MF-LF

1/16W8.2K

U2100

AC1

B2

AB18

A20

B23

F19

E19

R4

E22

AC22

AC20

AH18

AF21

AF19

R3

D20

A21

B21

E23

AG18

AC19

U2

AD21

AH19

AE19

AD20

AE20

AC21

AC18

E21

E20

C19

A26

C23

AA4

A28

Y4

AH21

B24

D23

F22

C22

B22

B25

A25

A19

A27C20

A22

AF20

C21

AD22

F20

ICH7-MSBBGA

OMIT

R23881

2

10K5%

MF-LF1/16W

402

R2323

1

2

NO_REBOOT_MODE

1/16W1K

5%

402MF-LF

R2326

1

25%402MF-LF1/16W10K

NOSTUFF

R2327

1

2

10K

4021/16W

MF-LF5%

NOSTUFF

R23431

2 MF-LF1/16W

8.2K

402

5%

B

23 105

051-7270

SYNC_MASTER=M59_MG SYNC_DATE=07/25/2006

SB: 3 OF 4

INT_SERIRQ

=PP3V3_S0_SB_GPIO

SATA_C_PWR_EN_L

PM_DPRSLPVR

PM_BATLOW_L

SB_CLK48M_USBCTLR

SV_SET_UP

SMB_CLK

SATA_C_DET_L

SB_GPIO19

SB_GPIO21

SB_GPIO37

SB_CLK14P3M_TIMER

SUS_CLK_SB

PM_SLP_S3_L

PM_SLP_S4_L

PM_SLP_S5_L

PM_SB_PWROK

PM_SYSRST_L

PM_SUS_STAT_L

BIOS_REC

VR_PWRGD_CK410

=PP3V3_S5_SB

=PP3V3_S5_SB_PM

TP_SB_GPIO6

CRB_SV_DET

=PP3V3_S5_SB

FWH_MFG_MODE

BIOS_REC

=PP3V3_S0_SB_GPIO

SATA_C_PWR_EN_L

PM_BMBUSY_L

SB_SPKR

SMB_DATA

=PP3V3_S5_SB

SMC_RUNTIME_SCI_L

PM_RSMRST_L

PM_LAN_ENABLE

PM_PWRBTN_L

PCIE_WAKE_L

FWH_MFG_MODE

PM_STPPCI_L

SMB_ALERT_L

PM_THRM_L

SMC_EXTSMI_L

PM_CLKRUN_L

PM_STPCPU_L

TP_AZ_DOCK_RST_L

TP_GPU_D3COLD_RST_L

=PP3V3_S5_SB

SMS_INT_L

IDE_RESET_L

SV_SET_UP

CRB_SV_DET

TP_SB_GPIO25_DO_NOT_USE

SB_CLK100M_SATA_OE_L

TP_SB_GPIO38

SB_GPIO26

SMC_WAKE_SCI_L

LAN_ENERGY_DET

SMC_SB_NMI

SMLINK<1>

SMLINK<0>

SMB_LINK_ALERT_L

PM_RI_L

58C6

65D3

65D3

65D3

65D3

58C6

65B3

64C8

51B5

25C8

25C8

65B3

25C8

58C6

25C8

51C5

23B3

84C6

51B5

49C5

64B8

49B7

50A2

23D8

65D3

23D8

23D5

23D8

47C3

51C4

23D4

51B5

49C7

21D3

59C8

23C3

43B7

49C5

50A2

26C5

49C5

23D4

26C5

23D4

21D3

23B7

39C6

49C5

23B7

50B2

23B6

5C2

21C3

23A3

14B7

49B7

34C7

5C2

27D8

36B5

34A6

6C6

42A8

41B6

49C5

26A6

5B2

5C2

23A6

26B8

23A7

11B5

23C3

23B7

23C5

23C5

21C3

23B3

14B6

27D8

23A7

49B7

49D7

49D7

49D7

5B1

23A6

33C4

49B7

49B7

5C2

33C4

26A4

23A7

49B5

36D5

5C2

23B6

33B4

64B7

49D5

40A3

49D7

(6 OF 6)

VSS

V5REF_SUS

VCC3_3

VCCDMIPLL

VCCSATAPLL

VCC3_3

VCCRTC

VCCUSBPLL

VCCSAUS1_5

VCC PAUX

USB COREVCC1_5_A

ARX

USB

PCI

IDE

VCCA3GP

CORE

ATX

VCC1_5_A

VCC3_3

VCC3_3

VCCSUS3_3

VCC1_5_A

VCCSUS3_3

VCCSUS3_3

VCC1_5_A

VCC1_5_A

VCC1_5_A

VCCLAN1_5

V_CPU_IO

VCC3_3/VCCHDA

VCCSUS3_3/VCCSUSHDA

VCCLAN_3_3

VCC1_05

V5REF

VCC1_5_B

(5 OF 6)

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

CODEC IC’S CONSIDERED SO FAR ARE 3.3V

DEPENDING ON VIO OF AZALIA INTERFACE

VCCHDA AND VCCSUSHDA CAN BE 1.5V OR 3.3V

NOTE:

VOLTAGE GENERATED INTERNALLY

SO NO CONNECT HERE

VOLTAGE GENERATED INTERNALLY

SO NO CONNECT HERE

CHANGE SYMBOL TO 1.05

CHANGE SYMBOL TO 1.05

S0 OR S3 IF NOT

S3 IF INTERNAL LAN IS USED

NOTE FOR VCCLAN_3_3:

0 0

U2100A4

A23

B1

B8

B11

B14

B17

B20

B26

B28

C2

C6

C27

D10

D13

D18

D21

D24

E1

E2

E4

E8

E15

F3

F4

F5

F12

F27

F28

G1

G2

G5

G6

G9

G14

G18

G21

G24

G25

G26

H3

H4

H5

H24

H27

H28

J1

J2

J5

J24

J25

J26

K24

K27

K28

L13

L15

L24

L25

L26

M3

M4

M5

M12

M13

M14

M15

M16

M17

M24

M27

M28

N1

N2

N5

N6

N11

N12

N13

N14

N15

N16

AE24

AE25

AF2

AF4

AF8

AF11

AF27

AF28

N17

AG1

AG3

AG7

AG11

AG14

AG17

AG20

AG25

AH1

AH3

N18

AH7

AH12

AH23

AH27

N24

N25

N26

P3

P4

P12

P13

P14

P15

P16

P17

P24

P27

P28

R1

R11

R12

R13

R14

R15

R16

R17

R18

T6

T12

T13

T14

T15

T16

T17

U4

U12

U13

U14

U15

U16

U17

U24

U25

U26

V2

V13

V15

V24

V27

V28

W6

W24

W25

W26

Y3

Y24

Y27

Y28

AA1

AA24

AA25

AA26

AB4

AB6

AB11

AB14

AB16

AB19

AB21

AB24

AB27

AB28

AC2

AC5

AC9

AC11

AD1

AD3

AD4

AD7

AD8

AD11

AD15

AD19

AD23

AE2

AE4

AE8

AE11

AE13

AE18

AE21

OMIT

BGA

ICH7-MSB

U2100

G10

AD17

F6

AE23

AE26

AH26

L11

P18

T11

T18

U11

U18

V11

V12

V14

V16

V17

L12

V18

L14

L16

L17

L18

M11

M18

P11

AB7

AC6

AB9

AC10

AD10

AE10

AF10

AF9

AG9

AH9

AB17

AC17

AC7

T7

F17

G17

AB8

AC8

A1

H6

H7

J6

J7

AD6

AE6

AF5

AF6

AG5

AH5

AB10

AA22

AA23

AD28

D26

D27

D28

E24

E25

E26

F23

F24

G22

AB22

G23

H22

H23

J22

J23

K22

K23

L22

L23

M22

AB23

M23

N22

N23

P22

P23

R22

R23

R24

R25

R26

AC23

T22

T23

T26

T27

T28

U22

U23

V22

V23

W22

AC24

W23

Y22

Y23

AC25

AC26

AD26

AD27

U6

B27

AH11

AG19

A5

B13

B16

B7

C10

D15

F9

G11

G12

AA7

G16

AB12

AB20

AC16

AD13

AD18

AG12

AG15

AG28

AA2

Y7

V5

V1

W2

W7

W5

AD2

K7

C28

G20

R7

P7

A24

L1

L2

L3

L6

L7

M6

M7

N7

E3

C24

D19

D22

G19

K3

K4

K5

K6

C1

OMIT

BGASB

ICH7-M


SB: 4 OF 4

B

24 105

051-7270

=PP1V5_S0_SB_VCCUSBPLL

=PP1V5_S0_SB_VCC1_5_A_USB_CORE

=PP1V5_S0_SB_VCC1_5_A

=PP3V3_S5_SB_VCCSUS3_3_USB

=PP3V3_S5_SB_VCCSUS3_3

PP3V3_S5_SB_RTC

=PP3V3_S0_SB_VCC3_3_PCI

=PP3V3_S0_SB_VCC3_3_IDE


=PP1V5_S0_SB_VCC1_5_A_ATX

=PP3V3_S0_SB_VCC3_3

=PP1V5_S0_SB_VCCSATAPLL

=PP1V5_S0_SB_VCC1_5_A_ARX

PP1V5_S0_SB_VCCDMIPLL

=PP3V3_S0_SB_VCC3_3


=PP3V3_S5_SB_3V3_1V5_VCCSUSHDA

=PP3V3_S0_SB_3V3_1V5_VCCHDA

=PP3V3_S0_SB_VCCLAN3_3

=PPVCORE_S0_SB

PP5V_S5_SB_V5REF_SUS

PP5V_S0_SB_V5REF

PP1V5_S0_SB_VCC1_5_B

65C3

65C3

65B3

65B3

25D2

26D3

25D2

25C6

25C6

65D6

65C6

65C6

65C6

65C3

25B6

25A4

65B3

65B3

25B6

65C6

25B8

65C6

65C6

25B8

25C4

65B3

65B3

65D6

25B6

25B6

25B2

25C2

25D2

24A5

21D6

25A4

25B4

24B3

25C6

24B5

25D6

25D6

25A5

24B5

21C1

65D3

25C4

25D3

25D3

25C7

25D7

22C1

NC

NC

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

SECONDARY SIDE OR 3.56MM ON PRIMARY

ICH VCCDMIPLL BYPASS

PLACE C2520 NEAR PIN E3 OF SB

PLACEMENT NOTE:

PLACE C2503 < 2.54MM OF PIN AD17 OF SB

ON SECONDARY SIDE OR 3.56MM ON PRIMARY


PLACE C2504 < 2.54MM OF PIN F6 OF SB

PLACEMENT NOTE:

(ICH REFERENCE FOR 5V TOLERANCE ON RESUME WELL LOGIC)

ICH V5REF_SUS BYPASS

(ICH SUSPEND 3.3V PWR)

ICH VCCSUS3_3 BYPASS

(ICH LOGIC&IO[ATX] 1.5V PWR)

(ICH LOGIC&IO[ARX] 1.5V PWR)

ICH VCC1_5_A/ARX BYPASS

ICH VCC3_3 BYPASS

PLACE C2509 NEAR PIN B27 OF SB

PLACEMENT NOTE:

ICH VCC3_3 BYPASS

(ICH RTC 3.3V PWR)

ICH VCCRTC BYPASS

V5, W2, OR W7

3.56MM ON PRIMARY NEAR PINS AA7 ... AG19

3.56MM ON PRIMARY NEAR PIN AD2

ICH VCC_PAUX/VCCLAN3_3 BYPASS

(ICH LAN I/F BUFFER 3.3V PWR)

PLACEMENT NOTE:

PLACE CAPS NEAR PINS

AB8 AND AC8 OF SB

ICH USB/VCCSUS3_3 BYPASS

(ICH SUSPEND USB 3.3V PWR)

PLACE CAPS NEAR PINS

K3 ... N7 OF SB

PLACE C2520 NEAR PIN C1 OF SB

NEAR PINS D28, T28, AD28

PLACEMENT NOTE:

ICH VCC1_5_A/ATX BYPASS

(ICH IO BUFFER 3.3V PWR)

(ICH REFERENCE FOR 5V TOLERANCE ON CORE WELL INPUT)

ICH VCCSATAPLL BYPASS

(ICH SATA PLL 1.5V PWR)

PLACE < 2.54MM OF SB ON SECONDARY OR

ICH V_CPU_IO BYPASS

(ICH CPU I/O 1.05V PWR)

ICH IDE/VCC3_3 BYPASS


(ICH PCI I/O 3.3V PWR)

A24 ... G19 AND P7 OF SB

DISTRIBUTE IN PCI SECTION OF SB

NEAR PINS A5 ... G16

(ICH IO BUFFER 3.3V PWR)

3.56MM ON PRIMARY NEAR PIN AG9

3.56MM ON PRIMARY NEAR PIN AG5

PLACEMENT NOTE:

PLACEHOLDER

FOR 270UFPLACE CAPS NEAR PINS

PLACEMENT NOTE:

PLACE CAPS NEAR PIN W5 OF SB

PLACEMENT NOTE:

PLACEMENT NOTE:

SB: 4 OF 4


ICH V5REF BYPASS

PLACEMENT NOTE:

ICH CORE/VCC1_05 BYPASS

(ICH CORE 1.05V PWR)

PLACEMENT NOTE:

PLACE CAP UNDER SB NEAR PINS V1,

3.56MM ON PRIMARY NEAR PIN U6

PLACEMENT NOTE:

PLACEMENT NOTE:

PLACEMENT NOTE:

(ICH SUSPEND 3.3V PWR)

ICH VCCSUS3_3 BYPASS

PLACEMENT NOTE:

PLACEMENT NOTE:

ICH VCC1_5A BYPASS

(ICH LOGIC&IO 1.5V PWR)

(ICH USB CORE 1.5V PWR)

3.56MM ON PRIMARY NEAR PINS A1 ... J7


ICH USB CORE/VCC1_5_A BYPASS

PLACEMENT NOTE:

PLACEMENT NOTE:

PLACEMENT NOTE:

3.56MM ON PRIMARY NEAR PIN AH11


PLACEMENT NOTE:


PLACEMENT NOTE:

(ICH IDE I/O 3.3V PWR)

ICH PCI/VCC3_3 BYPASS

(ICH DMI PLL 1.5V PWR)

(ICH USB PLL 1.5V PWR)

ICH VCCUSBPLL BYPASS


PLACE C2500 & C2505-07 < 2.54MM OF SB

PLACE NEAR PINS AE23, AE26 & AH26 OF SB

(ICH INTEL HDA CORE 3.3V PWR)

ICH VCC3_3/VCCHDA BYPASS

PLACE CAPS AT EDGE OF SB

PLACEMENT NOTE:


PLACE < 2.54MM OF SB ON

ICH VCCA3GP(VCC1_5_B BYPASS

(ICH IO,LOGIC 1.5V PWR)

C25101

2 X5R16V10%0.1UF

402

0

C25121

2402

0.1UF10%16VX5R

0

R25001 2

1

5%1/10WMF-LF 603

C25241

2

4.7UF20%6.3VCERM603

C25221

2

0.1UF10%16VX5R402

D25021

6

5BAT54DWSOT-363

D25024

3

2BAT54DWSOT-363

L2507

1 2

1206

0.28-OHM

C25001

2

CASE-B2

2.5VPOLY

220UF20%

C25031

2

0.1UF

402

10%16VX5R

0

C25041

2 X5R16V10%0.1UF

402

0

R2501

12

5%

MF-LF1/16W

402

10

L2500

1 2

100-OHM-EMISM-3

0

C25051

2

0.1UF10%16VX5R402

C25061

2 X5R16V10%0.1UF

402

C25071

2

0.1UF16V10%

X5R402

C25011

2

0.01UF10%16VCERM402

C25081

2603

10UF20%6.3VX5R

0

C25091

210%16VX5R402

0.1UF

0

C25111

2 X5R402

16V10%0.1UF

0

C25171

2

0.1UF

402X5R16V10%

0

C25131

2

0.1UF10%16VX5R402

0

0

C25141

2402

6.3VCERM

10%1UF

0

C25201

2

0.1UF10%16VX5R402

C25151

2402X5R16V10%0.1UF

0

0

C25161

2

CASE-C2POLY

20%2.5V

330UF

R2502

1

2

5%

1/16W

402MF-LF

100C25021

2

1UF10%6.3VCERM402

C25181

2402

0.1UF10%16VX5R

0

C25191

2 X5R16V10%0.1UF

402

0

C25211

2

0.1UF10%16V

402X5R

0

C25231

2 X5R16V10%0.1UF

402

0

C25251

2

0.1UF

X5R16V10%

402

0

C25261

2 X5R16V10%0.1UF

402

C25271

2 X5R16V10%0.1UF

402

C25281

2 X5R16V10%0.1UF

402

C25291

2402

0.1UF10%16VX5R

0

C25301

2402

0.1UF10%16VX5R

C25341

2402

0.1UF10%16VX5R

0

C25311

2402

0.1UF10%16VX5R

C25321

2402

0.1UF10%16VX5R

0

C25331

2402

0.1UF10%16VX5R

051-7270

10525

B

=PP1V5_S0_SB


=PPVCORE_S0_SB




MIN_NECK_WIDTH=0.25MMMIN_LINE_WIDTH=0.5MM

VOLTAGE=1.5VPP1V5_S0_SB_VCCDMIPLLPP1V5_S0_SB_VCCDMIPLL_F

VOLTAGE=1.5VMIN_LINE_WIDTH=0.5MMMIN_NECK_WIDTH=0.25MM




=PP1V5_S0_SB


=PP3V3_S0_SB_VCC3_3



=PP3V3_S0_SB_VCC3_3





PP3V3_S5_SB_RTC

=PP5V_S5_SB

=PP3V3_S0_SB

=PP3V3_S5_SB

=PP5V_S0_SB

PP5V_S5_SB_V5REF_SUS

MIN_NECK_WIDTH=0.25MM

VOLTAGE=5VMIN_LINE_WIDTH=0.3MM

PP5V_S0_SB_V5REFVOLTAGE=5V

MIN_LINE_WIDTH=0.3MMMIN_NECK_WIDTH=0.25MM

PP1V5_S0_SB_VCC1_5_BVOLTAGE=1.5V

MIN_LINE_WIDTH=0.5MMMIN_NECK_WIDTH=0.25MM

65D3

65C3

65C3

23D8

65D6

25B6

25D2

65B3

65B3

26D3

23D4

65C6

65C6

65D6

65B3

24C3

65C6

65B3

65C6

24B3

65C6

24B3

25C6

65C6

65B3

25B8

65C6

65C3

65C6

65B3

24B3

65B3

23B7

24D5

25A8

24A5

24D3

24C3

21C1

24A5

24B5

24C3

24A3

24A5

25C8

24A5

24B5

24B5

24B3

24B5

24B5

24B3

24A3

24D3

21D6

65B1

22B5

23A7

65A1

24D5

24D5

22C1

IO

IO

IN

IN

IN

IN

IO

IO

IO

IO

IO

IO

OUT

OUT IN

IN

OUT

IN OUT

IN

NCNC

IN

OUT

OUT

IO

IO

IO

IO

IO

IO

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

518S0487

Initial resistor values are based on CRB,

but may change after characterization.

fault protection for RTC battery.

for use as DVI_HPD in muxed graphics solution.

Pullup on SB_GPIO4 removed as it now defaults low

Platform Reset Connections

NC

NOTE: R2607 and D2600 form the double-

NC

Silk: "SYS RST"

Unbuffered

NC

NC

SB RTC Crystal Circuit

1G00 used as small & cheap inverter

100-ohm on NB page

Linda Card represents 3 loads

This part is never stuffed,

NCNC

on the board to short or

LIO represents X loads (2?)

Hook to inverter PWM AND gate (except M59)

This RST is used to mask a glitch output fromthe NB PWM output during reset.

On M59 this RST is used for layout reasons

Buffered

D3Cold Reset for GPU

to solder a reset button.

it provides a set of pads

RTC Battery Connector

R26001 2

MF-LF

5%

402

1/16W

20K

C2611 1

2

0.1UF

402CERM10V20%

C26051

2

402CERM6.3V10%1UF

R26981

2

5%1/16W

100K

MF-LF402

OMIT

R26061

2

1M

402MF-LF1/16W5%

R26971

2

MF-LF

10K

402

5%1/16W

R26072 1

402

5%

MF-LF1/16W

1K

C2608

1 2

12pF

CERM402

5%50V

C2609

1 2

CERM

12pF

50V5%

402

Y2600

24

13

SM-2

CRITICAL

32.768K

R26101 2

0

402MF-LF1/16W5%

R26091

2

10M

402MF-LF1/16W

5%

C26801

2

0.1UF20%

CERM402

10V

R26801

2

MF-LF402

100K

1/16W5%

R26811 2

5%1/16W

402

0

MF-LF R26831 2

1/16WMF-LF402

100

5%

R26841 2

MF-LF

0

1/16W5%

402

R26851 2

0

402MF-LF1/16W5%

R26821 2

MF-LF402

5%1/16W

0

R26961 2

1K

ITP

402

5%1/16WMF-LF

U2603

3

2

1

4

5MC74VHC1G00

SC70-5

U2680

3

2

1

4

5 MC74VHC1G08SC70

U2601

3

2

1

4

5

SC70MC74VHC1G08

D2600

1

4

6

3

5 2

BAT54DWSOT-363

R26881

2

100K

MF-LF402

1/16W5%

U2685

3

2

1

4

5

SC70MC74VHC1G08

C26851

2

0.1UF

CERM

20%10V

402

R26861

2

1/16WMF-LF

5%

402

10KR2687

1 2

5%1/16WMF-LF402

0

R26891 2

402

5%1/16WMF-LF

1K

C26891

2

10%50V

402CERM

0.001UF

J2600

3

4

1

2

BM02B-ACHKS-GAN-TF-LF-SN-M

CRITICAL

M-RT-SM

R26111

2

1/16W

402MF-LF

5%1.8K

C2607 1

2

0.1UF

402CERM10V20%

R26121

2402

MF-LF1/16W

5%10K R26221

2

10K5%1/16WMF-LF402

R2623 1 2 8.2KR2624 1 2 8.2KR2625 1 2 8.2KR2626 1 2 8.2KR2627 1 2 8.2KR2628 1 2 8.2K

R2629 1 2 8.2K

R2630 1 2 8.2K

R2631 1 2 8.2K

R2632 1 2 8.2K

R2633 1 2 8.2KR2634 1 2 8.2K

R2636 1 2 8.2K

R2637 1 2 8.2K

R2638 1 2 8.2KR2639 1 2 8.2KR2640 1 2 8.2KR2642 1 2 8.2K

C26101

2

402

6.3V10%

CERM

1UF

SB Misc

26

051-7270 B

105


=GPU_HPD_ENABLEMAKE_BASE=TRUE

GPU_SIGNAL_ENABLE

=PP3V3_S5_SB_PM

PLTRST_D3COLD_L

=GPU_DDC_ENABLE

PEG_RESET_L

=PP3V3_S0_RSTBUF

TP_GPU_D3COLD_RST_L

MAKE_BASE=TRUEPLT_RST_L

=PP3V3_S0_RSTBUF

TPM_LRESET_L

PLTRST_D3COLD_IN_L

MAKE_BASE=TRUEGPU_D3COLD_RESET_L

LIO_PLT_RESET_LMAKE_BASE=TRUE

M59_INVERTER_PLT_RST_L

INVERTER_PLT_RST_L

PLTRST_D3COLD_IN_L

=PP3V3_S0_SB_PM

PCI_IRDY_L

PCI_SERR_L

PCI_DEVSEL_L

PCI_PERR_L

PCI_REQ0_L

PCI_REQ1_L

PCI_REQ2_L

PCI_REQ3_L

INT_PIRQA_L

INT_PIRQB_L

INT_PIRQC_L

INT_PIRQD_L

SB_GPIO2

SB_GPIO3

=PP3V3_S0_SB_PCI

SB_RTC_X2

ENET_RST_L

MAKE_BASE=TRUEVOLTAGE=3.3V

PP3V3_G3C_SB_RTC_D

PCI_LOCK_L

PCI_STOP_L

PCI_TRDY_L

PCI_FRAME_L

PP3V3_S5_SB_RTC

PPVBATT_G3C_RTC_RVOLTAGE=3.3V

VR_PWRGOOD_DELAY

ALL_SYS_PWRGD

PM_SB_PWROKMAKE_BASE=TRUEVR_PWRGD_CK410_L

MAKE_BASE=TRUEPM_SYSRST_L

SB_SM_INTRUDER_L

SB_RTC_X1

DEBUG_RST_L

SMC_LRESET_L

NB_RST_IN_L

VR_PWRGD_CK410

CK410_PD_VTT_PWRGD_L

SB_RTC_RST_L

SB_RTC_X1_R

XDP_DBRESET_L

=PP3V3_S0_SB_PM

PLT_RST_BUF_L

=PP3V42_G3H_SB_RTC

VOLTAGE=3.3VPPVBATT_G3C_RTC

65D3

25A4

23D1

65A3

79A4

65A3

47C6

65B3

37D3

37C3

37D3

37D3

22B6

37D3

37C3

37C3

37D3

24B3

59C7

64B1

51B4

33A4

65B3

77B2

11B5

79A7

67A5

26B4

23C5

22A6

26B4

58B7

26C1

5C1

6C5

26A4

26B6

22A6

22A6

22A6

22A6

22B6

22B6

22B6

6B7

22A7

22A7

22A7

22A7

22A6

22A6

65B3

21D6

39C6

22A6

22A6

22A6

22A7

21D6

14B6

49D7

23C3 59C7

21D6

21D6

5C2

49C7

14B7

23C5

21D6

26B8

37A7

65D3

5A2

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

SLGLP436: U3301

(MASTER)

U5800

SMC

SMCU5800

(MASTER)

U5800

SMC

(MASTER)

Left I/O SMBus Connections:

SMC "B" SMBus Connections

SMC "Battery B" SMBus Connections

SMC "Battery A" SMBus Connections

J8250

(Write: 0x16 Read: 0x17)

Battery

J5400

(See Table)

CPU Temp

Left I/O Board


TMP401: U1001

SO-DIMM "B"

(Write: 0xA0 Read: 0xA1)

SMC

SO-DIMM "A"

U2 - Keyboard Controller

U1 - Trackpad Controller

Trackpad I2C Connections:



Left I/O SMBus Connections: Left I/O Board

(See Table)

(MASTER)

U5800

J2800

Clock Chip

(Write: 0xD2 Read: 0xD3)

U2100

(MASTER)

MAX6695: U6100


ICH7-M

J5500

(See Table)

(Write: 0xA4 Read: 0xA5)

J2900

TrackpadJ4900

ICH7-M SMBus Connections


GPU TempTMP401: U6150

Remote Temps

SMC "0" SMBus Connections

ExpressCard Slot(Address determined by ARP)

LIO - TMP106(Write: 0x92 Read: 0x93)

M35B - TMP106(Write: 0x90 Read: 0x91)

J4900

(See Table)

Top-Case

SMC "A" SMBus ConnectionsNOTE: SMC RMT bus remains powered and may be active in S3 state

SMC

(MASTER)

U5800

Top-Case SMBus Connections:


Palm Rest Temp - TMP275

R27001

2

4.7K5%

1/16W

402MF-LF

R27011

2

4.7K

1/16W5%

402MF-LF

R27801

2

4.7K

MF-LF402

5%1/16W

R27811

2

4.7K

MF-LF402

5%1/16W

R27911

2

MF-LF402

1/16W5%100K

R27901

2

MF-LF402

5%1/16W

100K

R27611

2

4.7K5%1/16WMF-LF402

R27601

2

4.7K

MF-LF402

1/16W5%

R27711

2

1/16WMF-LF402

5%4.7K

R27701

2

1/16W

402MF-LF

5%4.7K

R27511

2

4.7K5%1/16WMF-LF402

R27501

2

4.7K

1/16W5%

402MF-LF

051-7270 B

27 105


M1 SMBus Connections

SMB_A_S3_DATA

SMB_A_S3_CLK

=SMBUS_TOPCASE_SDA

=SMBUS_TOPCASE_SCL

SMBUS_SMC_A_S3_SDAMAKE_BASE=TRUE

MAKE_BASE=TRUESMBUS_SMC_A_S3_SCL

=PP3V3_S3_SMBUS_SMC_A_S3

SMBUS_SMC_0_S0_SDAMAKE_BASE=TRUE

=SMBUS_REMTHMSNS_SDA

=SMBUS_REMTHMSNS_SCL

=I2C_TRACKPAD_SDA

=I2C_TRACKPAD_SCL

=I2C_SODIMMB_SCL

=I2C_SODIMMB_SDA

=SMBUS_LIO_SB_SCL

=SMBUS_LIO_SB_SDA

SMB_CLK

SMB_DATA

=I2C_SODIMMA_SCL

SMB_CK410_DATA

SMB_CK410_CLK

SMB_0_S0_DATA

SMB_0_S0_CLK

=SMBUS_GPU_TDIODE_SDA

=SMBUS_GPU_TDIODE_SCL

=I2C_SODIMMA_SDA

SMBUS_SMC_0_S0_SCLMAKE_BASE=TRUE

=PP3V3_S0_SMBUS_SMC_0_S0

SMBUS_SB_SDAMAKE_BASE=TRUE

SMBUS_SB_SCLMAKE_BASE=TRUE

=PP3V3_S0_SMBUS_SB =PP3V3_S0_SMBUS_SMC_B_S0

MAKE_BASE=TRUESMBUS_SMC_B_S0_SCL

MAKE_BASE=TRUESMBUS_SMC_B_S0_SDA

=PP3V42_G3H_SMBUS_SMC_BSA

=PP3V3_S0_SMBUS_SMC_BSB

SMB_THRM_DATA

SMB_THRM_CLK

=SMBUS_LIO_SMC_SDA

=SMBUS_LIO_SMC_SCL

=SMBUS_BATT_SCLSMBUS_SMC_BSA_SCLMAKE_BASE=TRUE

=SMBUS_BATT_SDAMAKE_BASE=TRUESMBUS_SMC_BSA_SDA

SMB_B_S0_CLK

SMB_B_S0_DATA

SMB_BSA_CLK

SMB_BSA_DATA

SMBUS_SMC_BSB_SCLMAKE_BASE=TRUE

MAKE_BASE=TRUESMBUS_SMC_BSB_SDA

SMB_BSB_CLK

SMB_BSB_DATA

47C3

47C3

47C3

47C3

66B5

66B5 49B5

49B5

78C2

78C2

65C3

52C2

52C2

78C2

78C2

29A6

29A6

5B1

5B1

23D5

23D5

28A6

33B6

33B6

49C5

49C7

52B3

52B3

28A6

65B3 65B3 65B3

65D3

65B3

10B3

10B3

5B1

5B1

5D1

5D1

49B5

49B5

49B5

49B5

49C5

49C7

VSS2

DQS0*

DQ5

VSS0

DQ4

VSS5

DQ6

VSS29

DM0

VSS7

DM1

DQ7

VDD1

DQ30

DQ23

VSS22

NC/ODT1

RAS*

SA1

SA0

VSS58

DQ63

DQ62

VSS56

DQS7

DQS7*

VSS54

DQ60

VSS52

DQ54

VSS50

VSS48

CK1*

CK1

VSS46

DQ53

DQ52

VSS44

VSS42

DQS5

DQS5*

VSS39

DQ45

DQ44

VSS37

DQ39

DQ38

VSS35

DM4

VSS34

DQ37

DQ36

VSS32

NC3

VDD11

NC/A13

ODT0

VDD9

S0*

BA1

VDD7

A0

A2

A4

VDD5

A6

A7

A11

VDD3

NC/A14

NC/A15

NC/CKE1

VSS30

DQ31

DQS3

DQ29

DQ28

VSS24

DQ22

DM2

NC0

VSS19

DQ21

DQ20

VSS17

VSS15

DQ15

DQ14

VSS13

CK0*

CK0

VSS11

DQ13

DQ12

DQ47

DQ46

DQ61

DQ55

DM6

VDDSPD

SCL

SDA

VSS57

DQ59

DQ58

VSS55

DM7

VSS53

DQ56

VSS51

DQ50

VSS49

DQS6*

VSS47

NC_TEST

VSS45

DQ49

DQ48

VSS43

VSS41

DM5

VSS40

DQ41

VSS38

DQ35

VSS36

DQS4

DQS4*

VSS33

DQ33

DQ32

VSS31

VDD10

NC/S1*

CAS*

VDD8

WE*

BA0

A10/AP

VDD6

A1

A3

A5

VDD4

A8

A9

A12

VDD2

BA2

NC2

VDD0

CKE0

DQ27

DQ26

VSS27

NC1

DM3

DQ25

DQ24

VSS23

DQ19

DQ18

VSS21

DQS2

DQS2*

VSS18

DQ17

DQ16

VSS16

VSS14

DQ11

DQ10

VSS12

DQS1

DQS1*

DQ9

DQ8

VSS8

DQ3

DQ2

VSS6

DQS0

VREF

DQ34

DQ40

DQ42

DQ43

DQS6

DQ51

DQ57

KEY

VSS9

DQ1

VSS4

DQ0

VSS1

DQS3*

VSS26

VSS28

VSS25

VSS10

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

NC

DDR2 Bypass Caps(For return current)

ADDR=0xA0(WR)/0xA1(RD)

NC

NC

NC

NC

- =PPSPD_S0_MEM (2.5V - 3.3V)

- =PP1V8_S3_MEM

BOM options provided by this page:

(NONE)

Power aliases required by this page:

NC

- =I2C_SODIMMA_SCL

- =I2C_SODIMMA_SDA

NOTE: This page does not supply VREF.

The reference voltage must be provided

by another page.

Signal aliases required by this page:

Page Notes

516S0471

"Expansion" (surface-mount) slot

C28131

2

402

6.3VCERM

1UF10%

C28121

2

402

6.3VCERM

1UF10%

C28091

2

10UF

X5R603

20%6.3V

C28111

2

402

6.3VCERM

1UF10%

C28081

2

10UF

X5R603

20%6.3V

C28101

2

402

6.3VCERM

1UF10%

C28191

2

402

10%6.3VCERM

1UFC28181

2

402

10%6.3VCERM

1UF

C28171

2

402

6.3VCERM

1UF10%

C28161

2

402

6.3VCERM

1UF10%

C28211

2

402

10%6.3VCERM

1UFC28201

2

402

10%6.3VCERM

1UF

C28151

2

402

6.3VCERM

1UF10%

C28141

2

402

6.3VCERM

1UF10%

C28001

2

0.1uF

CERM402

20%10V

J2800

102A

105A

90A89A

101A

100A99A

98A97A

94A

92A

93A

91A

107A

106A

85A

113A

30A

32A

164A

166A

79A

10A

26A

52A

67A

130A

147A

170A

185A

5A

35A

37A

20A

22A

36A

38A

43A

45A

55A

57A

7A

44A

46A

56A

58A

61A

63A

73A

75A

62A

64A

17A

74A

76A

123A

125A

135A

137A

124A

126A

134A

136A

19A

141A

143A

151A

153A

140A

142A

152A

154A

157A

159A

4A

173A

175A

158A

160A

174A

176A

179A

181A

189A

191A

6A

180A

182A

192A

194A

14A

16A

23A

25A

13A

11A

31A

29A

51A

49A

70A

68A

131A

129A

148A

146A

169A

167A

188A

186A

201

202

203

204

116A

86A

84A

80A

119A

115A

50A

69A

83A

120A

163A

114A

108A

110A

198A

200A

197A

195A

81A

117A 118A

82A

87A 88A

95A 96A

103A 104A

111A 112A

199A

1A 2A

27A 28A

33A 34A

39A 40A

41A 42A

47A 48A

3A

53A 54A

59A 60A

65A 66A

71A 72A

77A

8A

78A

121A 122A

127A 128A

132A

133A

138A

139A

144A

145A

149A 150A

155A 156A

161A 162A

165A

168A

171A

9A

172A

177A 178A

183A 184A

187A

190A

193A

196A

12A

15A

18A

21A

24A

109A

F-RT-SM-M9

CRITICAL

DDR2-SODIMM-DUAL

C2801 1

2

2.2uF20%

603CERM16.3V


DDR2 SO-DIMM Connector A

051-7270 B

10528

=PP1V8_S3_MEM

MEM_A_DQ<28>

MEM_A_DQ<25>

MEM_A_DQ<30>

MEM_A_A<10>

MEM_A_DQ<43>

MEM_A_DQ<56>

MEM_A_DQS_N<7>

MEM_A_DQ<63>

MEM_A_DQS_P<7>

MEM_A_DQ<62>

MEM_A_DQ<57>

MEM_A_DQ<60>

MEM_A_DQ<55>

MEM_A_DQ<45>

MEM_A_DQ<61>

MEM_A_DQ<59>

MEM_A_DQS_N<1>

MEM_A_DQS_P<1>

MEM_A_DQ<10>

MEM_A_DM<1>

MEM_A_DQ<15>

MEM_A_DQ<9>

MEM_A_DQ<3>

MEM_A_DQ<26>

MEM_A_DQS_P<3>

MEM_A_DQ<44>

DIMM_OVERTEMP_L

MEM_A_DQ<49>

MEM_A_DQ<52>

MEM_A_DQS_P<6>

MEM_A_DQS_N<6>

MEM_A_DQ<54>

MEM_A_DQ<47>

MEM_A_DM<5>

MEM_CLK_N<1>

MEM_A_DQ<42>

MEM_A_DQ<40>

MEM_A_DQ<36>

MEM_A_DQ<32>

MEM_A_DM<4>

MEM_A_DQ<34>

MEM_A_DQ<38>

MEM_A_A<13>

MEM_CS_L<0>

MEM_A_A<2>

MEM_A_A<4>

MEM_A_A<6>

MEM_A_A<7>

MEM_A_A<14>

MEM_A_A<15>

MEM_A_DQ<21>

MEM_A_DQ<0>

MEM_CLK_N<0>

MEM_CLK_P<0>

MEM_A_DQ<8>

=I2C_SODIMMA_SCL

=I2C_SODIMMA_SDA

MEM_A_DQ<48>

MEM_A_DQ<53>

MEM_A_DM<6>

MEM_A_DQ<50>

MEM_A_DQ<51>

MEM_A_DQ<46>

MEM_A_DQ<41>

MEM_A_DQS_P<5>

MEM_A_DQS_N<5>

MEM_A_DQ<58>

MEM_A_DM<7>

MEM_A_DQ<33>

MEM_A_DQ<37>

MEM_A_DQS_P<4>

MEM_A_DQS_N<4>

MEM_A_DQ<39>

MEM_A_DQ<35>

MEM_ODT<1>

MEM_A_DQ<7>

MEM_A_WE_L

MEM_A_BS<0>

MEM_A_A<1>

MEM_A_A<3>

MEM_A_A<5>

MEM_A_A<8>

MEM_A_A<9>

MEM_A_A<12>

MEM_A_BS<2>

MEM_CKE<0>

MEM_A_DQ<27>

MEM_A_DM<3>

MEM_A_DQ<16>

MEM_A_DQ<20>

MEM_A_DQS_P<2>

MEM_A_DQS_N<2>

MEM_A_DQ<18>

MEM_A_DQ<19>

MEM_A_DQ<6>

MEM_A_DQS_P<0>

MEM_A_DQS_N<0>

MEM_A_DQ<4>

MEM_A_DQ<5>

MEM_A_DQ<11>

MEM_A_DQ<14>

MEM_CKE<1>

MEM_A_BS<1>

MEM_A_DQ<1>

MEM_A_DQ<22>

MEM_A_DM<2>

MEM_A_DQ<17>

MEM_A_DQ<29>

MEM_A_DQ<24>

MEM_A_DQ<31>

MEM_A_A<11>

MEM_A_A<0>

MEM_A_RAS_L

MEM_ODT<0>

MEM_CS_L<1>

MEM_A_CAS_L

MEM_A_DQ<23>

MEM_A_DQS_N<3>

MEM_A_DQ<12>

MEM_A_DQ<13>

MEM_A_DQ<2>

=PP1V8_S3_MEM

=PPSPD_S0_MEM

=PP1V8_S3_MEM

MEM_CLK_P<1>

MEM_A_DM<0>

MEM_VREF

65B6

65B6 65B6

29D6

29D6 29D6

29D3

29D3 29D3

29B2

29B2

65A3

29B2

28D6

30C6

50D3

30C6

30D6

30C6

30C6

30C6

30C6

30C6

30B6

30B6

30C6

30C6

30C6

30C6

30C6

30C6

30B6

30D6 30D6

30B6

30C6

30C6

30B6

30C6

30D6

30B6

28D3

29A6

28D6

32B3

28D3

15C7

15C7

15C7

15B5

15B7

15B7

15C5

15A7

15C5

15A7

15B7

15A7

15B7

15B7

15A7

15B7

15C5

15C5

15C7

15D5

15C7

15C7

15D7

15C7

15C5

15B7

29C3

15B7

15B7

15C5

15C5

15B7

15B7

15C5

14D4

15B7

15B7

15B7

15C7

15C5

15B7

15B7

15B5

14C4

15C5

15B5

15B5

15B5

6D6

6D6

15C7

15D7

14D4

14D4

15C7

27D6

27D6

15B7

15B7

15C5

15B7

15B7

15B7

15B7

15C5

15C5

15B7

15C5

15C7

15B7

15C5

15C5

15B7

15B7

14C4

15D7

15B5

15D5

15C5

15B5

15B5

15B5

15B5

15B5

15D5

14C4

15C7

15C5

15C7

15C7

15C5

15C5

15C7

15C7

15D7

15C5

15C5

15D7

15D7

15C7

15C7

14C4

15D5

15D7

15C7

15D5

15C7

15C7

15C7

15C7

15B5

15C5

15B5

14C4

14C4

15D5

15C7

15C5

15C7

15C7

15D7

28B2

29A3

28B2

14D4

15D5

29D6

VSS7

VSS12

VSS9

KEY

DQ57

DQ51

DQS6

DQ43

DQ42

DQ40

DQ34

DQ1

DQ0

VSS1

DQS0*

DQS0

VSS6

DQ2

DQ3

DQ8

DQ9

VSS10

DQS1*

DQS1

DQ10

DQ11

VSS14

VSS16

DQ16

DQ17

VSS18

DQS2*

DQS2

VSS21

DQ18

DQ19

VSS23

DQ24

DQ25

VSS25

DM3

NC1

VSS27

DQ26

DQ27

VSS29

CKE0

VDD0

NC2

BA2

VDD2

A12

A9

A8

VDD4

A5

A3

A1

VDD6

A10/AP

BA0

WE*

VDD8

CAS*

NC/S1*

VDD10

NC/ODT1

VSS31

DQ32

DQ33

VSS33

DQS4*

DQS4

VSS36

DQ35

VSS38

DQ41

VSS40

DM5

VSS41

VSS43

DQ48

DQ49

VSS45

NC_TEST

VSS47

DQS6*

VSS49

DQ50

VSS51

DQ56

VSS53

DM7

VSS55

DQ58

DQ59

VSS57

SDA

SCL

VDDSPD

DM6

DQ55

DQ61

DQ46

DQ47

DQ12

DM1

DM0

DQ7

DQ13

VSS11

CK0

CK0*

VSS13

DQ14

DQ15

VSS15

VSS17

DQ20

DQ21

VSS19

NC0

DM2

VSS22

DQ22

DQ23

VSS24

DQ28

DQ29

VSS26

DQS3*

DQS3

VSS28

DQ30

DQ31

VSS30

NC/CKE1

VDD1

NC/A15

NC/A14

VDD3

A11

A7

A6

VDD5

A4

A2

A0

VDD7

BA1

RAS*

S0*

VDD9

ODT0

NC/A13

VDD11

NC3

VSS32

DQ36

DQ37

VSS34

DM4

VSS35

DQ38

DQ39

VSS37

DQ44

DQ45

VSS39

DQS5*

DQS5

VSS42

VSS44

DQ52

DQ53

VSS46

CK1

CK1*

VSS48

VSS50

DQ54

VSS52

DQ60

VSS54

DQS7*

DQS7

VSS56

DQ62

DQ63

VSS58

SA0

SA1

DQ5

VSS2

VREF

VSS4

VSS8

VSS0

DQ4

VSS5

DQ6

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

"Factory" (thru-hole) slot

DDR2 Bypass Caps(For return current)

ADDR=0xA4(WR)/0xA5(RD)

Resistor prevents pwr-gnd short

NC

NC

NC

NC

NC


- =PPSPD_S0_MEM (2.5V - 3.3V)

- =PP1V8_S3_MEM


(NONE)


NC

Page Notes

- =I2C_SODIMMB_SCL

- =I2C_SODIMMB_SDA

by another page.

The reference voltage must be provided

NOTE: This page does not supply VREF.

516-0140

C29131

26.3V10%1UF

CERM402

C29121

26.3V10%1UF

CERM402

C29091

2

10UF

X5R603

20%6.3V

C29111

2

20%

402CERM

0.1uF

10V

C29081

2

10UF

X5R6.3V20%

603

C29101

26.3V10%1UF

CERM402

C29191

2

20%

402CERM

0.1uF

10V

C29181

2

20%

402CERM

0.1uF

10V

C29171

210V20%

402CERM

0.1uFC29161

26.3V10%1UF

CERM402

C29211

2

20%

402CERM

0.1uF

10V

C29201

2

20%

402CERM10V

0.1uF

C29151

26.3V10%1UF

CERM402

C29141

26.3V10%1UF

CERM402

R29001

2

10K5%1/16WMF-LF402

J2900

102B

105B

90B89B

101B

100B99B

98B97B

94B

92B

93B

91B

107B

106B

85B

113B

30B

32B

164B

166B

79B

10B

26B

52B

67B

130B

147B

170B

185B

5B

35B

37B

20B

22B

36B

38B

43B

45B

55B

57B

7B

44B

46B

56B

58B

61B

63B

73B

75B

62B

64B

17B

74B

76B

123B

125B

135B

137B

124B

126B

134B

136B

19B

141B

143B

151B

153B

140B

142B

152B

154B

157B

159B

4B

173B

175B

158B

160B

174B

176B

179B

181B

189B

191B

6B

180B

182B

192B

194B

14B

16B

23B

25B

13B

11B

31B

29B

51B

49B

70B

68B

131B

129B

148B

146B

169B

167B

188B

186B

201

202

116B

86B

84B

80B

119B

115B

50B

69B

83B

120B

163B

114B

108B

110B

198B

200B

197B

195B

81B

117B 118B

82B

87B 88B

95B 96B

103B 104B

111B 112B

199B

1B 2B

27B 28B

33B 34B

39B 40B

41B 42B

47B 48B

3B

53B 54B

59B 60B

65B 66B

71B 72B

77B

8B

78B

121B 122B

127B 128B

132B

133B

138B

139B

144B

145B

149B 150B

155B 156B

161B 162B

165B

168B

171B

9B

172B

177B 178B

183B 184B

187B

190B

193B

196B

12B

15B

18B

21B

24B

109B

F-RT-TH1

DDR2-SODIMM-DUAL

CRITICAL

C29001

210V20%

402CERM

0.1uFC2901 1

26.3V

CERM1603

20%2.2uF

DDR2 SO-DIMM Connector BSYNC_DATE=(MASTER)SYNC_MASTER=(MASTER)

B051-7270

29 105

MEM_B_DQ<1>

MEM_CLK_N<3>

MEM_B_DQ<0>

=PP1V8_S3_MEM

MEM_B_DQ<20>

=PP1V8_S3_MEM

MEM_B_DQ<27>

MEM_B_A<15>

MEM_B_DQ<31>

MEM_B_DQ<30>

MEM_B_DQ<26>

MEM_B_DQ<7>

MEM_B_DQ<5>

MEM_B_DQ<2>

MEM_B_DQ<3>

MEM_B_DQ<6>

MEM_B_DQ<4>

MEM_CLK_P<3>

MEM_B_DM<0>

MEM_B_DQ<10>

MEM_B_DQ<13>

MEM_B_DQS_P<1>

MEM_B_DQS_N<1>

MEM_B_DQ<22>

DIMM_OVERTEMP_L

MEM_B_DQS_P<0>

MEM_B_DQ<8>

MEM_B_DQ<59>

MEM_B_DQ<58>

MEM_B_DQ<63>

MEM_B_DQ<62>

MEM_CLK_P<2>

MEM_B_DM<7>

MEM_B_DQ<56>MEM_B_DQ<60>

MEM_B_DQ<57>MEM_B_DQ<61>

MEM_B_DQ<47>

MEM_B_DQS_N<7>

MEM_B_DQS_N<6>

MEM_B_DQS_P<6>

MEM_B_DQS_P<7>

MEM_B_A<5>

MEM_CKE<3>

MEM_B_A<14>

MEM_B_DM<3>

MEM_B_DQ<19>

MEM_B_DQ<11>

MEM_B_DQ<9>

MEM_B_BS<1>

MEM_B_A<0>

MEM_B_A<2>

MEM_B_A<4>

MEM_B_A<6>

MEM_B_A<7>

MEM_B_A<11>

MEM_B_DQS_P<3>

MEM_B_DQS_N<3>

MEM_B_DQ<28>

MEM_B_DQ<16>

MEM_B_DQ<17>

MEM_B_DM<2>

MEM_B_DQ<12>

MEM_B_DQ<32>

MEM_B_DQ<55>

MEM_CLK_N<2>

MEM_B_DQ<46>

MEM_B_DQS_P<5>

MEM_B_DQS_N<5>

MEM_B_DQ<45>

MEM_B_DQ<44>

MEM_B_DQ<39>

MEM_B_DQ<38>

MEM_B_DM<4>

MEM_B_DQ<37>

MEM_B_A<13>

MEM_ODT<2>

MEM_CS_L<2>

MEM_B_RAS_L

MEM_B_DQ<42>

MEM_B_DQ<49>

MEM_B_DQ<52>

MEM_B_DM<6>

MEM_B_DQ<51>

MEM_B_DQ<54>

MEM_B_DQ<43>

MEM_B_DM<5>

MEM_B_DQ<41>

MEM_B_DQ<40>

MEM_B_DQ<35>

MEM_B_DQ<34>

MEM_B_DQS_P<4>

MEM_B_DQS_N<4>

MEM_B_DQ<33>

MEM_B_DQ<36>

MEM_ODT<3>

MEM_CS_L<3>

MEM_B_CAS_L

MEM_B_WE_L

MEM_B_BS<0>

MEM_B_A<10>

MEM_B_A<1>

MEM_B_A<3>

MEM_B_A<8>

MEM_B_A<9>

MEM_B_A<12>

MEM_B_BS<2>

MEM_CKE<2>

MEM_B_DQ<25>

MEM_B_DQ<24>

MEM_B_DQ<29>

MEM_B_DQ<23>

MEM_B_DQS_P<2>

MEM_B_DQS_N<2>

MEM_B_DQ<21>

MEM_B_DQS_N<0>

MEM_B_DQ<14>

MEM_B_DM<1>

MEM_B_DQ<15>

=PPSPD_S0_MEM

=I2C_SODIMMB_SCL

=I2C_SODIMMB_SDA

MEM_B_DQ<48>

MEM_B_DQ<53>

MEM_B_DQ<50>

SODIMM_A_SA1

=PPSPD_S0_MEM

MEM_VREF

MEM_B_DQ<18>

=PP1V8_S3_MEM

65B6 65B6

65B6

29D6 29D3

29D6

29B2 29B2

29D3

28D6 28D6

65A3

65A3

28D6

28D3 28D3

50D3

30B6

30D6

30A6

30B6

30B6

30B6

30B6

30B6

30B6

30B6

30C6

30D6

30A6

30C6

30D6

30A6

30A6

30A6

30B6

30B6

30B6

30B6

30B6

30B6

30A6

30D6

29A3

29A6

32B3

28D3

15D4

14D4

15D4

28B2

15C4

28B2

15C4

6D6

15C4

15C4

15C4

15D4

15D4

15D4

15D4

15D4

15D4

14D4

15D2

15C4

15C4

15C2

15C2

15C4

28C3

15C2

15C4

15B4

15B4

15A4

15A4

14D4

15C2

15B4 15A4

15B4 15A4

15B4

15C2

15C2

15C2

15C2

15B2

14C4

6D6

15C2

15C4

15C4

15C4

15D2

15C2

15C2

15B2

15B2

15B2

15B2

15C2

15C2

15C4

15C4

15C4

15D2

15C4

15C4

15B4

14D4

15B4

15C2

15C2

15B4

15B4

15B4

15B4

15C2

15B4

15B2

14C4

14C4

15B2

15B4

15B4

15B4

15C2

15B4

15B4

15B4

15C2

15B4

15B4

15B4

15B4

15C2

15C2

15C4

15B4

14C4

14C4

15D2

15B2

15D2

15B2

15C2

15B2

15B2

15B2

15B2

15D2

14C4

15C4

15C4

15C4

15C4

15C2

15C2

15C4

15C2

15C4

15D2

15C4

28A6

27C6

27C6

15B4

15B4

15B4

28A6

28D6

15C4

28B2

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

One cap for each side of every RPAK, one cap for every two discrete resistors

Ensure CS_L and ODT resistors are close to SO-DIMM connector

C30511

2

402

10V20%

CERM

0.1uF

C30531

2

0.1uF

402CERM10V20%

C30521

2

0.1uF

CERM10V20%

402

C30501

2 CERM

0.1uF20%10V

402

C30551

2

20%10VCERM402

0.1uF

C30571

2

0.1uF

402CERM10V20%

C30591

2

20%10VCERM402

0.1uFC30581

2

0.1uF20%

CERM402

10V

C30561

2

402CERM10V20%0.1uF

C30541

2

0.1uF

402CERM10V20%

0

1

2

3

5

4

6

7

8

9

10

11

12

13

0

2

1

15B2 15C2 29B3 29B6 29C3 29C6

15D2 29B3 29B6 29C6

15B2 29B3

15D2 29B6

15B2 29B6

RP3058 3 6

SM-LF1/16W5%

56

RP3058 4 556SM-LF1/16W5%

RP3032 2 756SM-LF1/16W5%

RP3032 1 8

5% SM-LF1/16W

56

RP3052 2 7

1/16W SM-LF5%

56

RP3050 1 8565% 1/16W SM-LFRP3054 1 8565% 1/16W SM-LF

RP3056 1 8

1/16W5% SM-LF

56

RP3005 1 8

5% 1/16W SM-LF

56

RP3056 4 5

SM-LF1/16W5%

56

RP3058 2 7

SM-LF1/16W5%

56

RP3058 1 8

SM-LF1/16W5%

56

RP3054 4 5

SM-LF1/16W5%

56

RP3054 3 6

SM-LF1/16W5%

56

RP3052 1 8

SM-LF1/16W5%

56

RP3054 2 7

SM-LF1/16W5%

56

RP3052 3 6

SM-LF1/16W5%

56

RP3050 4 5

SM-LF1/16W5%

56

RP3050 3 6

SM-LF1/16W5%

56

RP3005 2 7

SM-LF1/16W5%

56

RP3050 2 7

SM-LF1/16W5%

56

RP3056 3 6

SM-LF1/16W5%

56

RP3056 2 7

1/16W5% SM-LF

56

RP3052 4 5

SM-LF1/16W5%

56

R3000 1 2

1/16W5% MF-LF 402

56

R3002 1 2

402MF-LF5% 1/16W

56

R3001 1 2

5% MF-LF 4021/16W

56

R3003 1 2

5% MF-LF 4021/16W

56

RP3005 4 5565% 1/16W SM-LF

RP3030 4 556SM-LF1/16W5%

RP3030 3 6565% 1/16W SM-LF

RP3010 1 856SM-LF1/16W5%

RP3010 2 756SM-LF1/16W5%

RP3034 2 7

5% 1/16W SM-LF

56

RP3030 1 8

5% 1/16W SM-LF

56

RP3032 3 6

5% 1/16W SM-LF

56

RP3030 2 7

5% 1/16W

56SM-LF

RP3005 3 6

5% 1/16W

56SM-LF

RP3034 1 8

5% 1/16W

56SM-LF

RP3034 4 5

5% 1/16W SM-LF

56

RP3032 4 5

5% 1/16W

56SM-LF

RP3036 1 8

SM-LF5% 1/16W

56

RP3034 3 6

5% 1/16W

56SM-LF

RP3036 3 6

5% 1/16W

56SM-LF

RP3036 4 556SM-LF1/16W5%

RP3036 2 756SM-LF1/16W5%

RP3010 4 556SM-LF1/16W5%

RP3010 3 6565% 1/16W SM-LF

R3010 1 2

402MF-LF5% 1/16W

56

R3011 1 2561/16W5% MF-LF 402R3012 1 2

402MF-LF5% 1/16W

56

R3013 1 2

402MF-LF1/16W

565%

0

1

0

1

1

0

2

0

1

2

3

4

5

6

7

10

11

9

8

13

12

14C4 28B3 28B6 29B3 29B6

14C4 28C3 28C6 29C3 29C6

15B5 15C5 28B3 28B6 28C3 28C6

15D5 28B3 28B6 28C6

15B5 28B3

15D5 28B6

15B5 28B6

2

3

2

3

C30391

2

20%10VCERM402

0.1uFC30381

2

0.1uF20%

CERM402

10V

C30331

2

20%10VCERM402

0.1uFC30321

2

402

20%10VCERM

0.1uF

C30311

2

402CERM10V20%0.1uF

C30301

2 CERM

0.1uF20%10V

402

C30111

2

0.1uF

10V20%

402CERM

C30101

2

0.1uF

402

20%10VCERM

C30071

2

20%

CERM402

0.1uF

10V

C30051

2

0.1uF

402CERM10V20%

C30021

2

20%10VCERM402

0.1uFC30001

2

402CERM10V20%0.1uF

C30371

2

0.1uF

402CERM10V20%

C30361

2

402CERM10V20%0.1uF

C30351

2

20%10VCERM402

0.1uFC30341

2

0.1uF

402CERM10V20%

0

1

2

3

14C4 28B3 28B6 29B3 29B6

30 105

B051-7270

Memory Active TerminationSYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)

MEM_CKE<3..0>

MEM_A_BS<2..0>

MEM_B_A<13..0>

MEM_ODT<3..0>

MEM_CS_L<3..0>

MEM_A_A<13..0>

MEM_B_BS<2..0>

=PP0V9_S0_MEM_TERM

MEM_B_RAS_L

MEM_B_CAS_L

MEM_A_RAS_L

MEM_A_CAS_L

MEM_A_WE_L

MEM_B_WE_L

65D6

VLDOIN VIN

VTT

VTTSNS

VTTREF

VDDQSNS

S3

S5

PGNDTHRML GNDPAD

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

Page Notes

- =PP0V9_S0_MEMVTT_LDO

- =PP1V8_S0_MEMVTT

- =PP5V_S0_MEMVTT




(NONE)

(NONE)

Okay to turn off 5V and

leave 1.8V powered in S3.

disable MEMVTT in sleep.

MEMVTT_EN can be used to

If power inputs are not S0,

DDR2 Vtt Regulator

C31021

2

10%

402

25V

0.1UF

X5R

U3100

84

7

9

11

1

10

2

3

6

5

TPS51100MSOP

CRITICAL

C3104 1

2

4.7UF

6.3V

603CERM

20%

C3101 1

2

10UF20%

X5R6.3V

603

R31001

2

1K

402MF-LF1/16W

5%

MEMVTT_EN_PU

C31051

2

22UF20%6.3VX5R805

C31061

2

22UF20%6.3VX5R805

31 105

B051-7270

Memory Vtt SupplySYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)

=PP0V9_S0_MEMVTT_LDO

=PP1V8_S0_MEMVTT

MEMVTT_VREFMEMVTT_EN

=PP5V_S0_MEMVTT

65D8

65B6

65A1

V+

V-

IN

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

U3200

3

4

1

5

6

2

CRITICAL

MAX4236EUTTSOT23-6-LF

C3200 1

2

20%0.1UF

402

10VCERM

C3205 1

2CERM402

220pF

25V5%

R32061

2

10K

1/16W1%

402MF-LF

R32051

2

10K

MF-LF402

1%1/16W

R32021

2

100K

MEMVREF_S3

MF-LF402

5%1/16W

R320312

5%1/16WMF-LF402

0

MEMVREF_S0

32 105

B051-7270

DDR2 VRefSYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)

MIN_NECK_WIDTH=0.15 mmVOLTAGE=0.9V


MAKE_BASE=TRUE

MEMVREF_OUT

=PP1V8_S3_MEMVREF

MEMVREF_UNBUFMIN_LINE_WIDTH=0.2 mmMIN_NECK_WIDTH=0.2 mmVOLTAGE=0.9V

MEM_VREF_NB_1

MEM_VREF_NB_0

MEM_VREF

=MEMVREF_EN

=PP3V3_S3_MEMVREF

MEMVREF_SHDN_L

29D6

65B6

14C2

14C2

28D6

64C6

65C3

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

IN

IO

OUT

IN

IO

IO

OUT

OUT

IN

IN

IN

IN

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

IN

VSS_SRC

THRML_PAD

VSS_REF

VSS_PCI

VSS_CPU

VSS_48

NC

SDA

PCIF_1

PCIF_0/ITP_EN

PCI_5/FCT_SEL_1

PCI_4

PCI_3

PCI_2

PCI_1

FS_B_TEST_MODE

REF_1/FCT_SEL_0

REF_0/FS_C/TEST_SEL

48M/FS_A

VTT_PWRGD*/PD

VDD_AVSS_A

XTAL_IN

XTAL_OUT

CLKREQ_8*

CLKREQ_6*

CLKREQ_5*

CLKREQ_4*

CLKREQ_3*

CLKREQ_1*

CPU_STOP*

PCI_STOP*

VDD_CPU

VDD_48

SCL

CPU_0*

CPU_0

CPU_1

CPU_1*

CPU_ITP/SRC_11*

CPU_ITP/SRC_11

SRC_0/LCD_CLK

SRC_0/LCD_CLK*

SRC_1

SRC_1*

SRC_2*

SRC_2

SRC_3

SRC_3*

SRC_4

SRC_4*

SRC_5*

SRC_5

SRC_7*

SRC_7

SRC_8*

SRC_6*

SRC_6

SRC_8

DOT_96*/27M_SS*

DOT_96/27M

VDD_SRC

VDD_REF

VDD_PCI

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

(NB CRT/TV GRAPHICS DOTCLK 100MHZ)

(GIGA LAN PCI-E 100 MHZ )

(INT PU)

(INT PU)

(INT PU)

(INT PU)

(GMCH HOST 133/167MHZ)

* FOR EXT. GRAPHIC SYSTEM

PIN 10

100MT_SSTDOT96C

DOT96T

DOT96T

27M NONSPREAD

OFF LOW

(PLACED 0.1UF NEAR THE RELATIVE POWER PIN)

(PORT80 LPC 33MHZ)

(NO USED)

(PULL UP PIN 68 TO ENABLE ITP HOST CLK)

(ICH SM BUS)

(ICH7M PCI 33MHZ)

0

(INT PU)

(ICH7M,SIO,LPC REF. 14.318MHZ)

(INT PD)

(GMCH G_CLKIN 100 MHZ )

(FROM ICH7 GPIO18 STPPCI* )(FROM ICH7 GPIO20 STPCPU* )

(ITP HOST 133/167MHZ)

(GMCH D_REFSSCLKIN DISPLAY PLL B 100MHZ)

(CPU HOST 133/167MHZ)

(INT PD)

(INT PD)

(INT PU)

PIN 6

* FOR INT. GRAPHIC SYSTEM

SRCT0

SRCT0

DOT96C

PIN 7 PIN 11

100MC_SST

FCTSEL1

00

0 1

1

1 1

27MSPREAD

TBD

SRCT0

SRCC0

SRCC0

SRCC0

FCTSEL0

(ICH SATA 100 MHZ)

(TPM LPC 33MHZ)(SMC LPC 33MHZ)

(EACH POWER PIN PLACED ONE 0.1UF)

(INT PU)

(INT PU)

(GPU PCI-E 100 MHZ )

NEED TO DECIDE THE CLKREQ CONNECTION,TO GPIO?(ICH7M DMI 100 MHZ )

(FROM ICH7 GPIO35)

(FROM GMCH CLK_REQ*)

(WIRELESS PCI-E 100 MHZ )

(GMCH D_REFCLKIN DISPLAY PLL A 96MHZ)

(FROM CPU VCORE PWR GOOD)

(ICH7M USB 48MHZ)

(FOR PCI-E CARD)

(FW PCI 33MHZ)

C33091

2 6.3V20%10UF

X5R603

C33051

2402

16VX5R

10%0.1UF

C33061

2

0.1UF10%

402X5R16V

C33071

2402

10%0.1UF

X5R16V

C33081

2 X5R16V

402

10%0.1UF

R33001

2

NO STUFF

1/16W

402

4751%

MF-LF

C33121

2603X5R6.3V

10UF20%

C33111

210%

X5R402

0.1UF16V

C33041

2402

10%16VX5R

0.1UFC33031

2 X5R16V

402

0.1UF10%

C33021

2

0.1UF10%16VX5R402

C33011

2402X5R16V

0.1UF10%

C33101

2402

10%

CERM6.3V

1UF

C33161

2

10UF6.3V20%

X5R603

C33151

210%

X5R16V

402

0.1UF

C33141

2402

6.3VCERM

10%1UF

R33031 2

1

MF-LF

5%1/16W

402

C33171

2 X5R

10UF20%6.3V

603

R33011

2

1/16W402MF-LF5%10K

Y33011 2

14.31818

5X3.2-SM

CRITICAL

U3301

4

9

59

20

60

25

34

45

44

42

41

37

36

55

6

7

8

40

57

58

63

64

65

56

68

1

54

53

47

48

10

11

13

14

15

16

18

19

21

22

23

24

26

27

29

30

33

32

69

3

38

43

61

67

49

12

17

28

35

5

39

46

62

66

52

31

2

51

50

CRITICAL

SLG8LP436QFNOMIT

L3302

1 2

0402-LF

FERR-120-OHM-1.5A

L3301

1 2

0402-LF

FERR-120-OHM-1.5A

C33891

2

12PF

402CERM

5%50V

C33901

2

12PF5%

CERM402

50V


CLOCKS

10533

051-7270 B

CK410_XTAL_INCK410_XTAL_OUT

=PP3V3_S0_CK410

CK410_PCIF1_CLK

CK410_PCI4_CLKCK410_PCI3_CLK

CK410_FSB_TEST_MODE

CK410_CLK14P3M_TIMERCK410_USB48_FSA

CK410_PD_VTT_PWRGD_L

CK410_DOT96_27M_P

CK410_SRC8_PCK410_SRC8_N


CK410_SRC_CLKREQ6_L

CK410_SRC6_NCK410_SRC6_P

CLK_NB_OE_LCK410_SRC5_PCK410_SRC5_N

SB_CLK100M_SATA_OE_LCK410_SRC4_PCK410_SRC4_N

CK410_SRC_CLKREQ3_L


CK410_SRC_CLKREQ1_LCK410_SRC1_PCK410_SRC1_N

CK410_LVDS_PCK410_LVDS_N

CK410_CPU2_ITP_SRC10_PCK410_CPU2_ITP_SRC10_N

CK410_CPU1_N

PM_STPCPU_LPM_STPPCI_L

MIN_NECK_WIDTH=0.2mmMIN_LINE_WIDTH=0.5mm

VOLTAGE=3.3VPP3V3_S0_CK410_VDD_REF

CK410_CPU1_P

CK410_CPU0_N

CK410_REF1_FCTSEL0

CK410_DOT96_27M_N

CK410_SRC_CLKREQ8_L

CK410_CPU0_P

CK410_SRC3_NCK410_SRC3_P

CK410_PCI5_FCTSEL1

CK410_PCIF0_CLK

CK410_PCI1_CLK

CK410_IREF

CK410_PCI2_CLK

SMB_CK410_DATASMB_CK410_CLK

PP3V3_S0_CK410_VDD48_PCIVOLTAGE=3.3V

MIN_NECK_WIDTH=0.2mmMIN_LINE_WIDTH=0.5mm

=PP3V3_S0_CK410

=PP3V3_S0_CK410 PP3V3_S0_CK410_VDD_CPU_SRC_A

MIN_NECK_WIDTH=0.2mmMIN_LINE_WIDTH=0.5mmVOLTAGE=3.3V

65B3

65B3

65B3

34A8

34A8

34A8

33D8

33D8

33D3

5A7

33D3

34D8

34B8

34B8

34C8

26A8

34B5

34C5

34C5

34B5

34B5

34A4

34D5

34D5

14B6

34C5

34C5

23C3

34C5

34C5

34A4

34C5

34C5

34A4

34B5

34B5

34B5

34B5

34D5

34D5

34D5

23C8

23C8

34D5

34D5

34A8

34B5

34A4

34D5

34B5

34C5

34A8

34D8

34D8

27D6

27D6

33C7

33C7

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

IN

IN

IN

IN OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUTIN

IN

OUTIN

OUT

OUT

OUTOUT

OUT

IO

IO

OUT

IN

OUT

OUT

IN

IN

IN

IN

IN

OUT

OUT

IN

OUT

IN

IN

IN

OUT

OUT

OUT

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

OUT

OUT

OUTIN

IN

IN

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

(TO ICH7M USB 48MHZ)

(PORT80 LPC 33MHZ)

(TO ICH7M PCI 33MHZ)

(TO SMC PCI 33MHZ)

(TO TPM PCI 33MHZ)

(TO FIREWIRE PCI 33MHZ)

as possible to the resistorscaps should be closePLACEMENT of these

(TO MCH FS_C)

(ICH7M 14.318MHZ)

(FROM CPU FS_C)

(TO MCH FS_A)

NEED TO CHECK THE BSEL PULLS

(TO MCH FS_B)

(FROM CPU FS_B)

(FROM CPU FS_A)

(GPU PCI-E Graphics 100MHz)

# NAPA PLATFORM ONLY SUPPORT 133M/166M CPU SPEED

RESERVED

400M

1

FS_A

(WIRELESS PCI-E MINI 100MHZ)

(ITP HOST 133/167MHZ)

(GMCH HOST 133/167MHZ)

(ExpressCard Slot)

NOSTUFF R3450,R3451,R3453 FOR MANUAL CPU FREQUENCY

(ICH7M DMI 100MHZ)

(GMCH G_CLKIN 100MHZ)

266M

133M

#

# 1

0

0

333M

100M

111

11

11

1

1

1

0

0

00

0

0

00

0

FS_C CPUFS_B

0

(Yukon PCI-E 100MHZ)

(GPU 27MHz Spread / Non-Spread)

200M

166M

(ICH7M SATA 100MHZ)

(CPU HOST 133/167MHZ)

GPU CLK OE*

Yukon CLK OE*

(NB CRT/TV GRAPHICS DOTCLK 100MHZ)

(NB LVDS GRAPHICS 100MHZ)

39C6

39C6

22C2

R34291 2

MF-LF

33

402

5%1/16W R3430

1 2

1/16W5%

402MF-LF

33

TPM

R34331 2

33

MF-LF402

5%1/16W

R34321 2

33

1/16W

402

5%

MF-LF

37B6

58C6

49C7

22A6

51C5 5C2

R34631 2

402

33

MF-LF

5%1/16W

22C2

R34671

2

5%

MF-LF

10K

402

1/16W

R34661

2

1/16W5%

402MF-LF

10K

R34691

2

MF-LF1/16W5%

402

1K

R34681 2

1/16W5%

402MF-LF

1K

R34721 2

1/16W5%

402MF-LF

1K

R34701

2

1/16W5%

402MF-LF

1K

R34711 2

1/16W5%

402MF-LF

1K

R34731

2

1/16W5%

402MF-LF

1K

R34751 2

1/16W5%

402MF-LF

1KR34741 2

1/16W5%

402MF-LF

1K

23D3

21B6 5A7

21B6 5A7

R34801

2

NOSTUFF

1/16W5%

MF-LF

1K

402

R34761 2

1/16W5%

402MF-LF

33

R34501 2

1/16W5%

402MF-LF

0

R34531 2

1/16W5%

402MF-LF

0

R34541

2

1/16W5%

402MF-LF

1K

NOSTUFF

R34511 2

1/16W5%

402MF-LF

0

R34521

2

NOSTUFF

1/16W5%

402

1K

MF-LF

47B3 5B1

47B3 5B1

12A6

12A6

7C6

R34861 2

5%

1K

1/16W

402MF-LF

R34851 2

5%

1K

MF-LF1/16W

402

7C6

84C6 11B3

84C6 11B3

R34241 2

MF-LF402

1/16W

0

5% R34251 2

5%

0

1/16W

402MF-LF

R34431 2

1/16W5%

0

402MF-LF

NO STUFF

R34441 2

NO STUFF

5%1/16WMF-LF402

0

R34021 2

1%

71.5

1/16W

402MF-LF

NO STUFF

R34051 2

1%

71.5

1/16W

402MF-LF

R34181 2

1%

121

MF-LF402

1/16W R34191 2

56

5%1/16W

402MF-LF

R34261

2MF-LF

5%1/16W

402

100K

NO STUFF

C34041

2

NOSTUFF

5%15PF

402CERM50V

C34031

2

NOSTUFF

5%15PF

50VCERM402

C34021

2

NOSTUFF

5%15PF

50VCERM402

C34011

2

NOSTUFF

5%15PF

CERM402

50V

C34001

2

NOSTUFF

15PF5%50VCERM402

R34171 2

1/16W5%

402MF-LF

33

R34011 2

1/16W5%

402MF-LF

2.2K

051-7270 B

10534


Clock Termination

GPU_CLK27MSS_IN

GPU_CLK27MGPU_CLK27MCK410_DOT96_27M_P

GPU_CLK27MSS_INCK410_DOT96_27M_N

NB_CLK_DREFCLKIN_N

CK410_SRC_CLKREQ1_L

CK410_SRC_CLKREQ8_L

CK410_SRC_CLKREQ6_L MINI_CLKREQ_LMAKE_BASE=TRUE

CK410_SRC_CLKREQ3_L EXCARD_CLKREQ_LMAKE_BASE=TRUE

CK410_27M_SPREADMAKE_BASE=TRUE

CK410_27M_NONSPREADMAKE_BASE=TRUE

=PP3V3_S0_CK410

CK410_REF1_FCTSEL0

CK410_PCI5_FCTSEL1

CK410_SRC1_P

CK410_CPU0_PMAKE_BASE=TRUEFSB_CLK_CPU_P

CK410_CPU0_NMAKE_BASE=TRUEFSB_CLK_CPU_N

CK410_CPU1_PMAKE_BASE=TRUEFSB_CLK_NB_P

CK410_CPU2_ITP_SRC10_PMAKE_BASE=TRUECPU_XDP_CLK_P

CK410_CPU2_ITP_SRC10_NMAKE_BASE=TRUECPU_XDP_CLK_N

CK410_SRC6_PMAKE_BASE=TRUEPCIE_CLK100M_MINI_P

CK410_SRC5_PMAKE_BASE=TRUENB_CLK100M_GCLKIN_P

MAKE_BASE=TRUENB_CLK100M_GCLKIN_N

CK410_SRC2_PMAKE_BASE=TRUESB_CLK100M_DMI_P

CK410_SRC8_PMAKE_BASE=TRUEENET_CLK100M_PCIE_P

CK410_SRC8_NMAKE_BASE=TRUEENET_CLK100M_PCIE_N

CK410_SRC3_PMAKE_BASE=TRUEPCIE_CLK100M_EXCARD_P

CK410_SRC3_NMAKE_BASE=TRUEPCIE_CLK100M_EXCARD_N

MAKE_BASE=TRUEPEG_CLK100M_GPU_P

MAKE_BASE=TRUEPEG_CLK100M_GPU_NCK410_SRC1_N

CK410_LVDS_N NB_CLK_DREFSSCLKIN_NMAKE_BASE=TRUE

CK410_LVDS_PMAKE_BASE=TRUENB_CLK_DREFSSCLKIN_P

CK410_SRC2_NMAKE_BASE=TRUESB_CLK100M_DMI_N

CK410_SRC6_NMAKE_BASE=TRUEPCIE_CLK100M_MINI_N

MAKE_BASE=TRUESB_CLK100M_SATA_NCK410_SRC4_N

MAKE_BASE=TRUEFSB_CLK_NB_N

MAKE_BASE=TRUESB_CLK100M_SATA_P

CK410_CPU1_N

CK410_SRC4_P

NB_CLK_DREFCLKIN_N

CK410_SRC7_P

CK410_SRC7_N

NB_CLK_DREFCLKIN_PNB_CLK_DREFCLKIN_P


CK410_SRC5_N

CK410_PCIF0_CLK

CK410_PCIF1_CLK

CK410_PCI1_CLK

CK410_PCI2_CLK

CK410_PCI4_CLK

CK410_PCI3_CLK

=PP1V05_S0_FSB_NB

=PP1V05_S0_FSB_NB

=PP1V05_S0_FSB_NB

CK410_USB48_FSA

CPU_BSEL_R<0>

CPU_BSEL_R<1>

CPU_BSEL_R<2>

CK410_CLK14P3M_TIMER

SB_CLK48M_USBCTLR

CPU_BSEL<0>

CPU_BSEL<1>

NB_BSEL<1>

CPU_BSEL<2>

NB_BSEL<2>

CK410_FSB_TEST_MODE

SB_CLK14P3M_TIMER

NB_BSEL<0>

MAKE_BASE=TRUETP_CK410_PCI4_CLK

PCI_CLK_PORT80_LPC

PCI_CLK_SB

PCI_CLK_FW

PCI_CLK_TPM

PCI_CLK_SMC

65D6

65D6

65D6

34C8

34C6

34C8

34B8

34B8

34C6

65B3

19D7

19D7

19D7

33D8

47C3

47C3

12C2

12C2

12C2

71C5

71C2 71C2

71C5

34B4

47C6

47C6

33D3

33B4

33C4

33C4

33C4

33C4

33C4

33B4 5B1

33B4 14C4

14C4

33B4

33A4

33A4

33B4

33B4

67A5

67A5 33B4

33B4 14C4

33B4 14B4

33B4

33B4 5B1

33B4

33C4

33B4

34B2

34B2 34B4

19A6

33B4

33B6

12B7

12B7

12B7

34B4

34B4 34B2 33A4

34B2 33A4

14C4

33B4

33A4

33B4 5C1

33B4 5C1

33C7

33A4

33B6

14C4

33B4

33B4

14C4 14C4

17C6

33B7

33B6

33B6

33B6

33B6

12A7

12A7

12A7

33A4

33A4

23D3

7B4

7B4

14C6

7B4

14C6

33C6

14C6

NC7

NC6

NC5

NC4

NC2

NC3

OUT

VDD

NC0

NC1

VIO

GND

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

NC

NC

NC

NC

NC

NC

NC

NC

SMC G3Hot Oscillator

TPM Crystal Circuit

NC

NCY3720

24

13

TPM

32.768K

CRITICAL

SM-2

R37211 2

TPM

MF-LF1/16W

0

402

5%

R37201

2

10M

NO STUFF

MF-LF402

5%1/16W

U3750

6

2

3

4

5

8

9

10

11

7

12

1

32.768KHZ-9-3.6V

CRITICAL

SG-3040LC-SM

C3751 1

2

0.1uF20%

402CERM10V

L3750

1 2

FERR-EMI-100-OHM

SM

C37501

26.3V

603CERM

20%4.7uF

R37501 2

402

22

MF-LF1/16W5%

C3720

1 2

TPM

5%

402CERM50V

15pF

C3721

1 2

TPM

50V5%

402CERM

15pF

37 105

B051-7270


Mobile Clocking

TPM_XTALI

TPM_XTALO_R

SMC_CLK32K_SUSCLK_R

=PP3V42_G3H_SMC_CLK

TPM_XTALO

MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.2 mmPP3V42_G3H_SMC_CLK_F

VOLTAGE=3.425V

MAKE_BASE=TRUESMC_CLK32K_SUSCLK SMC_SUS_CLK

58C6

65D3

58C6

49C5

IN

IO

IO

IO

IO

IO

IN

IO

IO

IO

IN

IN

IN

OUT

G

DS

IN

IO

IO

IO

IO

IO

IO

IO

IO

IN

OUT

OUT

INOUT

IN

IN

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE


(UATA_CS1*)

(UATA_HSTROBE)

(UATA_STOP) (UATA_DSTROBE)

NC

Indicates disk presence

IDE (ODD) Connector

Placement notePlace within 12.7mm

from ball of SB

(UATA_CS0*)

Counters 10K pull-up to 5V in

ODD to keep SB GPIO <= 3.3V

R38501

2

5%

MF-LF402

100

1/16W

J3800

1

10

11

12

13

14

15

16

17

18

19

2

20

21

22

23

24

25 26

27

28

29

3

30

31

32

33

34

35

36

37

38

39

4

40

41

42

43

44

45

46

47

48

49

5

50

6

7

8

9

OMIT

M-ST-SM1-LF

CRITICAL

R38601

2402MF-LF1/16W

24.91%

R38011

2

5%4.7K

NO STUFF

MF-LF402

1/16W

R38021

2

1/16W5%

MF-LF

4.7K

402

R38031

2

MF-LF1/16W5%

402

6.2K

R38101

2

1/16W5%

402MF-LF

33K

Q3820

C1

C2

C3

A1

A2

A3

B1

B2

B3

CRITICAL

FDZ293PBGA

R38201

2

1/16W5%

402MF-LF

91K

C3821

1 2

0.22uF

20%6.3VX5R402

R38211

2

1/16W5%

402MF-LF

10K

R38111

2

1/16WMF-LF

402

5%15K

SYNC_DATE=(MASTER)

PATA Connector

051-7270 B

38 105

SYNC_MASTER=(MASTER)

CONN,PLUG,0.5MM PITCH,1.5MM STK,50P516S0335 J3800 CRITICAL ODD_NONLOCK_CONN1

CONN,PLUG,0.5MM PITCH,1.5MM STK,50P,LOCK J3800516S0557 1 ODD_LOCK_CONNCRITICAL

SATA_RBIAS_N

SATA_RBIAS_P

IDE_PDA<1>

IDE_PDD<11>

SATA_A_R2D_C_N

SATA_C_DET_L

SATA_A_R2D_C_PMAKE_BASE=TRUE

TP_SATA_A_R2DP

SATA_A_D2R_PMAKE_BASE=TRUE

TP_SATA_A_D2RP

SATA_A_D2R_NMAKE_BASE=TRUE

TP_SATA_A_D2RN

MAKE_BASE=TRUETP_SATA_A_R2DN

MAKE_BASE=TRUESATA_RBIAS

ODD_PWR_EN_L

IDE_PDD<13>

=PP5V_S0_IDE

IDE_PDD<3>

=PP3V3_S0_IDE

IDE_PDD<6>

IDE_PDD<4>

IDE_PDIOW_L

IDE_PDD<1>

IDE_PDD<0>

ODD_PWR_EN_L_RC

IDE_PDD<7>

IDE_PDD<5>

SMC_ODD_DETECT

IDE_PDDREQ

IDE_PDD<2>

IDE_PDD<8>

IDE_PDIORDY

IDE_IRQ14

IDE_PDA<0>

IDE_PDD<15>

IDE_PDD<14>

IDE_PDD<12>

IDE_PDD<10>

IDE_PDD<9>

IDE_PDCS3_L

IDE_PDDACK_L

IDE_PDCS1_L

IDE_PDA<2>

VOLTAGE=5V

PP5V_S0_IDE_ODD


IDE_RESET_L

IDE_PDIOR_L

21B6

21B6

21B5

21B5

21B6

23D2

21B6

21B6

21B6

22A6

21B5

65B1

21B5

65B3

21B5

21B5

21B6

21B5

21C5

21B5

21B5

49B7

21B6

21B5

21B5

21B6

21B6

21B5

21B5

21B5

21B5

21B5

21B5

21B5

21B6

21B5

21B5

23C3

21B6

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

OUT

OUT

IN

IN

IN

IN

OUT

IO

IO

IO

IO

IO

IO

OUT

IN

IN

IO

IO

OUT

OUT

SDA

SCL

PCI_AD19

PCI_AD18

PCI_AD17

PCI_AD16

PCI_AD15

PCI_AD14

PCI_AD13

PCI_AD12

PCI_AD11

PCI_AD10

PCI_AD31

PCI_AD30

PCI_AD28

PCI_AD29

PCI_AD27

PCI_AD25

PCI_AD26

PCI_AD24

PCI_AD23

PCI_AD21

PCI_AD20

PCI_AD9

PCI_AD8

PCI_AD7

PCI_AD6

PCI_AD5

PCI_AD4

PCI_AD3

PCI_AD2

PCI_PAR

PCI_CLK

PCI_IDSEL

GND

PCI_AD1

PCI_AD0

VCC

MFUNC

G_RST_L

REG18_1

REG18_0

REG_EN_L

PHY_PINT

PHY_PCLK

PHY_LREQ

PHY_LPS

PHY_LINKON

PHY_LCLK

PHY_D7

PHY_D6

PHY_D5

PHY_D4

PHY_D3

PHY_D1-D1

PHY_D2

PHY_D0-D0

PHY_CTL1-CTL1

PHY_CTL0-CTL0

PCI_ACK64_L

PCI_TRDY_L

PCI_STOP_L

PCI_SERR_L

PCI_RST_L

PCI_REQ64_L

PCI_REQ_L

PCI_PME_L

PCI_PERR_L

PCI_IRDY_L

PCI_INTA_L

PCI_GNT_L

PCI_FRAME_L

PCI_DEVSEL_L

VCCP

PCI_AD22

PCI_C_BE2_L

PCI_C_BE0_L

PCI_C_BE3_L

PCI_C_BE1_L

IN

DS

G

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

GPIO

MFUNC as a

Might use

when there’s no power on VCCP

G_RST* is clamped to VCCP

aliased to the same rail)

It must not be taken high

(OK if VCCP and VCC are

G_RST* assertion min 2ms

THIS IS FROM ICH-7M

Gated Platform Reset Option

From PCI clock generator via 33 Ohms

RC Reset Option

C39081

2 X5R10V

1uF10%

402

C39091

210%1uF

X5R402

10V

C39041

210V

402X5R

1uF10%

C39031

2

1uF10%

X5R402

10V

C39021

2402X5R

10%1uF

10V

C39011

2402X5R10V

1uF10%

C39001

2

1uF

402

10VX5R

10%

R39021

2

4.7K5%1/16WMF-LF402

R39011

2

1/16WMF-LF402

5%4.7K

R39901

2

220

402MF-LF1/16W5%

R39801

2

1K

402MF-LF1/16W5%

R39911

2

2205%1/16WMF-LF402

R39101

2

10K5%1/16WMF-LF402

R39041 2

1/16W

402MF-LF

1K

1%

C39771

210%10V

1UF

X5R402

R38791 2

0

402MF-LF1/16W5%

U3900

E4

C7

C8

F7

F8

F9

F10

G6

G7

G8

G9

G10

H6

D6

H7

H8

H9

H10

J8

J9

J10

K10

D7

E6

E7

E8

E9

E10

F6

A1

N12

L12

N11

N6

M6

M7

K9

K8

M5

K3

N1

L4

M2

M11

M1

L1

J4

H3

H4

J3

H2

G3

H1

F1

N10

F2

G4

M10

K12

M9

N9

L8

M8

N8

M3

K5

K2

D3

N2

L3

E3

L2

B3

K4

N3

L6

F4

J13

F3

D1

L7

L5

J5

F13

F12

E13

E12

C13

B9

B10

C11

B12

A11

B7

B4

A2

D4

B6

A3

G11

G12

C2

C3

C4

D5

D8

D9

E5

F5

H11

J6

J7

J11

E11

F11

(2 OF 2)BGA

CRITICAL

TSB83AA22AZAJ

R39771

2

10K

1/16W

402MF-LF

5%

C39791

250V10%0.001uF

402CERM

R39791 2

10K

5%1/16WMF-LF402

Q3970

3

1

2

SOT23-LF2N7002

R39001 2

22

MF-LF402

5%1/16W

C39101

216V10%

402X5R

0.1uFC39111

2

402X5R16V10%0.1uF

R39031 2

402MF-LF

5%1/16W

100


39 105

B051-7270

FireWire Link (TSB83AA22)

=PP3V3_S3_FW

FW_SDA

FW_SCL

PCI_AD<19>

PCI_AD<18>

PCI_AD<17>

PCI_AD<16>

PCI_AD<15>

PCI_AD<14>

PCI_AD<13>

PCI_AD<12>

PCI_AD<11>

PCI_AD<10>

PCI_AD<31>

PCI_AD<30>

PCI_AD<28>

PCI_AD<29>

PCI_AD<27>

PCI_AD<25>

PCI_AD<26>

PCI_AD<24>

PCI_AD<23>

PCI_AD<21>

PCI_AD<20>

PCI_AD<9>

PCI_AD<8>

PCI_AD<7>

PCI_AD<6>

PCI_AD<5>

PCI_AD<4>

PCI_AD<3>

PCI_AD<2>

PCI_PAR

PCI_CLK_FW

FW_PCI_IDSEL

PCI_AD<1>

PCI_AD<0>

FW_MFUNCFW_G_RST_L

=PP1V8_S3_FW

FW_LLC_PP1V8LDO_EN_L

FW_PINT

CLKFW_LINK_PCLK

FW_LREQ

FW_LPS

FW_PHY_LKON

CLKFW_PHY_LCLK

FW_DATA<7>

FW_DATA<6>

FW_DATA<5>

FW_DATA<4>

FW_DATA<3>

TP_FW_DATA<1>

FW_DATA<2>

TP_FW_DATA<0>

TP_FW_CTL<1>

TP_FW_CTL<0>

PCI_ACK64_L

PCI_TRDY_L

PCI_STOP_L

PCI_SERR_L

PCI_RST_FW_L

PCI_REQ64_L

=FW_PCI_REQ_L

PCI_PME_FW_L

PCI_PERR_L

PCI_IRDY_L

INT_PIRQD_L

=FW_PCI_GNT_L

PCI_FRAME_L

PCI_DEVSEL_L

=PP3V3_S3_PCI

PCI_C_BE_L<0>

PCI_C_BE_L<3>

PCI_AD<22>

PCI_C_BE_L<2>

PCI_C_BE_L<1>

=SMC_FWRSTGATE_L

PLT_RST_BUF_L FW_G_RST_L_R FW_G_RST_L

SMC_RSTGATE_RC_L

=PP3V3_S3_FW

PCI_RST_L

=FW_PCI_IDSEL

FW_LKON

=PP3V3_S3_FW

65C3

65C3

65C3

37C3

22A7

26D2

26D2

26D2

26D2

26D2

26D2

26D2

26D2

37D7

38C3

37D7

37A7

6B7

22B7

22B7

22B7

22B7

22B7

22B7

22B7

22B7

22B7

22A7

22A7

22A7

22A7

22A7

22A7

22A7

22A7

22A7

22A7

22A7

22B7

22B7

22B7

22B7

22B7

22B7

22B7

22B7

22A6

34D6

22B7

22B7

37A5

65B6

38C3

38C3

38C5

38C5

38C5

38B6

38B6

38B6

38B6

38B6

38B6

22A6

22A6

22A6

6B6

22B5

22A6

22A6

22A7

6B6

22A7

22A6

65C3

22B6

22B6

22A7

22B6

22B6

6B6

26B3 37B2

37C3

22A6

6B6

38A3

37A7

SE

SM

RESET

D7

D5

D6

D4

D3

D2

CPS

PD

BMODE

PC2

PC0

PC1

LREQ

LPS

DS1

LCLK

DS0

XI

R1

R0

TESTM

TESTW

TPBIAS0

TPBIAS1

TPB1N

TPB1P

TPB0N

TPB0P

TPA1N

TPA1P

TPA0P

TPA0N

PINT

PCLK

AVDD_3P3

DVDD_3P3

DVDD_CORE

PLLVDD_3P3

PLLVDD_CORE

PLLGND

LKON_DS2

CNA

IO

IO

IO

IO

IO

IO

IO

IO

OUT

OUT

OUT

OUT TRI-ST/NC

VCC

GND

IN

IN

IN IO

OUT

IO

IO

IO

IO

IO

IO

IO

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

NC

1MA (MAX) BUS HOLDERSSINGLE PORT DEVICES ARE POWER CLASS 0 (’000’)IMPLEMENT 1K PULLUP OR PULLDOWN ON PORT PAGE

NC

RESET PULSE WHEN PHY FIRST

RECEIVES POWER

CAPACITOR IN CONJUCTION WITH

INTERNAL PULLUP PROVIDES

DUAL PORT DEVICES ARE POWER CLASS 4 (’100’)

FW_A is DS_ONLY

FW_B is BILINGUAL

C40501

2 X5R

0.22uF

402

20%6.3V

R40551 2390K

1/16W5%

402MF-LF

U3900

D10

D11

G5

H5

L9

M12

A5

D13

C9

C10

C12

B13

B11

A6

B8

D12

H12

J12

K7

K6

C5

C6

G13

L13

N13

K13

N4

M4

N5

H13

K11

M13

A10

A7

A8

A12

A13

L10

A4

B5

L11

N7

E2

E1

J1

J2

B1

C1

G1

G2

D2

K1

A9

TSB83AA22AZAJ

(1 OF 2)BGA

CRITICAL

C40101

220%

402

0.01uF

16VCERM

C40021

210VX5R

10%1uF

402

C40211

2402X5R10V10%1uF

R40622 16.34K

1%1/16W

402MF-LF

C40011

2 X5R10V

402

10%1uF

C40031

2

1uF

10VX5R

10%

402

C40041

2 X5R

10%1uF

402

10V

C40111

210VX5R

10%1uF

402

C40121

210VX5R

10%1uF

402

C40131

2402

1uF10%

X5R10V

C40141

2402

1uF10%

X5R10V

G4080

2

3 1

4CRITICAL

98P3040MHZSM

R40451

2

1K

402

5%1/16WMF-LF

R40421

2

1/16W5%

402MF-LF

1K

C4031 1

2

1uF

X5R402

10%10V

C4030 1

2X5R10V10%1uF

402

C40351

2603CERM16.3V

2.2uF10%

R405612

MF-LF402

5%1/16W

10K

R40861 2

MF-LF402

5%1/16W

4.7

R40631

2

1K

NO STUFF

MF-LF402

1%1/16W

R40001 2

402

1

MF-LF1/16W5%

R40351 2

1

402MF-LF1/16W5%

R40201 2

402MF-LF1/16W5%

1

R40801 2

5%

22

402MF-LF1/16W

C40801

26.3V20%0.22uF

402X5R

R4061

2

1

MF-LF402

1/16W

4701%

R40911

2

1/16W

1K5%

MF-LF402

R40401

2

MF-LF

1K

402

5%1/16W

R40901

2

5%1K

1/16W

402MF-LF

FireWire PHY (TSB83AA22)SYNC_DATE=(MASTER)

051-7270 B

10540


FW_A_DS

=PP3V3_FWPHY

FW_PHY_RESET_L

FW_DATA<7>

FW_DATA<5>

FW_DATA<6>

FW_DATA<4>

FW_DATA<3>

FW_DATA<2>

FW_CPS

FW_BMODE

=FW_PC0

FW_LREQ

FW_LPS

FW_B_DS

CLKFW_PHY_LCLK

CLK98P304_FW_XI

FW_R1

FW_R0

FW_TESTM

FW_TESTW

FW_A_TPBIAS

FW_B_TPBIAS

FW_B_TPB_N

FW_A_TPB_N

FW_A_TPB_P

FW_B_TPA_N

FW_B_TPA_P

FW_A_TPA_P

FW_A_TPA_N

FW_PINT

CLKFW_LINK_PCLK

VOLTAGE=3.3VMIN_LINE_WIDTH=0.38 mm

PP3V3_FWPHY_AVDD

MIN_NECK_WIDTH=0.22 mm =PP1V95_FWPHY

VOLTAGE=3.3VMIN_LINE_WIDTH=0.38 mm

PP3V3_FWPHY_PLLVDD


PP1V95_FWPHY_PLLVDDVOLTAGE=1.95VMIN_LINE_WIDTH=0.38 mmMIN_NECK_WIDTH=0.22 mm

FW_LKON

FW_B_TPB_P

=PPFW_FW_CPS

FW_LKON

=PP1V8_FWPHY_OSC

CLK98P304M_FW_XI_R

MIN_NECK_WIDTH=0.20 mmMIN_LINE_WIDTH=0.25 mmVOLTAGE=1.83V

PP1V8_FWPHY_OSC

44B8

38A3

38C3

6C6

37C4

37C4

37C4

37C4

37C4

37C4

44B8

37C4

37C4

37C4

44D7

44D7

44B7

44C7

44C7

44B7

44B7

44C7

44C7

37C4

37C4

6B6

37C3

44B7

65C1

37C3

6B6

OUT

OUT

AVDDL0

AVDDL4

AVDD

THRML_PAD

VDDO_TTL0

AVDDL6

VDDO_TTL1

RX_N

TESTMODE

TSTPT

LINK*

LED_LINK10/100*

LED_LINK1000*

LED_ACT*

RSET

CTRL25

CTRL12

HSDACN

HSDACP

SWITCH_VAUX

SWITCH_VCC

VMAIN_AVLBL

VAUX_AVLBL

LOM_DISABLE*

XTALO

XTALI

SPI_DO

SPI_CLK

SPI_CS

SPI_DI

VPD_CLK

VPD_DATA

MDIP3

MDIN3

MDIN2

MDIP2

MDIN1

MDIP1

MDIN0

MDIP0

WAKE*

REFCLKN

TX_N

VDDO_TTL3

VDDO_TTL2

VDDO_TTL4

VDD0

VDD1

VDD3

VDD2

VDD6

VDD5

VDD4

VDD7

AVDDL1

AVDDL2

AVDDL5

VDD25

PERST*

REFCLKP

RX_P

AVDDL3

TX_P

PU_VDDO_TTL0

PU_VDDO_TTL1TEST

TESTTWSI

SPI

MAIN CLK

PCI EXPRESSANALOG

MEDIALED

E2

WC*

NC0NC1

VCC

VSS

SCL

SDA

IN

IN

IO

IO

IO

IO

IO

IO

IO

IO

G

D

S

IN

IN

IN

OUT

OUT

OUT

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

find correct topolgyto help constraint manager

Setting attribute VOLTAGEto arbitrary value

NC

INTERNAL PULL-UP

NC

NC

1. KEEP ENET_XTALI AND ENET_XTALO

NC

NC

NC

NC

2. DO NOT ROUTE UNDER CRYSTAL

NC

NC

SCHEME MATCHES DOC MVL100258-01 SCHEME MATCHES DOC MVL100258-01

PLACE C4107 NEAR U4101 AVDD

12 MIL OF U4101 PIN 49 AND 50PLACE C4110 AND C4111 WITHIN

SCHEME MATCHES DOC MVL100258-01

PLACE C4100-C4106 NEAR PINS AVDLL0-AVDLL6.

NO PULL-UP NEEDED

PLACE C4135-C4139 NEAR VDDO_TTL0-VDD_TTL4 ON U4101

PLACE C4140 NEAR U4102 VCC

PLACE RESISTORS CLOSE TO U4101

TRACE LENGTH <12MIL

ASF IS UNAVAILABLE ON 8053

PLACE C4127-C4134 NEAR PINS VDD0-VDD7 ON U4101

OPTIONAL EXTERNAL LDO

12 MIL OF U2100 E27 AND E28PLACE C4113 AND C4112 WITHIN

NC

NC

NC

C41511

2

27pF

50VCERM

5%

402

R4122

12

10K

5%

402

MF-LF

1/16W

R4123

12

10K

1/16W

402

5%

MF-LF

C41011

2

402

16VX5R

10%0.1UF

U4101

23

19

22

28

32

51

52

57

3

4

25

24

59

60

62

63

10

18

21

27

31

17

20

26

30

5

42

43

56

55

16

53

54

37

36

35

34

9

11

46

65

29

50

49

12

27

13

64

33

39

44

48

58 18

40

45

61

47

38

41

6

15

14

CRITICALOMIT

QFN

88E8053

C41401

216V10%0.1UF

402X5R

U4102

3

1

2

6

5

8

4

7

OMIT

M24C08

CRITICAL

SO8

R4102

12

1/16W

1%

4.87K

MF-LF

402

C41071

2

0.1UF

X5R402

10%16V

C4110

1 2

402

10%16VX5R

0.1UF

C4111

1 2

16V10%

0.1UF402

X5R C4112

1 2

10%0.1UF402

16V

X5R

C4113

1 2

402X5R16V10%

0.1UF

R41061

2402MF-LF

1%49.9

1/16W

R41171

2402

1%1/16WMF-LF

49.9R41181

2402MF-LF1/16W

49.91%

R41191

2

1%49.9

1/16WMF-LF402

R41201

2402

1/16W1%

MF-LF

49.9R41031

2

MF-LF

49.9

402

1%1/16W

R41041

2402MF-LF1/16W1%49.9

R41051

2402MF-LF1/16W1%49.9

C41161

2

0.001UF

CERM402

10%50V

C41181

2

402

10%0.001UF

50VCERM

C41171

2

0.001UF

CERM

10%

402

50V

C41151

2

402

50V10%

CERM

0.001UF

C41001

2

402CERM6.3V10%1UF

R41311

2

4.7K5%1/16WMF-LF402

R41301

2402MF-LF1/16W5%4.7K

Q4100

3

1

2

SOT23-LF2N7002

R41011

2

4.7K5%

402MF-LF1/16W

L4100

1 2

0402-LF

FERR-120-OHM-1.5A

R41321

2

100K5%

1/16WMF-LF

402

C41051

2

0.001UF

CERM

10%50V

402

C41041

2 X5R

10%0.1UF

16V

402

C41031

2

402

0.1UF

X5R

10%16V

C41021

2

10%0.1UF

X5R402

16V

C41061

2

0.001UF

402CERM50V10%

C41281

2

402

16V

0.1UF

X5R

10%

C41331

2

0.001UF10%

402

50VCERM

C41341

250V

402CERM

0.001UF10%

C41311

2

402CERM

0.001UF10%50V

C41321

2

10%0.001UF

CERM402

50V

C41271

216V10%

X5R402

0.1UFC41261

2

10%

X5R402

16V

0.1UFC41291

216V

402X5R

0.1UF10%

C41301

216V10%

402X5R

0.1UF

C41391

2

402CERM

10%50V

0.001UFC41381

2

0.001UF

50VCERM402

10%

C41371

216V

0.1UF

X5R402

10%

C41361

2

402

10%

X5R

0.1UF

16V

C41351

2

402X5R

0.1UF10%16V

Y410124

13

25.0000MSM-3.2X2.5MM

CRITICAL

C41501

2

27pF

402CERM50V5%

B051-7270

105

ETHERNET CONTROLLER

41


=PP2V5_S3_ENET

MIN_NECK_WIDTH=0.22MM

MIN_LINE_WIDTH=0.4MM

VOLTAGE=2.5VPP2V5_S3_ENET_AVDD

ENET_VPD_DATA

ENET_VPD_CLK

=PP3V3_S3_ENET

=ENET_VMAIN_AVLBL

ENET_RSET

=PP1V2_S3_ENET

ENET_MDI_N<0>

ENET_LOM_DIS_L

ENET_CTRL25

ENET_MDI_P<2>ENET_MDI_N<2>

ENET_MDI2VOLTAGE=1.234V

ENET_MDI_N<1>

=PP1V2_S3_ENET

ENET_CTRL12

ENET_VPD_CLK

=PP3V3_S3_ENET

PCIE_A_D2R_P

PCIE_A_D2R_NPCIE_A_D2R_C_N

=PP3V3_S3_ENET


PCIE_A_R2D_C_PPCIE_A_R2D_C_N

ENET_PU_VDD_TTL0

PCIE_A_R2D_P

=PP3V3_S3_ENET

ENET_PU_VDD_TTL1

PCIE_WAKE_L

PCIE_A_D2R_C_P

ENET_PU_VDD_TTL1

ENET_CLK100M_PCIE_PENET_CLK100M_PCIE_N

ENET_RST_L

ENET_PU_VDD_TTL0

ENET_VPD_DATA

ENET_MDI_P<0>

PCIE_A_R2D_N

ENET_MDI_P<1>

ENET_MDI_N<3>ENET_MDI_P<3>

ENET_XTALIENET_XTALO

=PP3V3_S3_ENET



ENET_LOWPWR_EN

=PP3V3_S3_ENET

ENET_LOM_DIS_L

65D1

65D1

65D1

65D1

65D1

65D1

39D8

39D8

39D8

39D8

39D6

39D8

39D6

39D6

39B8

39D6

39B8

39D6

39B8

39B8

39B5

39B8

47C3

39B5

39B5

39B5

65D6

40C4

40C4

65D6 39B5

39B4

39B4

23C8

39B4

39B4

65B6 40D5

39C6

39C6

39A5

64C6

39A8

40B7

39B7

6D4

40C4

40C4

40A7

39D7

6D4

39A2

39B4

22D4

22D4

39A5

22D4

22D4

39C6

39A5

39B6

5B1

39A6

34C3

34C3

26B1

39A6

39A2

40D4

40C4

40B4

40C4

39A5

6C4

39A5

39C8

SYM_VER2

NC2 NC3NC4

LINE

SIDE

CHIP

SIDENC1

SYM_VER2

NC2 NC3NC4

LINE

SIDE

CHIP

SIDENC1

IN

IO

IO

IO

IO

IO

IO

IO

IO

OUT

V-

V+

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

to arbitrary valueSetting attribute VOLTAGE

to help constraint managerfind correct topolgy

NEAR ENET_MDI_N<0/1>

PLACE C4220 & C4221

- =GND_CHASSIS_ENET

PHY

ETHERNET

BY

- =PP2V5_ENET

(NONE)


(NONE)


Page Notes

SPACING

NET_TYPE

ELECTRICAL_CONSTRAINT_SET

PROVIDED

PHYSICAL


514-0277

Place one cap at each pin of transformer

mirrored on oppositesides of the board

Transformers should be

Place close to connector

Short shielded RJ-45

LAN ENERGY DETECT

R42101 2

0

MF-LF

5%1/16W

402

NO STUFF

C42031

2

402CERM

10%6.3V

1uFC42021

2

402CERM

10%6.3V

1uF

C4204

21

3KV10%

1808CERM

100pF

R42031

2

755%1/16W

402MF-LF

R42021

2

75

MF-LF402

5%1/16W

R42011

2

75

MF-LF402

5%1/16W

R42001

2

75

402

5%

MF-LF1/16W

C42011

2 CERM

10%1uF

402

6.3V

C42001

2

402

10%6.3VCERM

1uF

T42001

10

11

14

15

16

2

3

6

7

8 9

4

5 12

13

1000BT-824-00275CRITICAL

XFR-SM

T42011

10

11

14

15

16

2

3

6

7

8 9

4

5 12

13

CRITICAL1000BT-824-00275

XFR-SM

J4200

9

10

11

12

1

2

3

4

5

6

7

8

F-RT-TH-RJ45JM36113-P2054-7F

CRITICAL

C42231

2

0.1uF10%16VX5R402

R42241

2MF-LF

100K

1/16W

402

1%

R42231

2 402MF-LF1/16W5%3.3K

U42004

3

1

5

2

SM-LF

LMC7211

R42251

2 402MF-LF

1%1/16W

51.1K

C42221

25%50VCERM402

100pF

NO STUFF

R42201 2

MF-LF

2.4K

1/16W

402

5%

C4220

1 2

402-1

50V5%

68PF

CERM

R42211 2

2.4K

MF-LF1/16W

402

5%

C4221

1 2

402-1

50V5%

68PF

CERM

R42271

2

1%1/16WMF-LF402

470K

Q42202

6

1

SOT-363-LFMMDT3904XF

Q42205

3

4

SOT-363-LFMMDT3904XF

R42281

2

1%

MF-LF

392K

1/16W

402

R42261

2MF-LF

10K5%1/16W

402


Ethernet Connector

105

051-7270

42

B

EDET_ACT

=PP3V3_S0_EDET

EDET_MDIN_AMP

EDET_REF

ENETCONN_N<3>

ENET_CTAP0

ENET_MDI_N<1> ED_MDIN1_CVOLTAGE=1.234V

ENET_MDI_N<0>

PP2V5_S3_ENET_AVDD

ENET_CTAP3

ENET_CTAP2

ENETCONN_N<2>

ENET_CTAP_COMMON


ENET_MDI_N<3>

ENET_MDI_P<3>

ENET_MDI_N<1>

ENET_MDI_P<1>

ENET_MDI_N<0>

ENET_MDI_P<0>

ENET_CTAP1

=GND_CHASSIS_ENET

ENETCONN_P<3>

ENETCONN_N<1>

ENETCONN_N<0>

ENETCONN_P<0>

ENETCONN_P<1>

ENET_100DENETCONN ENETCONN_P<1>

ENET_100DENETCONN ENETCONN_N<3>

ENET_100DENETCONN ENETCONN_N<1>

ENET_100DENETCONN ENETCONN_N<0>ENET_100DENETCONN ENETCONN_P<0>

ENET_100DENETCONN ENETCONN_P<3>ENET_100DENETCONN ENETCONN_N<2>ENET_100DENETCONN ENETCONN_P<2>

ENET_MDI_P<2>

ENET_MDI_N<2>

ENETCONN_P<2>

ED_MDIN0_CVOLTAGE=1.234V

LAN_ENERGY_DET

ED_MDIN_R40C4

40C4

40A7

40B7

65A3

40D7

39C3

39C3

39D5

40D7

39C3

39C3

39C3

39C3

39C3

39C3

6A6

40D7

40D7

40D7

40D7

40D7

40C3

40B3

40C3

40C3

40D3

40C3

40C3

40C3

39C3

39C3

40D7

23C3

N-CHN

S

D

G

P-CHN

G

DS

G

D

S

G

D

S

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

Allows powering Yukon down during battery sleep to save power

When ENETPWR_S3 BOMOPTION is active:

When ENETPWR_S3AC BOMOPTION is active:

Yukon Power Control

1.2V enable has pull-up to 3.3V

State FWPWR_EN_L PM_SLP_S4_L PM_SLP_S3BATT PM_SLP_S3BATT_L P2V5S3_EN P1V2S3_RUNSS

S0 AC 0V 3.3V 0V (3.3V ON) 3.3V 3.3V (2.5V ON) 3.3V (1.2V ON)

S0 Batt 0V 3.3V 0V (3.3V ON) 3.3V 3.3V (2.5V ON) 3.3V (1.2V ON)

S3 AC 0V 3.3V 0V (3.3V ON) 3.3V 3.3V (2.5V ON) 3.3V (1.2V ON)

S3 Batt PBUS 3.3V PBUS (3.3V OFF) 0V 0V (2.5V OFF) 0V (1.2V OFF)

S5 AC 0V 0V PBUS (3.3V OFF) 0V 0V (2.5V OFF) 0V (1.2V OFF)

S5 Batt PBUS 0V PBUS (3.3V OFF) 0V 0V (2.5V OFF) 0V (1.2V OFF)

G3H Batt PBUS 0V PBUS (3.3V OFF) 0V 0V (2.5V OFF) 0V (1.2V OFF)

S3 3.3V 0V (3.3V ON) 3.3V 3.3V (2.5V ON) 3.3V (1.2V ON)

S0 3.3V 0V (3.3V ON) 3.3V 3.3V (2.5V ON) 3.3V (1.2V ON)

State PM_SLP_S4_L PM_SLP_S3BATT PM_SLP_S3BATT_L P2V5S3_EN P1V2S3_RUNSS

S5 0V PBUS (3.3V OFF) 0V 0V (2.5V OFF) 0V (1.2V OFF)

G3H 0V PBUS (3.3V OFF) 0V 0V (2.5V OFF) 0V (1.2V OFF)

R43021

2

5%1/16WMF-LF402

470K

R43041

2

MF-LF

100K

1/16W5%

402

R43001 2

0

ENETPWR_S3AC

402MF-LF1/16W5%

R43011

2

0

402MF-LF1/16W5%

ENETPWR_S3

Q4300

6

2

1

SC70-6FDG6332C_NL

Q4300

3

5

4

SC70-6FDG6332C_NL

Q4302

3

1

2

2N7002SOT23-LF

Q4304

3

1

2

SOT23-LF2N7002


Yukon Power Control

051-7270 B

10543

MAKE_BASE=TRUEPM_SLP_S3BATT_L

PPVIN_S3_P2V5S3_SVIN

=P2V5S3_EN

PM_SLP_S3BATT

P1V2S3_RUNSS

=PP3V3_S3_P3V3S3AC =PP3V3_S3AC_FET

FWPWR_EN_L_OR_GND

PM_SLP_S4_L

=PPBUS_G3H_S3AC

FWPWR_EN_L

64B8

61B7

49C5

61D6

61D8

5D7

65C3 65D3

23C3

65C1

43C7

OUTINNR

NC THRML

EN

GND PAD

FB

BIAS

SWSHDN*

NC

VIN BOOST

GND

DSG

G

D

S

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

Vout = 3.316

PBUS S0 FET

3.3V Supply for FWPHY

<Rb>

NC

<Ra>

NC

Vout = 1.25V * (1 + Ra / Rb)

1.95V Supply for FW PHY

165MA MAX LOAD

200mA max output

(Switcher limit)

400mA max output

(Regulator limit)

Vout = 1.95V

C44221

24VX5R402

2.2uF20%

C4421 1

2

0.01uF

402CERM16V10%

C4420 1

2

402CERM

1uF

6.3V10%

U4420

4

3

6

5

2

1

7

CRITICAL

TPS799195SON

R44101

2MF-LF402

1%1/16W

324K

R44111

2MF-LF402

1%1/16W

196K

C4410 1

250V

22pF

CERM402

5%

C4405 1

26.3V20%

402X5R

0.22uFC4400 1

2X7R-CERM

10%

1206

50V

4.7UF

U4400

7

6

8

4

2

1 5

3

CRITICAL

TSOT23-8LT3470

D4400

1

2

3

SMD20E40C-X-F

SC-59

L4400

1 2

CRITICAL

33uH

CDPH4D19F-SM

C44011

2805X5R6.3V20%22UF

Q4450

3

1

2

SOT23

IRLML6302PBF

R44501

2

470K5%

1/16WMF-LF

402

R44511

2402MF-LF1/16W

5%330K

Q44513

1

2

2N7002SOT23-LF

C4450 1

2

0.0022UF10%50V

CERM402

44 105

B051-7270


FW PHY Power Supply

=PP1V95_FWPHY_CORE_LDO

PPBU_S0_FW_EN_DIV

PPBU_S0_FW_EN

PM_SLP_S3_L

=PPBUS_S0_PPBU_S0_FW

SWITCH_NODE=TRUEMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mmFWPHY3V3_SW

FWPHY3V3_FB

=PP3V3_FWPHY_CORE

FWPHY_CORE_NR

FWPHY3V3_BOOST

PP5VR33V_FWPHY3V3

PPBU_S0_FW

=PPFW_P3V3FWPHY

=PP3V3_FWPHY_REG


PPBU_S0_FW

64C8 49C5 43B7

6B8

23C3

65C1

6C6

42B6

65C1

6C8

42C8

G

D

S

G

D

S

V-

V+

G

D

S

G

D

S

NC

NC

NC

GATE2

OR_ADJIFAULT*

ILIM

GNDON

LATCH

TIM

ONQ1

SENSEGATE1

OUTIN

S

G

D

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

0.030 ohm => 1.66A (ideal)

0.020 ohm => 2.4A0.025 ohm => 2A

0.033 ohm => 1.5A

Current Limit determined by R4500

UL compliance forsingle-point failure protection

for redundancy andQ4501 is a dual FET

Current Limit/Active Late-VG Protection

is running or on AC.

Enables port power when machine


- =FWPWR_PWRON (see related text note below)


Page NotesPower aliases required by this page:

- =PP3V3_S0_FWPORTPWRSW

(NONE)

2.95V when port power is on

- =PPBUS_S0_FWPWRSW (system supply for bus power)

NC

NC

NC

NC

Late-VG Event Detection

2.81V on late Vg event and port power is off

FWLATEVG_3V_REF Hysteresis:

Q4561

3

5

4

SOT-3632N7002DW-X-F

Q4561

6

2

1

SOT-3632N7002DW-X-F

R45191

2 402MF-LF1/16W5%2.0M

C45121

2

0.33UF

CERM-X5R

10%10V

603

C45101

2

402CERM10V20%0.1UF

R45101 2200K

MF-LF

1%

402

1/16W

U45104

3

1

5

2

SM-LF

LMC7211

R45111

2

1/16W

10K5%

402MF-LF

C45111

2

100pF

CERM402

50V5%

R45121

2

10K

1/16WMF-LF402

1%

R45131

2

80.6K

402

1%1/16WMF-LF

Q4560

6

2

1

SOT-3632N7002DW-X-F

Q4560

3

5

4

2N7002DW-X-FSOT-363

R45601

2

5%1/16WMF-LF402

10K

D4510

12

MBR0540XXG

SOD-123

U4500

14

12

9

2

4

16

5

7

10

13

1

8

6

11

15

3

CRITICAL

QSOP1MAX5943

Q4500

3

1

2

CRITICAL

SOT23-3SI2318DS

Q45022

6

1

MMDT3906XFSOT-363

Q45025

3

4

SOT-363MMDT3906XF

R45021

2

5%1/16WMF-LF

1K

402

R45041

2

1/16W

402MF-LF

5%1K

R45031

2

1/16WMF-LF402

5%100K

R45011

2402MF-LF1/16W

5%100K

R45611

2

200K5%

1/16WMF-LF402

C45001

2

1UF10%35VX5R603

C4560 1

216V20%

402CERM

0.01uF

Q4501

5

4

3

PWRPK-1212-8SI7222DN

CRITICAL

Q4501

6

2

1

PWRPK-1212-8SI7222DN

CRITICAL

R450012

0.020

0.25W

805MF

1%


B051-7270

45 105

FireWire Port Power

=PP3V3_FWLATEVG_ACTIVE

FWLATEGV_3V_REF

LATEVG_EVENT_L

PPBUS_S5_FW_FET2


FW_PWRCTRL_GATE2_2

=PPBUS_S5_FW_FET

FW_PWRCTRL_GATE2_1

PPBUS_S5_FW_FET1


VOLTAGE=12.6V

FW_PWRCTRL_GATE1

FWPWR_LATEVG_EN

FW_PWRCTRL_GATE2

FW_PWRCTRL_GATE2_2_R

FW_PWRCTRL_GATE2_1_R

SMC_ADAPTER_EN

PM_SLP_S3_L

LATEVG_EVENT_D_L

FWPWR_EN_L

PP2V4_FWLATEVG_RC

PP2V4_FWLATEVG

FWPWR_LATEVG_EN_L

LATEVG_EVENT_D_L

=PPBUS_S5_FWPWRSW

MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mmVOLTAGE=12.6V

PPBUS_S5_FW_R

50A2

64C8

49D5

49C5

44D5

47C6

42A8

44B5

6B6

65C3

5C1

23C3

43A5

41B6

44A5

43C7

65C1

TPO#

TPI

TPO

TPI#

VGND

VP

SYM_VER-2

SYM_VER-2

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE


pin 5 of connectorPlace C4629 close to

DFM rules for only Rs and Cs

placement in an area restricted by

were changed to resistors to allow

Note: The peaking inductors

Note:Trace PPFW_PORT1_VP should handle up to 5A

(GND_FW_PORT1_VG)

(PPFW_PORT1_VP)

(FW_PORT1_BREF)

TPB+

per 1394b V1.33

Place close to FireWire PHY

Termination

and connection detection currents

BREF should be hard-connected tologic ground for speed signaling

"Snapback" & "Late VG" Protection

"Snapback" & "Late VG" ProtectionCable Power

1394A

(TPA+)

PORT 2

514S0133

BILINGUAL

PORT 1

OUTPUTTPB<R>

(PPFW_PORT2_VP)

(GND_FW_PORT2_VG)

AREF needs to be isolated from

When a bilingual device isconnected to a beta-only device,there is no DC path between them(to avoid ground offset issue)

PAGE

(NONE)

to apply to entire TPA/TPB XNets.

1394b implementation based on Apple

(NONE)

514-0255

(TPB-)

(TPB+)

(TPA-)

all local grounds per 1394b spec Cable Power

TPA-

PP2V4_FWLATEVG needs to be biased

Late-VG Protection Power

to at least 2.1V for FW signal integrity

and should be biased to 2.4V for margin

R4690 should be 390 Ohms max for a 3.3V rail

- =PPFW_PORT1

BY

PHY

INPUT

TPB-

TPA+

TPA<R>

VP

VG

NCNC

provide the appropriate constraints

FireWire Design Guide (FWDG 0.6, 5/14/03)

PHYSICAL

assumed that FireWire PHY page will

constrained on this page. It is

NOTE: FireWire TPA/TPB pairs are NOT

NET_TYPE

SPACING

- =PP3V3_S5_FWLATEVG

- =GND_CHASSIS_FW_PORT1


PROVIDED



NOTE: This page is expected to contain

the necessary aliases to map the

FireWire TPA/TPB pairs to their

appropriate connectors and/or to

properly terminate unused signals.


ESD and late-VG rail

for snap-back diodes

(Common to all ports)

TI PHYs require 1uF even though

FW spec calls out 0.33uF

to arbitrary valueSetting attribute VOLTAGE

to help constraint managerfind correct topolgy

C46501

2 CERM402

6.3V10%1uF

R46511

2

1/16W

402MF-LF

1%56.2

R46501

2

MF-LF402

1%1/16W

56.2

R46531

2

MF-LF402

56.21%

1/16W

R46521

2

MF-LF402

1%1/16W

56.2

R46541

2

1/16W1%

402MF-LF

4.99KC46541

2

220pF

25V5%

402CERM

R46991 2

1/16W5%

402MF-LF

0

L4630

1 2

SM

FERR-250-OHM

C46341

2

0.001uF

CERM50V20%

402

DP4630

4

5

3

BAV99DW-X-FSOT-363

J4630

7 8 9 10

4

3

6

5

2

1

1394A

CRITICAL

F-RT-TH-LF

C4636 1

2

402

16V20%

CERM

0.01uFC46351

2

603

50V

0.01uF

CERM

20%

DP4631

4

5

3

BAV99DW-X-FSOT-363

C4631 1

2X7R

10%0.01uF

402

50V

DP4630

1

2

6

SOT-363BAV99DW-X-F

C4630 1

2X7R

10%0.01uF

402

50V

C4633 1

2X7R

10%0.01uF

402

50V

DP4631

1

2

6

SOT-363BAV99DW-X-F

C4632 1

2X7R

10%0.01uF

402

50V

R46631

2

56.21%

MF-LF1/16W

402

R46641

2

1/16W

4.99K1%

MF-LF402

R46621

2

56.21%1/16W

402MF-LF

C46641

225V5%

402CERM

220pF

R46611

2402

1%56.2

1/16WMF-LF

C46601

2 CERM402

10%6.3V

1uF

R46601

2

1%56.2

402MF-LF1/16W

C46271

2

NO STUFF

CERM

20%16V

0.01uF

402

C4629 1

2

0.1uF10%50VX7R

603-1

R46291

2

1M5%

402MF-LF1/16W

C46241

2

0.001uF

50V20%

402CERM

L4620

1 2

SM

FERR-250-OHM

C4625 1

2

603CERM50V20%

0.01uF

C46261

2

0.01uF20%16VCERM402

C4620 1

2

0.01uF10%

X7R402

50V

DP4620

1

2

6

BAV99DW-X-FSOT-363

C4621 1

2X7R

10%0.01uF

402

50V

DP4620

4

5

3

SOT-363BAV99DW-X-F

DP4621

1

2

6

SOT-363BAV99DW-X-F

DP4621

4

5

3

BAV99DW-X-FSOT-363

C4623 1

2

402

50V

0.01uF10%

X7R

C4622 1

2X7R

10%0.01uF

402

50V

R46901 2

1%

332

402MF-LF1/16W

C4691 1

2

0.01UF10%50VX7R402

D4690

1

3 CRITICAL

MMBZ5227BSOT23

J4620

1

10

11

2

3

4

5

6

7

8

9

F-RT-SM1

CRITICAL

1394B-UG31903

FL4630

1

2 3

4

CRITICAL

90-OHM-100MA1210-4SM1

FL4631

1

2 3

4

1210-4SM1

CRITICAL

90-OHM-100MA

L46601

2

OMIT

1/16W

402MF-LF

05%

L46611

2

OMIT

0

MF-LF402

1/16W5%

L46621

2

OMIT

5%1/16W

402MF-LF

0L46631

2

OMIT

0

MF-LF402

1/16W5%

10546

B051-7270

FireWire PortsSYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)

CRITICAL4 IND,18nH-15mA,0402 L4660,L4661,L4662,L4663152S0414

=GND_CHASSIS_FW_PORT2L

=GND_CHASSIS_FW_PORT2U

FW_PORT2_TPB_N

FW_PORT2_TPB_P

FW_PORT2_TPB_FL_P

FW_PORT2_TPB_FL_N

FW_PORT2_TPA_N

FW_PORT2_TPA_P

FW_PORT2_TPA_FL_P

FW_PORT2_TPA_FL_N

FW_A_TPBIAS

VOLTAGE=1.234V

VOLTAGE=2.4VMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.38 mmPP2V4_FWLATEVG

FW_B_TPB_N

FW_A_TPB_P

=FW_PC0

FW_B_TPA_N

FW_A_TPB_N

FW_PORT2_TPB_FL_NFW FW_110D

FW_PORT2_TPB_FL_PFW_110DFW

FW_PORT1_TPA_PFW_110DFW

=GND_CHASSIS_FW_PORT1

=PP3V3_FWLATEVG

=GND_CHASSIS_FW_EMI_R

FW_B_TPB_P

FW_B_TPA_P

FW_A_TPA_P

FW_PORT2_TPA_NMAKE_BASE=TRUE

FW_PORT2_TPA_PMAKE_BASE=TRUE

FW_PORT2_TPB_NMAKE_BASE=TRUE

FW_PORT2_TPB_PMAKE_BASE=TRUE

FW_PORT1_TPA_PMAKE_BASE=TRUE

FW_PORT1_TPB_PMAKE_BASE=TRUE

FW_PORT1_TPB_NMAKE_BASE=TRUE

VOLTAGE=33VMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mmPPFW_PORT2_VP

=PPFW_PORT2_VP

FW_PORT1_TPA_P

FW_A_TPA_N

FW_PORT1_TPA_NMAKE_BASE=TRUE

VOLTAGE=1.234VFW_PORT2_TPB_C

=PPFW_PORT1_VP

FW_PORT1_AREF

PP2V4_FWLATEVG

FW_PORT2_TPA_FL_NFW_110DFW

FW_PORT2_TPA_FL_PFW FW_110D

FW_PORT1_TPB_NFW_110DFW

FW_PORT1_TPB_PFW_110DFW

FW_PORT1_TPA_NFW_110DFW

FW_PORT1_TPB_N

FW_PORT1_TPB_P

FW_PORT1_TPA_N

=PP3V3_FWPHY

FW_PC0

VOLTAGE=33VMIN_NECK_WIDTH=0.25 mm

PPFW_PORT1_VPMIN_LINE_WIDTH=0.5 mm

PP2V4_FWLATEVG

VOLTAGE=1.234VFW_B_TPA_L_P

FW_B_TPBIAS

VOLTAGE=1.234V

VOLTAGE=1.234VFW_B_TPA_L_N

VOLTAGE=1.234VFW_B_TPB_L_N

VOLTAGE=1.234VFW_B_TPB_L_P

VOLTAGE=1.234VFW_PORT1_TPB_C

44D5

44B5

44D5

44B5

44C5

44D7

44D7

44D7

44D7

44D7

44A5

44C5

44C5

44C5

44D7

44D7

44D7

38D7

44A5

6B6

6A6

44C5

44C5

44D7

44D7

44C5

44C5

44D7

44D7

38B3

43B7

38B3

38B3

38B5

38B3

38B3

44B2

44B2

44B5

6A6

6C6

6B6

38B3

38B3

38B3

44B4

44B4

44B4

44B4

44C5

44C5

44C5

65C1

44B5

38B3

44C5

65C1

43B7

44B2

44B2

44B5

44B5

44B5

44B5

44B5

44B5

6C6

43B7

38B3

IO

IO

SYM_VER-1

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

Camera Connector

Twin-Ax Pair 2

(40 AWG)

(28 AWG)

Twin-Ax Pair 1

Standard wires

Connector shield

(40 AWG)

518S0371

NCNC

Connector shield

C49321

2402X7R50V10%0.01UF

L4931

1 2

CRITICAL

FERR-220-OHM-2A

0603

L4930

1 2

0402

FERR-220-OHM

J4931

7

8

1

2

3

4

5

6

F-RT-SMCAMERA-M1-CUS

CRITICALC4931 1

250V20%

402CERM

0.001uF

NO STUFF

L4950

1 2

0603

FERR-220-OHM-2A

CRITICAL

FL4935

1

2 3

4

1210-4SM190-OHM-100MA

CRITICAL

051-7270 B

10549


Camera Connector

=GND_CHASSIS_CAMERA

=GND_CHASSIS_CAMERA

GND_CAMERA


VOLTAGE=5VMIN_LINE_WIDTH=0.25 mm

PP5V_S3_CAMERA_F

=USB2_CAMERA_N

=USB2_CAMERA_P

USB2_CAMERA_N_F

USB2_CAMERA_P_F

=PP5V_S3_CAMERA

45B5

45C5

6C3

6D3

65B1

6A6

6A6

5A4

5A4

5A4

OUT

VBUS

D-

D+

GND

IN

IN

OUT

OUT

OUT

EN OC*

GNDTHRMLPAD

VDD

THRM_PAD GND

0I0 Y0

SEL

1I1

1I0

0I1

Y1IO

IO

IO

IO

SYM_VER-1

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

SEL=1 Choose USBSEL=0 Choose SMC

514S0115

Right USB PortPort Power Switch

USB/SMC Debug MuxPlace L5200, L5205 and L5206 across moat

L5205

1 2

FERR-220-OHM-2A

0603

CRITICAL

C52961

2 6.3V20%

B2POLY

100UFC5295 1

2

10uF

CERM805-1

6.3V20%

C5290 1

2CERM

20%6.3V

10uF

805-1

C52911

210V20%

402CERM

0.1UF

C5205 1

2

402

16VCERM

20%0.01uF

C5206 1

2

0.01uF20%

402

16VCERM

L5206

1 2

0603

FERR-220-OHM-2A

CRITICAL

J5200

1

2

3

4

5

6

7

8

F-RT-SM-USB-RGT1UAR2X

CRITICAL

D5200

3

12

RCLAMP0502B

SC-75

RTUSB_ESD

CRITICAL

U5290

4

1

2

3

5

8

7

6

9

CRITICAL

TPS2051MSOP

U525012

10

11

9

157

6

13

28

3

4

CRITICAL

PI3USB10TDFN

C5250 1

2402

0.1UF

CERM10V20%

R52501

2

10K5%1/16WMF-LF402

L5200

1

2 3

4

90-OHM-100MA1210-4SM1

CRITICAL

External USB ConnectorSYNC_DATE=(MASTER)SYNC_MASTER=(MASTER)

051-7270 B

10552

USB_DEBUGPRT_EN_L

=PP3V42_G3H_SMCUSBMUX

PP5V_S3_RTUSB_F


MIN_LINE_WIDTH=0.5 mmGND_RTUSB

MIN_NECK_WIDTH=0.5 mmVOLTAGE=0V

=RTUSB_EN

=PP5V_S3_RTUSB

=GND_CHASSIS_RTUSB


PP5V_S3_RTUSB_ILIMMIN_LINE_WIDTH=0.5 mm

=USB2_RT_P

SMC_RX_L

SMC_TX_L

=USB2_RT_N

=RTUSB_OC_L

USB2_RT_F_N

USB2_RT_F_PUSB2_RT_MUXED_P

USB2_RT_MUXED_N

51B4 50B3 50B2 49C7

50B3

65D3

64A6

65B1

6B6

6D3

5C2

6D3

6D3

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

516S0361

NC

Place XW5515 at 5V switcher

Left I/O Board Connector

(Input from LIO)



(2 Amps)

(500 mA)


NCNC

(2 Amps)

(500 mA)

NC

J5500

1

10

11 12

13 14

15 16

17 18

19

2

20

21 22

23 24

25 26

27 28

29

3

30

31 32

33 34

35 36

37 38

39

4

40

41 42

43 44

45 46

47 48

49

5

50

51 52

53 54

55 56

57 58

59

6

60

61 62

63 64

65 66

67 68

69

7

70

71 72

73 74

75 76

77 78

79

8

80

81

82 83

84

9

CRITICAL

F-ST-SMQT510806-L111-7F

XW5500

1 2

SM

XW5505

1 2

SM

XW5510

1 2

SM

XW5515

1 2

SM

55 105

B051-7270

Left I/O Board ConnectorSYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)

=SMBUS_LIO_SB_SDA

=USB2_LT_P

=USB2_LT_N

LIO_PLT_RESET_L

LIO_P3V3S3_EN


VOLTAGE=5V

PP5V_S0_AUDIO

EXCARD_OC_L

SMC_BATT_TRICKLE_EN_L

LIO_DCIN_ISENSE

=PCIE_MINI_R2D_P

=PCIE_MINI_R2D_N

=PCIE_MINI_D2R_N

PCIE_CLK100M_MINI_P

PCIE_CLK100M_MINI_N

=SMBUS_LIO_SB_SCL

=USB2_EXCARD_N

=SMBUS_LIO_SMC_SCL

=SMBUS_LIO_SMC_SDA

PCIE_WAKE_L

ACZ_SYNC

ACZ_SDATAIN<0>

ACZ_SDATAOUT

SMC_BC_ACOK

SMC_SYS_ISET

LIO_BATT_ISENSE

MINI_CLKREQ_L

EXCARD_CLKREQ_L

SMC_BATT_CHG_EN

SMC_ADAPTER_EN

SYS_ONEWIRE

=PP5V_S0_AUDIO_XW

SMC_BATT_ISET

LIO_P3V3S0_EN_L

SMC_EXCARD_CP

LTUSB_OC_L

=PPDCIN_G3H_LIO

=PP3V42_G3H_LIO

=PP1V5_S0_LIO

=USB2_EXCARD_P

=PCIE_MINI_D2R_P

ACZ_BITCLK

=PP5V_S5_LIO

PCIE_CLK100M_EXCARD_P

PCIE_CLK100M_EXCARD_N

=PCIE_EXCARD_D2R_N

=PCIE_EXCARD_R2D_P

ACZ_RST_L

=PCIE_EXCARD_R2D_N

=PCIE_EXCARD_D2R_P

MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.4 mmGND_AUDIO

VOLTAGE=0V


PP5V_S0_AUDIO_PWR

GND_AUDIO_PWRMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.4 mmVOLTAGE=0V

SMC_EXCARD_PWR_EN

50A2

50B3

50A2

39C6

84B4

84B4

84B4

50A2

50A2

49D5

50B2

50A2

84B4

84B4

27B6

6D3

6D3

26C1

64A6

6C3

49D7

53C5

48C6

48C6

48C6

34D4

34D4

27B6

6C3

27D1

27D1

23C8

21C7

21C7

21C7

49C5

49B5

53C3

34A3

34A3

49D7

43B7

49B7

49B5

64C6

49B7

6D3

65A8

65D3

65C6

6C3

48C6

21C7

65B1

34C3

34B3

48B6

48C6

21C7

48C6

48C6

49B7

5B1

5B1

5B1

5C1

5C1

5D1

5C1

5C1

5C1

5B1

5B1

5B1

5B1

5B1

5B1

5B1

5B1

5B1

5B1

5C1

5C1

5C1

5C1

5C1

5C1

5C1

5C1

5C1

5C1

5C1

65A1

5C1

5C1

5C1

5C1

5D1

5D1

5D1

5B1

5B1

5C1

5D1

5B1

5B1

5B1

5B1

5C1

5B1

5B1

5C1

5D1

5C1

5C1

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

PCI-E x1 Port "B" = PCI-E Mini Card

PCI-E x1 Port "A" = Ethernet (Yukon)

PCI-E x1 Port "C" = ExpressCard

PCI-E x1 Port "F" = Unused

PCI-E x1 Port "E" = Unused

PCI-E x1 Port "D" = Unused

Place caps close to SB

Place caps close to SB

C5710

1 2

10%16VX5R402

0.1uF

C5711

1 2

0.1uF

10%16VX5R402

C5721

1 2

0.1uF

10%16VX5R402

C5720

1 2

0.1uF

10%16VX5R402


PCI-E Connections

051-7270 B

10557

PCIE_F_R2D_C_P

PCIE_B_R2D_C_P

PCIE_B_D2R_N

MAKE_BASE=TRUETP_PCIE_F_R2DN

=PCIE_MINI_D2R_P

=PCIE_MINI_D2R_N

=PCIE_MINI_R2D_N

=PCIE_MINI_R2D_P

PCIE_B_R2D_C_NMAKE_BASE=TRUEPCIE_MINI_R2D_C_N

PCIE_MINI_D2R_NMAKE_BASE=TRUE

PCIE_B_D2R_P

PCIE_MINI_R2D_C_PMAKE_BASE=TRUE

=PCIE_EXCARD_R2D_P

=PCIE_EXCARD_R2D_N

=PCIE_EXCARD_D2R_P

=PCIE_EXCARD_D2R_N

PCIE_EXCARD_R2D_C_NMAKE_BASE=TRUE

PCIE_EXCARD_D2R_PMAKE_BASE=TRUE

MAKE_BASE=TRUEPCIE_EXCARD_D2R_N

PCIE_C_R2D_C_P

PCIE_C_R2D_C_N

PCIE_C_D2R_N

PCIE_C_D2R_P

MAKE_BASE=TRUETP_PCIE_D_R2DNMAKE_BASE=TRUE

TP_PCIE_D_R2DP

PCIE_D_D2R_N

PCIE_E_R2D_C_P

PCIE_E_R2D_C_N

PCIE_E_D2R_N

PCIE_E_D2R_P

MAKE_BASE=TRUETP_PCIE_E_R2DP

MAKE_BASE=TRUETP_PCIE_E_R2DN

MAKE_BASE=TRUETP_PCIE_E_D2RNMAKE_BASE=TRUE

TP_PCIE_E_D2RP

PCIE_F_R2D_C_N

PCIE_F_D2R_N

PCIE_F_D2R_P

MAKE_BASE=TRUETP_PCIE_F_R2DP

MAKE_BASE=TRUETP_PCIE_F_D2RNMAKE_BASE=TRUE

TP_PCIE_F_D2RP

MAKE_BASE=TRUETP_PCIE_D_D2RP

MAKE_BASE=TRUETP_PCIE_D_D2RN

PCIE_D_D2R_P

PCIE_D_R2D_C_N

PCIE_D_R2D_C_P

PCIE_EXCARD_R2D_C_PMAKE_BASE=TRUE

PCIE_MINI_D2R_PMAKE_BASE=TRUE

47C3

47C3

47B3

47B3

47B3

47B3

47B3

47B3

22C4

22D4

22D4

5B1

5B1

5B1

5B1

22D4

22D4

5B1

5B1

5B1

5B1

22D4

22D4

22D4

22D4

22D4

22C4

22C4

22C4

22C4

22C4

22C4

22C4

22D4

22D4

22D4

IN

IN

IN

OUT

OUT

OUT

OUT

IN

IN

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

IN

IN

OUT

OUT

OUT

P16

P51

P50

P42/SDA1

P97/IRQ15*/SDA0

P95/IRQ14*

P94/IRQ13*

P93/IRQ12*

P92/IRQ0*

P91/IRQ1*

P86/IRQ5*/SCK1/SCL1

P83/LPCPD*

P82/CLKRUN*

P80/PME*

P35/LRESET*

P34/LFRAME*

P10

P12

P13

P14

P15

P17

P31/LAD1

P30/LAD0

P32/LAD2

P33/LAD3

P36/LCLK

P37/SERIRQ

P44/TMO1

P77/AN7

P76/AN6

P81/GA20

P96/EXCL

P11

P47/PWX1/PWM1

P45

P46/PWX0/PWM0

P40/TMIO

P43/TMI1/EXSCK1

P27

P26

P25

P24

P23

P22

P21

P20

P41/TMO0

P52/SCL0

P60/KIN0*

P61/KIN1*

P62/KIN2*

P63/KIN3*

P64/KIN4*

P65/KIN5*

P66/IRQ6*/KIN6*

P67/IRQ7*/KIN7*

P70/AN0

P71/AN1

P72/AN2

P73/AN3

P74/AN4

P75/AN5

P84/IRQ3*/TXD1

P85/IRQ4*/RXD1

P90/IRQ2*

(1 OF 4)

PA2/KIN10*/PS2AC

PA3/KIN11*/PS2AD

PA5/KIN13*/PS2BD

PA4/KIN12*/PS2BC

PB2

PB3

PB4

PE0

PG6/EXIRQ14*/EXSDAB

PG5/EXIRQ13*/EXSCLA

PH1/EXIRQ7*

PH0/EXIRQ6*

PG7/EXIRQ15*/EXSCLB

PG4/EXIRQ12*/EXSDAA

PH3/EXEXCL

PH2/FWE

PB5

PF4/PWM4

PF2/IRQ10*/TMOY

PG2/EXIRQ10*/SDA2

PG0/EXIRQ8*/TMIX

PF7/PWM7

PC3/TIOCD0/TCLKB/WUE11*

PH5

PB7

PB6

PH4

PF5/PWM5

PF6/PWM6

PG1/EXIRQ9*/TMIY

PA6/KIN14*/PS2CC

PA7/KIN15*/PS2CD

PD0/AN8

PD1/AN9

PD2/AN10

PD3/AN11

PD4/AN12

PD5/AN13

PD6/AN14

PD7/AN15

PF0/IRQ8*/PWM2

PF1/IRQ9*/PWM3

PB0/LSMI*

PB1/LSCI

PC0/TIOCA0/WUE8*

PC1/TIOCB0/WUE9*

PC2/TIOCC0/TCLKA/WUE10*

PC4/TIOCA1/WUE12*

PC5/TIOCB1/TCLKC/WUE13*

PC6/TIOCA2/WUE14*

PC7/TIOCB2/TCLKD/WUE15*

PG3/EXIRQ11*/SCL2

PF3/IRQ11*/TMOX

PA1/KIN9*/PA2DD

PA0/KIN8*/PA2DC

PE1*/ETCK

PE2*/ETDI

PE3*/ETDO

PE4*/ETMS

(2 OF 4)

VCL

AVREF

VCC

VCC

VCC

AVCC

XTAL

EXTAL

AVCC

VCC

MD1

MD2

NMI

RES*

ETRST*

AVREF

AVSSVSS

(3 OF 4)

NC22

NC21

NC20

NC19

NC18

NC17

NC16

NC15

NC14

NC13

NC12

NC9

NC6

NC11

NC10

NC8

NC7

NC5

NC4

NC3

NC2

NC1

NC0

(4 OF 4)

OUT

OUT

IO

OUT

IN

IN

IN

OUT

IN

IO

IN

IO

OUT

OUT

IN

IN

OUT

OUT

IN

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

IN

IN

IN

OUT

OUT

OUT

OUT

IO

IO

IO

IO

IO

IO

IO

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

OUT

IN

IN

OUT

OUT

IN

OUT

OUT

IN

OUT

OUT

OUT

IO

IO

IO

IO

IN

IN

IN

OUT

OUT

OUT

IO

IN

IN

IN

IN

IO

IO

IN

IN

IO

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

SMC_XXX WHERE XXX IS THE PORT NUMBER.

CAN BE LEFT NO-CONNECTED.

UNUSED PINS HAVE THE FORMAT

LAYOUT NOTE:

SMC

PLACE R5899 AND C5820 NEAR SMC PIN N14,N15

VCL IS INTERNAL RAIL

PLACE C5807 NEAR PIN F1

LAYOUT NOTE:

DRIVEN OUTPUTS ALWAYS SO THEYTHEY ARE SET BY SOFTWARE TO BE

C58021

2805

20%6.3VCERM

22UF

OMIT

C58071

2 CERM-X5R6.3V

0.47UF

402

10%

C58031

210V

0.1UF20%

CERM402

C58201

2

0.1UF20%

CERM10V

402

R58991 2

5%1/16W

4.7

402MF-LF

C58041

2

0.1UF20%10VCERM402

XW58001 2

SM

C58051

2402

10V20%0.1UF

CERM

C58061

220%10VCERM402

0.1UFU5800B12

C13

A15

B14

B15

C14

D12

C15

D13

D14

D15

E12

E14

E15

E13

F14

D9

C9

A9

B9

D8

C8

A8

D7

A5

B5

D5

C3

B1

C2

D3

C1

G1

G4

F2

L13

L14

L15

K12

K13

K14

J12

J13

N12

R13

P13

R14

P14

R15

N13

P15

C7

A7

B7

D6

C6

A6

B6

K4

J2

J1

J3

J4

H2

H1

G2

SMC_H8S2116

OMIT

BGA

U5800R3

P3

R2

N3

R1

N2

M4

N1

B10

A10

D10

A11

B11

C11

A12

D11

G14

G15

G13

G12

H14

H15

H13

H12

M11

P11

R11

N11

P10

R10

N10

M10

M3

M2

M1

L4

L2

M7

P6

R6

N6

M6

R5

P5

N5

P9

R9

N9

P8

R8

M8

P7

R7

E1

F3

K2

C4

D4

B3

OMIT

SMC_H8S2116BGA

U5800

N14

N15

M14

M15

P12

R12

L1

B2

E2

K1

F4

E3

P2

P1

J15

A1

F1

D1

P4

R4

F12

F13

B13

A13

A4

B4

D2

A2

BGASMC_H8S2116

OMIT

U5800

G3

H3

K15

J14

F15

A14

C12

C10

C5

A3

B8

E4

K3

H4

M9

N8

L3

N4

M5

N7

M12

M13

L12

BGASMC_H8S2116

OMIT

R58091

2MF-LF5%

4021/16W10K

R58011

2MF-LF402

5%10K1/16W

R58021

2

1/16W5%10KMF-LF402

R58031

2

05%1/16WMF-LF402

NOSTUFFR58981

2

10KMF-LF5%1/16W402

051-7270 B

58 105

SMC_XDP_TDO_3_3

PM_SYSRST_LSMC_USB_DEBUG_MUX

PM_THRM_LPM_EXTTS_L

SMC_ODD_DETECTISENSE_CAL_ENSMC_EXCARD_CP

SMC_CASE_OPEN

SMB_B_S0_DATASMB_A_S3_CLK

SMC_THRMTRIPSMC_PROCHOT

SMB_B_S0_CLK

SMB_A_S3_DATA

ALS_GAINSMC_FWE

SMC_EXCARD_PWR_EN

SMC_BATT_ISET

SMC_LID

SMB_BSA_DATA

SPI_CE_L

SMC_SYS_VSET

SMC_FAN_3_CTL

SMS_ONOFF_L

SMC_EXCARD_OC_L

SMS_INT_L

SMC_BATT_VSETSMC_SYS_ISET

SMC_XDP_TCK_3_3

SYS_ONEWIREPM_BATLOW_L

SMS_X_AXISSMS_Y_AXISSMS_Z_AXISSMC_ANALOG_IDSMC_NB_ISENSESMC_MEM_ISENSEALS_LEFTALS_RIGHT

SMC_PF0SMC_PF1

SMC_EXTSMI_LSMC_RUNTIME_SCI_L

SMC_FAN_0_CTLSMC_FAN_1_CTLSMC_FAN_2_CTL

SMC_FAN_0_TACHSMC_FAN_1_TACHSMC_FAN_2_TACHSMC_FAN_3_TACH

SMB_BSA_CLK

SMC_CPU_RESET_3_3_L

BOOT_LPC_SPI_LSMC_RCIN_L

SMC_TCKSMC_TDISMC_TDOSMC_TMS

SMC_RST_L

=PP3V3_S5_SMC

SMC_VCL

=PP3V3_S5_SMC

GND_SMC_AVSS

GND_SMC_AVSS

SMC_NMI

SMC_TRST_L

PP3V3_AVREF_SMC

SMC_MD1KBC_MDE

=PP3V3_S5_SMC

PP3V3_AVCC_SMCMIN_LINE_WIDTH=0.25 MM

MIN_NECK_WIDTH=0.20 MM

SMC_EXTALSMC_XTAL

SMC_CPU_VSENSE

SMC_ONOFF_L

SC_RX_LSC_TX_L

SMC_PBUS_VSENSESMC_DCIN_ISENSESMC_GPU_VSENSESMC_GPU_ISENSE

SMC_CPU_ISENSE

SMC_CPU_INIT_3_3_LSMC_PROCHOT_3_3_LSPI_SOSPI_SISPI_SCLKSPI_ARBSMC_ADAPTER_ENSMC_PM_G2_EN

SMB_0_S0_CLK

SMC_SYS_LED_16B

SMC_P20SMC_P21SMC_P22SMC_P23

SMC_BATT_TRICKLE_EN_LSMC_BATT_CHG_ENSMC_P26SMC_P27

SMC_TPM_PP

SMC_XDP_TMS

SMC_SYS_LEDSMC_XDP_TCK

SMC_SYS_KBDLED

SMC_RSTGATE_L

SMC_SUS_CLK

SMC_TPM_GPIO

SMC_BATT_ISENSESMC_NB1V5_ISENSE

SMC_XDP_TRST_L

INT_SERIRQPCI_CLK_SMC

LPC_AD<3>LPC_AD<2>

LPC_AD<0>LPC_AD<1>

PM_PWRBTN_L

PM_RSMRST_LSMC_SB_NMIRSMRST_PWRGDALL_SYS_PWRGD

PM_LAN_ENABLE

LPC_FRAME_LSMC_LRESET_L

SMC_WAKE_SCI_L

PM_CLKRUN_LPM_SUS_STAT_L

SMB_BSB_CLK

SMC_BC_ACOKSMC_BS_ALRT_LPM_SLP_S3_LPM_SLP_S4_LPM_SLP_S5_L

SMB_0_S0_DATA

SMB_BSB_DATA

SMC_TX_LSMC_RX_L

IMVP_VR_ON

55C6

55C6

55C2

55C2

53D6

53D6

53C6

53C6

53C1

53C1

53B7

53B7

65D3

65D3

53B5

53B5

65D3

58C6

51B4

51B5

50D7

50D7

53B3

53B3

50D7

78C2

50A2

58C6

58C6

58C6

58C6

58C6

58C6

58C6

51B5

64C8

50B3

50B3

26C5

50A2

78C6

50B2

51B4 51B5

51B5

51B4

51B4

51B5

50B1

50B1

53B1

53B1

50B1

50C6

47C6

50A2

50A2

51C5

51C5

51C5

51C4

51C4

51C4

51C4

50A2

50A2

66B5

43B7

64B8

50B2

50B2

23C5

50D5

53A8

47B6

6D5

47B6

47B6

78C3

54C7

50B2

47C6

47C6

22B3 50B2

50B2

50B2

50B2

50D6

49D3

49D4

50B6

50B6

51B5

51B4

51B4

49D4

50B2

54C1

54C1

54C7

43B7

47B6

47C6

6D4

23C8

21D4

21D4

21D4

21D4

64B1

21C5

23C8

23C5

47B6

50B2

42A8

41B6

50A2

46B5

46B5

50B2

5B2

50B5

23C8

14B7

36C4

5A2

5C1

50A2

27D3

27C6

50C2

50C2

27D3

27C6

5B2

50B2

5C1

5C1

50B2

27C3

22C6

50D5

50D5

57C6

50B5

23C3

50D5

5C1

50B2

5C1

23C1

57C3

57C3

57C3

50D5

50D5

50A2

55C7

55D2

50C5

50C5

23B8

23C8

56B7

56B4

50D5

56B7

56B4

50D5

50D5

27C3

50B2

5C2

21C3

5C2

5C2

5C2

5C2

5C2

49C2

49C2

49B2

49C4

5C2

5C2

50B6

5C2

49D3

50C8

50C8

53D6

5B2

50B5

50B5

53D2

53C4

53C6

53B6

53B7

50D5

50D1

22C6

22C6

22C6

22C6

5C1

64A8

27D6

50A8

50C5

50C5

50C5

50C5

5C1

5C1

50C5

50C5

50B5

50C5

50D5

50D5

55A6

6B7

35B2

50C5

53C2

50D5

50C5

5C2

34D6

5C2

5C2

5D2

5C2

23C3

23C1

23C3

50A4

26A5

23C3

5C2

26B1

23C1

5C2

5C2

27B3

5C1

5D1

23C3

23C3

23C3

27D6

27B3

5C2

5C2

59C7

G

D

S

G

D

S

IN OUT

GND

IN OUT

V-

V+

V-

V+OUT

NCCD

GND

OUT

VDD

OUT

OUT

G

D

SIN

OUT

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

SMC PWRGD Circuit

SMC 1.05V to 3.3V Level Shifting

1.05V Mid-Reference

Silk: "SMC RST"

SMC Reset Button / Brownout Detect

NC

System (Sleep) LED Circuit

NOTE: R5965 acts as 10K pull-up for PGOOD signal

1.71V Reference

Silk: "PWR BTN"

Debug Power ButtonSMC 3.3V to 1.05V Level Shifting

SMC AVREF Supply

ISL6269 undervoltage threshold 81-87% (2.67 - 2.87V)

5V Comp threshold set to 4.480V (89.6%)

SMC Crystal Circuit

Reports when 5V S5 and 3.3V S5 are in regulation

C5900 1

2

0.1uF

CERM402

20%10V

R59901 2

SMC_TPM_GPIO1

0

1/16W5%

MF-LF402 R5991

1 20

SMC_TPM_GPIO2

5%1/16WMF-LF402

Q5995

6

2

1

2N7002DW-X-FSOT-363

Q5995

3

5

4

2N7002DW-X-FSOT-363

R59921 2

1/16WMF-LF

0

5%

402R59931 2

1/16WMF-LF

0

5%

402

C5977 1

2

0.1uF

CERM402

20%10V

R59711

2

1K

MF-LF402

5%1/16W

R59701

2

5%

402

6.2K

1/16WMF-LF

C59651

2

402CERM-X5R6.3V

0.47UF10%

C59671

2

0.01uF20%16VCERM402C5966 1

26.3V20%

X5R

10uF

603

VR5965

3

1 2

SOT23-3REF3133

CRITICAL

C5960 1

2

0.1uF

10V20%

402CERM

R59611

2

10K

MF-LF402

1%1/16W

R59621

2

MF-LF402

1%1/16W

10K

R59651

2

5%

402MF-LF

10K

1/16W

U59774

3

1

5

2

LMC7211SM-LF

U59604

3

1

5

2

SM-LF

LMC7211

R59941 2

402MF-LF

5%1/16W

0

R59951 2

1/16WMF-LF

SMC_TPM_PP

5%

402

0

R5931 1 2

402MF-LF5% 1/16W

10K

R5932 1 2

402

10K1/16W5% MF-LFR5933 1 2100K

402MF-LF5% 1/16WR5934 1 210K1/16W5% MF-LF 402R5935 1 2

402MF-LF5% 1/16W

10K

R5936 1 2100K5% MF-LF 4021/16W

R5937 1 22.0K402MF-LF5% 1/16WR5938 1 2

402MF-LF5% 1/16W

100K

R5939 1 2

402MF-LF5% 1/16W

10K

R5940 1 210K1/16W5% 402MF-LFR5941 1 210K

4025% 1/16W MF-LFR5942 1 210K1/16W5% 402MF-LF

R5943 1 210K1/16W5% MF-LF 402R5944 1 2

402MF-LF5% 1/16W

10K

R5945 1 2

402MF-LF5% 1/16W

10K

R5946 1 2

1/16W5% MF-LF 402

10K

R5947 1 2470K402MF-LF5% 1/16WR5948 1 210K

1/16W5% MF-LF 402

R5930 1 2

402MF-LF5% 1/16W

10K

Y59201

2

20.00MHZ5X3.2-SM

CRITICAL

U5900

5

3

4

1

2

SOT23-5RN5VD30A-F

CRITICAL

R59641

2

10K

1/16W1%

402MF-LF

R59631

2

16.2K

MF-LF402

1%1/16W

C59691

2 CERM402

0.0022uF10%50V

R5980 1 2

402MF-LF5% 1/16W

10K

R5981 1 2

5%

10K1/16W MF-LF 402R5982 1 2

1/16W

10K5% MF-LF 402

R5983 1 2

MF-LF 4025% 1/16W

100K

R5984 1 2100K1/16W5% MF-LF 402R5985 1 2100K1/16W5% MF-LF 402

R59961 2

402MF-LF

5%1/16W

0

R59001

2

1/16W5%

402MF-LF

1K

R59011

2

OMIT

0

MF-LF603

5%1/10W

R59101

2

MF-LF603

5%

OMIT

0

1/10W

Q5952

3

1

2

2N7002SOT23-LF

Q59501

3

2

2N3906SOT23-LF

R59501

2

100

MF-LF402

5%1/16W

R59511

2

1/16W5%

402MF-LF

2.2K

R59521

2

MF-LF402

1/16W

10K5%

C5920

1 2

15pF

CERM402

5%50V

C5921

1 2

15pF

402CERM50V5%

C5901 1

2CERM

10%16V

0.01UF

402


59

051-7270 B

105

SMC Support

USB_DEBUGPRT_EN_L

TP_SMC_FAN_3_TACHMAKE_BASE=TRUE

TPM_GPIO2

SMS_INT_L

SMC_TPM_RESET_L

SMC_LID

SMC_ONOFF_L

SMC_FWE

SMC_TX_L

SMC_RX_L

=PP3V3_S3_SMS

=PP3V3_S3_TPM

SYS_ONEWIRE

SMC_EXTAL

SMC_XTAL

SMC_TMS

SMC_BS_ALRT_L

SMC_TDO

SMC_TDI

SMC_XDP_TCK_3_3

SMC_TCK

SMC_CPU_RESET_3_3_L

SMC_ADAPTER_EN

SMC_CASE_OPEN

SMC_BC_ACOK

GND_SMC_AVSS


VOLTAGE=0V

PM_SUS_STAT_L

SMC_EXCARD_CP

SMC_BATT_TRICKLE_EN_L


PP3V3_AVREF_SMCMIN_LINE_WIDTH=0.4 mm

VOLTAGE=3.3V

=PP3V42_G3H_SMCVREF

CPU_PROCHOT_L

PM_THRMTRIP_L

SMC_PROCHOT

SMC_THRMTRIP

SMC_ONOFF_L

PP5V_S5

=PP3V42_G3H_SMC_PWRGD

MAKE_BASE=TRUERSMRST_PWRGD

P5VS5_PGOOD

P1V71_SMC_REF

P5VS5_COMP_POS

=P3V3S5_PGOOD

SYS_LED_ILIM

=PP5V_S3_SYSLED

SYS_LED_L

SYS_LED_ANODE

SYS_LED_L_VDIV

SMC_SYS_LED_16B

=PP3V3_S5_SMC

SMC_MANUAL_RST_L SMC_RST_L

MAKE_BASE=TRUEFWH_INIT_LSMC_CPU_INIT_3_3_L

SMC_P1V05S0_ISENSEMAKE_BASE=TRUE

SMC_NB_ISENSE

DIMM_OVERTEMP_LPM_EXTTS_LMAKE_BASE=TRUE

MAKE_BASE=TRUESMC_P1V5S0_NB_ISENSESMC_NB1V5_ISENSE

TP_SMC_ANALOG_IDMAKE_BASE=TRUE

SMC_ANALOG_ID

MAKE_BASE=TRUETP_SMC_SYS_LEDSMC_SYS_LED

MAKE_BASE=TRUETP_SMC_BATT_VSETSMC_BATT_VSET

MAKE_BASE=TRUETP_SMC_SYS_VSETSMC_SYS_VSET

TP_SMC_FAN_2_CTLMAKE_BASE=TRUE

SMC_FAN_2_CTL

TP_SMC_FAN_2_TACHMAKE_BASE=TRUE

SMC_FAN_2_TACH

SMC_FAN_3_TACHMAKE_BASE=TRUETP_SMC_FAN_3_CTLSMC_FAN_3_CTL

TP_SMC_XDP_TCKMAKE_BASE=TRUE

SMC_XDP_TCK

MAKE_BASE=TRUETP_SMC_XDP_TMSSMC_XDP_TMS

MAKE_BASE=TRUETP_SMC_XDP_TRST_LSMC_XDP_TRST_L

MAKE_BASE=TRUETP_SMC_P20SMC_P20

MAKE_BASE=TRUETP_SMC_P21SMC_P21

TP_SMC_P22MAKE_BASE=TRUE

SMC_P22


SMC_P23


SMC_P27

TP_SMC_PF0MAKE_BASE=TRUE

SMC_PF0

MAKE_BASE=TRUETP_SMC_PF1SMC_PF1

VOLTAGE=0.46VP0V46_SMC_LSREF

=PP3V3_S0_SMC_LS

SMC_PROCHOT_3_3_L

SC_TX_L

SMC_TPM_PP

SC_RX_L

TPM_PP

SMC_RX_L

TPM_GPIO1

SMC_TX_L

SMC_BATT_CHG_EN

PM_SLP_S5_L

CPU_PROCHOT_L

SMC_EXCARD_OC_L EXCARD_OC_L

SMC_USB_DEBUG_MUX

SMC_XDP_TDO_3_3

=PP3V3_S5_SMC

SMC_P26MAKE_BASE=TRUETP_SMC_P26

SMC_TPM_GPIO

SMC_MEM_ISENSE

55C6 55C2 53D6 53C6 53C1 53B7

51B4

51B5

53B5

58C6

65D3

51B5

51B4

65D3

78C2

50B3

50B3

49D5

53B3

51B5

78C2

50B1

50B2

50B2

50D7

50C6

49C7

49C7

49B7

51B4

66B5

51B4

51B5

51B5

47C6

49C5

53B1

49C5

49B7

49D7

21C2

50B2

49D4

51B5

51C5

49C7

49C7

49D7

47C6

49D4

49B5

78C3

49C5

46B5

46B5

65C3

65C3

47C6

49B5

49C5

49B5

49B5

49C5

43B7

47B6

49C4

23C5

47B6

47B6

50D3

14B6

49C5

63C7

49D3

49C3

21C4

29C3 49B7

46B5

46B5

47C6

49C5

50C1

6C3

49D3

46B3

58C6

23C3

58B7

49B5

5B2

49B5

5C2

5C2

57C6

58C2

5C1

49C3

49C3

5C2

5D1

5C2

5C2

49B5

5C2

49B5

5C1

49C5

5C1

49B2

5C2

5C1

5C1

49D2 65D3

7C6

7C6

49B5

49B5

5B2

65C1

65D3

49D7

64A8

65B1

78B4

49C7

49C2

5C2

5C2 49D5

53B2 49A7

28C3 14B7

53B4 49D5

49A7

49C7

49B5

49B5

49B7

49B7

49B7

49B7

49C7

49C7

49C7

49D7

49D7

49D7

49D7

49D7

49B5

49B5

65A3

49D5

49C5

49C7

49C5

58C6

5C2

58C6

5C2

5C1

23C3

7C6

49B7 5C1

49B7

49B7

49C2

49D7

49D5

49A7

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

NC NC

NC

516S0384

NC

(GPIO15)

J6000

1

10

1112

1314

1516

1718

19

2

20

2122

2324

2526

2728

29

3

30

3132

3334

4

56

78

9

QT500306-L021-9FM-ST-SM

LPCPLUS

CRITICAL


LPC+ Debug Connector

051-7270 B

10560

SMC_TX_L

SMC_MD1

SMC_TDO

SMC_TRST_L

DEBUG_RST_L

SMC_TMS

PM_CLKRUN_L

LPC_FRAME_L

BOOT_LPC_SPI_L

LPC_AD<1>

LPC_AD<0>

SV_SET_UP

SMC_RX_L

SMC_NMI

SMC_RST_L

SMC_TCK

SMC_TDI

PM_SUS_STAT_L

INT_SERIRQ

LPC_AD<3>

LPC_AD<2>

PCI_CLK_PORT80_LPC

FWH_INIT_L

=PP5V_S0_LPCPLUS

=PP3V3_S5_LPCPLUS

50B3

50B3

58C6

50B2

58C6

58C6

58C6

58C6

50B2

50A2

58C6

58C6

58C6

49C7

50B2

50B2

49C5

49C7

49C7

49D7

49D7

23C3

49C7

50D6

50B2

50B2

49C5

49C7

49C7

49C7

50D3

46B5

49C1

49B5

49C1

26B1

49B5

23C8

21C5

22B3

21D4

21D4

23B6

46B5

49C1

49C3

49C5

49B5

23C5

23C8

21D4

21D4

34D6

21C4

65A1

65D3

5C2

5C2

5C2

5C2

5C2

5C2

5C2

5C2

5C2

5C2

5D2

5C2

5C2

5C2

5C2

5C2

5C2

5C2

5C2

5C2

5C2

5C2

5C2

5D2

5D2

IO

IO

GND

VDD

SDATA

SCLK

THM*

ALERT*/

D+

D-

THM2*

SMBDATA

SMBCLK

ALERT*

OT2*

DXP2

OT1*

DXN

DXP1

GND

VCC

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

518S0487

NC

518S0487NC

(Th0H)

(Th1H)

GPU Die Thermal Sensor

(TG0T)

(TG0H)

Place U6150 near GPU

GPU/Heat Pipe & Bottom Case Skin Thermal Sensor

Placement note:Place on left side of fan cutout

NC

NC

Placement note:

Placement note:

NC

NC

NC

Place in between VRAM

Placement note:

Keep all 4 XWs as close

to U6100 as possible

C6120 1

250V

CERM402

10%0.0022uF

XW6120

1 2

SM

XW6121

1 2

SM

XW6111

1 2

SM

XW6110

1 2

SM

C61601

2

0.001UF10%

402CERM50V

C61001

2

0.1uF

CERM402

20%10V

R61521

2

1/16WMF-LF402

5%10K

R61001 2

47

MF-LF

5%1/16W

402

C6150 1

2

0.1UF

X5R402

10%16V

R61511

2

1/16W

10K5%

402MF-LF

U61506

3

2

5

8

7

4

1

MSOPTMP401

R61601 2

402MF-LF1/16W1%

499

R61611 2

402MF-LF1/16W1%

499

C6110 1

2

10%

402CERM

0.0022uF

50V

J6160

3

4

1

2

BM02B-ACHKS-GAN-TF-LF-SN-M

CRITICAL

M-RT-SM

J6120

3

4

1

2

BM02B-ACHKS-GAN-TF-LF-SN-MM-RT-SM

CRITICAL

U6100

8

3

2

4

6

5

10

7

9

1

UMAX1MAX6695AUB

CRITICAL


051-7270 B

10561

Thermal Sensors



MIN_LINE_WIDTH=0.38 mmPP3V3_S0_GPUTHMSNS_R

=SMBUS_REMTHMSNS_SDA

=SMBUS_REMTHMSNS_SCL

REMTHMSNS_DXP2

REMTHMSNS_DXN

REMTHMSNS_DXP1

=PP3V3_S0_REMTHMSNS

RSTHMSNS_THM_L

RSTHMSNS_ALERT_L

GPUTHMSNS_DXP

GPUTHMSNS_DXN =SMBUS_GPU_TDIODE_SDA

ATI_TDIODE_P

ATI_TDIODE_N

=SMBUS_GPU_TDIODE_SCL

=PP3V3_S0_GPU_TDIODE

RSFSTHMSNS_D_N

RSFSTHMSNS_D_P

HSTHMSNS_DX_N

HSTHMSNS_DX_P

27D3

27D3

65B3

27D3

74A3

74A3

27D3

65A3

5B2

5B2

5B2

5B2

IN

OUT

N-CHN

S

D

G

P-CHN

G

DS

N-CHN

S

D

G

P-CHN

G

DS

D

S

G

D

S

G

D

S

G

OUT

OUTIN OUTIN

OUTIN IN OUT

OUTINOUTIN

OUT

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

1.05A / 1.1W

PBUS Voltage Sense Enable & Filter

Enables PBUS VSense divider when high.

1.5V S0 (NB) Current Sense Filter

CPU Voltage Sense / Filter

Place short near U0700 center

GPU Voltage Sense / Filter

GPU Current Sense Filter

DCIN Current Sense Filter

Place short near U8400 center

Battery Current Sense Filter

Place RC close to SMC

1.2A / 1.44W



1.05V S0 (NB) Current Sense Filter


Place RC close to SMCPlace RC close to SMC


Rthevanin = 4573 ohms


CPU Current Sense Filter


Switches in fixed load on power supplies to calibrate current sense circuits

Current Sense Calibration Circuit

R62281

2

470K5%1/16WMF-LF402

R62271

2402

MF-LF1/16W

5%100K

R62851

2

27.4K1%

1/16WMF-LF402

C62851

26.3V

0.22UF

402X5R

20%

R62861

2

5.49K

402MF-LF1/16W

1%

Q6229

6

2

1

FDG6332C_NLSC70-6

Q6229

3

5

4

FDG6332C_NLSC70-6

Q6215

6

2

1

SC70-6FDG6332C_NL

Q6215

3

5

4

FDG6332C_NLSC70-6

Q6220

5

4

1 2 3

FDM6296

CRITICAL

MICROFET3X3

Q6221

5

4

1 2 3

MICROFET3X3

FDM6296

CRITICAL

Q6223

5

4

1 2 3

MICROFET3X3

CRITICAL

FDM6296

C62591

2

0.22UF20%6.3VX5R402

R62591 2

1%1/16WMF-LF402

4.53K

R62701 2

1/16W

4.53K

402MF-LF

1%

C62701

26.3V

0.22UF

402X5R

20%

C62751

2

20%

X5R402

0.22UF

6.3V

R62751 2

1%1/16WMF-LF402

4.53K

C62801

26.3V

0.22UF

402X5R

20%

R62801 24.53K

402MF-LF1/16W1%

R62901 2

1%1/16WMF-LF402

4.53K

C62901

2

20%

X5R402

0.22UF

6.3V

C62401

2

20%

X5R402

0.22UF

6.3V

R62401 2

1%1/16WMF-LF402

4.53K

C62351

26.3V

0.22UF

402X5R

20%

R62351 24.53K

402MF-LF

1%1/16W

XW6259

1 2

SM

R62091 2

402

1%

4.53K

MF-LF1/16W

C62091

2

402X5R6.3V20%0.22UF

XW6209

1 2

SM

R62201

21206

MF-LF1/4W1%

1.00

R62291

2

470K5%

1/16WMF-LF402

R62211

21206

MF-LF1/4W

1%1.00

R62231

21206

MF-LF1/4W

1%1.00


Current & Voltage Sensing

62 105

B051-7270

PBUSVSENS_EN_L

GPUVCORE_ISENSE_CALMIN_LINE_WIDTH=0.50 mmMIN_NECK_WIDTH=0.20 mm

CPUVCORE_ISENSE_CALMIN_LINE_WIDTH=0.50 mmMIN_NECK_WIDTH=0.20 mm

SMC_CPU_ISENSE

GND_SMC_AVSS

SMC_PBUS_VSENSE

VOLTAGE=12.6VPPBUS_G3H_VSENSE

ISENSE_CAL_EN

=PP5V_S0_ISENSECAL

ISENSE_CAL_EN_L

GND_SMC_AVSS

LIO_DCIN_ISENSE

=PPVCORE_S0_CPU

SMC_DCIN_ISENSE

GND_SMC_AVSS

LIO_BATT_ISENSE SMC_BATT_ISENSE

GND_SMC_AVSS

CPUVCORE_IOUT GPUVCORE_IOUT SMC_GPU_ISENSE P1V5S0_NB_IOUT SMC_P1V5S0_NB_ISENSE SMC_P1V05S0_ISENSE

GND_SMC_AVSS GND_SMC_AVSS GND_SMC_AVSS

GPUVSENSE_IN

CPUVSENSE_IN

SMC_GPU_VSENSE

SMC_CPU_VSENSE

GND_SMC_AVSS

=PPVCORE_S0_GPU

GND_SMC_AVSS

=PPVCORE_S0_CPU =PPVCORE_S0_GPU

P1V05S0_IOUT

PPBUS_G3H

=PBUSVSENS_EN

=PP1V05_S0_REG

MIN_NECK_WIDTH=0.20 mmMIN_LINE_WIDTH=0.50 mmP1V05S0_ISENSE_CAL

ISENSE_CAL_EN_LS5V

55C6

55C6 55C6

55C6

55C6

55C2

55C2 55C2

55C6 55C6 55C2

55C6

55C6

55C2

53D6

53D6 53D6

55C2 55C2 53D6

55C2

55C2

53D6

53C6

53C6 53C6

53D6 53D6 53C6

53D6

53C6

53C6

53C1

53C1 53C1

53C6 53C6 53C1

53C1

53C1

53B7

53B7

53B7 53B7

53C1 53C1 53B7

53B7

53B7

53B5

53B5

53B5 53B5

53B5 53B7 53B5

53B5

53B5

53B3

53B3

65D1

53B3 53B3

53B3 53B3 53B3

53B3

53B3

65D1

53B1

53B1

53A6

53B1 53B1

53B1 53B1 53B1

53B1

74A7

53B1

53D7 74A7

50B6

50B6

9D7

50B6 50B6

50B6 50B6 50B6

50B6

69D8

50B6

9D7 69D8 65D8

49C4

49B7

65A1

49C4

47B6

8D7

49C4

47C6

49C4

49C4 49C4 49C4

49C4

65A6

49C4

8D7 65A6 63A2

49D5

49B2

49D5

5A2

5A2

49B2

5C1

8B5

49D5

49B2

5C1 49D5

49B2

59A5 68D1 49D5 60A6 50D3 50D3

49B2 49B2 49B2

49D5

49D5

49B2

53A5

49B2

8B5 53C7

63B1

65C1

64B6

5B2

SCK

SOWP*

SI

VDD

CE*

HOLD*VSS

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

R6309 IS NOT NEEDED WHEN SHARING SPI FLASH WITH ICH7M AND TEKOA(LAN CHIP)

R6303 SHOULD BE PLACED LESS THAN 100 MILS FORM FLASH ROM

R6307 AND R6306 SHOULD BE PLACED LESS THAN 100 MILS FORM ICH7M

C63121

2

0.1UF20%10VCERM402

R63011

2

3.3K

MF-LF

5%

402

1/16W

R63021

2MF-LF1/16W

5%3.3K

402

C63011

2 50V5%

CERM402

22pF

R63071 247

1/16W5%

402MF-LF

C63081

2 CERM

5%50V

22pF

402

C63091

2

22pF

402

50VCERM

5%

R63031 2

1/16W5%

47

MF-LF402

R63061 2

402

5%

MF-LF1/16W

47

C63111

2 50V5%

CERM402

22pF

U6301

1

7

6 5

2

8

4

3

SOI

SST25VF016B

16MBIT

CRITICAL OMITR6308

12

MF-LF1/16W

10K5%

402

R6309

12

402MF-LF1/16W

5%10K

NOSTUFF


105

B051-7270

SPI BOOTROM

63

SPI_WP_LSPI_HOLD_L

SPI_CE_LSPI_SO

SPI_SISPI_SCLK_RSPI_SCLK SPI_SI_R

SPI_SO_R

=PP3V3_S5_ROM

49B5 49D5

49D5 49D5

22C6 22C6

22C6 22C6

65C3

V+

V-

G

D

SIN

OUT

NC

CNTRL

THRML_PAD

VDD SW

AGNDPGND

FB

VOUT

ININ

OUT

OUT

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

Left ALS circuit has 1K series-R

Left ALS Filter

Keyboard LED Driver

NC

NC

Right ALS Circuit

RTALS_OP_IN and RTALS_OP_COMP need to be matched U6405

3

4

1

5

6

2

CRITICAL

SOT23-6-LFMAX4236EUTT

C6405 1

2

0.1UF

10V20%

402CERM

R64061

2

1/16W5%

402MF-LF

120KC6406 1

26.3V20%

402X5R

0.22UF

R64071

2

1/16W1%

402MF-LF

15.0KR64081

2

1/16W1%

402MF-LF

1K

R64011 2

1K

1/16W1%

402MF-LF

PD64001

2

CRITICAL

TH

BS520EOF R64001

2

1/16W5%

402MF-LF

5.1MC64001

2

402

16V20%

CERM

0.01UF

Q6408

3

1

2

SOT23-LF2N7002

R64101 2

1/16W1%

402MF-LF

4.53K

C64101

2

402

6.3V20%

X5R

0.22UF

U6450

2

3

46

5

7

9

1

8

CRITICAL

LLPMM3120

L6450

1 2

CRITICAL

3.8x3.8x1.5MM

22uH

C6450 1

26.3V10%

402CERM

1uFR64511

2

1/16W5%

402MF-LF

10K

KBDLED_NOT

R64521

2402

10K

KBDLED_HAS

1/16W5%

MF-LF

C64551

2

603X5R25V20%0.22uF

R64551

2

MF-LF1/8W1%

805

25.5

C64301

2

0.22UF

X5R402

20%6.3V

R64301 23.48K

MF-LF402

1%1/16W


B051-7270

10564

ALS Support

=RTALS_GAIN

RTALS_OP_COMP

=PP3V3_S3_RTALS

ALS_RT_OUT ALS_RIGHT

GND_SMC_AVSS

RTALS_OP_INRTALS_PHOTODIODE

RTALS_GAIN_L

SMC_SYS_KBDLED

=PP3V3_S0_KBDLED

KBDLED_RETURN

KBDLED_ANODE

KBDLED_SW

=PP5V_S0_KBDLED

GND_SMC_AVSS

LTALS_OUT ALS_LEFT

55C6

55C2

53D6

53D6

53C6

53C6

53C1

53C1

53B7

53B7

53B5

53B5

53B3

53B3

53B1

53B1

50B6

50B6

49C4

49C4

78C6

6D4

65C3

49A7

49B2

49C7

65B3

78C3

78C3

65A1

49B2

5B2 49A7

G

S D

G

S D

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

518S0369

NC

Right FanLeft Fan

518S0369

NC

NC

NC

R65501

2

5%

MF-LF402

47K

1/16W

R65551 2

47K

402MF-LF

5%1/16W

R65601

2

1/16W5%

47K

MF-LF402R6565

1 2

5%1/16WMF-LF

47K

402

R65511

2

100K

1/16W5%

MF-LF402

Q6560

3

5

4

SOT-3632N7002DW-X-F

R65611

2402

MF-LF

5%1/16W

100K

Q6560

6

2

1

2N7002DW-X-FSOT-363

J6550

5

6

1

2

3

4

M-RT-SMSM04B-ACH

CRITICAL

J6560

5

6

1

2

3

4

M-RT-SMSM04B-ACH

CRITICAL


65 105

051-7270 B

Fan Connectors

SMC_FAN_1_CTL

SMC_FAN_0_TACH

SMC_FAN_0_CTL FAN_RT_PWM

=PP5V_S0_FAN_RT

FAN_RT_TACH

=PP3V3_S0_FAN_LT

=PP5V_S0_FAN_LT

SMC_FAN_1_TACH

=PP3V3_S0_FAN_RT

FAN_LT_PWM

FAN_LT_TACH

65A1

49B7

49B7

49B7 5D2

65A1

5D2

65A3

5D2

49B7

65A3

5D2

5D2

CS*

SCL/SCLK

ADDR/SDI

MOT_ENABLE

ENABLE

VDD

X

Y

Z

FF/MOT

SDA/SDO

GND

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

APN:338S0354

placed on board bottom-side:placed on board top-side:

1

Desired orientation when Desired orientation when

+X

+Z (dn)

+Y

Top-through ViewPackage Top

1

+Z (up)

+X

+Y

M59 placement: Bottom-side

C66201

210V20%

402CERM

0.1uF

C66051

2

0.033UF

X7R402

20%10V

C66061

2

0.033UF

X7R402

20%10V

U6620

3

2

6

11

10

12

5

4

1 13

14

7

8

9

KXPS5-2050

CRITICAL

LGA

R66201

2

1/16W5%

402MF-LF

10K

C66041

210V20%

402X7R

0.033UF


Sudden Motion Sensor (SMS)

051-7270 B

10566

SMS_ONOFF_L

=PP3V3_S3_SMS

SMS_X_AXIS

SMS_Y_AXIS

SMS_Z_AXIS

TP_SMS_FF

65C3

49A5

50B1

49B7

49B7

49A7

IN

IO

IO

IO LAD1

LAD2

LCLK

LFRAME*

LRESET*

LPCPD*

SERRIRQ

LAD0

CLKRUN/GPIO*

PP/GPIO

GPIO_EXPRESS_00

GPIO/SM_DAT

GPIO/SM_CLK

XTALI/32K_IN

TESTBI/BADD/GPIO

TESTI

3V0

3V1

3V2

3VSB

VNC

VBAT

XTALO

GND2

GND3

GND0

GND1

LAD3

IO

IO

IN

IN

IO

IN

IN

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

VSB

BASE ADDR = 0X4E/4F

GPIO2TESTBI/BADD

1/8W (R6704/R6705) IS USED FOR NOW

SINCE CURRENT OF VSB IS NOT YET ON SPEC,

NOTE:

PLACE R6702-03 WHERE ACCESSIBLE

LAYOUT NOTE:

PLACE WHERE ACCESSIBLE

LAYOUT NOTE:

BASE ADDR = 0X2E/2F

NC

NC

NC

CLKRUN*

GPIO

PP

NC

VDD

VDD

VDD

NC

NC

GND

(INT PD)

C67001

2

TPM

402X5R16V10%0.1UF

C67011

2

TPM

0.1UF

402X5R16V10%

C67021

2

TPM

0.1UF10%16VX5R402

C67031

2

TPM

0.1UF10%16VX5R402

R67001

2

NOSTUFF

05%1/16WMF-LF402

U6700 10

19

24

5

15

4

11

18

25

2

1

6

26

23

20

17

21

22

28

16

7

27

9

8

12

3

13

14

TPMTSSOP

OMIT

R67021

2

TPM

MF-LF1/16W5%10K

402

R67031

2

NOSTUFF

5%1/16WMF-LF

10K

402

R67041 2

TPM

805MF-LF1/8W5%

0

R67051

2

NOSTUFF

805MF-LF1/8W5%0

R67981 2

TPM

0

5%

MF-LF1/16W

402

R67991 2

MF-LF

5%

0

NOSTUFF

1/16W

402


TPM

051-7270 B

67 105

SMC_TPM_RESET_L

TPM_LRESET_L

=PP3V3_S0_TPM

=PP3V3_S3_TPMLPC_AD<3>

TPM_XTALO

PP3V3_TPM_3VSBVOLTAGE=3.3VMIN_LINE_WIDTH=0.6MMMIN_NECK_WIDTH=0.15MM

=PP3V3_S0_TPM

TPM_BADD

TPM_XTALI

TPM_GPIO2

TPM_GPIO1

TPM_PP

PM_CLKRUN_L

LPC_AD<0>

INT_SERIRQ

PM_SUS_STAT_L

TPM_RST_L

LPC_FRAME_L

PCI_CLK_TPM

LPC_AD<2>

LPC_AD<1>

51B5

51C5

51C4

51C4

51C5

50A2

51C4

51C5

51C4

49C7

49C5

49D7

49C7

49C5

49C7

49C7

49D7

65B3

65C3

21D4

65B3

23C8

21D4

23C8

23C5

21C5

21D4

21D4

50B2

26B1

58D4

50B1

5C2

35D5

58C7

35C5

50C3

50C3

50B3

5C2

5D2

5C2

5C2

5C2

34D6

5C2

5C2

IN

IN

IN

IN

OUT

IN

OUT

OUT

V-

V++

-

NC

VW

COMP

FB

FB2

RBIAS

VR_TT*

NTC

VR_ON

PGOOD

CLK_EN*

PGD_IN

PSI*

RTN

VSEN

DFB

DROOP

VO

OCSET

VSUM

ISEN2

VID0

VID1

VID3

VID2

VID4

VID5

VID6

PGND2

VIN VDD PVCC

LGATE2

PHASE2

UGATE2

ISEN1

PGND1

LGATE1

UGATE1

PHASE1

BOOT1

BOOT2

3V3

DPRSTP*

VDIFF

SOFT

DPRSLPVR

TPADGND

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

(IMVP6_FB)

(GND_IMVP6_SGND)

(GND)

1 1 0 1-Phase DCM

(IMVP6_PHASE2)

Vout = Variable

(Inductors limit)

36A max output

1 0 1 1-Phase DCM

DPRSLPVR DPRSTP* PSI* Operation Mode

(IMVP6_COMP)

(GND_IMVP6_SGND)

(GND)

(IMVP6_VW)

<Rb>

(IMVP6_ISEN2)

<Ra>

(IMVP6_VSUM)

(IMVP6_VO)

<Rc>Voffset = (Vdrp_offset * Kdroop) + Vamp_offset

Voffset worst-case ~2.3mV (+/- ~1A offset)

Gain = Rc / (Ra + Rb)

Vout @ 36A = 2.44V-2.60V

<Rc>

CPU VCore Current Sense

(IMVP6_NTC)

0 1 1 2-Phase CCM

0 1 0 1-Phase CCM

These caps for Q7550These caps for Q7500

(IMVP6_ISEN1)

(IMVP6_PHASE2)

(IMVP6_VO)

Vout = Gain * ((2.1 mV/A * Iload) + Voffset)

<Ra + Rb>

C75011

250V

0.0022UF10%

NO STUFF

CERM402

C75021

2

0.0022UF10%50V

402CERM

NO STUFF

R75051 2

1%1/16WMF-LF

10K

402

C7505

1 2

402

6.3VX5R

20%

0.22UF

R75061

2

3.65K

MF-LF

1%1/10W

603

R75321

2

MF-LF402

1/16W1%147K

C7532 1

2X7R16V

0.015uF

402

10%

C7531 1

216VX5R402

10%0.1uF

R75351

2

MF-LF1/16W

1%

402

1.82K

R75371

2

1/16WMF-LF

1%

402

4.42KC7537 1

2

402

47pF

50VCERM

5%

R75341

2

1%

MF-LF402

1/16W

107K

C7535 1

250V10%

402CERM

470pF

C75001

2

20%0.22uF

603X5R25V

C7550 1

2

20%0.22uF

25VX5R603

R75421

2

13.7K

MF-LF

1%1/16W

402

R75401 23.01K

MF-LF402

1%1/16W

R75411

2

1/16W1%1K

MF-LF402

C7540 1

250V

CERM402

5%180pF

R75451 2

MF-LF402

1/16W1%

499

7B3 21C4

14B7 23C3 84C6

7A3

64B2

26A7

49D7

14B6 26B5

R75551 2

1/16WMF-LF

1%

402

10K

C7555

1 2

0.22UF

402X5R6.3V20%

R75561

2

MF-LF

1%3.65K

603

1/10WC75521

2

NO STUFF

402

50V10%

CERM

0.0022UFC75511

2

NO STUFF

50V10%0.0022UF

CERM402

C7530 1

2CERM6.3V

402

10%1uF

R75301 2

MF-LF402

10

5%1/16W

R75361

2

1/16WMF-LF

NO STUFF

2.0K1%

402

R75331

2

MF-LF402

1/16W1%301

C7533 1

250V10%

402CERM

820pF

C7544 1

2

20%

X5R

0.22uF

402

6.3V

R75431

2

MF-LF

1%1/16W

11K

402

R75931 2

402

30.1K

1%1/16WMF-LF

R75911 2

MF-LF1/16W

402

1%

30.1K

C7528 1

2

603

16V

1uF10%

X5R

C75291

2

603

20%6.3VCERM

4.7uF

R75311 2

5%

10

1/16W

402MF-LF

R75281 2

MF-LF402

10

5%1/16W

C7546 1

2

402

0.01uF10%16V

CERM

R75471

2

MF-LF

4.02K1%

1/16W

402

R75441

2

4991%1/16WMF-LF402

C7541 1

2

0.22UF

402X5R6.3V20%

C7580 1

225V

0.0068uF

402CERM

10%

C7542 1

2CERM402

10%50V

0.001uF

NO STUFF

R75481

2

5.23K

MF-LF1/16W

1%

402

C75431

2

402CERM16V10%0.01uF

R75071

2

MF-LF1/16W

15%

402

R75571

2

5%1/16WMF-LF

1

402

C75811

2

402

0.01uF

16V10%

CERM

NO STUFF

C7582 1

2

10%16V

0.01uF

CERM402

R75811 2

0

402

5%

MF-LF1/16W

R75821 2

0

402MF-LF1/16W5%

R75981 2

402

1M

1%1/16WMF-LF

R75921 2

1%

1M

MF-LF402

1/16W

53B8

C7595 1

2CERM6.3V10%

402

1uF

R7549

1

2

0603-LF

10KOHM-5%

CRITICAL

C7598

1 2

470pF

50VCERM402

10%

C7592

1 2

402

470pF

CERM50V10%

C75341

2

820pF

402

10%50VCERM

R7546

1

2

402

470K

CRITICAL

L7505

1 2

SM-IHLP

0.36uH-30A-1.2M-OHM

CRITICAL

L7555

1 2

0.36UH-30A-1.2M-OHM

SM-IHLP

CRITICAL

R75941 2

1/16W5%

0

402MF-LFC75941

2

0.1uF

NO STUFF

20%10VCERM402

XW7530

12

SM

C75111

2 X5R16V

1uF10%

603

C75101

2

CASED2E-SMPOLY

33uF20%16V

CRITICAL

C75611

2

603X5R16V

1uF10%

C75601

2POLY16V

33uF20%

CASED2E-SM

CRITICAL

Q7500

5

4

1 2 3

CRITICAL

LFPAKRJK0305DPB

Q7550

5

4

1 2 3

CRITICAL

RJK0305DPBLFPAK

Q7501

5

4

1 2 3

LFPAK

CRITICAL

RJK0301DPB

Q7502

5

4

1 2 3

LFPAKRJK0301DPB

CRITICAL

Q7551

5

4

1 2 3

CRITICAL

RJK0301DPBLFPAK

Q7552

5

4

1 2 3

CRITICAL

RJK0301DPBLFPAK

C75151

2

CASED2E-SMPOLY

33uF20%16V

CRITICAL

U75951

3

4

2

5SC70-5

HPA00141AIDCKR

CRITICAL

U7530

48

36

26

47

10

17

45

46

16

11

12

21

24

23

32

30

25

6

8

3

33

291

34

28

2

31

4

15

7

49

35

27

22

13

37

38

39

40

41

42

43

20

18

44

5

14

19

9

ISL9504CRZQFN

OMIT

IMVP6 CPU VCore RegulatorSYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)

10575

B051-7270

CPUISENS_NEG

IMVP6_DROOPCPUISENS_POS

CPUVCORE_IOUT

=PP3V3R5V_S0_CPUISENS

IMVP6_VDIFF_RC

IMVP6_VO_R

CPU_VCCSENSE_P

CPU_VCCSENSE_N

CPUISENS_NEG_RC

=PPVIN_S0_IMVP6

=PP3V3_S0_IMVP6

IMVP6_NTC_R

=PPVOUT_S0_IMVP6_REG

=PPVIN_S0_IMVP6

IMVP6_COMP_RC

IMVP_DPRSLPVR

IMVP6_SOFT

IMVP6_VDIFF

CPU_DPRSTP_L

IMVP6_BOOT2

IMVP6_BOOT1


IMVP6_PHASE1

MIN_LINE_WIDTH=0.5 mmIMVP6_UGATE1 MIN_NECK_WIDTH=0.25 mm

IMVP6_LGATE1MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mm

IMVP6_ISEN1


IMVP6_UGATE2


IMVP6_PHASE2

MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mmIMVP6_LGATE2

IMVP6_VID<2>

IMVP6_VID<3>

IMVP6_VID<1>

IMVP6_VID<0>

IMVP6_ISEN2

IMVP6_VSUM

IMVP6_OCSET

IMVP6_VO

IMVP6_DROOP

IMVP6_DFB

IMVP6_VSEN_P

IMVP6_VSEN_N

CPU_PSI_L

IMVP_PWRGD_IN

VR_PWRGD_CK410_L

VR_PWRGOOD_DELAY

IMVP_VR_ON

IMVP6_NTC

IMVP6_VR_TT

IMVP6_RBIAS

IMVP6_FB2

IMVP6_FB

IMVP6_COMP

IMVP6_VW

PM_DPRSLPVRIMVP6_VID<6>

VOLTAGE=3.3VMIN_NECK_WIDTH=0.25 mm

PP3V3_S0_IMVP6_RMIN_LINE_WIDTH=0.25 mm

IMVP6_VID<5>

GND_IMVP6_SGND

IMVP6_VID<4>

=PP5V_S0_IMVP6

PP5V_S0_IMVP6_VDDMIN_LINE_WIDTH=0.25 mm


PPVIN_S0_IMVP6_R

VOLTAGE=12V


84B6

84B6

65C1

65C1

59C6

65A3

5C7

8B6

8B6

59D4

65B3

65D3

59D7

5C7

84C6

5C7

9C1

9C1

9C1

9C1

5C7

59A2

5C7

84B6

84B6

5D7

5C7

5D7

9C1

9C1

9C1

65A1

NC4

NC3

NC2

NC1

EXTVCC

FCB

INTVCC

PGOOD

3_3VOUT

RUN_SS2

ITH2

RUN_SS1

ITH1

SW1

TG1

BOOST1

BG1

PLLIN

SENSE1+

SENSE1-

VOSENSE1

BOOST2

TG2

BG2

SW2

PLLFLTR

SENSE2+

VOSENSE2

SENSE2-

THRML_PAD

SGND

PGND

VIN

D

S

G

D

S

G

D

S

G

R1-

R1+ R2

V-

V+

+

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

PLACE C7675 NEAR U7670 PIN 7

Placement Note:

5V S3 FET

5V S0 FET

Vout = 0.8V * (1 + Ra / Rb)

NC

NC

NC

<Rb>

(L7660 & Q7660 limit)

8A max output

Vout = 1.49V

<Rb>

<Ra>

NC

NC

NC

<Ra>

NOTE: Be aware of pull-ups to VIN on these signals.

If unconnected, powers up with VIN.

Connect to RUNSS pins to control outputs.

Ra changed to increase Vout

to 5.192V for improved

ODD power delivery.

Vout = 5.192V

11.5A max output

(Q7621 limit)

D76241

2

SOD-323

CMDSH-3

CRITICAL

C7605 1

26.3V10%

402CERM

1uF

C76071

2 CERM402

10%16V

0.01uF

R76301

2

1M

402

5%1/16WMF-LF

C76301

210V

402

0.1uF20%

CERM

C7625 1

2

402

10%50V

470pF

CERM

C76261

2 CERM

47pF5%50V

402

R76001

2

MF-LF1/16W

402

105%

C76001

216V

1uF

603X5R

10%

U7600

7

18

17

21

4

20

5 8

10

16

29

32

19

27

2

28 13

30 12

11

6

15

26 14

33

1 9

CRITICAL

QFNLTC3728LXC

D76641

2

SOD-323

CMDSH-3

CRITICAL

C7670 1

2

0.1uF

CERM402

20%10V

C76651

2

402

50VCERM

10%470pF

C7666 1

250V5%

402CERM

100pF

R76651

2

1/16W5%

402MF-LF

10K

C76621

2

10%

402

0.001uF

50VCERM

C76281

2

10%1000pF

X7R25V

402

NO STUFFR76281

2

1%

402MF-LF1/16W

10K

L7660

1 2

CRITICAL

2.2uH-14A

IHLP2525CZ-SM

R76681

2

39.2K

MF-LF1/16W1%

402

C7668 1

2

1000pF

X7R402

10%25V

NO STUFF

R76671

2 402MF-LF

1%1/16W

34.0KC7667 1

2

470pF

CERM402

10%50V

R76701

2

1M

402

5%1/16WMF-LF

C76021

2 CERM

1uF10%6.3V

402

C7601 1

2CERM

20%6.3V

603

4.7uFR76031

2

5%30K

402MF-LF1/16W

R76041

2

1/16W5%

402MF-LF

10KC76041

2

0.01uF

16V10%

402CERM

C76411

2

603X5R16V

1uF10%

R76641

2

5%0

1/16W

402MF-LF

R76241

2

1/16W5%

402

0

MF-LF

C7661 1

225V

1000pF

402X7R

10%

NO STUFF

C7664 1

2

0.1uF20%

CERM402

10V

C76901

2

OMIT

22UF20%6.3VCERM805

C7691 1

2

OMIT

22UF20%6.3VCERM805

C76241

2

402CERM10V20%0.1uF

C76211

2

10%25VX7R402

1000pF

NO STUFF

C7622 1

2

0.001uF

402

50VCERM

10%

C7652 1

2

CASE-C3

150UF20%

CRITICAL

POLY6.3V

C7650 1

2

OMIT

805CERM6.3V

22UF20%

C76511

2

20%22UF

CERM

OMIT

6.3V

805

R76061

2

0

MF-LF402

5%1/16W

P5VP1V5_SKIP

R76071

2

1/16W5%

402MF-LF

0

P5VP1V5_CONT

XW7600

1 2

SM

C7620 1

2

0.1uF10%

402X5R16V

C76231

2

402X5R16V10%0.1uF

R76231

2

4.02K

1/16WMF-LF

1%

402

C76601

2

0.1uF

402X5R16V10%

R76601

2

3.65K

MF-LF1/16W

402

1%

C7663 1

2

0.1uF10%16VX5R402

R76631

2

1/16WMF-LF402

9091%

C76921

2 2.5V

CASE-D2E-LF

330UF

CRITICAL

POLY

20%

Q7661

5 6 7 8

4

1 2 3

CRITICAL

SO-8

IRF7832Z

R76691

2

1.21K1%

402

1/16WMF-LF

R76291

2

23.7K

402

1/16WMF-LF

1%

C76171

2

OMIT

22UF

805CERM6.3V20%

C7616 1

2

OMIT

22UF

805CERM6.3V20%

C76151

210%50VCERM402

0.0022uF

R76151 2

402MF-LF1/16W5%

100K

Q7610

1

2

5

6

3

4

CRITICAL

SM-LFFDC638P

C7610

1 2

50V10%

CERM402

0.0022uFR76101 2100K

402

5%1/16WMF-LF

Q7621

5

4

123

FDM6296MICROFET3X3

CRITICAL

Q7620

5

4

123

CRITICAL

FDM6296MICROFET3X3

Q7660

5

4

1 2 3

CRITICAL

FDM6296MICROFET3X3

C76401

2

CRITICAL

33uF20%16VPOLYCASED2E-SM

C7681 1

2

603X5R16V10%1uF

C7680 1

2

CRITICAL

16V20%

33uF

POLYCASED2E-SM

L7620

1 2

CRITICAL

2.0UH

SM-IHLP

Q7615

1 5 8

4

2 3 6 7

CRITICAL

TSSOPIRF7707PBF

R7671

1 2

101%1/16WMF-LF402

C7675 1

2X5R402

0.1UF

16V10%

C76741

2

402CERM50V10%0.001UF

U76703

2

6

1

8

5

4

7

CRITICAL

MSOPINA326EA-250

R76741

2MF-LF402

1/16W1%100K

C76711

2

OMIT

6.3VCERM

20%

805

22UFC76721

2

OMIT

CERM805

6.3V20%22UF

R7675

1 2

1206MF-LF1/4W1%0.002

R76721

2

2.0K1%1/16WMF-LF402

R76201

2

1/16WMF-LF402

1%4.53K

R76251

2 402

5%

MF-LF

33K

1/16W

C76271

250VCERM

5%47PF

402

R76271

2

1/16W

402MF-LF

1%54.9K

5V / 1.5V Power Supply

76 105

B051-7270


=PP5V_S5_REG

P5VS5_ITH_RC

P5VP1V5_FCB

GND_P5VP1V5_SGNDVOLTAGE=0VMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.25 mm P5VS5_SW

P5VS5_VOSNS

=PPVIN_S5_P5VP1V5


P5VS5_SNS_N

MIN_LINE_WIDTH=0.6 mmP5VS5_TGMIN_NECK_WIDTH=0.25 mm

PP5V_S5_P5VP1V5_INTVCC

MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.6 mmVOLTAGE=5V

=PP1V5_S0_NB1V5_SENSE NB1V5_ISENSE_VCC

NB1V5_ISENSE_R2

P1V5S0_NB_IOUT

MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.25 mmP1V5S0_SW

MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.25 mmP1V5S0_BG

P1V5S0_ITH_RC

PP5V_S5_P5VP1V5_INTVCC PP5V_S5_P5VP1V5_INTVCC

P5VP1V5_FSEL

MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.6 mmP5VS5_BOOST_RC P1V5S0_BOOST_RC


=PP1V5_S0_REG

=PP5V_S0_P5VS0

=P5VS0_EN_L

=PP5V_S3_P5VS3 =PP5V_S3_FET

P5VS3_EN_L_RC=P5VS3_EN_L

=PP3V3_S0_NB1V5ISENS

P1V5S0_SNS_R_N


P1V5S0_VOSNS

P1V5S0_SNS_R_P


P5VP1V5_FSEL

P1V5S0_TGMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.25 mmP1V5S0_BOOST

P5VS5_BGMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.25 mm

MIN_NECK_WIDTH=0.25 mm P5VS5_BOOSTMIN_LINE_WIDTH=0.6 mm

PPVIN_S5_P5VP1V5_R



P5VS5_ITH

P5VS5_RUNSS

P1V5S0_ITH

P1V5S0_RUNSS

=P5VP1V5_PGOOD

=PP5V_S5_P5VP1V5_VCC

=PP1V5_S0_NB

=PP5V_S0_FET

NB1V5_ISENSE_R1_P

NB1V5_ISENSE_R1_N

P5VS5_SNS_P


P5VS0_EN_L_RC

65C8

60D6

60D3 60D6

65C8

65C6

65B3

65C1

60D3

65C6

53B5

60B3 60B3

60C4

5A2

65B1

64C6

65B1 65B3

64B6

65A3

60B3

64C2

65B1

19D7

65B3

SW

SGND PGND PADTHERM

SVIN PVIN

PGOOD

VFB

ITHSYNC/MODE

RUN/SSRT

THRM_PAD

PVINAVIN

PGMODE

OVT FB

AGND PGND

SWEN

D

S

G

D

S

G

D

S

G

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

1.5A max output

(U7700 limit)

Vout = 2.50V

1.2V S3 Regulator

2.5A max output

(Switcher limit)

Vout = 1.205V

2.5V S0 FET

Vout = 0.6V * (1 + Ra / Rb)

<Ra>

<Rb>

<Rc>

Vout = 0.8V * (1 + Ra / (Rb + Rc))

If unconnected, powers up with PVIN.

Connect RUNSS off-page to control

NOTE: Be aware of pull-up on this signal.

Burst

Continuous

2.5V S3 Regulator

<Ra>

<Rb>

2.5V D3Cold FET

1.2V D3Cold FET

L7700

1 2

CRITICAL

2.2uH-1.9A-23M-OHM

SM-MSS5131

C7706 1

2

10pF

50V

402CERM

5% R77071

2

1/16W1%634K

MF-LF402

R77081

2

MF-LF402

1%1/16W

200K

C77011

2

402

10%

X5R16V

0.1uF

R77001 2

1/16W5%

402MF-LF

1

C77561

2

OMIT

CERM6.3V20%

805

22UF

C7755 1

2

OMIT

6.3V20%

805CERM

22UF

C77521

2

OMIT

6.3V20%

805CERM

22UFC7751 1

2

OMIT

20%6.3VCERM

22UF

805

C77501

2

22pF

CERM402

5%50V

R77501

2

47.0K

MF-LF402

1%1/16W

R77511

2

61.9K

1/16W1%

402MF-LF

L7750

1 2

1.0UH-3.48A

CRITICAL

SM-LF

R77521

2

30.9K

1/16W1%

402MF-LF

U7750

3

12

13

2

9 16

5

7

8

110

11

14

15

6

17

4

LTC3412TSSOP-LF

CRITICAL

XW7750

1 2

SM

R77541

2

1/16W1%

402MF-LF

309KC7757 1

2

10%

402CERM

470pF

50V

R77551

2

NO STUFF

0

MF-LF402

5%1/16W

R77571

2

MF-LF402

5%1/16W

1M

R77561

2

1/16W5%

402MF-LF

0

C7754 1

2

22pF

50V5%

402CERM

R77531

2

8.25K

1/16W1%

402MF-LF

C77531

2

0.0022uF

50V10%

402CERM

C7720 1

2

402CERM

10%0.0022uF

50V

R77201 2100K

MF-LF1/16W5%

402

C7770 1

2CERM402

50V10%

0.0022uF

R77701 2

402MF-LF1/16W5%

100K

C7700 1

2

OMIT

6.3V20%

805CERM

22uF

U7700

39

6

4

7

5

8

210

1

11

CRITICAL

BQATPS62510

Q7720

1

2

5

6 3

4

SOT23FDC637AN

Q7721

1

2

5

6 3

4

SOT23FDC637AN

C7721 1

250V

0.0022uF10%

CERM402

R77211 2

MF-LF1/16W5%

402

160K

C77591

2

OMIT

22UF

805

20%6.3VCERM

C7758 1

2

OMIT

22UF

CERM805

20%6.3V

Q77701

2

5

6 3

4

CRITICAL

FDC637ANSOT23

C77101

2

OMIT

805CERM

22UF20%6.3V

C77111

2

OMIT

805CERM

22UF20%6.3V

C77221

210%

402

0.01UF

50VX7R

C77091

2

OMIT

805CERM

22UF20%6.3V

10577

051-7270 B

2.5V & 1.2V RegulatorsSYNC_MASTER=M59_MG SYNC_DATE=05/07/2006

=PP2V5_S3_REG

P2V5S3_VFB

P1V2D3C_EN_RC

=PP1V2_D3C_FET=PP1V2_S0_P1V2S0

=P2V5S3_EN


P2V5S3_SW

=PPVIN_S3_P1V2S3

P1V2S3_RT

P1V2S3_VFB_DIV

P1V2S3_ITH_RC

P1V2S3_RUNSS

P1V2S3_MODE

P1V2S3_ITH

GND_P1V2S3_SGNDVOLTAGE=0VMIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mm

=P1V2D3C_EN

=P1V2S3_PGOOD

P1V2S3_SWMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.25 mm

P1V2S3_VFB

=P2V5S3_PGOOD

=P2V5S0_EN

=PP2V5_S0_P2V5S0

P2V5S0_EN_RC

=PP2V5_S0_FET

=PP2V5_S0_P2V5S0

=P2V5D3C_EN

=PP1V2_S3_REG

PPVIN_S3_P2V5S3_SVIN

MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mmVOLTAGE=3.3V

=PP2V5_D3C_FET

P2V5D3C_EN_RC

=PPVIN_S3_P2V5S3

41C4

65A6

65A6

65B8

65C8 65D6

41C3

65C3

5D7

5D7

64D5

64B8

64B8

64D5

61C3 65A8

61D3

64D5

65D8

41C3

65A8

65C3

G

SD

V5FILT

PGNDGNDTHRM_PAD

VBST

EN_PSV

TON

DRVH

DRVL

TRIP

VFB PGOOD

VOUT

LL

V5DRV

SYM (1 OF 2)

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

Vout = 1.825V

1.8V D3Cold FET

<Ra>

(P1V8S3_FB)

<Rb>

18A max output

(L7820 limit)

Vout = 0.75V * (1 + Ra / Rb)

C7842 1

2POLY

CASE-D2E-LF

20%330UF

2.5V

R78211

2

1/16W

402

1%

MF-LF

21.5K

R78221

2

1/16W

402MF-LF

15K5%

C7802 1

2X5R16V

603

10%1uF

C78411

2

805

6.3VCERM

22UF20%

OMIT

C78431

2POLY

20%

CASE-D2E-LF

330UF

2.5V

C78471

2

20%

CERM805

6.3V

22UF

OMIT

C7846 1

2CERM

22UF

805

6.3V20%

OMIT

C78451

225V

0.0047UF10%

CERM402

R78451 2150K

402MF-LF1/16W5%

C7820 1

2

5%47PF

402CERM50V

R78461

2402

MF-LF1/16W

5%470K

Q7845

5

4

1

2

3

FDM6296MICROFET3X3

CRITICAL

C78311

2 X5R16V

603

10%1uF

C78301

2

CASED2E-SMPOLY16V20%33uF

C78321

2

1uF10%

603

16VX5R

Q7820

5

4

1 2 3

CRITICAL

LFPAKRJK0305DPB

Q7822

5

4

1 2 3

CRITICAL

RJK0303DPBLFPAK

Q7821

5

4

1 2 3

RJK0303DPBLFPAK

CRITICAL

L7820

1 2

1.2UH

FDA1055

CRITICAL

C7801 1

26.3V

603

4.7UF

CERM

20%

R78011 2

10

MF-LF402

1%1/16W

C7803 1

2402

10%16V

0.1UF

X5R

R78041

2MF-LF402

1/16W1%12.1K

R78031

2

1%1/16W

402MF-LF

182K

C7800 1

26.3V10%

CERM

1UF

402

U7800 13

9

1

7

12

8

6

15

2

11

10

4

14

5

3CRITICAL

QFNTPS51117RGY_QFN14

SYNC_DATE=05/07/2006SYNC_MASTER=M59_MG

1.8V Supply

051-7270

78 105

B

=P1V8S3_PGOOD

P1V8S3_TRIP

P1V8S3_FB

=PP5V_S3_P1V8S3



P1V8S3_V5FILT

=P1V8S3_EN

P1V8S3_TON

P1V8S3_VBST


P1V8S3_DRVL


P1V8S3_DRVHMIN_LINE_WIDTH=0.6 mm

=PPVIN_S3_P1V8S3

=PPBUS_S0_P1V8S0

=PP1V8_D3C_FET

P1V8D3C_EN_RC

=PP1V8_S0_P1V8S0

=P1V8D3C_EN

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.6 mmP1V8S3_LL


=PP1V8_S3_REG 65B8

64C2

65B1

64A6

65C1

65C1

65B8

65B6

64D5

5A2

PGND

PHASE

UG

LG

PVCC

FCCM

EN

PGOOD

COMP

FSET

ISEN

FB

VO

BOOT

VIN

THRMLPAD

VCC

OUT

D

S

G

D

S

G

D

S

G

V-

V++

-

PGND

PHASE

UG

LG

PVCC

FCCM

EN

PGOOD

COMP

FSET

ISEN

FB

VO

BOOT

VIN

THRMLPAD

VCC

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

(L7970 limit)

4.5A max output

3.3V S3 FET

Vout = 3.32V

<Rb>

<Ra>

(L7920 limit)

10A max output

Vout = 1.05V<Ra>

(P1V05S0_FB)

<Rb>

Vout = 0.6V * (1 + Ra / Rb)

Vout = 0.6V * (1 + Ra / Rb)

3.3V S5 Regulator

1.05V S0 Regulator

1.05V Current Sense

3.3V S0 FET

3.3V D3Cold FET

close to inductor

Placement Note:Keep C7990, C7991,

R7990, R7994 and R7997C7951 1

2

603X5R

10%1uF

16V

U7950

13

5

4

6

3

7

9

11

10

16

15

12

17

14

2

1

8

ISL6269BCRZ

CRITICAL

QFN

C7957 1

250V5%

402CERM

15PF

C7958 1

2CERM402

20%16V

0.01uF

R79581

2

MF-LF402

1%1/16W

30.9K

R79541

2

1/16W5%

MF-LF

0

NO STUFF

402

R79551

2

0

MF-LF402

5%1/16W

R79561

2

57.6K1%

402MF-LF1/16W

C7956 1

216V10%

402CERM

0.01UFQ7971

5 6 7 8

4

1 2 3

IRF7832Z

CRITICAL

SO-8

C79891

2

CASE-D2E-LFPOLY

20%330UF

2.5V

C7998

12

470pF

402

50VCERM

10%

C79951

2 CERM

1uF

402

10%6.3V

R79981 2

402MF-LF1/16W

1M

1%

C7992

12

50V

470pF

402CERM

10%

R79921 2

402MF-LF1/16W

1M

1%

R7997

1

2

CRITICAL

0603-LF

10KOHM-5%

R79961

2402

MF-LF1/16W

1K1%

R79931 2

1%

20.0K

402

1/16WMF-LF

C7990

12

10%

CERM-X5R

0.47UF

6.3V

402

R79911 2

MF-LF

1%1/16W

20.0K

402

R79941 2

1%

1K

MF-LF

NO STUFF

402

1/16W

R79901

2

1%1/16W

402MF-LF

649

53B3

R79491 2

0

402

5%1/16WMF-LF

C79491

2

20%16V

0.01uF

402CERM

NO STUFF

C79201

2

402

10%25VCERM

0.0047uF

R792012

0

1/16WMF-LF402

5%

C7947

1 2

CERM25V

0.0047uF

10%

402

Q7947

1

2

5

6

3

4

FDC638PSM-LF

R79471 2

1/16W

100K

5%

MF-LF402

C7945

1 2

0.0022uF

402CERM50V10%

Q7945

1

2

5

6

3

4

SM-LFFDC638P

R79451 2

402MF-LF1/16W5%

100KR79091

2

MF-LF402

1/16W5%0

C79091

26.3V20%

X5R402

0.22uF

C79591

2

0.22uF

402X5R6.3V20%

C7970 1

2

402CERM

10%0.0022uF

50V

NO STUFF

R79701

2 402MF-LF1/16W

05%

NO STUFF

Q7920

5

4

1 2 3

MICROFET3X3

CRITICAL

FDM6296

Q7921

5

4

1 2 3

MICROFET3X3

FDM6296

CRITICAL

Q7970

5

4

1 2 3

FDM6296MICROFET3X3

CRITICAL

C7980 1

2

CRITICAL

33uF

CASED2E-SMPOLY16V20%

R79101 2

1/16W1%

402

5.62K

MF-LF

Q7948

1

2

5

6

3

4

SM-LFFDC638P

R79481 2

402MF-LF1/16W5%

150K

C79481

210%25VCERM

0.0047uF

402

L7970

1 2

1.8UH

SM-IHLP

CRITICAL

C79301

2

CRITICAL

33UF20%16VPOLYCASED2E-SM

C7991

12

402

6.3V

0.22UF

CERM-X5R

10%

U79951

3

4

2

5

CRITICAL

SC70-5HPA00141AIDCKR

R79591

2

4.7

402MF-LF1/16W

5%

C79421

2

150UF

CASE-C3POLY

20%6.3V

C7902 1

2

603CERM1

20%6.3V

2.2UF

C7921 1

2

1000pF

402X7R25V10%

NO STUFF

XW7900

1 2

SM

C7900 1

26.3V

2.2UF

CERM1603

20%

C7901 1

2

1uF

16VX5R603

10%

U7900

13

5

4

6

3

7

9

11

10

16

15

12

17

14

2

1

8

QFN

CRITICAL

ISL6269BCRZ

C7907 1

2

10%470pF

CERM402

50V

C7908 1

2

0.022uF

CERM-X5R

10%16V

402

R79041

2

MF-LF

5%0

402

1/16W

NO STUFF

R79081

2

51.1K

402MF-LF1/16W1%

R79051

2

5%

402MF-LF

0

1/16W

R79061

2

MF-LF

1%

402

57.6K

1/16W

C7906 1

2

0.01UF

CERM402

10%16V

C7941 1

2

22UF

805

6.3VCERM

20%

OMIT

C79401

2

805

22UF20%6.3VCERM

OMITR79211

2

1/16W

402MF-LF

3.32K0.1%

R79221

2

732

402

0.1%

MF-LF1/16W

L7920

1 2

IHLP

CRITICAL

4.7uH

C7952 1

2

2.2UF

CERM1603

20%6.3V

C7986 1

2

20%22UF

CERM6.3V

805

OMIT

C79851

2

805

22UF20%6.3VCERM

OMITR79711

2

1/16W1%

402MF-LF

3.32K

R79721

2

1/16W1%

MF-LF

4.42K

402

R79601 2

402MF-LF

1%1/16W

2.8K

C7971 1

2

NO STUFF

1000pF

402X7R25V10%

XW7950

1 2

SM

C7950 1

2

2.2UF

CERM1603

20%6.3V

051-7270

79 105

B

SYNC_DATE=05/07/2006

3.3V / 1.05V Power Supplies

SYNC_MASTER=M59_MG


SWITCH_NODE=TRUE

P1V05S0_PHASE

P1V05S0_UGMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.25 mm

P1V05S0_LGMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.25 mm

=PP5V_S0_P1V05S0

P1V05S0_FCCM

=P1V05S0_EN

=P1V05S0_PGOOD

P1V05S0_COMP

P1V05S0_FSET

P1V05S0_ISEN

P1V05S0_FB

=PP1V05_S0_REG

MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.25 mmP1V05S0_BOOT

=PPVIN_S0_P1V05S0

P3V3S5_EN_RC

P1V05S0_BOOT_R


P1V05ISENS_NEG

P1V05ISENS_POS

P1V05S0_IOUT

=PP3V3R5V_S0_P1V05ISENS

P1V05ISENS_RC

=PP3V3_S0_P3V3S0

=PP3V3_S0_P3V3S0

=P3V3D3C_EN_L

=PP3V3_D3C_FET

=PP3V3_S0_FET

=P3V3S0_EN_L

=PP5V_S5_P3V3S5

=P3V3S5_PGOOD

P3V3S5_FB

GND_P3V3S5_SGND

P3V3S5_COMP

P3V3S5_FSET

P1V05S0_FB_RC

GND_P1V05S0_SGND

P1V05S0_COMP_R

P3V3S5_FB_RC

=P3V3S5_EN

=P3V3S3_EN_L P3V3S3_EN_L_RC

=PP3V3_S3_FET

=PP3V3_S3_P3V3S3

P1V05ISENS_NTC

P3V3S5_BOOT


P3V3S5_FCCM

P3V3S5_COMP_R

P3V3S5_BOOT_RMIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mm

P3V3S5_ISEN


P3V3S5_PHASE

SWITCH_NODE=TRUE


P3V3S5_LG


P3V3S5_UGMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.25 mm

=PPVIN_S5_P3V3S5

P3V3D3C_EN_L_RC

=PP3V3_S5_REG

P3V3S0_EN_L_RC

65D8

5D7

5D7

53A4

65C3

65C3

5D7

5D7

5B7

5B7

5B7

65B1

64C6

64B5

5C7

5B7

5B7

5B7

5B2

5C7

65C1

5C7

65A3

63D8

63C8

64D5

65A5

65B5

64D5

65B1

50A5

5B7

5B7

5B7

5B7

5C7

5B7

64A6

64B6

65C5

65C3

5B7

5B7

5B7

5B7

5B7

5B7

65C1

65D5

FB

BIAS

SWSHDN*

NC

VIN BOOST

GND

G

D

S

G

D

S

G

D

S

V3

V4 RST*

V2

V1

GND

V-

V+

OUT

IN

G

D

S

G

D

S

OUT

G

D

S

G

D

S

G

D

S

G

D

S

G

D

S

G

D

S

IN

IN

IN

IN

IN

IN

IN

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

to test for 2v5 and 1v2 S3 valid for GPUVCORE_EN.

But was disconnected for C8053 placement.

This signal was used as an option previously

GPIO38 low.

The SB can turn off the GPUVcore (and by

extension all D3Cold rails) by driving

1.5V / 1.05V PWRGD Circuit

Does not include D3C rails for GPU!!

deassert while GPU

GPU requires 1.2V, 1.8V, 2.5V and

3.3V rise after VCore is up.

1.5V Enable has pull-up to PBUS

1.8V Enable has pull-up to PBUS

Need to ensure that

ISL6269 PGOOD does not

2.5V S3 and 1.2V S3 supplies are controlled

Supply needs to guarantee 3.31V delivered to SMC VRef generator

State

Soft-Off (S5)

Sleep (S3)

Run (S0)

Battery Off (G3Hot) 0

1

1

1

SMC_PM_G2_ENABLE

0

0

1

1

PM_SLP_S4_L

0

0

0

1

PM_SLP_S3_L

(Switcher limit)

200mA max output

Vout = 3.425

<Rb>

NC

Vout = 1.25V * (1 + Ra / Rb)

by ethernet power control circuit.

(P5VS5_PGOOD)

(PM_SLP_S4_L)

PowerPlay is changing

GPU core voltage.

Unused PGOOD Signals

<Ra>

3.425V "G3Hot" Supply

LTC2903 guaranteed threshold is 93.5% (3.055V, 4.725V, 2.325V, 0.840V)

NOTE: R8065 acts as 10K pull-up for PGOOD signal

1.5V Comp threshold set to 1.32V (88%)

0.89V Reference

Reports when 1.5V S0 and 1.05V S0 are in regulation

5V Enable has pull-up to PBUS

Other S0 Rails PWRGD Circuit

ISL6269 undervoltage threshold 81-87% (0.85 - 0.91V)

(PM_SLP_S3_L)

Power Control Signals


U8000

7

6

8

4

2

1 5

3

CRITICAL

TSOT23-8

LT3470

Q8056

3

5

4

2N7002DW-X-FSOT-363

C8000 1

225V10%

X5R

10UF

1206-1

R80691

2

1/16W5%

402MF-LF

10KR80681

2

1/16W5%

402MF-LF

10K

Q8058

3

5

4

SOT-3632N7002DW-X-F

Q8058

6

2

1

2N7002DW-X-FSOT-363

U8070

2

6

1

3

4

5

CRITICAL

TSOT-23LTC2903

C8070 1

2

402CERM10V20%

0.1uF

C80151

26.3V20%

805CERM

22UF

OMIT

R80111

2

200K

MF-LF

1%1/16W

402

R80651

2

10K5%1/16WMF-LF402

C80811

210V20%

402CERM

0.1uF

U8081

3

2

1

4

5

SC70MC74VHC1G08

R80811

2402

10K5%

MF-LF1/16W

C8060 1

210V20%

402CERM

0.1uF

R80761

2

1/16W

402MF-LF

10K5%

R80701

2

MF-LF402

1%1/16W

845K

C80711

2 CERM

0.1UF20%10V

402

R80711

2

100K

MF-LF402

1%1/16W

R80721

2

1/16W1%

402MF-LF

365K

C80731

2 CERM

0.1UF20%10V

402

R80731

2

100K

MF-LF402

1%1/16W

C80751

2402

10V20%0.1UF

CERM

R80741

2

68.1K

1/16W1%

402MF-LF

R80751

2

1/16W1%

402MF-LF

100K

C8053 1

2

0.047UF10%16V

CERM402

U80604

3

1

5

2

LMC7211SM-LF

U8080

3

2

1

4

5

SC70MC74VHC1G08

C8080 1

2

402CERM10V20%

0.1UF

59C7

R80631

2

1/16W1%

402MF-LF

4.99KR80611

2

1/16W1%

402MF-LF

27.4K

R80641

2

1/16W1%

402MF-LF

10KR80621

2

1/16W

402MF-LF

10K1%

63B8

R80511

2

5%

402MF-LF1/16W

10KR80501

2

10K

1/16W5%

402MF-LF

Q8057

6

2

1

SOT-3632N7002DW-X-F

Q8050

6

2

1

2N7002DW-X-FSOT-363

49D7 26A5

R80541

2

1/16W5%

402MF-LF

100K

Q8057

3

5

4

SOT-3632N7002DW-X-F

R80101

2

348K

MF-LF402

1%1/16W

R80551

2

5%

402MF-LF

10K

1/16W

Q8055

6

2

1

SOT-3632N7002DW-X-F

Q8055

3

5

4

2N7002DW-X-FSOT-363

L8010

1 2

CRITICAL

33uH

CDPH4D19F-SM

Q8059

3

5

4

2N7002DW-X-FSOT-363

R80591

2

470K

MF-LF402

5%1/16W

Q8059

6

2

1

2N7002DW-X-FSOT-363

Q8050

3

5

4

2N7002DW-X-FSOT-363

68C8

C8010 1

2

22pF

CERM402

5%50V

R80561

2402

1/16WMF-LF

5%100K

49C5 43B7 42A8 23C3

R80571

2

MF-LF

5%

402

1/16W

100K

49C5 41B6 23C3

R80581

2

1/16W5%

402MF-LF

100K

50A4

49D5

C8005 1

2

0.22uF

X5R402

20%6.3V

61B5

61C8 R80531

2

1/16W

402

10K5%

MF-LF

R80521

2

10K

MF-LF402

1/16W5%

3.3V G3Hot Supply & Power Control


10580

051-7270 B

SYNC_MASTER=M59_MG

=PP3V42_G3H_REG

P1V5S0_PGOOD

=PP3V3_S5_P1V5PG

P1V0_P1V5PG_REF

P1V5S0_COMP_POS

PP0V9_S0

S0PGOOD_0V9_DIV

S0PGOOD_2V5_DIV

PP2V5_S0

PP3V3_S0

S0PGOOD_5V_DIV

PP5V_S0

MAKE_BASE=TRUEPM_SLP_S3_LS5V

=PP3V3_S3_PWRCTL

PM_SLP_S3_LS5V_LMAKE_BASE=TRUE

=GPUVCORE_ENGPUVCORE_ENMAKE_BASE=TRUE

P5VS5_RUNSS

=P5VS0_EN_L

P1V5S0_RUNSS

LIO_P3V3S0_EN_L

=GPUVCORE_PGOOD

=PP3V42_G3H_PWRCTL

PGOOD_MUXED_S0_OR_S0D3C

=P5VP1V5_PGOOD

=PP3V3_S0_ALLSYSPG

=P2V5S3_PGOOD

PM_SLP_S4_L

MAKE_BASE=TRUE

=PP5V_S5_PWRCTL

=P1V2S3_PGOOD

=P1V8S3_PGOOD TP_P1V8S3_PGOODMAKE_BASE=TRUE

TP_P5V_P1V5_PGOODMAKE_BASE=TRUE

IMVP_PWRGD_IN

ALL_SYS_PWRGD

MAKE_BASE=TRUEP1V5P1V05S0_PGOOD

PP1V5_S0

SMC_PM_G2_EN

SMC_PM_G2_EN_L

=P3V3S5_EN

LIO_P3V3S3_EN

=RTUSB_EN

=P1V8S3_EN

=P5VS3_EN_L

=MEMVREF_EN

=P1V05S0_EN

PM_SLP_S4_LS5VMAKE_BASE=TRUE

=PP3V42_G3H_PWRCTL

P3V42G3H_FB

MIN_NECK_WIDTH=0.25 mmSWITCH_NODE=TRUE

P3V42G3H_SWMIN_LINE_WIDTH=0.5 mm

P3V42G3H5_BOOST

=PPVIN_G3H_P3V42G3H

=P3V3S3_EN_L

PM_SLP_S3

=P1V05S0_PGOOD

=P2V5D3C_EN

=P3V3D3C_EN_L

=P1V2D3C_EN

=P1V8D3C_ENMAKE_BASE=TRUEP1V8D3C_EN

=P3V3S0_EN_LMAKE_BASE=TRUEP3V3S0_EN_L

=P2V5S0_EN

MAKE_BASE=TRUEP5VS5_PGOOD

=PBUSVSENS_EN

=ENET_VMAIN_AVLBL

=PP5V_S5_PWRCTL

PM_SLP_S3_L

MAKE_BASE=TRUE=PP3V3_S0_PWRCTL

S0PGOOD_PWROK

TP_P2V5S3_P1V2S3_PGOODMAKE_BASE=TRUE

P1V2R2V5D3C_EN_LS5VMAKE_BASE=TRUE

P3V3D3C_EN_LMAKE_BASE=TRUE

MAKE_BASE=TRUESB_GPUVCORE_DISABLE_LTP_SB_GPIO38

PM_SLP_S3_L_GPUVCORE_EN

60C4

60C5

5D7

47B6

65D3

79D5

65B1

47B6

65D3

65B1

79D5

65D5

65C3

65D6

65A6

65C3

65B1

65C3

68C8

5D7

60B3

5B7

5C1

64A8

79A2

60B3

65A3

64D8

62B4

65C6

63D7

5C1

46C7

62C8

60A4

32B3

63B8

64C8

5D7

65A6

63D3

61C3

63C8

61B3

62A6

63D8

61D3

53C3

39C8

64B8

65A3

79A4

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

"S3AC" rail is ON in S3 on AC, OFF in S3 on battery


Power Aliases

105

B

81

051-7270


GNDMIN_LINE_WIDTH=0.5 mm

MAKE_BASE=TRUE


PP5V_S0

=PP1V5_S0_LIO

PPBUS_G3H



=PPBUS_S0_P1V8S0

=PPBUS_S0_PPBU_S0_FW

=PP5V_S0_FET

=PP5V_S0_ISENSECAL

=PP5V_S0_AUDIO_XW

=PP5V_S0_GPUBBCTL

=PP5V_S0_LPCPLUS

=PP5V_S0_KBDLED

=PP5V_S0_FAN_RT

=PP5V_S0_FAN_LT

=PP5V_S0_MEMVTT

=PP5V_S0_SB

=PP5V_S0_INVERTER

=PP5V_S0_HDD

=PP5V_S0_IMVP6

=PP5V_S0_IDE

=PP5V_S0_DVI_DDC

=PP5V_S3_TOPCASE

=PP5V_S3_IR

=PP5V_S3_FET

=PP5V_S5_REG

=PP5V_S3_CAMERA

=PP5V_S3_SYSLED

=PP5V_S0_P1V05S0

=PP5V_S3_RTUSB

=PP5V_S0_GPUVCORE

=PP5V_S0_P5VS0

=PP5V_S3_P5VS3

=PP5V_S3_P1V8S3

=PP5V_S5_PWRCTL

=PP5V_S5_P5VP1V5_VCC

=PP5V_S5_LIO

=PP5V_S5_SB

=PP5V_S5_P3V3S5

=PPBUS_S5_FW_FET

=PPFW_P3V3FWPHY

=PPFW_FW_CPS

=PPFW_PORT2_VP

=PPFW_PORT1_VP

VOLTAGE=5VMAKE_BASE=TRUE

PP5V_S3


VOLTAGE=33V

PPBUS_S5_FW_FETMIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.3 mm

MAKE_BASE=TRUE

PP3V3_D3CMIN_LINE_WIDTH=0.5 mm

MAKE_BASE=TRUE


=PP3V3_D3C_GPU


PP3V42_G3H

VOLTAGE=3.425VMAKE_BASE=TRUE


=PP3V42_G3H_SMCUSBMUX

=PP3V3_S5_SMC

=PP3V3_S5_LPCPLUS

=PP3V42_G3H_LIDSWITCH

=PP5V_S0_SB_HPD







=PP1V5_S0_SB

=PP1V5_S0_REG

=PP1V2_D3C_FET

=PP1V5_S0_CPU

=PP1V5_S0_NB1V5_SENSE

=PP1V2_S0_PCIE_GPU_VDDR

=PP1V2_S0_PCIE_GPU_PVDD

=PP1V2_S0_PCIE_GPU

=PP1V2_S0_GPU_VDDPLL

=PP1V2_S3_REG

=PP1V2_S0_P1V2S0

=PP1V2_S3_ENET

PP1V2_D3C




MAKE_BASE=TRUE


VOLTAGE=1.2V

PP1V2_S3

=PPVCORE_S0_GPU_REG

=PP2V5_D3C_FET

=PPVCORE_S0_GPU_BBP

=PPVCORE_S0_GPU

=PP2V5_S0_GPU_VDDC_CT

=PP2V5_S0_GPU_VDD25

=PP2V5_S0_GPU_PVDD

=PP2V5_S0_GPU

MAKE_BASE=TRUEVOLTAGE=1.2VMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.6 mmPPVCORE_D3C_GPU

PP2V5_D3C

VOLTAGE=0MAKE_BASE=TRUE


=PPDCIN_G3H_LIO =PPVIN_G3H_P3V42G3HMAKE_BASE=TRUEVOLTAGE=18.5V

PPDCIN_G3HMIN_LINE_WIDTH=0.4 mmMIN_NECK_WIDTH=0.2 mm

=PP1V05_S0_CPU

=PP1V05_S0_FSB_NB

=PP1V05_S0_NB_CRT


=PP1V05_S0_NB_VTT

=PP1V05_S0_REG

=PPVCORE_S0_NB

=PPVCORE_S0_SB

=PP0V9_S0_MEM_TERM=PP0V9_S0_MEMVTT_LDO

MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mmVOLTAGE=1.05V

PP1V05_S0

MAKE_BASE=TRUE


VOLTAGE=0.9V

PP0V9_S0

MAKE_BASE=TRUE

=PPVIN_S0_P1V05S0

=PPVIN_S0_GPUVCORE

=PP3V42_G3H_SB_RTC

=PP3V42_G3H_SMC_CLK

=PP3V42_G3H_LIO

=PPVOUT_S0_IMVP6_REG

=PPBUS_G3H_LIO_CONN

=PPVIN_S5_P5VP1V5

=PPVIN_S0_IMVP6

=PPVIN_S5_P3V3S5

=PPBUS_S5_FWPWRSW

=PPVCORE_S0_CPU

=PP3V42_G3H_SMCVREF

=PP3V42_G3H_SMC_PWRGD

=PP3V42_G3H_PWRCTL

=PP3V42_G3H_SMBUS_SMC_BSA


PPBB_S0_GPU

MAKE_BASE=TRUE


=PPVIN_S3_P1V8S3

=PPBUS_G3H_S3AC

=PP3V42_G3H_REG

=PPVOUT_S0_GPUBBP_LDO =PPBB_S0_GPU

=PNVOUT_S0_GPUBBN_REG =PNBB_S0_GPU

=PP3V3_S3AC_FET =PP3V3_S3_ENET


MAKE_BASE=TRUE

PNBB_S0_GPU

VOLTAGE=-0.7V

MIN_LINE_WIDTH=0.38 mmPP3V3_S3AC

MAKE_BASE=TRUE



PPVCORE_S0_CPUMIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.2 mm

=PPBUS_S0_INVERTER



MIN_LINE_WIDTH=0.6 mmPP2V5_S0




=PP2V5_S0_NB_DPLL

=PP2V5_S0_LVDS_MUX

=PP2V5_S0_FET



MAKE_BASE=TRUE

PP1V8_D3C

=PP1V8_S3_MEM

=PP1V8_S3_MEM_NB

=PP1V8_S3_MEMVREF

=PP1V8_S0_MEMVTT

=PP1V8_S3_FW

=PP1V8_S0_P1V8S0

=PP1V8R2V0_S0_FB_GPU

=PP1V8_S0_FB_VDD

=PP1V8_S0_FB_VDDQ

=PP2V5_S3_ENET

=PP2V5_S0_P2V5S0

=PP1V8_D3C_FET

=PP1V8_S3_REG

PP1V5_S0_NB

VOLTAGE=0


MAKE_BASE=TRUE=PP1V5_S0_NB

=PP1V5_S0_NB

=PP1V5_S0_NB_3G

=PP1V5_S0_NB_3GPLL

=PP1V5_S0_NB_PCIE

=PP1V5_S0_NB_PLL


=PP1V5_S0_NB_TVDAC

=PP1V5_S0_NB_VCCAUX


=PP1V5_S0_ITPMOUNT

VOLTAGE=0


MAKE_BASE=TRUE

PP1V5_S0


PP3V3_S5MIN_LINE_WIDTH=0.4 mmMIN_NECK_WIDTH=0.25 mm

=PP3V3_S5_SB_3V3_1V5_VCCSUSHDA

=PP3V3_S5_SB

=PP3V3_S5_SB_IO

=PP3V3_S5_SB_PM

=PP3V3_S5_SB_USB



=PP3V3_S5_REG

=PP3V3_S5_ROM

=PP3V3_S5_P1V5PG

=PP3V3_S3_P3V3S3

=PP3V3_S0_LCD

=PPVIN_S3_P2V5S3

=PP3V3_S0_P3V3S0

=PP3V3_S3_P3V3S3AC

=PP3V3_S3_RTALS

=PP3V3_S3_FET

=PP3V3_S3_TPM

=PP3V3_S3_SMBUS_SMC_A_S3

=PP3V3_S3_SMS

=PP3V3_S0_GPU

=PP3V3_S0_GPUBBP

=PP3V3_S0_GPUBBN

=PP3V3_S0_GPU_VDDR3

=PP3V3_D3C_GPU_GPIOS

=PP3V3_D3C_FET

=PP3V3_D3C_DDC_DVI

=PP1V8R3V3_S0_GPU_VDDR5


=PP3V3_D3C_VGASYNC

=PP3V3_D3C_GPU_LVDS_DDC

=PP3V3_S0_DDC_LCD

=PP3V3_S0_IDE

=PP3V3_S0_CK410

=PP3V3_S0_FET

=PP3V3_S0_INVERTER

=PP3V3_S0_IMVP6

=PP3V3_S0_NB

=PP3V3_S0_NB_VCC_HV

=PP3V3_S0_SB

=PP3V3_S0_SB_GPIO


=PP3V3_S0_SB_PCI

=PP3V3_S0_SB_PM

=PP3V3_S0_SB_VCC3_3




=PP3V3_S0_TPM

=PP3V3_S0_KBDLED

=PP3V3_S0_THRM_SNR

=PP3V3_S0_REMTHMSNS

=PP3V3_S0_SMBUS_SB

=PP3V3_S0_SMBUS_SMC_0_S0

=PP3V3_S0_SMBUS_SMC_B_S0

=PP3V3_S0_SMBUS_SMC_BSB

=PP3V3_S0_SMC_LS

=PP3V3_S0_RSTBUF

=PP3V3_S0_FAN_LT

=PP3V3_S0_ALLSYSPG

=PP3V3_S0_FAN_RT

=PP3V3R5V_S0_GPUISENS

=PP3V3R5V_S0_CPUISENS

=PPSPD_S0_MEM

=PP3V3R5V_S0_P1V05ISENS

=PP3V3_S0_EDET

=PP3V3_S0_NB1V5ISENS

=PP3V3_S0_LVDS_MUX

=PP3V3_S0_GPU_TDIODE

=PP3V3_S0_PWRCTL

MAKE_BASE=TRUEVOLTAGE=3.3VMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.38 mmPP3V3_S0

=PP3V3_S3_TOPCASE

=PP3V3_S3_LTALS

=PP3V3_S3_MEMVREF

=PP3V3_S3_FW

=PPVIN_S3_P1V2S3

=PP3V3_S3_PWRCTL

=PP3V3_S3_PCI

PP3V3_S3

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MMVOLTAGE=3.3V

MIN_LINE_WIDTH=0.5 MM

VOLTAGE=1.8V

PP1V8_S3

MAKE_BASE=TRUE



MAKE_BASE=TRUEVOLTAGE=5V

PP5V_S5


MAKE_BASE=TRUE

PP2V5_S3

VOLTAGE=2.5V


=PP2V5_S3_REG

11C5

34C8

11B3

34C6

39D8

29D6

50D7

9B7

34B8

19D7

53D7

39D6

29D3

70B8

25C8

20B4

50B1

74A7

8C7

19D7

19D2

53A6

39B8

29B2

70B5

73D8

73D8

19D7

23D8

25D2

34A8

20A4

23D5

49D4

69D8

7D5

12C2

25C4

19D7

63A2

19C8

9D7

39B5

19D7

19D7

28D6

19D7

70A8

73D5

73D5

65C6

65C8

19D7

19C4

23D4

26C5

25B6

33D8

19C7

19C7

23B3

25C6

29A6

79C6

37D7

47D6

53A8

51C4

56C7

45C3

64D8

47C6

49D3

51C4

25B6

25D6

25C6

25B2

25D6

25C2

25C8

60C1 9B7

39D7

53C7

47C6

7B6

12B7

19D7

24C3

19C8

53A4

16D3

25D3

47D6

66C4

59D7

8D7

64C8 39B4

19C5

19A6

19A4

79D3

28D3

16B6

70A5

72D8

72D8

61D3

62C1

60A7

60A7

19D7

19D7

19D7

19D7

19A5

19D6

17B6

19D7

23B7

23D1

25D2

24B3

63D8

58C2

57C6

74D2

33D3

14D6

19C6

25D8

21D3

25C4

26B8

25B8

25B4

25D3

25A4

58D4

79D5

29A3

79B3

78C5

37C3

64B5

5D1

53D3

62A6

42B8

60B1

5A2

47D3

68A6

5D2

55B5

56C4

5D2

31C5

25D8

76B8

78B5

59D7

36D6

77B5

78D3

78B5

60A2

60C8

5A4

50B8

63B7

46C7

68D7

60B2

60A4

62C8

64B8

60B6

5D1

25C8

63D6

43C1

42C8

38B7

44B3

44D3

79D7

71B2

46B5

49C2

5D2

78D3

77A1

24A5

24B5

24A5

24A3

24B5

24A3

25A8

5A2

61B1

8B7

60A8

67C7

67C7

67A1

74B8

61B3

61B3

39A8

79D7

68C1

61C1

68B7

53A5

74C6

74C6

74A8

75C8

79D7

5D1 64D5

7B5

12A7

19D6

21C1

17D3

5B2

16C8

24D3

30D5 31C2

64B5

63B7

68D7

26D6

35B7

5D1

59D1

5A1

60D7

59D4

63D6

43D7

8B5

50B7

50B5

64A8

27C3

62D7

41C6

64D2

68B5 69D6

68A2 69D2

41C4 39A5

5A2

76B7

64B5

17D6

17D6

17C6

19A8

79C5

61D1

79D7

28B2

14C2

32C6

31C5

37B2

62A6

69B8

72D5

72D5

39D3

61C3

62A4

5A2

19D7

19D7

19B5

19B5

13D2

19B8

17C6

19D2

16D1

17C6

11C4

64C5

24C3

23A7

22C6

11B5

22D8

24B3

24A5

63D1

54D4

64C5

63D2

76D5

61D8

63C8

41C5

55D4

63D1

50B1

27C5

50B1

68C4

68B8

68A4

74C6

71D6

63C7

77B2

74B7

74B7

77D5

79A7

76D3

36D6

33C7

63D6

76A8

59D8

14C7

17C6

22B5

21C3

24C3

26D1

26B6

24B5

24C3

24D3

24B3

58C7

55B6

10C5

52D4

27D8

27D5

27D3

27C3

50D3

26B4

56C7

64B1

56C4

68D2

59A5

28A6

63B3

40B6

60A6

79A4

52B5

64B6

64B5

78D3

5B2

32C5

37A7

61B7

64C6

37D5

50B5

61D4

OUT

IO

IO

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

Battery Connector (Digital Signals)

518S0369

NC

NC

Left I/O Power Connector

518S0458

J8200

1

2

3

4

5

6

CRITICAL

M-RT-SM87438-0663

J8250

5

6

1

2

3

4

CRITICAL

SM04B-ACHM-RT-SM

R82501

2

5%1/16WMF-LF402

10

PBus-In,Batt. & 3G Pwr Connectors


82 105

B051-7270

=PPBUS_G3H_LIO_CONN

GND_BATT

=SMBUS_BATT_SCL

SMC_BS_ALRT_L

=SMBUS_BATT_SDA

65C3

27C1

27C1

5A1

5D1

5D1

5D1

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

PCIE_PVSS

PCIE_VDDR_12

PCIE_PVDD_12

PCIE_VSS

(1.2V)

(1.2V)

PCIE_VSS

(2 OF 7)

PCI EXPRESS POWER & GROUND

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

PCIE_REFCLKP

PCIE_REFCLKN

PERST*

PERST*_MASK

PCIE_TEST

PCIE_RX15N

PCIE_RX14P

PCIE_RX13N

PCIE_RX12N

PCIE_RX12P

PCIE_RX1P

PCIE_TX0P

PCIE_TX0N

PCIE_TX1P

PCIE_TX2N

PCIE_TX1N

PCIE_TX2P

PCIE_TX3P

PCIE_TX3N

PCIE_TX4P

PCIE_TX4N

PCIE_TX5P

PCIE_TX5N

PCIE_TX6P

PCIE_TX6N

PCIE_TX7P

PCIE_TX7N

PCIE_TX8N

PCIE_TX8P

PCIE_TX9P

PCIE_TX10P

PCIE_TX9N

PCIE_TX10N

PCIE_TX11P

PCIE_TX11N

PCIE_TX12P

PCIE_TX12N

PCIE_TX13N

PCIE_TX13P

PCIE_TX14N

PCIE_TX14P

PCIE_TX15N

PCIE_TX15P

PCIE_CALRP

PCIE_CALRN

PCIE_CALI

PCIE_RX1N

PCIE_RX2N

PCIE_RX2P

PCIE_RX3P

PCIE_RX3N

PCIE_RX4P

PCIE_RX4N

PCIE_RX5P

PCIE_RX5N

PCIE_RX6N

PCIE_RX6P

PCIE_RX7N

PCIE_RX7P

PCIE_RX8P

PCIE_RX8N

PCIE_RX9P

PCIE_RX9N

PCIE_RX10P

PCIE_RX10N

PCIE_RX11P

PCIE_RX11N

PCIE_RX13P

PCIE_RX14N

PCIE_RX0N

PCIE_RX0P

PCIE_RX15P

PCI-EXPRESS BUS INTERFACE

(1 OF 7)

OUT

OUT

OUT

OUT

OUT

OUT

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

2000mA

NC

100mA

C8481 1 2

X5R 402

0.1uF

16V10%

C8482 1 2

402

0.1uF

X5R16V10%

C8479 1 20.1uF

40216V10% X5R

C8480 1 2

402

0.1uF

X5R16V10%

C8477 1 2

402

0.1uF

X5R16V10%

C8478 1 2

402X5R16V10%

0.1uF

C8475 1 2

402

0.1uF

X5R16V10%

C8476 1 2

402

0.1uF

X5R16V10%

C8473 1 2

402

0.1uF

X5R16V10%

C8474 1 2

402

0.1uF

X5R16V10%

C8420 1 2

40210% 16V X5R

0.1uF

C8471 1 2

402

0.1uF

X5R16V10%

C8472 1 2

402

0.1uF

X5R16V10%

C8469 1 2

402

0.1uF

X5R16V10%

C8470 1 2

402

0.1uF

X5R16V10%

C8467 1 2

402

0.1uF

X5R16V10%

C8421 1 2

10%

0.1uF

16V X5R 402

C8468 1 2

402

0.1uF

X5R16V10%

C8465 1 2

402

0.1uF

X5R16V10%

C8466 1 2

402

0.1uF

X5R16V10%

C8463 1 2

402

0.1uF

X5R16V10%

C8464 1 2

402

0.1uF

X5R16V10%

C8450 1 2

10% 16V X5R

0.1uF

402

C8461 1 2

402

0.1uF

X5R16V10%

C8462 1 20.1uF

402X5R16V10%

C8459 1 2

402

0.1uF

X5R16V10%

C8460 1 2

402

0.1uF

X5R16V10%

C8457 1 2

402

0.1uF

X5R16V10%

C8451 1 2

10% 16V X5R 402

0.1uF

C8458 1 20.1uF

402X5R16V10%

R84961

2

MF-LF1/16W

402

1%562

R84951

2

1%2.0K

MF-LF402

1/16W

R84971

2

1.47K1%

402MF-LF1/16W

U8400

N23

P23

U23

V23

W23

N25

N26

AM28

AM29

AM30

AM31

N27

N28

N29

AL29

AL30

AL31

AL32

AM27

N24

N30

R25

R26

R29

R31

T24

T26

T27

T29

U24

U26

P24

U28

U29

U30

V24

V25

V26

V29

V31

W24

W26

P25

W27

W29

Y24

Y26

Y28

Y29

Y30

AA23

AA25

AA26

P26

AA29

AA31

AB23

AB26

AB27

AB29

AC23

AC24

AC26

AC28

P28

AC29

AC30

AD25

AD26

AD29

AD31

AE26

AE27

AE29

AF26

P29

AF28

AF29

AF30

AG25

AG26

AG29

AG31

AH24

AH26

AH27

P30

AH29

AJ26

AJ28

AJ29

AJ30

AJ32

AK26

AK29

AK30

AK31

R23

AK32

AL27

R24

BGA

M56P

OMIT

C8402 1

2CERM

1uF

6.3V

402

10%

C8448 1 2

10% 16V X5R

0.1uF

402

C8401 1

2

402CERM

10%6.3V

1uF

C8407 1

2

10%6.3VCERM402

1uF

C8449 1 2

10% 16V X5R

0.1uF

402

C8413 1

2

10%6.3VCERM402

1uF

C8406 1

2

1uF

402CERM6.3V10%

C8411 1

2

1uF

402CERM6.3V10%

C8412 1

2

10%6.3VCERM402

1uF

C84001

2

20%

CERM805

6.3V

22UF

OMIT

C84101

2

22UF

6.3V

805CERM

20%

OMIT

C8446 1 2

10% 16V X5R

0.1uF

402

C84051

2

22UF

6.3V

805CERM

20%

OMIT

L8400

1

2

200-OHM-EMI0402

C8447 1 2

10% 16V X5R

0.1uF

402

C8444 1 2

10% 16V X5R

0.1uF

402

C8445 1 2

10% 16V X5R

0.1uF

402

C8442 1 2

10% 16V X5R

0.1uF

402

C8443 1 2

10% 16V X5R

0.1uF

402

C8440 1 2

10% 16V X5R

0.1uF

402

C8441 1 2

10% 16V X5R

0.1uF

402

C8438 1 2

10% 16V X5R

0.1uF

402

C8439 1 2

10% 16V X5R 402

0.1uF

C8436 1 2

10% 16V X5R

0.1uF

402

C8437 1 2

10% 16V X5R

0.1uF

402

C8434 1 2

10% 16V X5R

0.1uF

402

C8435 1 2

10% 16V X5R

0.1uF

402

C8432 1 2

10% 16V X5R

0.1uF

402

C8433 1 2

10% 16V X5R

0.1uF

402

C8430 1 2

10% 16V X5R

0.1uF

402

C8431 1 2

10% 16V X5R 402

0.1uF

C8428 1 2

10% 16V X5R

0.1uF

402

C8429 1 2

10% 16V X5R

0.1uF

402

C8426 1 2

10% 16V X5R

0.1uF

402

C8427 1 2

10% 16V X5R

0.1uF

402

C8424 1 2

16V X5R

0.1uF

40210%

C8425 1 2

10% 16V X5R

0.1uF

402

C8422 1 20.1uF

10% X5R 40216V

C8423 1 2

10% 16V X5R

0.1uF

402

C8455 1 2

10% 16V X5R

0.1uF

402

C8456 1 2

10% 16V X5R

0.1uF

402

U8400

AB24

AE24

AD24

AK28

AL28

AH31

AJ31

V30

W30

U32

V32

T31

U31

R30

T30

P32

R32

N31

P31

AG30

AH30

AF32

AG32

AE31

AF31

AD30

AE30

AC32

AD32

AB31

AC31

AA30

AB30

Y32

AA32

W31

Y31

AA24

AJ27

AK27

W25

Y25

V28

W28

U27

V27

T25

U25

R28

T28

P27

R27

AH25

AJ25

AG28

AH28

AF27

AG27

AE25

AF25

AD28

AE28

AC27

AD27

AB25

AC25

AA28

AB28

Y27

AA27

AG24

AF24

M56PBGA

OMIT

C8485 1 2

402

0.1uF

X5R16V10%

C8486 1 2

402

0.1uF

X5R16V10%

C8483 1 2

402

0.1uF

X5R16V10%

C8484 1 2

402

0.1uF

X5R16V10%

051-7270

SYNC_DATE=(MASTER)

B

10584

ATI M56 PCI-ESYNC_MASTER=(MASTER)

=PP1V2_S0_PCIE_GPU_PVDD

PP1V2_S0_PCIE_GPU_PVDD_F

VOLTAGE=1.2V


PEG_D2R_N<1>

PEG_D2R_N<12>

PEG_R2D_P<5>

PEG_R2D_C_P<9>

=PP1V2_S0_PCIE_GPU_VDDR

PEG_D2R_C_N<2>

PEG_R2D_N<4>

PEG_R2D_C_P<5>

PEG_R2D_C_N<13>

PEG_R2D_C_P<14>

PEG_R2D_C_N<14>

GPU_PCIE_CALRP

GPU_PCIE_CALI

PEG_R2D_N<0>

PEG_R2D_N<1>

PEG_R2D_N<2>

PEG_R2D_N<3>

PEG_R2D_N<6>

PEG_R2D_N<5>

PEG_R2D_N<9>

PEG_R2D_N<8>

PEG_R2D_N<7>

PEG_R2D_N<11>

PEG_R2D_N<10>

PEG_R2D_N<12>

PEG_R2D_N<13>

PEG_R2D_N<14>

PEG_R2D_N<15>

PEG_R2D_P<0>

PEG_R2D_P<1>

PEG_R2D_P<2>

PEG_R2D_P<3>

PEG_R2D_P<4>

PEG_R2D_P<6>

PEG_R2D_P<7>

PEG_R2D_P<8>

PEG_R2D_P<9>

PEG_R2D_P<10>

PEG_R2D_P<11>

PEG_R2D_P<12>

PEG_R2D_P<13>

PEG_R2D_P<14>

PEG_R2D_P<15>

PEG_R2D_C_N<0>

PEG_R2D_C_P<0>

PEG_R2D_C_N<1>

PEG_R2D_C_P<1>

PEG_R2D_C_P<2>

PEG_R2D_C_N<2>

PEG_R2D_C_P<3>

PEG_R2D_C_N<3>

PEG_R2D_C_P<4>

PEG_R2D_C_N<4>

PEG_R2D_C_P<6>

PEG_R2D_C_N<5>

PEG_R2D_C_N<6>

PEG_R2D_C_P<7>

PEG_R2D_C_N<7>

PEG_R2D_C_N<8>

PEG_R2D_C_P<8>

PEG_R2D_C_N<9>

PEG_R2D_C_P<10>

PEG_R2D_C_N<10>

PEG_R2D_C_P<11>

PEG_R2D_C_N<11>

PEG_R2D_C_P<12>

PEG_R2D_C_P<13>

PEG_R2D_C_N<12>

PEG_R2D_C_P<15>

PEG_CLK100M_GPU_P

PEG_RESET_L

PEG_CLK100M_GPU_N

PEG_R2D_C_N<15>

GPU_PCIE_CALRN

PEG_D2R_C_N<0>

PEG_D2R_C_N<1>

PEG_D2R_C_N<3>

PEG_D2R_C_N<4>

PEG_D2R_C_N<5>

PEG_D2R_C_N<6>

PEG_D2R_C_N<7>

PEG_D2R_C_N<8>

PEG_D2R_C_N<9>

PEG_D2R_C_N<10>

PEG_D2R_C_N<11>

PEG_D2R_C_N<12>

PEG_D2R_C_N<13>

PEG_D2R_C_N<14>

PEG_D2R_C_N<15>

PEG_D2R_P<0>

PEG_D2R_N<0>

PEG_D2R_P<1>

PEG_D2R_N<2>

PEG_D2R_P<2>

PEG_D2R_N<3>

PEG_D2R_P<3>

PEG_D2R_N<4>

PEG_D2R_P<4>

PEG_D2R_P<5>

PEG_D2R_P<6>

PEG_D2R_N<5>

PEG_D2R_N<6>

PEG_D2R_P<7>

PEG_D2R_N<7>

PEG_D2R_P<8>

PEG_D2R_N<8>

PEG_D2R_N<9>

PEG_D2R_P<9>

PEG_D2R_N<10>

PEG_D2R_P<10>

PEG_D2R_N<11>

PEG_D2R_P<11>

PEG_D2R_P<12>

PEG_D2R_P<13>

PEG_D2R_P<14>

PEG_D2R_N<13>

PEG_D2R_P<15>

PEG_D2R_N<14>

PEG_D2R_N<15>

PEG_D2R_C_P<0>

PEG_D2R_C_P<1>

PEG_D2R_C_P<2>

PEG_D2R_C_P<3>

PEG_D2R_C_P<4>

PEG_D2R_C_P<5>

PEG_D2R_C_P<6>

PEG_D2R_C_P<7>

PEG_D2R_C_P<8>

PEG_D2R_C_P<9>

PEG_D2R_C_P<10>

PEG_D2R_C_P<11>

PEG_D2R_C_P<12>

PEG_D2R_C_P<13>

PEG_D2R_C_P<14>

PEG_D2R_C_P<15>

=PP1V2_S0_PCIE_GPU

65C6

13D3

13C3

13B3

65C6

13B3

13B3

13A3

13B3

13C3

13B3

13C3

13B3

13B3

13C3

13B3

13B3

13B3

13B3

13B3

13B3

13B3

13B3

13B3

13B3

13B3

13B3

13B3

13B3

13B3

13B3

13A3

13A3

13B3

13A3

34B4

26B1

34B4

13B3

13C3

13D3

13C3

13D3

13C3

13D3

13C3

13D3

13C3

13C3

13C3

13D3

13D3

13C3

13D3

13C3

13D3

13D3

13C3

13C3

13C3

13C3

13C3

13C3

13C3

13C3

13C3

13C3

13C3

13C3

65C6

PGND

PHASE

UG

LG

PVCC

FCCM

EN

PGOOD

COMP

FSET

ISEN

FB

VO

BOOT

VIN

THRMLPAD

VCC

PG

EN

VIN

ADJ

VOUT

GND

G

D

S

OUT

G

D

S

G

D

S

G

D

S

CAP-

FB

OUT

SHDN_L

CAP+

LIN/SKIP_L

IN

GND

V-

V++

-

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

close to inductor

Placement Note:

R8590, R8594 and R8597

Keep C8590, C8591

Req = Rb || Rc

Back-Bias Negative Supply

GPU VCore Current Sense

Back-bias negative supply provides VSS - 0.55V when active.

Vout = -0.55V

Vout = 1.10V / 0.95V

<Rb> Recommended values:

Ra = Vin / 50 uA

Rb = -Vout / 50 uA

When inactive, provides VSS to BBN pins.

(LDO limit)

180mA max output

Vout = (1.58V /) 1.50V

Req = Rb || Rc

Vout(low) = 0.59V * (1 + Ra/Rb)

<Rc>

<Ra>

GPU VCore Supply

125mA max output

(Regulator limit)

Vout = -Vin * Rb / Ra

<Ra>

satisfy BBP FET Vgs (where Vs = 1.2V)

<Ra>

<Rb>

When inactive, provides VDDC to BBP pins.

For proper M56 power sequence, thisVin must be > 2.8V

SI3446DV max Vgs is 1.6V

Pull-up voltage must be high enough to

NOTE: BBP tracks VDDC based on GPU voltage GPIO.

pull-up must be powered before VCore

Vout(high) = 0.59V * (1 + Ra/Req)

Back-bias positive supply provides VDDC + 0.5V when active.

Back-Bias Positive Supply

<Rb>

Vout(low) = 0.6V * (1 + Ra / Rb)

Vout(high) = 0.6V * (1 + Ra / Req)

(L8520 limit)

18A max output

(GPUVCORE_FB)

<Rc>

Stuff 4.7ohm fordecreased slew rate

C8542 1

220%

CASE-D2E-LFPOLY

330UF

2.5V

R85211

2

3.01K

1/16WMF-LF

1%

402

R85221

2

1/16WMF-LF

5.11K1%

402

R85101 25.11K

MF-LF402

1%1/16W

C8502 1

26.3V

CERM1603

2.2UF20%

C8500 1

26.3V

CERM1

20%

603

2.2UF

C8501 1

2

1uF10%16VX5R603

U8500

13

5

4

6

3

7

9

11

10

16

15

12

17

14

2

1

8

CRITICAL

ISL6269BCRZQFN

C8507 1

2CERM402

50V

15pF5%

R85081

2

MF-LF402

1%1/16W

150K

C8508 1

2

10%

402

50VCERM

470pF

R85041

2

0

1/16WMF-LF

5%

402

R85051

2

NO STUFF

MF-LF402

5%1/16W

0

R85061

2

1/16W1%

402MF-LF

57.6KC8506 1

216V10%

402CERM

0.01UF

C8540 1

2

OMIT

22UF

805CERM

20%6.3V

C85411

2

OMIT

CERM805

20%22UF

6.3VXW8500

1 2

SM

C8522 1

2

NO STUFF

10%

402X7R

1000pF

25V

C85211

2

10%1000pF

X7R25V

402

NO STUFF

C8556 1

2

OMIT

22UF

CERM805

20%6.3V

C85571

2

OMIT

22UF20%

CERM6.3V

805

R85551

2

1/16WMF-LF402

1%24.9K

R85561

2

16.2K

1/16W1%

402MF-LF

C8555 1

216V10%

402CERM

0.01UF

U8550

53

2

4

1 6

FAN2558SOT23-6-LF

CRITICAL

C8551 1

2CERM1603

2.2uF

6.3V20%

C85431

2POLYCASE-D2E-LF

20%330UF

2.5V

R85231 212.4K

402

1%

MF-LF1/16W

R85601

2

1/16W5%

402MF-LF

10K

Q8570

3

1

2

2N7002SOT23-LF

R85701

2

1%4.7K

402

1/16WMF-LF

C85701

2

NO STUFF

50V

0.0022uF10%

402CERM

R85611 2

GPU_BB_CTL

0

MF-LF402

5%1/16W

C8598

12

50V

470pF

402CERM

10%

53B6

C8592

12

402

50V

470pF

CERM

10%

R85981 2

402MF-LF

1M

1%1/16W

R85921 2

402

1M

1%

MF-LF1/16W

C85951

2

1uF

CERM402

10%6.3V

R85931 220.0K

MF-LF402

1/16W1%

R85911 220.0K

1%

MF-LF402

1/16W

R85901

2

6491%

1/16WMF-LF

402

R85941 2

NO STUFF

1%

1K

402MF-LF1/16W

C8590

12

402

6.3V

0.47UF

CERM-X5R

10%

R8597

1

2

CRITICAL

10KOHM-5%

0603-LF

R85961

2

MF-LF1/16W

1K1%

402

R85541

2

NO STUFF

1%1/16W

174K

402MF-LF

C8523 1

2CERM-X5R

0.022uF

16V10%

402

R85241

2

5%1/16WMF-LF402

10K

R85251 2

10K

402MF-LF

5%1/16W

C8520 1

2

402

NO STUFF

0.0022uF10%50V

CERM

R85261

2402

10K

MF-LF1/16W

5%

Q8523

3

5

4

SOT-3632N7002DW-X-F

Q8523

6

2

1

2N7002DW-X-FSOT-363

Q8554

3

1

2

NO STUFF

2N7002SOT23-LF

R85871

2

68.1K

402

1/16WMF-LF

1%

R85881

2

11.3K1%

402

1/16WMF-LF

C85811

2

2.2uF

603CERM16.3V20%

C8580 1

26.3VX5R

10uF20%

603

C85891

2

OMIT

805

22UF

CERM

20%6.3V

U8580

3

2

6

7

8

1

5

4

CRITICAL

SOI

MAX1673

Q8575

1

2

5

63

4

SI3446DVTSOP-LF

R85201

2

1/16W5%

402MF-LF

0

NO STUFF

C85091

2

0.22UF

402X5R6.3V20%

C85301

2

CRITICAL

CASED2E-SMPOLY16V

33uF20%

Q8520

5

4

1 2 3

LFPAK

CRITICAL

RJK0305DPB

Q8522

5

4

1 2 3

LFPAK

CRITICAL

RJK0301DPB

Q8521

5

4

1 2 3

RJK0301DPBLFPAK

CRITICAL

L8520

1 2

FDA1055

1.2UH

CRITICAL

C8591

12

CERM-X5R

0.22UF

6.3V

402

10%

U85951

3

4

2

5SC70-5

CRITICAL

HPA00141AIDCKR

R85091

2

5%1/16WMF-LF402

4.7

XW8502

1 2

SM

XW8501

1 2

SM

051-7270


105

B

85

GPU (M56) Core SuppliesSYNC_DATE=(MASTER)

MIN_LINE_WIDTH=0.25 mmGPUVCORE_BOOT_R


GPUVCORE_BOOTMIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mm

GND_GPUVCORE_SGND

=GPUVCORE_PGOOD

GPUVCORE_FB

GPUVCORE_LG


MIN_LINE_WIDTH=0.6 mmGPUVCORE_PHASE

SWITCH_NODE=TRUEMIN_NECK_WIDTH=0.25 mm

GPUISENS_POS

GPUVCORE_IOUT

=PP3V3R5V_S0_GPUISENS

GPUBBP_ADJ

GPUBB_EN_L

=PPVCORE_S0_GPU_BBP

GPUBB_EN_L

=PPVOUT_S0_GPUBBP_LDO

GPUBB_EN

GPU_GENERICD

=PP5V_S0_GPUBBCTL

GPU_VCORE_HIGH

GPUBB_EN

=PP3V3_S0_GPUBBP

GPUBBP_ADJ_LOW

GPUVCORE_COMP_R

GPUVCORE_FSET

GPUVCORE_COMP

GPUVCORE_FCCM

=GPUVCORE_EN

GPU_VCORE_LOW

GPU_VCORE_HIGH_RC

=PP3V3_S0_GPUBBN

GPUBBN_CAPNMIN_LINE_WIDTH=0.38 mmMIN_NECK_WIDTH=0.25 mm

GPUBBN_CAPPMIN_LINE_WIDTH=0.38 mmMIN_NECK_WIDTH=0.25 mm

GPUBB_EN

GPUVCORE_FB_RC

GPUVCORE_FB_LOW

GPUISENS_NTC

=PNVOUT_S0_GPUBBN_REG

=PP3V3_S0_GPU

GPUBBN_FB

=PP5V_S0_GPUVCORE

GPU_VCORE_HIGH


GPUVCORE_UGMIN_LINE_WIDTH=0.6 mm

GPUVCORE_ISEN

GPUISENS_RC

GPUISENS_NEG

=PPVIN_S0_GPUVCORE

GND_GPUVCORE_PGND

=PPVCORE_S0_GPU_REG

68B8

68A6

68B8

74D2

64D8

5C7

5C7

5C7

65A3

5D7

68B7

65A6

68A5

65D3

68A4

74C3

65A1

68B4

68A4

65A3

5D7

5D7

64B5

71C5

65A3

68A6

5C7

65D3

65A3

5C7

65B1

68A8

5C7

5C7

65C1

65A8

MEMORY & CORE POWER / GROUND

(1.0V/1.2V)

(1.0V/1.2V)

(7 OF 7)

VDDR1

VSS

VSS

(1.8V/2.0V) VSS

VDDC

BBP BBN

VDDCI

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

100mA (Preliminary)

100mA (Preliminary)

2.0A @ 500MHz 1.8V GDDR3

14.2A @ 445/452MHz Core/Mem Clk for VDDC+VDDCI

- =PP1V5_GPU_VDD15


Page Notes



- =PP1VR1V3_GPU_VCORE

(NONE)

(NONE)U8400

K15

R10

Y23

AC17

K18

M23

V10

AC14

P14

P18

U15

U16

U17

V14

V15

V16

V18

W14

W15

W19

P19

AC11

AC12

AD11

R15

R17

R18

R19

T16

T17

T18

K14

P16

T14

T23

U19

W10

W17

A3

A9

F32

H13

H19

J1

J10

J11

J13

J18

J19

J20

A12

J32

K11

K13

K19

K20

K21

K24

L23

L24

L32

A15

M1

M10

N9

N10

P8

P9

P10

R1

R9

V1

A18

Y8

Y9

Y10

AA1

A21

A24

A30

C1

C32

K23

A2

B1

R3

R6

R14

R16

T10

T15

T19

U1

U5

U6

B32

U7

U8

U9

U10

U14

U18

V3

V6

V17

V19

C4

W16

W18

Y1

Y5

Y6

Y7

AA4

AA6

AC9

AC10

C5 AD6

AD7

AD8

AD9

AD10

AD13

AD14

AD15

AD16

AD17

C6

AE8

AE14

AE15

AE16

AE17

AF14

AF16

AG11

AG16

AG23

C9

AH10

AH11

AH16

AJ10

AK16

AL1

AL13

AM2

AM13

C10

C15

C18

C20

A8

C21

C24

C27

D11

D30

E5

E8

E9

E12

E13

A11

E16

E19

E25

E28

E30

E32

F3

F6

F10

F13

A13

F15

F16

F18

F19

F21

F22

F24

F27

F30

G13

A16

G16

G19

G20

G21

G22

G25

H1

H5

H7

H16

A19

H20

H21

H28

H32

J3

J6

J9

J12

J16

J21

A22

J24

J28

J30

K10

K12

K16

K17

K27

K30

L1

A25

L6

L7

L29

M3

M6

M7

M8

M9

M24

M28

A31

M32

N3

N7

N8

P1

P5

P6

P7

P15

P17

OMIT

BGA

M56P

C8697 1

2

0.1uF

402X5R16V10%

C8696 1

2

10%

402

1uF

CERM6.3V

C86911

2

10%

402

1uF

CERM6.3V

C86921

2

0.1uF

402X5R16V10%

C86101

2 CERM6.3V

1uF

402

10%

C86091

26.3VCERM

1uF

402

10%

C86081

26.3VCERM

1uF

402

10%

C86071

26.3VCERM

1uF

402

10%

C86061

26.3VCERM

1uF

402

10%

C86051

26.3VCERM

1uF

402

10%

C86041

2

402

6.3VCERM

1uF10%

C86161

2

10%

402

1uF

CERM6.3V

C86151

2

10%

402

1uF

CERM6.3V

C86141

2

10%

402

1uF

CERM6.3V

C86131

2

10%

402

1uF

CERM6.3V

C86121

2

10%

402

1uF

CERM6.3V

R86301

2

1/10W

603

05%

MF-LF

C86341

26.3VCERM

1uF

402

10%

C86331

26.3VCERM

1uF

402

10%

C86321

26.3VCERM

1uF

402

10%

C86311

26.3VCERM

1uF

402

10%

C86601

26.3VCERM

1uF

402

10%

C86661

2

10%

402

1uF

CERM6.3V

C86591

26.3VCERM

1uF

402

10%

C86581

26.3VCERM

1uF

402

10%

C86571

26.3VCERM

1uF

402

10%

C86651

2

10%

402

1uF

CERM6.3V

C86641

2

10%

402

1uF

CERM6.3V

C86631

2

10%

402

1uF

CERM6.3V

C86561

26.3VCERM

1uF

402

10%

C86621

2

10%

402

1uF

CERM6.3V

C86551

26.3VCERM

1uF

402

10%

C86611

2

10%

402

1uF

CERM6.3V

C86721

26.3VCERM

1uF

402

10%

C86781

2

10%

402

1uF

CERM6.3V

C86711

26.3VCERM

1uF

402

10%

C86701

26.3VCERM

1uF

402

10%

C86691

26.3VCERM

1uF

402

10%

C86771

2

10%

402

1uF

CERM6.3V

C86761

2

10%

402

1uF

CERM6.3V

C86751

2

10%

402

1uF

CERM6.3V

C86681

26.3VCERM

1uF

402

10%

C86741

2

10%

402

1uF

CERM6.3V

C86671

2 CERM6.3V

1uF

402

10%

C86731

2

10%

402

1uF

CERM6.3V

C8653 1

2

OMIT

6.3VCERM

22UF

805

20%

C8652 1

2

OMIT

20%6.3VCERM805

22UFC8651 1

2

OMIT

CERM6.3V

22UF

805

20%

C8650 1

2

OMIT

22UF

805CERM6.3V20%

C86831

2

10%

402

1uF

CERM6.3V

C86821

2

10%

402

1uF

CERM6.3V

C86811

2

10%

402

1uF

CERM6.3V

C86801

2

10%

402

1uF

CERM6.3V

C86791

26.3VCERM

1uF

402

10%

C8601 1

2

OMIT

22UF

805CERM6.3V20%

C86111

26.3VCERM

1uF

402

10%

C8690 1

2

OMIT

20%6.3VCERM805

22UF

C86951

2

OMIT

20%6.3VCERM805

22UF

C8630 1

2

OMIT

20%6.3VCERM805

22UF

C8600 1

2

OMIT

20%6.3VCERM805

22UF

ATI M56 Core PowerSYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)

B051-7270

10586

=PNBB_S0_GPU

=PP1V8R2V0_S0_FB_GPU

=PPBB_S0_GPU


PPVCORE_S0_GPU_VDDCIVOLTAGE=1.2V

=PPVCORE_S0_GPU

70B8 70B5

74A7

70A8

65A6

70A5

53C7

65D1

65B6

65D1

53A5

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IN

IN

IN

IN

IN

IN

IN

IN

IO

IO

IO

IO

IO

IO

IO

IO IO

IO

IO

IO

IO

IO

IO

IO

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

DQA_58

DQA_59

WEA1*

DQA_61

DQA_62

MVREFD_0

MVREFS_0

VDDRH0

MAA_0

MAA_1

MAA_2

MAA_3

MAA_4

MAA_5

MAA_6

MAA_7

MAA_8

MAA_9

MAA_10

MAA_11

MAA_12

MAA_13

MAA_14

MAA_15

DQMA_0*

DQMA_1*

DQMA_2*

DQMA_3*

DQMA_4*

DQMA_5*

DQMA_6*

DQMA_7*

QSA_1

QSA_2

QSA_0

QSA_3

QSA_4

QSA_5

QSA_6

QSA_7

QSA_0*

QSA_1*

QSA_2*

QSA_3*

QSA_4*

QSA_5*

QSA_6*

QSA_7*

CLKA0

CLKA0*

CSA0_0*

CKEA0

RASA0*

CASA0*

WEA0*

ODTA0

CLKA1*

CSA1_0*

CKEA1

RASA1*

CASA1*

ODTA1

DQA_0

DQA_1

DQA_2

DQA_3

DQA_4

DQA_5

DQA_6

DQA_7

DQA_8

DQA_9

DQA_10

DQA_11

DQA_12

DQA_13

DQA_14

DQA_15

DQA_16

DQA_17

DQA_18

DQA_19

DQA_20

DQA_21

DQA_22

DQA_23

DQA_24

DQA_25

DQA_26

DQA_27

DQA_28

DQA_29

DQA_30

DQA_31

DQA_32

DQA_33

DQA_34

DQA_35

DQA_36

DQA_37

DQA_38

DQA_39

DQA_40

DQA_41

DQA_42

DQA_43

DQA_45

DQA_44

DQA_46

DQA_47

DQA_48

DQA_50

DQA_51

DQA_49

DQA_52

DQA_53

DQA_54

DQA_55

DQA_56

DQA_57

DQA_60

DQA_63

VSSRH0

CLKA1

CSA0_1*

CSA1_1*

WRITE STROBE

READ STROBE

MEMORY INTERFACE A

(3 OF 7)

2.0V)(1.8V/

DQB_62

VDDRH1

MVREFS_1

MAB_0

MAB_1

MAB_2

MAB_3

MAB_4

MAB_5

MAB_6

MAB_7

MAB_8

MAB_9

MAB_10

MAB_11

MAB_12

MAB_15

MAB_14

MAB_13

DQMB_0*

DQMB_1*

DQMB_2*

DQMB_3*

DQMB_4*

DQMB_5*

DQMB_6*

DQMB_7*

QSB_0

QSB_1

QSB_2

QSB_4

QSB_3

QSB_5

QSB_6

QSB_7

QSB_0*

QSB_1*

QSB_2*

QSB_3*

QSB_4*

QSB_5*

QSB_6*

QSB_7*

CLKB0*

CLKB0

CSB0_0*

CKEB0

RASB0*

WEB0*

CASB0*

ODTB0

CLKB1

CLKB1*

CKEB1

RASB1*

WEB1*

CASB1*

ODTB1

DRAM_RST

DQB_0

DQB_1

DQB_2

DQB_3

DQB_4

DQB_5

DQB_6

DQB_7

DQB_8

DQB_9

DQB_10

DQB_11

DQB_12

DQB_15

DQB_14

DQB_13

DQB_16

DQB_17

DQB_18

DQB_20

DQB_19

DQB_22

DQB_21

DQB_23

DQB_25

DQB_24

DQB_27

DQB_26

DQB_28

DQB_30

DQB_29

DQB_33

DQB_31

DQB_32

DQB_35

DQB_34

DQB_37

DQB_36

DQB_38

DQB_40

DQB_41

DQB_42

DQB_43

DQB_44

DQB_45

DQB_46

DQB_48

DQB_47

DQB_52

DQB_53

DQB_56

DQB_55

DQB_54

DQB_58

DQB_57

DQB_60

DQB_59

DQB_61

DQB_63

MVREFD_1

VSSRH1

TEST_MCLK

TEST_YCLK

MEMTEST

DQB_39

CSB1_0*

DQB_51

DQB_50

DQB_49

CSB0_1*

CSB1_1*

WRITE STROBE

READ STROBE

MEMORY INTERFACE B

(4 OF 7)

(1.8V/ 2.0V)

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

- =PP1V8R2V0_S0_FB_GPU




(NONE)

(NONE)

NC

NC NC

NC

Page Notes

R87221

2

40.2

402MF-LF1/16W1%

R87201

2

40.2

402MF-LF1/16W

1%

C87231

2

10%16VX5R402

0.1uF

R87231

2

1%1/16WMF-LF402

100R87211

2

1%

MF-LF402

100

1/16W

C8721 1

2

10%

X5R402

0.1uF

16V

C87131

2

0.1uF

402X5R16V10%

R87121

2

40.2

402MF-LF1/16W1%

R87131

2

1/16W1%

MF-LF402

100C8711 1

2

0.1uF10%16VX5R402

R87101

2

40.2

402MF-LF1/16W

1%

R87111

2

1%1/16WMF-LF402

100

R87321

2

MF-LF1/16W1%243

402

R87311

2402

4.7K5%

1/16WMF-LF

R87301

2

MF-LF1/16W5%

402

4.7K

R87331

2

4.7K

402MF-LF1/16W5%

U8400

C29

B22

B30

C22

D31

E31

B20

C19

B29

C28

B23

C23

M31

M30

L28

L27

J27

H29

G29

G27

M26

L26

M25

L25

L31

J25

G28

H27

H26

F26

G26

H25

H24

H23

H22

L30

J23

J22

E23

D22

D23

E22

E20

F20

D19

D18

H30

B19

B18

C17

B17

C14

B14

C13

B13

D17

E18

G31

E17

F17

E15

E14

F14

D13

H18

H17

G18

G17

G30

G15

G14

H14

J14

F31

M27

M29

H31

J29

J26

G23

E21

B15

D14

J17

D26

F28

D29

B27

E27

E29

B25

C25

D28

D25

E24

E26

D27

F25

C26

B26

C31

C30

F29

D24

J31

K31

K29

K28

K25

K26

F23

G24

D20

D21

B16

C16

D16

D15

H15

J15

B28

B24

A27

A28

B31

B21

OMIT

BGA

M56PU8400

D3

L2

C2

L3

B4

B5

N2

P3

D2

E3

K2

K3

B12

C12

E11

F11

F9

D8

D7

F7

G12

G11

H12

H11

B11

H9

E7

F8

G8

G6

G7

H8

J8

K8

L8

C11

K9

L9

K5

L4

K4

L5

N5

N6

P4

R4

C8

P2

R2

T3

T2

W3

W2

Y3

Y2

T4

R5

B7

T5

T6

V5

W5

W6

Y4

R8

T8

R7

T7

C7

V7

W7

W8

W9

B6

F12

D12

B8

D9

G9

K7

M5

V2

W4

T9

AA3

G4

E6

D4

F2

F5

D5

H2

H3

E4

H4

J5

G5

F4

H6

G3

G2

AA7

B3

C3

D6

J4

B9

B10

D10

E10

H10

G10

K6

J7

N4

M4

U2

U3

U4

V4

V8

V9

E2

J2

AA5

AA2

F1

E1

B2

M2

OMIT

BGA

M56P

C8716 1

2

1uF

CERM

10%

402

6.3V

C8715 1

2

1uF

6.3VCERM402

10%

C8726 1

26.3VCERM

1uF

402

10%

C8725 1

2

10%

402

1uF

CERM6.3V

L8725

1 2

0402

FERR-220-OHML8715

1 2

0402

FERR-220-OHM

XW8725

1 2

SMXW8715

1 2

SM

87 105

051-7270 B

SYNC_DATE=(MASTER)

ATI M56 Frame Buffer I/FSYNC_MASTER=(MASTER)

=PP1V8R2V0_S0_FB_GPUMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.25 mm

PP1V8R2V0_S0_GPU_VDDRH0VOLTAGE=1.8V =PP1V8R2V0_S0_FB_GPU


PP1V8R2V0_S0_GPU_VDDRH1

FB_B_DQ<17>

FB_B_DQ<18>

FB_A_CLK_P<0>

FB_A_CS_L<0>

FB_A_BA<2>

VOLTAGE=0VMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.25 mmGND_GPU_VSSRH1

=PP1V8R2V0_S0_FB_GPU=PP1V8R2V0_S0_FB_GPU

FB_A_CLK_N<0>

FB_A_BA<0>

FB_B_MA<11>

FB_B_MA<10>

FB_A_MA<4>

FB_A_MA<3>

FB_A_DQ<0>

FB_B_DQ<62>

GPU_MVREFS1

FB_B_MA<0>

FB_B_MA<1>

FB_B_MA<2>

FB_B_MA<3>

FB_B_MA<4>

FB_B_MA<5>

FB_B_MA<6>

FB_B_MA<7>

FB_B_MA<8>

FB_B_MA<9>

TP_FB_B_MA12

FB_B_BA<1>

FB_B_BA<0>

FB_B_BA<2>

FB_B_DQM_L<0>

FB_B_DQM_L<1>

FB_B_DQM_L<2>

FB_B_DQM_L<3>

FB_B_DQM_L<4>

FB_B_DQM_L<5>

FB_B_DQM_L<6>

FB_B_DQM_L<7>

FB_B_RDQS<0>

FB_B_RDQS<1>

FB_B_RDQS<2>

FB_B_RDQS<4>

FB_B_RDQS<3>

FB_B_RDQS<5>

FB_B_RDQS<6>

FB_B_RDQS<7>

FB_B_WDQS<0>

FB_B_WDQS<1>

FB_B_WDQS<2>

FB_B_WDQS<3>

FB_B_WDQS<4>

FB_B_WDQS<5>

FB_B_WDQS<6>

FB_B_WDQS<7>

FB_B_CLK_N<0>

FB_B_CLK_P<0>

FB_B_CS_L<0>

FB_B_CKE<0>

FB_B_RAS_L<0>

FB_B_WE_L<0>

FB_B_CAS_L<0>

TP_FB_B_ODT<0>

FB_B_CLK_P<1>

FB_B_CLK_N<1>

FB_B_CKE<1>

FB_B_RAS_L<1>

FB_B_WE_L<1>

FB_B_CAS_L<1>

TP_FB_B_ODT<1>

FB_DRAM_RST

FB_B_DQ<0>

FB_B_DQ<1>

FB_B_DQ<2>

FB_B_DQ<3>

FB_B_DQ<4>

FB_B_DQ<5>

FB_B_DQ<6>

FB_B_DQ<7>

FB_B_DQ<8>

FB_B_DQ<9>

FB_B_DQ<10>

FB_B_DQ<11>

FB_B_DQ<12>

FB_B_DQ<15>

FB_B_DQ<14>

FB_B_DQ<13>

FB_B_DQ<16>

FB_B_DQ<20>

FB_B_DQ<19>

FB_B_DQ<22>

FB_B_DQ<21>

FB_B_DQ<23>

FB_B_DQ<25>

FB_B_DQ<24>

FB_B_DQ<27>

FB_B_DQ<26>

FB_B_DQ<28>

FB_B_DQ<30>

FB_B_DQ<29>

FB_B_DQ<33>

FB_B_DQ<31>

FB_B_DQ<32>

FB_B_DQ<35>

FB_B_DQ<34>

FB_B_DQ<37>

FB_B_DQ<36>

FB_B_DQ<38>

FB_B_DQ<40>

FB_B_DQ<41>

FB_B_DQ<42>

FB_B_DQ<43>

FB_B_DQ<44>

FB_B_DQ<45>

FB_B_DQ<46>

FB_B_DQ<48>

FB_B_DQ<47>

FB_B_DQ<52>

FB_B_DQ<53>

FB_B_DQ<56>

FB_B_DQ<55>

FB_B_DQ<54>

FB_B_DQ<58>

FB_B_DQ<57>

FB_B_DQ<60>

FB_B_DQ<59>

FB_B_DQ<61>

FB_B_DQ<63>

GPU_MVREFD1

GPU_TEST_MCLK

GPU_TEST_YCLK

GPU_MEMTEST

FB_B_DQ<39>

FB_B_CS_L<1>

FB_B_DQ<51>

FB_B_DQ<50>

FB_B_DQ<49>

FB_A_DQ<58>

FB_A_DQ<59>

FB_A_WE_L<1>

FB_A_DQ<61>

FB_A_DQ<62>

GPU_MVREFD0

FB_A_MA<0>

FB_A_MA<1>

FB_A_MA<2>

FB_A_MA<5>

FB_A_MA<6>

FB_A_MA<7>

FB_A_MA<11>

TP_FB_A_MA12

FB_A_DQM_L<0>

FB_A_DQM_L<1>

FB_A_DQM_L<2>

FB_A_DQM_L<3>

FB_A_DQM_L<4>

FB_A_CKE<0>

FB_A_RAS_L<0>

FB_A_CAS_L<0>

FB_A_WE_L<0>

TP_FB_A_ODT<0>

FB_A_CLK_N<1>

FB_A_CS_L<1>

FB_A_CKE<1>

FB_A_RAS_L<1>

FB_A_CAS_L<1>

TP_FB_A_ODT<1>

FB_A_DQ<1>

FB_A_DQ<2>

FB_A_DQ<3>

FB_A_DQ<4>

FB_A_DQ<5>

FB_A_DQ<6>

FB_A_DQ<7>

FB_A_DQ<8>

FB_A_DQ<9>

FB_A_DQ<10>

FB_A_DQ<11>

FB_A_DQ<12>

FB_A_DQ<13>

FB_A_DQ<14>

FB_A_DQ<15>

FB_A_DQ<16>

FB_A_DQ<17>

FB_A_DQ<18>

FB_A_DQ<19>

FB_A_DQ<20>

FB_A_DQ<21>

FB_A_DQ<22>

FB_A_DQ<23>

FB_A_DQ<24>

FB_A_DQ<25>

FB_A_DQ<26>

FB_A_DQ<27>

FB_A_DQ<28>

FB_A_DQ<29>

FB_A_DQ<30>

FB_A_DQ<31>

FB_A_DQ<32>

FB_A_DQ<33>

FB_A_DQ<34>

FB_A_DQ<35>

FB_A_DQ<36>

FB_A_DQ<37>

FB_A_DQ<38>

FB_A_DQ<39>

FB_A_DQ<40>

FB_A_DQ<41>

FB_A_DQ<42>

FB_A_DQ<43>

FB_A_DQ<45>

FB_A_DQ<44>

FB_A_DQ<46>

FB_A_DQ<47>

FB_A_DQ<48>

FB_A_DQ<50>

FB_A_DQ<51>

FB_A_DQ<49>

FB_A_DQ<52>

FB_A_DQ<53>

FB_A_DQ<54>

FB_A_DQ<55>

FB_A_DQ<56>

FB_A_DQ<63>

FB_A_CLK_P<1>

FB_A_MA<9>

FB_A_MA<8>

FB_A_MA<10>

FB_A_BA<1>

FB_A_DQM_L<7>

FB_A_DQM_L<6>

FB_A_RDQS<0>

FB_A_RDQS<1>

FB_A_RDQS<2>

FB_A_RDQS<3>

FB_A_RDQS<4>

FB_A_RDQS<5>

FB_A_RDQS<7>

FB_A_RDQS<6>

FB_A_WDQS<0>

FB_A_WDQS<1>

FB_A_WDQS<3>

FB_A_WDQS<2>

FB_A_WDQS<4>

FB_A_WDQS<5>

FB_A_WDQS<6>

FB_A_WDQS<7>

FB_A_DQ<60>

FB_A_DQM_L<5>

FB_A_DQ<57>

GPU_MVREFS0

GND_GPU_VSSRH0

VOLTAGE=0V


70B8

70B8

70B8

70B5

70B5

70B5

70A8 70A8

73A8

70A5 70A8

70A5 70A5

73A5

69B8 69B8

72A8

69B8 69B8

72A8

73B8

73B8

72B8

72B8

73B8

73B8

73B8

73B8

73B8

73B8

73B8

73B8

73B8

73B8

73A8

73A8

73A8

72A8

72B8

72B8

72B8

72B8

72B8

72B8

72B8

72B8

72B8

72B8

72A8

65B6 65B6

73B6

73B6

72B8

72B8

72A5

65B6 65B6

72B8

72A5

73B5

73B5

72B5

72B5

72B6

73A3

73B5

73B5

73B5

73B5

73B5

73B5

73B5

73B5

73B5

73B5

71C1

73A5

73A5

73A5

73B6

73B6

73B6

73B6

73B3

73B3

73B3

73B3

73A8

73A8

73A8

73A5

73A8

73A5

73A5

73A5

73A8

73A8

73A8

73A8

73A5

73A5

73A5

73A5

73B8

73B8

73B8

73B8

73A8

73A8

73A8

73B5

73B5

73B5

73A5

73A5

73A5

72A5

73A6

73A6

73A6

73A6

73A6

73A6

73A6

73A6

73B6

73B6

73B6

73B6

73B6

73B6

73B6

73B6

73B6

73A6

73B6

73A6

73A6

73A6

73A6

73A6

73A6

73A6

73A6

73A6

73A6

73A3

73A6

73A3

73A3

73A3

73A3

73A3

73A3

73A3

73A3

73A3

73A3

73B3

73B3

73B3

73B3

73B3

73B3

73B3

73A3

73B3

73B3

73A3

73A3

73A3

73A3

73A3

73A3

73A3

73B5

73B3

73B3

73B3

72A3

72A3

72A5

72A3

72A3

72B5

72B5

72B5

72B5

72B5

72B5

72B5

71C1

72B6

72B6

72B6

72B6

72B3

72B8

72A8

72A8

72A8

72B5

72B5

72B5

72A5

72A5

72B6

72B6

72B6

72B6

72B6

72B6

72B6

72B6

72B6

72B6

72B6

72A6

72A6

72A6

72A6

72A6

72A6

72A6

72A6

72A6

72A6

72A6

72A6

72A6

72A6

72A6

72A6

72A6

72A6

72A6

72A6

72B3

72B3

72B3

72B3

72B3

72B3

72B3

72B3

72B3

72B3

72B3

72B3

72A3

72A3

72A3

72A3

72A3

72A3

72A3

72A3

72A3

72A3

72A3

72A3

72A3

72A3

72B5

72B5

72B5

72B5

72A5

72B3

72B3

72A8

72A8

72A8

72A8

72A5

72A5

72A5

72A5

72A8

72A8

72A8

72A8

72A5

72A5

72A5

72A5

72A3

72B3

72A3

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

Required for debug access




0000 = 128MB

0010 = 256MB

0110 = Reserved

0100 = 64MB

ROMCFGID[3..0]

Renamed signals

Unused signals

TESTIN[0] TX_PWRS_ENb

TESTIN[6] Reserved

TESTIN[5] Reserved

TESTIN[3] Reserved

VDD_VCL TESTIN[2] Reserved

TESTOUT[11] ROMIDCFG[2]

TESTIN[4] DEBUG_ACCESS

IPD

Serial ROM TestBus Misc Straps

TESTIN[1] TX_DEEMPH_EN

IPD

TESTIN[8]

IPD

IPD

IPD

IPD


ROMSCK TESTOUT[8]

ROMSI ROMIDCFG[3]

ROMSO TESTWR Reserved

ENA_BL TESTIN[7]

IPD


Also required: GPIO10 - GPIO13


Thm Mon Int

SS_IN

TESTIN[9] PWRCNTL

R88001

2

1/16W5%

10K

MF-LF402

R88011

2402MF-LF1/16W5%10K

GPU_DEEPMH_EN

R88021

2

NO STUFF

402

10K

1/16W5%

MF-LF

R88031

2

NO STUFF

10K

402MF-LF1/16W5%

R88061

2

NO STUFF

MF-LF402

1/16W

10K5%

R88041

2

NO STUFF

MF-LF

10K5%

1/16W

402

R88081

2

NO STUFF

5%

402

10K

MF-LF1/16W

R88051

2

5%1/16WMF-LF402

10K

R88121

2

10K

402MF-LF1/16W

GPU_MEM_256M

5%

R88091

2

5%

NO STUFF

10K

402MF-LF1/16W

R88111

2

MF-LF402

10K

1/16W5%

NO STUFF

R88131

2

GPU_MEM_64M

5%1/16W

10K

MF-LF402

R88911

2

5%1/16WMF-LF

4.7K

402

R88901

2402

5%4.7K

1/16WMF-LF

R88241

2

1/16W

GPU_MEM_256M

5%10K

402MF-LF

R88271

2

GPU_MEM_NOT_SAM

5%

402

10K

MF-LF1/16W

SYNC_MASTER=M59_MG

GPU Straps

88 105

B051-7270


=PP3V3_D3C_GPU_GPIOS

GPU_GPIO_13

GPU_GPIO_14

GPU_GPIO_15

GPU_GPIO_16

GPU_DDC_B_DATA

=PP3V3_D3C_GPU

GPU_GPIO_17

GPU_GPIO_18

GPU_GPIO_19

GPU_GPIO_20

GPU_GPIO_7

GPU_GPIO_10

NC_GPU_GPIO_22


NC_GPU_GPIO_32


NC_GPU_GPIO_33


NC_GPU_GPIO_34


NC_GPU_GPIO_29


MAKE_BASE=TRUENC_GPU_GPIO_30

NO_TEST=TRUENC_GPU_GPIO_31


NC_GPU_GPIO_28


NC_GPU_GPIO_26MAKE_BASE=TRUENO_TEST=TRUE



NC_GPU_GPIO_20


NO_TEST=TRUE

NC_GPU_GPIO_18MAKE_BASE=TRUE

NO_TEST=TRUENC_GPU_GPIO_17MAKE_BASE=TRUE

NO_TEST=TRUENC_GPU_GPIO_14MAKE_BASE=TRUE

GPU_GPIO_21

GPU_GPIO_23

GPU_GPIO_22

GPU_GPIO_26

GPU_GPIO_25

GPU_GPIO_28

GPU_GPIO_31

GPU_GPIO_30

GPU_GPIO_29

GPU_GPIO_34

GPU_GPIO_33

GPU_GPIO_32

GPU_CLK27MSS_INMAKE_BASE=TRUE

MAKE_BASE=TRUETP_GPU_GPIO_10

GPU_BLONMAKE_BASE=TRUE

GPU_GPIO_0

GPU_GPIO_1


NC_GPU_GPIO_21

NC_GPU_GPIO_25


GPU_GPIO_24

GPU_GPIO_27

GPU_VCORE_LOWMAKE_BASE=TRUE

ATI_DVPDATA<15..0>NO_TEST=TRUEMAKE_BASE=TRUE

NC_ATI_DVPDATA<15..0>

ATI_DVPCNTL<2..0>NO_TEST=TRUEMAKE_BASE=TRUE

NC_ATI_DVPCNTL<2..0>

LVDS_L_DATA_N<3>MAKE_BASE=TRUE NO_TEST=TRUE

NC_LVDS_L_DATAN<3>

ATI_DVPCLKMAKE_BASE=TRUE NO_TEST=TRUE

NC_ATI_DVPCLK

LVDS_L_DATA_P<3>MAKE_BASE=TRUE NO_TEST=TRUE

NC_LVDS_L_DATAP<3>

LVDS_U_DATA_N<3>MAKE_BASE=TRUE NO_TEST=TRUE

NC_LVDS_U_DATAN<3>

LVDS_U_DATA_P<3>MAKE_BASE=TRUE NO_TEST=TRUE

NC_LVDS_U_DATAP<3>

GPU_TV_COMPNO_TEST=TRUEMAKE_BASE=TRUE

NC_GPU_TV_COMP

GPU_TV_YMAKE_BASE=TRUE NO_TEST=TRUE

NC_GPU_TV_Y

GPU_TV_CNO_TEST=TRUEMAKE_BASE=TRUE

NC_GPU_TV_C

GPU_VGA_VSYNCMAKE_BASE=TRUE

TP_GPU_VGA_VSYNC

GPU_VGA_HSYNCMAKE_BASE=TRUE

TP_GPU_VGA_HSYNC

GPU_VGA_BMAKE_BASE=TRUE NO_TEST=TRUE

NC_GPU_VGA_B

GPU_VGA_RNO_TEST=TRUEMAKE_BASE=TRUE

NC_GPU_VGA_R

GPU_VGA_GMAKE_BASE=TRUE NO_TEST=TRUE

NC_GPU_VGA_G

GPU_GENERICCMAKE_BASE=TRUE NO_TEST=TRUE

NC_GPU_GENERICC

GPU_GENERICBNO_TEST=TRUEMAKE_BASE=TRUE

NC_GPU_GENERICB

GPU_GENERICAMAKE_BASE=TRUE NO_TEST=TRUE

NC_GPU_GENERICA

TP_FB_B_MA12NO_TEST=TRUEMAKE_BASE=TRUE

NC_FB_B_MA12

TP_FB_A_MA12NO_TEST=TRUEMAKE_BASE=TRUE

NC_FB_A_MA12

TP_ATI_ROMCS_LNO_TEST=TRUEMAKE_BASE=TRUE

NC_ATI_ROMCS_L

GPU_XTALOUTNO_TEST=TRUEMAKE_BASE=TRUE

NC_GPU_XTALOUT

GPU_XTALINMAKE_BASE=TRUE

GPU_CLK27M

ATI_DVPDATA<23..16>MAKE_BASE=TRUE

TP_ATI_DVPDATA<23..16>

GPU_GPIO_5

GPU_GPIO_4

GPU_GPIO_12

GPU_GPIO_8

GPU_GPIO_6

GPU_GPIO_11

GPU_GPIO_3

GPU_GPIO_9

GPU_GPIO_2

GPU_MEM_256MMAKE_BASE=TRUE

GPU_MEMIDMAKE_BASE=TRUE

GPU_DDC_B_CLK

34B4

74C3

34B4

74B3

65A3

74C3

74C3

74C3

74C3

75A3

65A3

74C3

74D5

74D5

74D5

74D3

74C3

74D5

74D5

74D5

74D5

74D5

74D5

74C5

74C5

74C5

74C5

74C5

74C5

34B2

79A4

74D3

74D3

74D5

74D5

68B4

74B3

74B3

75A3

74C3

75A3

75B3

75B3

75B3

75B3

75B3

75B3

75B3

75C3

75C3

75C3

74C3

74C3

74C3

70D1

70D5

74A3

74A5

74A5 34B2

74A3

74D3

74D3

74C3

74D3

74D3

74C3

74D3

74C3

74D3

75A3

DQ1

DQ0

DQ2

DQ3

DQ5

DQ6

DQ4

DQ8

DQ7

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ24

DQ23

DQ22

DQ25

DQ26

DQ27

DQ29

DQ28

DQ30

DQ31

RDQS3

RDQS2

RDQS1

RDQS0

SEN

RESET

MF

ZQ

RAS*

CAS*

WE*

CS*

CK*

A9

A6

A7

A3

A4

A2

A0

A1

CK

WDQS2

WDQS1

WDQS0

WDQS3

BA0

BA2

BA1

RFU1

RFU2

DM3

DM2

DM1

DM0

A5

A11

A8/AP

A10

CKE

MFHIGH

MFHIGH

MFHIGH

(1 OF 2)

VSS0

VSS1

VSS2

VSS5

VSS3

VSS4

VSS7

VSS6

VSSA0

VSSA1

VSSQ0

VSSQ1

VSSQ2

VSSQ3

VSSQ5

VSSQ6

VSSQ4

VSSQ7

VSSQ8

VSSQ9

VSSQ10

VSSQ11

VSSQ12

VSSQ13

VSSQ14

VSSQ16

VSSQ15

VSSQ17

VSSQ18

VSSQ19VDDQ19

VDDQ20

VDDQ21

VREF1

VREF0

VDDQ10

VDDQ11

VDDQ12

VDDQ13

VDDQ14

VDDQ15

VDDQ18

VDDQ16

VDDQ17

VDDQ9

VDDA1

VDDQ0

VDDQ1

VDDQ2

VDDQ5

VDDQ3

VDDQ4

VDDQ6

VDDQ7

VDDQ8

VDD0

VDD1

VDD2

VDD5

VDD3

VDD4

VDD6

VDD7

VDDA0

(2 OF 2)

IN

IN

IN

IN

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

DQ1

DQ0

DQ2

DQ3

DQ5

DQ6

DQ4

DQ8

DQ7

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ24

DQ23

DQ22

DQ25

DQ26

DQ27

DQ29

DQ28

DQ30

DQ31

RDQS3

RDQS2

RDQS1

RDQS0

SEN

RESET

MF

ZQ

RAS*

CAS*

WE*

CS*

CK*

A9

A6

A7

A3

A4

A2

A0

A1

CK

WDQS2

WDQS1

WDQS0

WDQS3

BA0

BA2

BA1

RFU1

RFU2

DM3

DM2

DM1

DM0

A5

A11

A8/AP

A10

CKE

MFHIGH

MFHIGH

MFHIGH

(1 OF 2)

VSS0

VSS1

VSS2

VSS5

VSS3

VSS4

VSS7

VSS6

VSSA0

VSSA1

VSSQ0

VSSQ1

VSSQ2

VSSQ3

VSSQ5

VSSQ6

VSSQ4

VSSQ7

VSSQ8

VSSQ9

VSSQ10

VSSQ11

VSSQ12

VSSQ13

VSSQ14

VSSQ16

VSSQ15

VSSQ17

VSSQ18

VSSQ19VDDQ19

VDDQ20

VDDQ21

VREF1

VREF0

VDDQ10

VDDQ11

VDDQ12

VDDQ13

VDDQ14

VDDQ15

VDDQ18

VDDQ16

VDDQ17

VDDQ9

VDDA1

VDDQ0

VDDQ1

VDDQ2

VDDQ5

VDDQ3

VDDQ4

VDDQ6

VDDQ7

VDDQ8

VDD0

VDD1

VDD2

VDD5

VDD3

VDD4

VDD6

VDD7

VDDA0

(2 OF 2)

IN

IN

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IN

IN

IO

IO

IN

IN

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

Connect to designated pin, then GND

DQA0-7 or DQA8-15. Bits can be swapped

how these bits are mapped for GPU to support

GDDR3 vendor/device identification scheme.

(NONE)

(NONE)

- =PP1V8_S0_FB_VDD

- =PP1V8_S0_FB_VDDQ

U8900.J12U8900.J1

NC

NC NC

NC

Connect to designated pin, then GNDU8900.J1 U8900.J12

within byte-lane, but software must know

NOTE: U8900 DQ0-7 MUST connect to GPU




R89301

2

1/16W1%

402MF-LF

2.37K

R89311

2402

1/16W1%

MF-LF

5.49K

C89031

216V10%

402X5R

0.1uFC89021

2

0.1uF

16V10%

402X5R

C89041

216V10%

402X5R

0.1uFC89011

216V10%

402X5R

0.1uF

C89221

216V10%

402X5R

0.1uFC89231

2 X5R16V10%

402

0.1uFC89241

216V10%

402X5R

0.1uFC89251

216V10%

402X5R

0.1uFC89261

2

0.1uF

16V10%

402X5R

U8900K9

H11

K11

L9

K10

M9

K4

H2

K3

L4

K2

M4

G9

G4

H3

F9

J11

J10

H9

F4

E3

E10

N10

N3

B2

B3

C11

C10

E11

F10

F11

G10

M11

L10

N11

M10

C2

R11

R10

T11

T10

M2

L3

N2

M3

R2

R3

C3

T2

T3

E2

F3

F2

G3

B11

B10

A9

H10

D3

D10

P10

P3

V9

J2

J3

V4

D2

D11

P11

P2

H4

A4

16MX32-GDDR3-500MHZ

K4J52324QC-BC20

OMIT

CRITICAL

FBGA

U8900A2

A11

F1

F12

M1

M12

V2

V11

K1

K12

A1

A12

J4

J9

N1

N4

N9

N12

R1

R4

R9

R12

C1

V1

V12

C4

C9

C12

E1

E4

E9

E12

H1

H12

A3

A10

G1

G12

L1

L12

V3

V10

J1

J12

B1

B4

L2

L11

P1

P4

P9

P12

T1

T4

T9

T12

B9

B12

D1

D4

D9

D12

G2

G11

OMIT

CRITICAL

16MX32-GDDR3-500MHZ

K4J52324QC-BC20

FBGA

R89491

2

100

1/16W5%

402MF-LF

R89411

2

1K

1/16WMF-LF402

5%

R89481

2

1/16W1%

402MF-LF

243

R89451

2

1/16W1%

402MF-LF

60.4

R89461

2

60.4

MF-LF402

1%1/16W

C89331

2

0.1uF

X5R402

10%16V

R89321

2

2.37K

MF-LF402

1%1/16W

R89331

2

1/16W1%

402MF-LF

5.49K

C89211

2

10%0.1uF

X5R402

16V

L8910

1 2

FERR-220-OHM

0402

L8915

1 2

FERR-220-OHM

0402

C89151

216V10%

402X5R

0.1uFC89101

2

10%16V

402X5R

0.1uF

R89401

2

1%121

MF-LF402

1/16W

R89471

2

1%121

MF-LF402

1/16W

R89441

2

1/16W

402MF-LF

1211%

R89431

2

MF-LF

1%121

402

1/16W

R89421

2

1/16W

402MF-LF

1211%

R89911

2

1K

1/16W5%

402MF-LF

R89901

2

1/16W

402MF-LF

1211%

R89921

2

1%121

MF-LF402

1/16W

C89711

2

10%0.1uF

X5R402

16V

C89721

2

0.1uF

X5R402

10%16V

R89981

2

243

MF-LF402

1%1/16W

R89991

2

100

MF-LF402

5%1/16W

U8950K9

H11

K11

L9

K10

M9

K4

H2

K3

L4

K2

M4

G9

G4

H3

F9

J11

J10

H9

F4

E3

E10

N10

N3

B2

B3

C11

C10

E11

F10

F11

G10

M11

L10

N11

M10

C2

R11

R10

T11

T10

M2

L3

N2

M3

R2

R3

C3

T2

T3

E2

F3

F2

G3

B11

B10

A9

H10

D3

D10

P10

P3

V9

J2

J3

V4

D2

D11

P11

P2

H4

A4

CRITICAL

OMIT

16MX32-GDDR3-500MHZ

K4J52324QC-BC20

FBGA

R89931

2

1/16W

402MF-LF

1211%

R89951

2

60.4

MF-LF402

1%1/16W

R89941

2

1%121

MF-LF402

1/16W

R89971

2

1/16W

402MF-LF

1211%

R89961

2

1/16W1%

402MF-LF

60.4

R89811

2

5.49K

MF-LF402

1%1/16W

R89801

2

2.37K

MF-LF402

1%1/16W

R89831

2

5.49K

MF-LF402

1%1/16W

R89821

2

1/16W1%

402MF-LF

2.37K

C89731

2

0.1uF

X5R402

10%16V

C89811

2

0.1uF

X5R402

10%16V

C89741

2

0.1uF

X5R402

10%16V

C89751

2

0.1uF

X5R402

10%16V

C89831

216V10%

402X5R

0.1uF

U8950A2

A11

F1

F12

M1

M12

V2

V11

K1

K12

A1

A12

J4

J9

N1

N4

N9

N12

R1

R4

R9

R12

C1

V1

V12

C4

C9

C12

E1

E4

E9

E12

H1

H12

A3

A10

G1

G12

L1

L12

V3

V10

J1

J12

B1

B4

L2

L11

P1

P4

P9

P12

T1

T4

T9

T12

B9

B12

D1

D4

D9

D12

G2

G11

CRITICAL

OMIT

16MX32-GDDR3-500MHZ

K4J52324QC-BC20

FBGA

C89761

2

0.1uF

X5R402

10%16V

L8965

1 2

0402

FERR-220-OHM

L8960

1 2

0402

FERR-220-OHM

C89511

2 X5R

0.1uF

402

10%16V

C89521

2

402

0.1uF

X5R

10%16V

C89601

2

0.1uF

X5R402

10%16V

C89531

2

0.1uF

X5R402

10%16V

C89651

2

0.1uF

X5R402

10%16V

C89541

2

0.1uF

X5R402

10%16V

C8900 1

2

OMIT

22UF20%

805CERM6.3V

C8920 1

2

OMIT

CERM

22UF

805

6.3V20%

C8950 1

2

OMIT

20%6.3VCERM805

22UF

C8970 1

2

OMIT

805

20%6.3VCERM

22UF

C89311

216V10%

402X5R

0.1uF

GDDR3 Frame Buffer A

89 105

B051-7270


FB_A_RDQS<7>

FB_A_RDQS<6>

FB_A_RAS_L<0>

FB_A_MA<0>

FB_A_MA<2>

FB_A_MA<3>

=PP1V8_S0_FB_VDD

PP1V8_S0_FB_A0_VDDA0MIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mmVOLTAGE=1.8V


=PP1V8_S0_FB_VDD



MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.25 mmFB_A1_VREF1

FB_A_DQ<46>

FB_A_DQ<43>

FB_A_DQ<42>

FB_A_DQ<41>

FB_A_DQ<40>

FB_A_DQ<38>

FB_A_DQ<37>

FB_A_DQ<36>

FB_A_DQ<33>

FB_A_DQ<34>FB_A_MA<5>

FB_A_MA<4>

FB_A_CKE<0>

FB_A_CAS_L<0>

FB_DRAM_RST

FB_A_RDQS<0>

FB_A0_SEN

FB_A_RDQS<1>

FB_A_RDQS<2>

FB_A_RDQS<3>

FB_A_CLK_P<0>

FB_A_DQM_L<1>

FB_A_BA<2> FB_A_BA<2>

FB_A_RAS_L<1>

=PP1V8_S0_FB_VDDQ


FB_A_WDQS<1>

FB_A_WDQS<2>

FB_A_MA<11>

FB_A_MA<6>

FB_A_MA<7>

FB_A_DQ<1>

FB_A_DQ<0>

FB_A_DQ<2>

FB_A_DQ<3>

FB_A_DQ<5>

FB_A_DQ<6>

FB_A_DQ<4>

FB_A_DQ<8>

FB_A_DQ<7>

FB_A_DQ<9>

FB_A_DQ<10>

FB_A_DQ<11>

FB_A_DQ<15>

FB_A_DQ<14>

FB_A_DQ<12>

FB_A_DQ<13>

FB_A_DQ<19>

FB_A_DQ<16>

FB_A_DQ<18>

FB_A_DQ<17>

FB_A_DQ<23>

FB_A_DQ<21>

FB_A_DQ<24>

FB_A_DQ<22>

FB_A_DQ<20>

FB_A_DQ<25>

FB_A_DQ<26>

FB_A_DQ<27>

FB_A_DQ<30>

FB_A_DQ<29>

FB_A_DQ<28>

FB_A_DQ<31>

FB_A0_MF

FB_A0_ZQ

FB_A_WE_L<0>

FB_A_CS_L<0>

FB_A_CLK_N<0>

FB_A_MA<9>

FB_A_MA<1>

FB_A_WDQS<0>

FB_A_WDQS<3>

FB_A_BA<0>

FB_A_BA<1>

FB_A_DQM_L<3>

FB_A_DQM_L<2>

FB_A_DQM_L<0>

FB_A_MA<8>

FB_A_MA<10>

FB_A_DQ<32>

FB_A_DQ<35>

FB_A_DQ<39>

FB_A_DQ<44>

FB_A_DQ<47>

FB_A_DQ<45>

FB_A_DQ<48>

FB_A_DQ<49>

FB_A_DQ<50>

FB_A_DQ<51>

FB_A_DQ<52>

FB_A_DQ<55>

FB_A_DQ<60>

FB_A_DQ<53>

FB_A_DQ<54>

FB_A_DQ<59>

FB_A_DQ<61>

FB_A_DQ<57>

FB_A_DQ<56>

FB_A_DQ<62>

FB_A_DQ<63>

FB_A_DQ<58>

FB_A_RDQS<5>

FB_A_RDQS<4>

FB_A1_SEN

FB_DRAM_RST

FB_A1_MF

FB_A1_ZQ

FB_A_CAS_L<1>

FB_A_WE_L<1>

FB_A_CS_L<1>

FB_A_CLK_N<1>

FB_A_MA<9>

FB_A_MA<6>

FB_A_MA<7>

FB_A_MA<3>

FB_A_MA<4>

FB_A_MA<2>

FB_A_MA<0>

FB_A_MA<1>

FB_A_CLK_P<1>

FB_A_WDQS<6>

FB_A_WDQS<5>

FB_A_WDQS<4>

FB_A_WDQS<7>

FB_A_BA<0>

FB_A_BA<1>

FB_A_DQM_L<7>

FB_A_DQM_L<6>

FB_A_DQM_L<5>

FB_A_DQM_L<4>

FB_A_MA<5>

FB_A_MA<11>

FB_A_MA<8>

FB_A_MA<10>

FB_A_CKE<1>



=PP1V8_S0_FB_VDDQ

73D8 73D8

73A8

73D8

73A8

73D8

73D5 73D5

73A5

73D5

73A5

73D5

72B5

72B5

72B5

72D5 72D8

72B5

72B5

72A5

72A5 72A8

72D8

72B5

72B5

72B5

72B5

72B5

72A5

72A5

72B5

72B5

72A8

72B8

72B8

72B8

72B8

72B8

72B8

72B8

72B8

72A8

72A8

72B8

72B8

72B8

72B8

72D5

70C5

70C5

70B5

70D5

70D5

70D5

65B6 65B6

70B7

70C7

70C7

70C7

70C7

70C7

70C7

70C7

70C7

70C7 70D5

70D5

70B5

70B5

70A1

70C5

70C5

70C5

70C5

70B5

70C5

70D5 70D5

70B5

65B6

70C5

70C5

70D5

70D5

70D5

70D7

70D7

70D7

70D7

70D7

70D7

70D7

70D7

70D7

70D7

70D7

70D7

70D7

70D7

70D7

70D7

70C7

70D7

70C7

70D7

70C7

70C7

70C7

70C7

70C7

70C7

70C7

70C7

70C7

70C7

70C7

70C7

70B5

70B5

70B5

70D5

70D5

70C5

70C5

70D5

70D5

70C5

70C5

70D5

70D5

70D5

70C7

70C7

70C7

70B7

70B7

70B7

70B7

70B7

70B7

70B7

70B7

70B7

70B7

70B7

70B7

70B7

70B7

70B7

70B7

70B7

70B7

70B7

70C5

70C5

70A1

70B5

70B5

70B5

70B5

70D5

70D5

70D5

70D5

70D5

70D5

70D5

70D5

70B5

70C5

70C5

70C5

70C5

70D5

70D5

70C5

70C5

70C5

70C5

70D5

70D5

70D5

70D5

70B5

65B6

DQ1

DQ0

DQ2

DQ3

DQ5

DQ6

DQ4

DQ8

DQ7

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ24

DQ23

DQ22

DQ25

DQ26

DQ27

DQ29

DQ28

DQ30

DQ31

RDQS3

RDQS2

RDQS1

RDQS0

SEN

RESET

MF

ZQ

RAS*

CAS*

WE*

CS*

CK*

A9

A6

A7

A3

A4

A2

A0

A1

CK

WDQS2

WDQS1

WDQS0

WDQS3

BA0

BA2

BA1

RFU1

RFU2

DM3

DM2

DM1

DM0

A5

A11

A8/AP

A10

CKE

MFHIGH

MFHIGH

MFHIGH

(1 OF 2)

VSS0

VSS1

VSS2

VSS5

VSS3

VSS4

VSS7

VSS6

VSSA0

VSSA1

VSSQ0

VSSQ1

VSSQ2

VSSQ3

VSSQ5

VSSQ6

VSSQ4

VSSQ7

VSSQ8

VSSQ9

VSSQ10

VSSQ11

VSSQ12

VSSQ13

VSSQ14

VSSQ16

VSSQ15

VSSQ17

VSSQ18

VSSQ19VDDQ19

VDDQ20

VDDQ21

VREF1

VREF0

VDDQ10

VDDQ11

VDDQ12

VDDQ13

VDDQ14

VDDQ15

VDDQ18

VDDQ16

VDDQ17

VDDQ9

VDDA1

VDDQ0

VDDQ1

VDDQ2

VDDQ5

VDDQ3

VDDQ4

VDDQ6

VDDQ7

VDDQ8

VDD0

VDD1

VDD2

VDD5

VDD3

VDD4

VDD6

VDD7

VDDA0

(2 OF 2)

IN

IN

IN

IN

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

DQ1

DQ0

DQ2

DQ3

DQ5

DQ6

DQ4

DQ8

DQ7

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ24

DQ23

DQ22

DQ25

DQ26

DQ27

DQ29

DQ28

DQ30

DQ31

RDQS3

RDQS2

RDQS1

RDQS0

SEN

RESET

MF

ZQ

RAS*

CAS*

WE*

CS*

CK*

A9

A6

A7

A3

A4

A2

A0

A1

CK

WDQS2

WDQS1

WDQS0

WDQS3

BA0

BA2

BA1

RFU1

RFU2

DM3

DM2

DM1

DM0

A5

A11

A8/AP

A10

CKE

MFHIGH

MFHIGH

MFHIGH

(1 OF 2)

VSS0

VSS1

VSS2

VSS5

VSS3

VSS4

VSS7

VSS6

VSSA0

VSSA1

VSSQ0

VSSQ1

VSSQ2

VSSQ3

VSSQ5

VSSQ6

VSSQ4

VSSQ7

VSSQ8

VSSQ9

VSSQ10

VSSQ11

VSSQ12

VSSQ13

VSSQ14

VSSQ16

VSSQ15

VSSQ17

VSSQ18

VSSQ19VDDQ19

VDDQ20

VDDQ21

VREF1

VREF0

VDDQ10

VDDQ11

VDDQ12

VDDQ13

VDDQ14

VDDQ15

VDDQ18

VDDQ16

VDDQ17

VDDQ9

VDDA1

VDDQ0

VDDQ1

VDDQ2

VDDQ5

VDDQ3

VDDQ4

VDDQ6

VDDQ7

VDDQ8

VDD0

VDD1

VDD2

VDD5

VDD3

VDD4

VDD6

VDD7

VDDA0

(2 OF 2)

IN

IN

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IN

IN

IO

IO

IN

IN

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE




(NONE)

(NONE)

- =PP1V8_S0_FB_VDD

- =PP1V8_S0_FB_VDDQ

U9000.J12U9000.J1

NC

NC NC

NC

U9000.J1 U9000.J12Connect to designated pin, then GNDConnect to designated pin, then GND

R90301

2

2.37K

MF-LF402

1%1/16W

R90311

2

5.49K

MF-LF402

1%1/16W

C90031

2

402

0.1uF

X5R

10%16V

C90021

2

0.1uF

X5R402

10%16V

C90041

2

0.1uF

X5R402

10%16V

C90011

2

0.1uF

X5R

10%16V

402

C90221

2

0.1uF

X5R402

10%16V

C90231

2

0.1uF

X5R402

10%16V

C90241

2

0.1uF

X5R402

10%16V

C90251

2

0.1uF

X5R402

10%16V

C90261

216V

402

0.1uF

X5R

10%

U9000K9

H11

K11

L9

K10

M9

K4

H2

K3

L4

K2

M4

G9

G4

H3

F9

J11

J10

H9

F4

E3

E10

N10

N3

B2

B3

C11

C10

E11

F10

F11

G10

M11

L10

N11

M10

C2

R11

R10

T11

T10

M2

L3

N2

M3

R2

R3

C3

T2

T3

E2

F3

F2

G3

B11

B10

A9

H10

D3

D10

P10

P3

V9

J2

J3

V4

D2

D11

P11

P2

H4

A4

OMIT

CRITICAL

FBGA

K4J52324QC-BC20

16MX32-GDDR3-500MHZ

U9000A2

A11

F1

F12

M1

M12

V2

V11

K1

K12

A1

A12

J4

J9

N1

N4

N9

N12

R1

R4

R9

R12

C1

V1

V12

C4

C9

C12

E1

E4

E9

E12

H1

H12

A3

A10

G1

G12

L1

L12

V3

V10

J1

J12

B1

B4

L2

L11

P1

P4

P9

P12

T1

T4

T9

T12

B9

B12

D1

D4

D9

D12

G2

G11

FBGA

OMIT

CRITICAL

K4J52324QC-BC20

16MX32-GDDR3-500MHZ

R90491

2

100

MF-LF402

5%1/16W

R90411

2

1K

1/16W5%

402MF-LF

R90481

2

243

MF-LF402

1%1/16W

R90451

2

60.4

MF-LF402

1%1/16W

R90461

2

1/16W1%

402MF-LF

60.4

C90331

216V10%

402X5R

0.1uF

R90321

2

2.37K

1/16W1%

402MF-LF

R90331

2

5.49K

MF-LF402

1%1/16W

C90211

2

402

0.1uF

X5R

10%16V

L9010

1 2

0402

FERR-220-OHM

L9015

1 2

0402

FERR-220-OHM C90151

2

0.1uF

X5R402

10%16V

C90101

2

0.1uF

X5R402

10%16V

R90401

2

1/16W

402MF-LF

1211%

R90471

2

1/16W

402MF-LF

1211%

R90441

2

1%121

MF-LF402

1/16W

R90431

2

1/16W

402MF-LF

1211%

R90421

2

1%121

MF-LF402

1/16W

R90911

2

1K

MF-LF402

5%1/16W

R90901

2

1%121

MF-LF402

1/16W

R90921

2

1/16W

402

1%121

MF-LF

C90711

2

0.1uF

16V10%

402X5R

C90721

2

0.1uF

16V10%

402X5R

R90981

2

1%243

MF-LF402

1/16W

R90991

2

1005%

MF-LF402

1/16W

U9050K9

H11

K11

L9

K10

M9

K4

H2

K3

L4

K2

M4

G9

G4

H3

F9

J11

J10

H9

F4

E3

E10

N10

N3

B2

B3

C11

C10

E11

F10

F11

G10

M11

L10

N11

M10

C2

R11

R10

T11

T10

M2

L3

N2

M3

R2

R3

C3

T2

T3

E2

F3

F2

G3

B11

B10

A9

H10

D3

D10

P10

P3

V9

J2

J3

V4

D2

D11

P11

P2

H4

A4

FBGA

CRITICAL

OMIT

K4J52324QC-BC20

16MX32-GDDR3-500MHZ

R90931

2

121

1/16W

402MF-LF

1%

R90951

2

60.4

1/16W1%

402MF-LF

R90941

2402

1%1/16WMF-LF

121

R90971

2

121

MF-LF1/16W1%

402

R90961

2

60.4

MF-LF402

1%1/16W

R90811

2

1/16W1%

5.49K

MF-LF402

R90801

2

1/16W1%

2.37K

MF-LF402

R90831

2

1%1/16W

402

5.49K

MF-LF

R90821

2

2.37K1%

1/16W

402MF-LF

C90731

2

0.1uF

16VX5R402

10%

C90811

216V10%

402X5R

0.1uF

C90741

2

0.1uF

X5R402

10%16V

C90751

2

0.1uF

16V10%

402X5R

C90831

2

0.1uF

X5R16V10%

402

U9050A2

A11

F1

F12

M1

M12

V2

V11

K1

K12

A1

A12

J4

J9

N1

N4

N9

N12

R1

R4

R9

R12

C1

V1

V12

C4

C9

C12

E1

E4

E9

E12

H1

H12

A3

A10

G1

G12

L1

L12

V3

V10

J1

J12

B1

B4

L2

L11

P1

P4

P9

P12

T1

T4

T9

T12

B9

B12

D1

D4

D9

D12

G2

G11

16MX32-GDDR3-500MHZ

FBGA

CRITICAL

OMIT

K4J52324QC-BC20

C90761

2

0.1uF

16V10%

402X5R

L9065

1 2

FERR-220-OHM

0402

L9060

1 2

FERR-220-OHM

0402

C90511

216V10%

402X5R

0.1uFC90521

216V10%

402X5R

0.1uF

C90601

2

0.1uF

X5R402

10%16V

C90531

2

0.1uF

X5R402

10%16V

C90651

2

0.1uF

X5R402

10%16V

C90541

216V10%

402X5R

0.1uFC9000 1

2

20%6.3VCERM805

22UF

OMIT

C9020 1

2

20%6.3VCERM805

22UF

OMIT

C9050 1

2

20%6.3VCERM805

22UF

OMIT

C9070 1

2

22UF20%6.3VCERM805

OMIT

C90311

2 X5R

0.1uF

402

10%16V

051-7270


GDDR3 Frame Buffer BSYNC_DATE=(MASTER)

B

10590

FB_B_MA<4>

FB_B_CS_L<1>

FB_B_MA<9>

FB_B_DQ<2>

FB_B_DQ<7>

FB_B_DQ<24>

FB_B_DQ<13>

FB_B_DQ<14>

FB_B_DQ<12>

FB_B_DQ<15>

FB_B_DQM_L<3>

FB_B_WDQS<1>

FB_B_RDQS<0>

FB_B_RDQS<3>

FB_B_RDQS<2>

FB_DRAM_RST

FB_B0_ZQ

FB_B0_SEN

FB_B_DQ<23>

FB_B_CLK_N<1>

FB_B_CAS_L<1>

FB_B_WE_L<1>

FB_B_RAS_L<1>

FB_B1_ZQ

FB_B_DQ<61>

FB_B_DQ<46>

FB_B_CLK_P<1>

FB_B_MA<1>

FB_B_MA<2>

FB_B_MA<3>

FB_B_CKE<1>

FB_B_DQ<58>

FB_B_DQ<59>

=PP1V8_S0_FB_VDDQ

FB_B_MA<5>

FB_B_MA<7>

FB_B_BA<0>

FB_B_BA<1>

FB_B_CKE<0>

FB_B_DQ<9>

FB_B_DQ<11>

FB_B_DQ<8>

FB_B_DQ<18>

FB_B_DQ<10>

FB_B_DQ<17>

FB_B_DQ<19>

FB_B_DQ<16>

FB_B_DQ<20>

FB_B_DQ<22>

FB_B_DQ<21>

FB_B_DQ<29>

FB_B_DQ<30>

FB_B_DQ<28>

FB_B_DQ<31>

FB_B_DQ<27>

FB_B_DQ<1>

FB_B_DQ<25>

FB_B_DQ<26>

FB_B_DQ<6>

FB_B_DQ<0>

FB_B_DQ<5>

FB_B_DQ<3>

FB_B_DQ<4>

FB_B_RDQS<1>

FB_B0_MF

FB_B_CAS_L<0>

FB_B_WE_L<0>

FB_B_CS_L<0>

FB_B_CLK_N<0>

FB_B_MA<9>

FB_B_MA<6>

FB_B_MA<7>

FB_B_MA<0>

FB_B_MA<1>

FB_B_WDQS<3>

FB_B_WDQS<2>

FB_B_WDQS<0>

FB_B_DQM_L<0>

FB_B_DQM_L<2>

FB_B_DQM_L<1>

FB_B_MA<5>

FB_B_MA<11>

FB_B_MA<8>

FB_B_MA<10>

FB_B_DQ<53>

FB_B_DQ<54>

FB_B_DQ<52>

FB_B_DQ<55>

FB_B_DQ<48>

FB_B_DQ<49>

FB_B_DQ<50>

FB_B_DQ<44>

FB_B_DQ<51>

FB_B_DQ<47>

FB_B_DQ<45>

FB_B_DQ<43>

FB_B_DQ<41>

FB_B_DQ<42>

FB_B_DQ<40>

FB_B_DQ<37>

FB_B_DQ<32>

FB_B_DQ<39>

FB_B_DQ<34>

FB_B_DQ<36>

FB_B_DQ<35>

FB_B_DQ<63>

FB_B_DQ<33>

FB_B_DQ<62>

FB_B_DQ<60>

FB_B_DQ<56>

FB_B_DQ<57>

FB_B_RDQS<7>

FB_B_RDQS<4>

FB_B_RDQS<6>

FB_B1_SEN

FB_DRAM_RST

FB_B1_MF

FB_B_MA<6>

FB_B_WDQS<4>

FB_B_WDQS<5>

FB_B_WDQS<6>

FB_B_WDQS<7>

FB_B_BA<0>

FB_B_BA<1>

FB_B_DQM_L<7>

FB_B_DQM_L<4>

FB_B_DQM_L<5>

FB_B_DQM_L<6>

FB_B_MA<11>

FB_B_MA<8>

MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.25 mmFB_B1_VREF1




FB_B_RAS_L<0>

FB_B_BA<2> FB_B_BA<2>

FB_B_RDQS<5>

FB_B_MA<10>

FB_B_DQ<38>

=PP1V8_S0_FB_VDDQ

FB_B_MA<4>

FB_B_MA<3>

FB_B_MA<2>

FB_B_CLK_P<0>

PP1V8_S0_FB_B1_VDDA1MIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mmVOLTAGE=1.8V


=PP1V8_S0_FB_VDD



=PP1V8_S0_FB_VDD

FB_B_MA<0>

73A5

73D5

73A8

73D8

73D8 73D5

72A8

72D8

72A8

72D8

72D8 72D8

73B8

73B8

72A5

73B8

73B8

73B8

72D5

73B8

73B8

73A5

73A5

73B5

73B5

73B5

73B5

73B5

73B5

73B5

73B5

73B5

72A5

73B8

73A8

73A8

73B8

73B8

73A5 73A8

73B8

72D5

73B5

73B5

73B5

72D5 72D5

73B8

70D1

70B1

70D1

70D3

70D3

70C3

70D3

70D3

70D3

70D3

70C1

70C1

70C1

70C1

70C1

70A1

70C3

70B1

70B1

70B1

70B1

70B3

70B3

70B1

70D1

70D1

70D1

70B1

70B3

70B3

65B6

70D1

70D1

70D1

70D1

70B1

70D3

70D3

70D3

70C3

70D3

70D3

70C3

70D3

70C3

70C3

70C3

70C3

70C3

70C3

70C3

70C3

70D3

70C3

70C3

70D3

70D3

70D3

70D3

70D3

70C1

70B1

70B1

70B1

70B1

70D1

70D1

70D1

70D1

70D1

70C1

70C1

70C1

70D1

70C1

70C1

70D1

70D1

70D1

70D1

70B3

70B3

70B3

70B3

70B3

70B3

70B3

70B3

70B3

70B3

70B3

70C3

70C3

70C3

70C3

70C3

70C3

70C3

70C3

70C3

70C3

70B3

70C3

70B3

70B3

70B3

70B3

70C1

70C1

70C1

70A1

70D1

70C1

70C1

70C1

70C1

70D1

70D1

70C1

70C1

70C1

70C1

70D1

70D1

70B1

70D1 70D1

70C1

70D1

70C3

65B6

70D1

70D1

70D1

70B1

65B6 65B6

70D1

GPIO_0

GPIO_1

TESTEN

GPIO_2

GPIO_27

PLLTEST

XTALOUT

XTALIN

MPVSS

MPVDD

PVSS

PVDD

GPIO_16

GPIO_17

GPIO_15

GPIO_14

GPIO_13

GPIO_12

GPIO_11

GPIO_10

GPIO_9

GPIO_8

GPIO_7_BLON

GPIO_6

GPIO_5

GPIO_4

GPIO_3

VREFG

GPIO_33

GPIO_31

GPIO_32

GPIO_25

GPIO_26

GPIO_24

GPIO_21

GPIO_20

GPIO_19

DMINUS

DPLUS

ROMCS*

GPIO_34

GPIO_29

GPIO_30

NC_DVOVMODE_0

NC_DVOVMODE_1

DVPCLK

DVPCNTL_0

DVPCNTL_1

DVPCNTL_2

DVPDATA_2

DVPDATA_1

DVPDATA_0

DVPDATA_4

DVPDATA_3

DVPDATA_5

DVPDATA_7

DVPDATA_6

DVPDATA_9

DVPDATA_8

DVPDATA_10

DVPDATA_11

DVPDATA_13

DVPDATA_12

DVPDATA_15

DVPDATA_14

DVPDATA_16

DVPDATA_18

DVPDATA_17

DVPDATA_19

DVPDATA_21

DVPDATA_20

DVPDATA_23

DVPDATA_22

GENERICA

GENERICB

GENERICC

GENERICD

DIGON

VARY_BL

NC0

GPIO_18

VDDPLL

GPIO_28

GPIO_22

GPIO_23

GENERAL PURPOSE I/O

(1.2V)

(2.5V)

ROM

TEST

PLL & XTAL

VIP HOST / EXTERNAL TMDS

PANELCONTROL

VDDR3(3.3V)

(2.5V)VDD25

VDDR5

(1.8V/3.3V)

(1.8V/3.3V)

VDDR4

DIODETHERMAL

(2.5V)

(6 OF 7)

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

100mA


Typically <50mA

Typically <50mA

Typically <50mA

20mA

external TMDS transmitters

- =PP2V5_PVDD

(NONE)

external TMDS transmitters

- =PP1V8_GPU_LVDS_PLL

- =PP3V3_GPU_GPIOS

- =I2C_GPU_TMDS_SDA - I2C data line for

(PP2V5_S0_GPU_PVDD_F)

(GND_GPU_MPVSS)

(GND_GPU_PVSS)


NC

NC

NC

NC

(PP1V0R1V2_S0_GPU_MPVDD)

Page Notes

- =I2C_GPU_TMDS_SCL - I2C clock line for


70mA total for VDD25

20mA

C91121

2

10%16VX5R

0.1uF

402

C91111

26.3VCERM

1uF

402

10%

C91161

2

402

1uF

6.3VCERM

10%

C91171

26.3VCERM

1uF10%

402

C91371

2

10%

X5R402

0.1uF

16V

C91361

26.3VCERM402

10%1uF

L9135

1 2

FERR-220-OHM

0402

C91411

26.3VCERM

1uF

402

10%

L9140

1 2

FERR-220-OHM

0402

C91421

2 X5R16V

0.1uF10%

402

R91951

2

5%1/16WMF-LF402

1K

XW9140

1 2

SM

R91911

2

1%499

1/16WMF-LF402

R91901

2

1%499

402MF-LF1/16W

XW9135

1 2

SM

C9100 1

2

OMIT

22UF

805CERM6.3V20%

C9110 1

2

OMIT

20%6.3VCERM805

22UF

C9115 1

2

OMIT

22UF

805CERM6.3V20%

C9120 1

2

OMIT

20%6.3VCERM805

22UF

C9125 1

2

OMIT

22UF

805CERM6.3V20%

C91321

2

10%

402

1uF

6.3VCERM

C9130 1

2

OMIT

22UF

805CERM6.3V20%

C9135 1

2

OMIT

805CERM6.3V20%

22UF

C9140 1

2

OMIT

22UF

805CERM6.3V20%

C9191 1

2

10%16VX5R402

0.1uF

U8400

AE11

AH12

AG12

AG1

AF2

AF1

AF3

AG2

AG3

AL3

AM3

AE6

AF4

AF5

AG4

AJ3

AH4

AJ4

AG5

AH2

AH5

AF6

AE7

AG6

AH3

AJ2

AJ1

AK2

AK1

AK3

AL2

AK22

AF23

AE23

AD23

AD4

AD2

AC4

AB3

AB4

AB5

AD5

AB8

AA8

AB7

AE13

AF13

AD1

AF9

AG7

AE10

AE9

AF7

AF8

AH6

AF10

AG10

AH9

AD3

AJ8

AH8

AG9

AH7

AG8

AC1

AC2

AC3

AB2

AC6

AC5

A6

A5

AB6

AK4

AL4

AG14

AJ14

AH14

AC7

AG22

AD12K22

L10

AA10

AC13

AC16

AC18

AC15

AA9

AB9

AB10

AC19

AC20

AD18

AD19

AD20

AJ5

AK5

AL5

AM5

AE2

AE3

AE4

AE5

AC8

AL26

AM26

OMIT

BGA

M56P

C91271

2

0.1uF

402X5R16V10%

C91261

2

10%

402

1uF

CERM6.3V

C91221

2

10%16VX5R

0.1uF

402

C91211

26.3VCERM

1uF10%

402

L9120

1 2

FERR-220-OHM

0402

L9125

1 2

FERR-220-OHM

0402

L9130

1 2

200-OHM-EMI

0402

C91311

2

10%

402CERM6.3V

1uF

C91011

2

10%

402

1uF

CERM6.3V

C91021

26.3V

1uF10%

402CERM

C91031

26.3VCERM

1uF

402

10%


ATI M56 GPIO/DVO/Misc

91 105

B051-7270

=PPVCORE_S0_GPU


VOLTAGE=1.2V

PPVCORE_S0_GPU_MPVDD

=PP2V5_S0_GPU_PVDD


VOLTAGE=2.5V

PP2V5_S0_GPU_PVDD_F

=PP1V2_S0_GPU_VDDPLL


VOLTAGE=1.2V

PP1V2_S0_GPU_VDDPLL



VOLTAGE=3.3V

PP1V8R3V3_S0_GPU_VDDR5_F



VOLTAGE=3.3V

PP1V8R3V3_S0_GPU_VDDR4_F

GPU_GPIO_4GPU_GPIO_24

ATI_VREFG

=PP3V3_S0_GPU

ATI_TESTEN

GPU_GPIO_23

GPU_GPIO_22

GPU_GPIO_28

GPU_GPIO_18

GPU_VARY_BL

GPU_DIGON

GPU_GENERICD

GPU_GENERICC

GPU_GENERICB

GPU_GENERICA

ATI_DVPDATA<22>

ATI_DVPDATA<23>

ATI_DVPDATA<20>

ATI_DVPDATA<21>

ATI_DVPDATA<17>

ATI_DVPDATA<18>

ATI_DVPDATA<16>

ATI_DVPDATA<14>

ATI_DVPDATA<15>

ATI_DVPDATA<12>

ATI_DVPDATA<13>

ATI_DVPDATA<11>

ATI_DVPDATA<10>

ATI_DVPDATA<8>

ATI_DVPDATA<9>

ATI_DVPDATA<6>

ATI_DVPDATA<7>

ATI_DVPDATA<5>

ATI_DVPDATA<3>

ATI_DVPDATA<4>

ATI_DVPDATA<1>

ATI_DVPCNTL<2>

ATI_DVPCNTL<1>

ATI_DVPCNTL<0>

ATI_DVPCLK

GPU_GPIO_29

GPU_GPIO_34

TP_ATI_ROMCS_L

ATI_TDIODE_N

GPU_GPIO_19

GPU_GPIO_20

GPU_GPIO_21

GPU_GPIO_26

GPU_GPIO_25

GPU_GPIO_32

GPU_GPIO_33

GPU_GPIO_3

GPU_GPIO_5

GPU_GPIO_6

GPU_GPIO_7

GPU_GPIO_9

GPU_GPIO_10

GPU_GPIO_11

GPU_GPIO_12

GPU_GPIO_13

GPU_GPIO_14

GPU_GPIO_15

GPU_GPIO_17

GPU_GPIO_16

GPU_XTALIN

GPU_XTALOUT

GPU_GPIO_27

GPU_GPIO_2

GPU_GPIO_1

GPU_GPIO_0

ATI_TDIODE_P

ATI_DVPDATA<2>

ATI_DVPDATA<19>

ATI_DVPDATA<0>

GPU_GPIO_8

GPU_GPIO_31

GPU_GPIO_30

=PP2V5_S0_GPU_VDDC_CT

=PP2V5_S0_GPU_VDD25

=PP3V3_S0_GPU_VDDR3

GND_GPU_PVSS

VOLTAGE=0V


GND_GPU_MPVSS

VOLTAGE=0V


69D8 65A6 53C7

68C4

79B6

53A5

65A6

65C6

65A3

65A3

71C8 71B8

65A3

71B8

71B8

71B8

71B8

79A4

79A4

68A7

71C1

71C1

71C1

71B1

71B1

71B1

71B1

71B1

71B1

71B1

71B1

71B1

71B1

71B1

71B1

71B1

71B1

71B1

71B1

71B1

71B1

71B1

71B1

71B1

71B1

71B1

71B1

71B1

71B8

71B8

71C1

52B6

71B8

71B8

71B8

71B8

71B8

71B8

71B8

71C8

71C8

71C8

71C8

71C8

71C8

71C8

71C8

71C8

71C8

71C8

71C8

71C8

71C1

71C1

71B8

71C8

71C8

71D8

52B6

71B1

71B1

71B1

71C8

71B8

71B8

65A6

65A6

65A3

DDC3DATA

DDC3CLK

DDC2DATA

DDC2CLK

DDC1DATA

DDC1CLK

TXOUT_L3N

TXOUT_L3P

TXOUT_L2N

TXOUT_L2P

TXOUT_L1N

TXOUT_L1P

TXOUT_L0N

TXOUT_L0P

TXCLK_LP

TXCLK_LN

TXOUT_U3N

TXOUT_U2N

TXOUT_U3P

TXOUT_U2P

TXOUT_U1N

TXOUT_U1P

TXOUT_U0N

TXOUT_U0P

TXCLK_UN

TXCLK_UP

COMP

C

Y

V2SYNC

H2SYNC

B2

G2

R2

VSYNC

HSYNC

B

G

R

TX2M

TX2P

TX1M

TX0M

TX1P

TX0P

TXCM

HPD1

LPVSS

LPVDD

R2SET

VDD2DI

VSS2DI

A2VSSQ

NC_A2VDDQ

VSS1DI

RSET

AVSSQ

VDD1DI

TXCP

TPVSS

TPVDD

TX3P

TX3M

TX4P

TX4M

TX5P

TX5M

A2VSS

A2VDD(2.5V)

AVSS

(2.5V)AVDD

TXVSSR

IDENTIFICATION

(5 OF 7)

LVDDR

LVSSR

DAC (CRT)

DAC2 (TV/CRT2)

LVDS

MONITOR

TXVDDR

(2.5V)

(2.5V)

(2.5V)

(2.5V)

(2.5V)

(2.5V)

INTEGRATED TMDS

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IO

IO

IO

IO

IO

IO

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

20mA peak

20mA peak

20mA peak

130mA peak

- =PP1V8R2V5_S0_GPU_LVDDR

- =PP2V5_S0_GPU

(NONE)

(NONE)


NC

150mA peak

65mA peak

200mA peak

Comp B Pb

C R Pr

Y G Y

Composite/S-Video VGA Component

20mA peak



Sum of peak currents on this page: 605mA

Page Notes

U8400

AL16

AM16

AL17

AM17

AK13

AL25

AM25

AJ24

AK25

AK23AL24

AL15

AJ13

AH15

AH23

AH22

AG13

AH13

AF12

AE12

AM24

AM15

AF15

AF11

AJ23

AE19

AE18

AC21

AC22

AD21

AD22

AE20

AE21

AE22

AF19

AF20

AF17

AF18

AF21

AF22

AG17

AG19

AH17

AH19

AJ19

AK17

AL14

AK24

AK15

AK14

AL22

AM8

AL8

AK10

AL10

AL11

AM11

AL12

AM12

AK9

AJ9

AK11

AJ11

AK12

AJ12

AL18

AM18

AK21

AJ21

AL9

AM9

AK19

AL19

AL20

AM20

AL21

AM21

AK18

AJ18

AH18

AG18

AJ20

AK20

AH20

AG20

AG21

AH21

AJ6

AK6

AL6

AM6

AJ7

AK7

AK8

AL7

AM7

AG15

AM23

AJ16

AL23

AJ17

AJ22

AJ15

OMIT

M56PBGA

R93501

2

499

MF-LF402

1%1/16W

C93461

216V10%

402X5R

0.1uFC93421

216V10%

402X5R

0.1uFC93411

2

10%1uF

CERM402

6.3V

L9300

1 2

FERR-220-OHM

0402

C93011

2

402

6.3V10%

CERM

1uF

C93061

26.3V10%

402CERM

1uF

L9305

1 2

FERR-220-OHM

0402

C93071

216V

0.1uF

X5R402

10%

L9330

1 2

FERR-220-OHM

0402

C93311

2

1uF

CERM402

10%6.3V

C93221

216V

0.1uF10%

402X5R

C93211

26.3VCERM

10%

402

1uF

L9320

1 2

FERR-220-OHM

0402

C93121

216V

0.1uF

X5R402

10%

C93111

2

402

1uF

CERM

10%6.3V

L9310

1 2

FERR-220-OHM

0402

C93171

2

402

0.1uF

X5R

10%16V

C93161

2

1uF10%6.3VCERM402

C93271

2

0.1uF

X5R402

10%16V

C93261

2

1uF10%

CERM402

6.3V

L9325

1 2

FERR-220-OHM

0402

L9315

1 2

FERR-220-OHM

0402

L9345

1 2

FERR-220-OHM

0402

C93471

216V10%

402X5R

0.1uFC9340 1

2

22UF

805CERM6.3V20%

OMIT

C9345 1

2

22UF

805CERM6.3V20%

OMIT

C93321

2

1uF

CERM402

10%6.3V

C93021

26.3V

402

10%

CERM

1uFC9300 1

2

20%22UF

805CERM6.3V

OMIT

C9305 1

2

20%6.3VCERM805

22UF

OMIT

C9310 1

2

22UF

805CERM6.3V20%

OMIT

C9315 1

2

20%6.3VCERM805

22UF

OMIT

C9320 1

26.3V

805

22UF

CERM

20%

OMIT

C9325 1

2

805

22UF20%6.3VCERM

OMIT

C9330 1

2CERM

22UF

805

6.3V20%

OMIT

R93511

2

1/16W1%

402MF-LF

715

ATI M56 Video InterfacesSYNC_DATE=(MASTER)SYNC_MASTER=(MASTER)

051-7270 B

10593

GPU_TV_C

GPU_TV_COMP

GPU_TV_Y

GPU_VGA_R

GPU_VGA_G

GPU_VGA_B

GPU_R2

GPU_G2

GPU_B2

GPU_V2SYNC

ATI_R2SET

ATI_RSET

GPU_HPD

LVDS_U_DATA_N<3>

LVDS_U_DATA_P<3>

LVDS_U_DATA_N<1>

LVDS_U_DATA_P<1>

LVDS_L_CLK_P

LVDS_L_DATA_P<0>

LVDS_L_DATA_P<1>

LVDS_L_DATA_N<0>

GPU_VGA_VSYNC

GPU_VGA_HSYNC

LVDS_U_CLK_P

LVDS_U_CLK_N

LVDS_U_DATA_P<0>

LVDS_U_DATA_N<0>

TMDS_CLK_N

TMDS_DATA_N<0>

TMDS_DATA_N<1>

TMDS_DATA_N<2>

TMDS_DATA_N<5>

TMDS_DATA_N<4>

TMDS_DATA_N<3>

LVDS_L_DATA_N<1>

LVDS_L_DATA_N<2>

LVDS_L_DATA_P<2>

LVDS_L_DATA_P<3>

LVDS_L_DATA_N<3>

GPU_DDC_A_CLK

GPU_DDC_B_DATA

GPU_DDC_B_CLK

GPU_DDC_A_DATA

ATI_RSET

ATI_R2SET

LVDS_U_DATA_N<2>

LVDS_U_DATA_P<2>

LVDS_L_CLK_N

GPU_DDC_C_CLK

GPU_DDC_C_DATA

GPU_H2SYNC

TMDS_CLK_P

TMDS_DATA_P<5>

TMDS_DATA_P<4>

TMDS_DATA_P<3>

TMDS_DATA_P<2>

TMDS_DATA_P<1>

TMDS_DATA_P<0>

VOLTAGE=2.5V


PP2V5_S0_GPU_TPVDD

VOLTAGE=2.5V

PP2V5_S0_GPU_TXVDDRMIN_LINE_WIDTH=0.3 mmMIN_NECK_WIDTH=0.25 mm

VOLTAGE=2.5V

PP2V5_S0_GPU_AVDDMIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mm

VOLTAGE=2.5V


PP2V5_S0_GPU_VDD1DI

PP2V5_S0_GPU_A2VDD

VOLTAGE=2.5V


VOLTAGE=2.5V


PP2V5_S0_GPU_VDD2DI

VOLTAGE=2.5V

PP2V5_S0_GPU_LPVDDMIN_LINE_WIDTH=0.2 mmMIN_NECK_WIDTH=0.2 mm

=PP2V5_S0_GPU

PP2V5_S0_GPU_LVDDR

VOLTAGE=2.5V


84B4

84A4

84A4

77C3

77C3

77C3

79C3

79C3

79C3

79C3

79C3

79C3

79C3

79C3

79C3

79C3

79C3

79C3

79C3

79C3

79B3

79C3

77B8

77B8

77D8

71B1

71B1

71C1

71C1

71C1

71C1

76D7

76D7

76D7

77D5

75A8

75A8

77A1

71B1

71B1

76D7

76D7

76D7

76D7

76D7

76D7

71C1

71C1

76D7

76D7

76D7

76D7

76D7

76D7

76D7

71B1

71B1

77B1

71A2

71A2

77B1

75B5

75B5

76D7

76D7

76D7

79A7

79A7

77C5

76C7

76C7

76C7

65A6

D

S

G

G

D

S

N-CHN

S

D

G

P-CHN

G

DS

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

LCD (LVDS) INTERFACE

INVERTER EXPECTS ACTIVE HIGH PWM SIGNAL

518S0289

NC

NET_TYPE

INVERTER INTERFACE

PHYSICALSPACING

no-panel case (development).

100K pull-ups are for

Panel has 2K pull-ups


518S0369

NC

NC

R94501

2

1/16W5%

402MF-LF

100K

C9454 1

250V20%

402CERM

0.001uF

C94521

2

0.001uF

CERM402

20%50V

C94501

2

0.001uF

402

20%50VCERM

C9451 1

26.3V20%

603X5R

10UF

L9454

1 2

400-OHM-EMI

SM-1

C9453 1

2

0.1uF

CERM402

20%10V

L9452

1 2

400-OHM-EMI

SM-1

C9420 1

2402

50V20%

CERM

0.001uF

C9410 1

250V20%

CERM

0.001uF

402

C9421

12

50V

402CERM

20%

0.001uF

J9400

33

34

1

10

11

12

13

14

15

16

17

18

19

2

20

21

22

23

24

25

26

27

28

29

3

30

4

5

6

7

8

9

CRITICAL

F-RT-SMMSC-RB30-5-FA

C9401 1

2402

50V20%

CERM

0.001uF

L9400FERR-250-OHM

SM

C9400

1 2

402

10%

0.0022uF

CERM50V

R9401

5%1/16W

402MF-LF

100K

R94001

2

100K

1/16W5%

402MF-LF

Q9400

1

2

5

63

4

SI3443DVTSOP-LF

Q9401

3

1

2

SOT23-LF2N7002

R94891

2402

MF-LF1/16W

5%100K

R94941

2

1/16WMF-LF402

5%100K

U9453

3

2

1

4

5

SC70MC74VHC1G08

Q9450

6

2

1

FDG6332C_NLSC70-6

Q9450

3

5

4

FDG6332C_NLSC70-6

R94111

2402

100K5%1/16WMF-LF

R94101

2402MF-LF1/16W

5%100K

L9455

1

2

0603FERR-220-OHM-2A

CRITICAL

L9450

1 2

CRITICAL

FERR-220-OHM-2A

0603

J9450

5

6

1

2

3

4

M-RT-SMSM04B-ACH

CRITICAL

Internal Display Connectors

051-7270 B

10594


=INVERTER_PWM_PLT_RST_L

=PP3V3_S0_INVERTER

INVERTER_PWM_UNBUF

INVERTER_PWM_F

GND_INVERTER

INVERTER_PWM

VOLTAGE=5VMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mmPP5V_INVERTER_SW

PPBUS_S0_INVERTERMIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mmVOLTAGE=12.8V

=PPBUS_S0_INVERTER

=GND_CHASSIS_INVERTER

VGAVGA GPU_R2

VGAVGA GPU_B2

LVDS LVDS LVDS_U_CLK_P

TMDSTMDS TMDS_CLK_P

LVDSLVDS LVDS_L_DATA_CONN_N<2..0>

TMDSTMDS TMDS_DATA_N<5..3>

TMDSTMDS TMDS_DATA_N<2..0>

LVDSLVDS LVDS_U_DATA_N<2..0>LVDSLVDS LVDS_U_DATA_P<2..0>

LVDS LVDS LVDS_U_CLK_N

=PP3V3_S0_DDC_LCD

LVDS_CONN_DDC_CLK

LVDS_CONN_DDC_DATA

VGAVGA GPU_G2

LVDS LVDS LVDS_L_DATA_N<2..0>LVDSLVDS LVDS_L_DATA_P<2..0>LVDSLVDS LVDS_L_CLK_N

LVDS LVDS LVDS_L_CLK_P

TMDSTMDS TMDS_DATA_P<5..3>

TMDSTMDS TMDS_DATA_P<2..0>

TMDSTMDS TMDS_CLK_N

LVDS LVDS LVDS_L_DATA_CONN_P<2..0>LVDS LVDS LVDS_L_CLK_CONN_N

LVDSLVDS LVDS_L_CLK_CONN_P

LVDS LVDS LVDS_U_DATA_CONN_N<2..0>LVDS LVDS LVDS_U_DATA_CONN_P<2..0>

LVDSLVDS LVDS_U_CLK_CONN_N

LVDS_U_CLK_CONN_PLVDS LVDS

LVDS_U_CLK_CONN_P

LVDS_U_CLK_CONN_N

LVDS_U_DATA_CONN_P<2>

LVDS_U_DATA_CONN_N<2>




LVDS_L_DATA_CONN_N<1>

LVDS_L_DATA_CONN_P<1>



LVDS_L_CLK_CONN_P

LVDS_L_CLK_CONN_N




=PP3V3_S0_LCD

LCD_PWREN_L

LVDS_PANEL_EN

LCD_PWREN_L_RC PP3V3_LCD_SWMIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mmVOLTAGE=3.3V

=GND_CHASSIS_LCD1

VOLTAGE=3.3VMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mmPP3V3_LCD_CONN

=GND_CHASSIS_LCD4

=GND_CHASSIS_LCD3

FP_PWR_EN_L

INVERTER_BKLTON


MIN_LINE_WIDTH=0.5 mmPP5V_INVERTER_SW_F

=PP5V_S0_INVERTER

=GND_CHASSIS_LCD279D1

84A4

84A4

84A4

84A4

79C1

79D1

79C1

84B4

79C1

77B8

77D8

79C3

77B8

77D8

84B4

76C2

79C1

79C1

79C1

76C2

79C1

79C1

79C1

79C1

79C1

79D1

79C1

79C1

79D1

79C1

79C1

79C1

79C1

79C1

79C1

79D1

79C1

79C1

77C3

77C3

79C3

77B8

76C2

77A8

77C8

79C3

79B3

79C3

77C3

79C3

79C3

79C3

79C3

77A8

77C8

77C8

6B1

76C2

76C2

76C2

76B2

76B2

76B2

76D7

76D7

76D7

76D7

76D7

76D7

76D7

76D7

76D7

76D7

76D7

76D7

76D7

76D7

76D7

76D7

6C4

65B3

79A2

5A4

5A4

5A4

5A4

65C1

6A6

75B3

75B3

75B3

75C3

6A1

75C3

75C3

75B3

75B3

75B3

65B3

79A5

79A5

75B3

75A3

75A3

75A3

75A3

75C3

75C3

75C3

6A1

6B1

6B1

6B1

6B1

6B1

6B1

6B1

6B1

6B1

6B1

6B1

6B1

6B1

6A1

6A1

6A1

6A1

6B1

6B1

6B1

6A1

6B1

65C3

79A2

79B6

6A6

6A6

6A6

79A2

65A1

6A6

G

SD

G

SD

G

SD

LCFILTER

LCFILTER

LCFILTER

SYM_VER-1

G

SD

SYM_VER-1

SYM_VER-1

SYM_VER-1

SYM_VER-1

SYM_VER-1

SYM_VER-1

G

S D

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

Place termination components close to GPU, common mode chokes near connector.

(55mA requirement per DVI spec)

PLACE NEAR C5A & C5B

(PP5V_S0_DDC)

(DAC2 C)

Isolation required for DVI power switch

514-0278

PLACE NEAR 3, 11 & 19

3V LEVEL SHIFTERS

DVI DDC CURRENT LIMIT

DVI INTERFACE

VGA SYNC BUFFERS

ANALOG FILTERING

PLACE CLOSE TO CONNECTOR

(DAC2 Y)

(DAC2 Comp)

PLACE U9750 & U9751 CLOSE TO DVI CONNECTOR

ELECTRICAL_CONSTRAINT_SET PHYSICAL

NET_TYPE

SPACING

TMDS Filtering

R97211

2

1/16W

10K

402MF-LF

5%

R97201

2

10K

MF-LF402

5%1/16W

Q9711

6

2

1

2N7002DW-X-FSOT-363

Q9711

3

5

4

2N7002DW-X-FSOT-363

R97221

2

1/16WMF-LF

270K

402

5%

C97131

2

5%100pF

50VCERM402

R97121

2

MF-LF

4.7K

1/16W5%

402

R97101

2

5%4.7K

MF-LF402

1/16W

C97111

2

100pF

50V5%

402CERM

C9710 1

2

20%50V

603CERM

0.01uF

L9710

1 2

SM-1

400-OHM-EMI

Q9714

3

5

4

2N7002DW-X-FSOT-363

F9710

1 2

SM-LF

0.5AMP-13.2V

CRITICAL

D9710

1 2

SOD-123

B0530WXF

C97141

2

402

50V5%

CERM

100pF

R97111 2

100

1/16W5%

402MF-LF

R97131 2

402

100

1/16W5%

MF-LF

R97141 2

MF-LF402

5%1/16W

100

R973012

0

1/16WMF-LF

5%

402

R973112

402

1/16W5%

MF-LF

0

C97411

250V0.25%

402CERM

3.3pF

R97421

2

75

MF-LF402

1%1/16W

R97401

2

75

MF-LF402

1%1/16W

R97411

2

75

MF-LF402

1%1/16W

C97421

250V0.25%

402CERM

3.3pF

C97401

250V0.25%

402CERM

3.3pF

FL9740

1 2

3 4

SM-220MHZ-LF

CRITICAL

FL9741

1 2

3 4

CRITICAL

SM-220MHZ-LF

FL9742

1 2

3 4

SM-220MHZ-LF

CRITICAL

R97501 2

402MF-LF1/16W5%

33

R97511 2

33

MF-LF402

5%1/16W

J9700

C1

C2

C3

C4

C5AC5B

31

32

33

34

1

10

11

12

13

14

15

16

17

18

19

2

20

21

22

23

24

3

4

5

6

7

8

9

CRITICAL

F-RT-TH-DVIQH11121-RIG02-4F

R97151

2

MF-LF402

5%1/16W

20K

R97861

2

1/16W

182

MF-LF402

1%

R97821

2

1821%

1/16WMF-LF402

R97781

2

182

402

1/16W1%

MF-LF

R97731 2

5%1/16WMF-LF

0

402

R97721 2

0

1/16WMF-LF402

5%

R97701

2

1%1/16WMF-LF

182

402

R97661

2

1/16W1%

402

182

MF-LF

L9706

1

2 3

4

370-OHMSM

CRITICAL

C9751 1

2CERM

20%10V

0.1uF

402

C9750 1

2

20%10VCERM402

0.1uF

U9750

3

2

1

4

5 MC74VHC1G08SC70

U9751

3

2

1

4

5 MC74VHC1G08SC70

R97621

2

1%182

MF-LF402

1/16W

L9743

1

2

040247nH

L9748

1

2

47nH0402

L9747

1

2

47nH0402

L9746

1

2

040247nH

L9745

1

2

47nH0402

L9744

1

2

040247nH

Q9715

6

2

1

SOT-3632N7002DW-X-F

R97231

2 402MF-LF1/16W5%270K

R97741

2402

1%

MF-LF1/16W

182

L9700

1

2 3

4

1210-4SM190-OHM-100MA

CRITICAL

L9701

1

2 3

4

CRITICAL

90-OHM-100MA1210-4SM1

L9702

1

2 3

4

1210-4SM190-OHM-100MA

CRITICAL

L9704

1

2 3

4

CRITICAL

90-OHM-100MA1210-4SM1

L9703

1

2 3

4

CRITICAL

90-OHM-100MA1210-4SM1

L9705

1

2 3

4

CRITICAL

90-OHM-100MA1210-4SM1

Q9714

6

2

1

2N7002DW-X-FSOT-363

SYNC_MASTER=M59_MG

External Display Connector

97 105

B


051-7270

=PP5V_S0_SB_HPD

MAKE_BASE=TRUESB_DVI_HPD

DVI_HPD

SB_GPIO4

GPU_HPD_BILAT

GPU_HPD

=PP3V3_D3C_DDC_DVI

=GPU_HPD_ENABLE

TMDS_DATA_F_P<4>

TMDS_DATA_F_N<4>

TMDS_DATA_F_N<3>

=GND_CHASSIS_DVI3

TMDS_DATA_F_N<5..0>TMDSCONNTMDSCONN

TMDS_DATA_F_P<5..0>TMDSCONN TMDSCONN

TMDS_CLK_F_PTMDSCONNTMDSCONN

TMDS_CLK_F_NTMDSCONNTMDSCONN

TMDS_CLK_R_PTMDSTMDS

TMDS_CLK_R_NTMDSTMDS

TMDS_CLK_R_N

TMDS_CLK_R_PTMDS_CLK_P

TMDS_CLK_N

TMDS_DATA_RL<2>VOLTAGE=0VNO_TEST=TRUE

VOLTAGE=0VNO_TEST=TRUE

TMDS_DATA_RL<4>


TMDS_DATA_F_N<0>

NO_TEST=TRUEVOLTAGE=0V

TMDS_DATA_RL<3>

=GND_CHASSIS_DVI1

VGA_G

GPU_R2

GPU_G2

VGA_R

VGA_G

VGA_B

VGA_VSYNCVGA_VSYNC_R

VGA_HSYNCVGA_HSYNC_R

GPU_H2SYNC

=PP3V3_D3C_VGASYNC

TMDS_CLK_F_N

TMDS_CLK_F_P

TMDS_DATA_F_P<5>

TMDS_DATA_F_N<5>

VGA_HSYNC

VGA_B

TMDS_CLK_F_N

TMDS_CLK_F_P

DVI_DDC_CLK

=GND_CHASSIS_DVI2

=PP5V_S0_DVI_DDC

=GND_CHASSIS_DVI4

VGA_R

VGA_VSYNC

VOLTAGE=0VNO_TEST=TRUE

TMDS_DATA_RL<5>

GPU_B2

PP5V_S0_DDC_PULLUPS


VOLTAGE=5V

VOLTAGE=5V


PP5V_S0_DDC_F

GPU_DDC_A_CLK

GPU_DDC_A_DATA

=GND_CHASSIS_DVI5

DVI_DDC_DATA

=PP3V3_D3C_VGASYNC

GPU_V2SYNCTMDS_DATA_F_N<0>

TMDS_DATA_F_P<0>

TMDS_DATA_P<0>

TMDS_DATA_F_N<1>

TMDS_DATA_F_P<1>

TMDS_DATA_N<1>

TMDS_DATA_F_N<2>

TMDS_DATA_F_P<2>

TMDS_DATA_P<2>

TMDS_DATA_N<2>

TMDS_DATA_F_N<3>

TMDS_DATA_F_P<3>

TMDS_DATA_P<3>

TMDS_DATA_N<3>

TMDS_DATA_F_N<4>

TMDS_DATA_F_P<4>TMDS_DATA_P<4>

TMDS_DATA_N<4>

TMDS_DATA_F_N<5>

TMDS_DATA_F_P<5>TMDS_DATA_P<5>

TMDS_DATA_N<5>

TMDS_DATA_P<1>


TMDS_DATA_F_P<2>

TMDS_DATA_F_N<1>

TMDS_DATA_F_N<2>

DVI_HPD_R

TMDS_DATA_F_P<3>

TMDS_DATA_F_P<1>

DVI_DDC_CLK_R

DVI_DDC_DATA_R

PP5V_S0_DDC

MIN_LINE_WIDTH=0.38 mmVOLTAGE=5V


TMDS_DATA_F_P<0>

TMDS_DATA_N<0>

84A4

84A4

77D6

77D6

77C6

77C6

77B6

77B6

84A4

84A4

84A4

77B5

77B5

84A4

84A4

84B4

84B4

84A4

84A4

84A4

84A4

84A4

84A4

84A4

84A4

84A4

84A4

84A4

84A4

84A4

84A4

84A4

84A4

84A4

84A4

84A4

84A4

84A4

84A4

84A4 84A4

84A4

84A4

84A4 84A4

84A4

84A4

84A4

84A4

84A4

84A4

84A4

84A4

84A4

77D1

77D1

77D1

77B3

77B3

77B6

77C6

76C7

76C7

77D6

76D7

76D7

77D5

77D1

77D1

77D1

77D1

77D1

77D1

76D7

77D5

77D1

77D1

76C7

77D1

77D1

76C7

77D1

77D1

76C7

76C7

77D1

77D1

76C7

76C7

77D1

77D1 76C7

76C7

77D1

77D1 76C7

76C7

76C7

77D1

77D1

77D1

77D1

77D1

77D6

76C7

65A1

22A6

75A5

65A3

26A1

77A6

77A6

77B6

6A6

77A6

77A6

77B5

77A5

77B7

77C7

77D1

77D1 75C3

75C3

77D1

6A6

77C1

75B3

75B3

77A3

77A3

77A5

77A3

77A5

75B3

65A3

77A5

77B5

77A6

77A6

77C3

77C1

77C6

77B6

6B6

65B1

6B6

77C1

77D3

75B3

75A3

75A3

6A6

65A3

75B3 77B5

77B5

75C3

77B3

77B3

75C3

77B3

77B3

75C3

75C3

77B3

77B3

75C3

75C3

77B3

77B3 75C3

75C3

77B5

77B5 75C3

75C3

75C3

77C6

77C6

77C6

77B6

77C6

77D1

75C3

IN

OUT

IN

INOUT

OUT

SYM_VER-1

SYM_VER-1

OUT

IO

IO

IO

IO

OUT

OUT

IO

OUT

IO

IO

IOIO

IO

IN

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

NC

NC

Left ALS Connector

516S0412

Top-Case Connector

SATA HDD & IR & SIL Flex Connector

NOTE: _UF_ nets cross DDR2 signals and pick

up significant noise. Common-mode chokes

are to remove this noise from SATA signals.

516S0412

518S0469white colored version of 518S0369

C4960

1 2

0.0047uF

10%

CERM25V

402

PLACEMENT_NOTE=Place C4960 close to southbridge

C4961

1 2

25VCERM

0.0047uF

402

10%

PLACEMENT_NOTE=Place C4961 next to C4960

C4965

2 1

PLACEMENT_NOTE=Place C4965 close to J4960

25VCERM

0.0047uF

10%

402

C4966

2 1

PLACEMENT_NOTE=Place C4966 next to C4965

CERM

10%

402

0.0047uF

25V

FL4960

1

2 3

4

CRITICAL

90-OHM-100MA1210-4SM1

FL4965

1

2 3

4

CRITICAL

90-OHM-100MA1210-4SM1

J4900

1

10

11 12

13 14

15 16

17 18

19

2

20

3 4

5 6

7 8

9

M-ST-SM

CRITICAL

QT500206-L020

D4900

3

1

2

RCLAMP0502B

SC-75

CRITICAL

J6430

5

6

1

2

3

4

BM04B-ACH

CRITICAL

M-RT-SM

J4960

1

10

11 12

13 14

15 16

17 18

19

2

20

3 4

5 6

7 8

9

QT500206-L020M-ST-SM

CRITICAL

051-7270 B

10598


M59 Specific Connectors

ALS_GAIN

=PP3V3_S3_LTALS

LTALS_OUT

SATA_C_R2D_P

SATA_C_R2D_N

SATA_C_R2D_UF_P

SATA_C_R2D_UF_N

=PP5V_S0_HDD

SATA_C_D2R_C_P

=USB_IR_P

SYS_LED_ANODE

=USB_IR_N

SATA_C_R2D_C_N

SATA_C_R2D_C_P

SATA_C_D2R_C_N

=PP5V_S3_IR

SATA_C_D2R_P

SATA_C_D2R_UF_N

SATA_C_D2R_UF_P

SATA_C_D2R_N

=PP3V3_S3_TOPCASE

=PP5V_S3_TOPCASE

=PP3V42_G3H_LIDSWITCH

=USB_TRACKPAD_P

=USB_TRACKPAD_N

SMC_LID

KBDLED_RETURN

KBDLED_ANODE =USB_BT_P

=USB_BT_N

SMC_ONOFF_L

=SMBUS_TOPCASE_SDA

=SMBUS_TOPCASE_SCL

=I2C_TRACKPAD_SCL

=I2C_TRACKPAD_SDA

50C6

49B5

50B2

6D5

65C3

55C7

50B2 49C5

5B2

5B2

5B2

65B1

6C3

50A7

6C3

21B6

21B6

65B1

21B6

21B6

65C3

65B1

65D3

6D3

6D3

49B5

55A4

55A4 6C3

6C3

5B2

27C3

27C3

27C6

27C6

SYM_VER-3

GND

SEL

DB19*

DB18*

DB17*

DB16*

DB15*

DB14*

DB13*

DB12*

DB11*

DB10*

DB9* DH19

DH14

DH13

DH12

DH11

DH10

DH9

DH15

DH16

DH17

DH18

DB4*

DB5*

DB6*

DB7*

DB8*

DB0*

DB1*

DB2*

DB3*

DH4

DH3

DH2

DH1

DH0

DH8

DH7

DH6

DH5

DA15

DA16

DA17

DA18

DA19

DA13

DA14

DA12

DA11

DA10

DA5

DA6

DA7

DA8

DA9

DA0

DA1

DA2

DA3

DA4

VDD

G

S D

G

S D

1B1

4B2

2B1

2B2

3B1

3B2

4B1

1B2

1A

2A

3A

4A

OE*

S

THRMLPADGND

VCC

SYM_VER-2

V3

V4 RST*

V2

V1

GND

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

Divider set to rise to 1.88V nom/1.74V min when panel power is


D3CPGOOD_ALL BOM option stuffs LTC2903 circuit to monitor all D3C rails to qualify D3CPGOOD.

D3CPGOOD_3V3 BOM option uses only PP3V3_D3C to qualify D3CPGOOD.

the pump-up in the panel, though some voltage will still be seen

PGOOD Monitor for GPU Rails

NOTE: These parts are to counter an invalid state caused by the

M56 part. Bias voltage is present on LVDS interface pins even

when they should be tri-stated to meet panel power sequence

and long-term reliability issues. Pull-down resistors reduce

on LVDS signals when they should be 0V.

GPU LVDS I/F

NB LVDS I/F

NC

NC

NC

NOTE: SEL = LOW selects port B

NC

Panel/Backlight Control Mux

NOTE: SB_GPIO23 has internal 20K PU to default selection to GPU

NOTE: S = HIGH selects xB2

LVDS I/F Mux

R9981 can also be used as pad for cap, creating an RC filter.

at 3.3V/3.315V. Schmitt trigger voltage max is 1.70V (@2.625V Vcc).

Enables the GPU LVDS path in the mux with the qualification

panel power has risen to (near) 3.3V. This should

eliminate need for LVDS pulldowns

that the GPU has turned on panel power and that the

LVDS Mux Selection Qualification

requirements. Resulting pump-up in LCD panel can cause startup

LVDS Interface Pull-downs

GPU DDC Pass FETs

RP99001 8

LVDS_PD

1/16WSM-LF

8.2K

5%

RP99021 8

1/16W

8.2K

5%

LVDS_PD

SM-LF

R99961

2

D3CPGOOD_ALL

5%

MF-LF402

1/16W

470K

U9950

F1

H1

K1

K3

K4

K6

J7

K9

J10

G10

E10

C10

A10

A8

A7

A5

B4

A2

B1

D1

G1

J1

K2

J4

K5

K7

K8

K10

H10

F10

D10

B10

A9

B7

A6

A4

A3

A1

C1

E1

F2

H2

J2

J3

J5

J6

J8

J9

H9

F9

E9

C9

B9

B8

B6

B5

B3

B2

C2

E2

C5

C6

D2

D9

G2

G9

H5

H6

E3

E8

F3

F8

CBTV4020

CRITICAL

BGA-LF

U9985

3

2

1

4

5 MC74VHC1G08SC70

C9985 1

2402

0.1UF

CERM10V20%

Q9970

6

2

1

SOT-3632N7002DW-X-F

Q9970

3

5

4

SOT-3632N7002DW-X-F

C99931

2

D3CPGOOD_ALL

402

0.1UF20%10VCERM

RP99023 6

LVDS_PD

8.2K

5%1/16WSM-LF

C99951

2

D3CPGOOD_ALL

402

10V20%0.1UF

CERM

C99921

2

D3CPGOOD_ALL

CERM10V20%0.1UF

402

R99971

2

5%10K

1/16W

402MF-LF

U9961

3

2

1

4

5 MC74VHC1G08SC70

R99621

2

NO STUFF

402MF-LF1/16W5%0

C9961 1

2

0.1UF

402CERM

20%10V

C99961

2

D3CPGOOD_3V3

6.3V10%1UF

402CERM

RP99024 5

LVDS_PD

5%

SM-LF

8.2K

1/16W

RP99032 7

LVDS_PD

8.2K

5%1/16WSM-LF RP9903

1 88.2K

1/16W5%

LVDS_PD

SM-LF

RP99033 6

5%

LVDS_PD

8.2K

SM-LF1/16W

RP99034 58.2K

1/16W5%

LVDS_PD

SM-LF

RP99002 7

LVDS_PD

8.2K

5%

SM-LF1/16W

RP99004 5

LVDS_PD

SM-LF

8.2K

5%1/16W

C9950 1

2402

0.1UF

CERM10V20%

RP99003 68.2K

1/16WSM-LF

5%

LVDS_PD

C9960 1

210V20%

CERM402

0.1UF

RP99012 7

LVDS_PD

8.2K

SM-LF

5%1/16W

R99701

2

15.8K1%

402

1/16WMF-LF

R99711

2

15.8K1%

402

1/16WMF-LF

U996042

3

75

6

911

10

1214

13

15

8

1

17

16CRITICAL

74CBTLV3257QFN

RP99011 8

1/16W5%

SM-LF

LVDS_PD

8.2K

C9980 1

2402

CERM10V20%

0.1UF

R99601

2402

10K

MF-LF1/16W5%

R99611

2

100K

MF-LF1/16W

5%

402

RP99013 6

1/16W

LVDS_PD

8.2K

5%

SM-LF

U9980

3

1

2

4

5

SN74LVC1G132SC70-5

CRITICAL

RP99014 58.2K

1/16W5%

LVDS_PD

SM-LF

R998012

1/16W

402

5%

MF-LF

10K

R99811

2

1/16WMF-LF402

13.3K1%

C9991 1

2

0.1uF

CERM402

20%10V

U9991

3

2

1

4

5 MC74VHC1G08SC70

C9990 1

2

D3CPGOOD_ALL

402

0.1uF

CERM

20%10V

RP99022 7

LVDS_PD

8.2K

1/16W5%

SM-LF

U9990

2

6

1

3

4

5

CRITICAL

D3CPGOOD_ALL

LTC2903TSOT-23

R99901

2

D3CPGOOD_ALL

365K

1/16W1%

402MF-LF

R99921

2

D3CPGOOD_ALL

MF-LF1/16W1%237K

402

R99941

2

D3CPGOOD_ALL

1/16WMF-LF

1%

402

124K

R99911

2

D3CPGOOD_ALL

MF-LF1/16W

1%

402

100KR99931

2

D3CPGOOD_ALL

100K

MF-LF402

1%1/16W

R99951

2

D3CPGOOD_ALL

100K

1/16W1%

402MF-LF

SYNC_MASTER=M59_MG

051-7270

99

B

105


LVDS Interface Pull-downs

=LVDS_MUX_SEL_GPU

LVDS_MUX_SEL_GPU_MUXED

=PP3V3_S0_LVDS_MUX

PLT_RST_L

LVDS_DDC_DATA

LVDS_DDC_CLK

GPU_DDC_C_DATA

GPU_DDC_C_CLK

MAKE_BASE=TRUELVDS_CONN_DDC_DATA

LVDS_CONN_DDC_CLKMAKE_BASE=TRUE

=PP3V3_D3C_GPU_LVDS_DDC

=GPU_DDC_ENABLE

S0PGOOD_PWROK

PP1V8_D3C

PP1V2_D3C

GPU_DIGON

GPU_DIGON_AND_SELECTED

=PP3V3_S0_LVDS_MUX

=LVDS_PD_U_DATA_N<0>

=LVDS_PD_U_DATA_P<2>

=LVDS_PD_U_CLK_N

=PP3V3_S0_LVDS_MUX

PANEL_PWR_ON

=LVDS_MUX_SEL_GPU

=PP2V5_S0_LVDS_MUX

PP3V3_LCD_SW

LVDS_MUX_SEL_GPU_L

=PP2V5_S0_LVDS_MUX


LVDS_U_CLK_CONN_P

LVDS_U_CLK_CONN_N







LVDS_L_CLK_CONN_P

LVDS_L_CLK_CONN_N






LVDS_U_DATA_P<2>

LVDS_U_DATA_N<1>

LVDS_U_CLK_N

LVDS_U_CLK_P

LVDS_U_DATA_P<1>

LVDS_L_DATA_N<2>

LVDS_L_DATA_N<1>

LVDS_L_DATA_P<1>

LVDS_L_DATA_P<2>

LVDS_L_DATA_P<0>

LVDS_L_DATA_N<0>

LVDS_L_CLK_N

LVDS_L_CLK_P

LVDS_U_DATA_N<2>

LVDS_U_DATA_N<0>

LVDS_U_DATA_P<0>

LVDS_B_DATA_N<1>

LVDS_B_CLK_N

LVDS_B_CLK_P

LVDS_B_DATA_P<2>

LVDS_B_DATA_P<1>

LVDS_A_DATA_N<2>

LVDS_A_DATA_N<1>

LVDS_A_DATA_P<1>

LVDS_A_CLK_N

LVDS_A_DATA_N<0>

LVDS_A_DATA_P<0>

LVDS_A_DATA_P<2>

LVDS_B_DATA_N<0>

LVDS_B_DATA_N<2>

LVDS_B_DATA_P<0>

LVDS_A_CLK_P

=LVDS_PD_L_DATA_N<2>

S0D3CPGOOD_PWROK

=PP3V3_S0_ALLSYSPG=LVDS_PD_L_DATA_P<0>

GPU_BLON

=LVDS_PD_L_DATA_P<2>

PGOOD_MUXED_S0_OR_S0D3C

INVERTER_PWM_UNBUF

S0D3CPGOOD_PWROK

S0PGOOD_PWROK

TP_SB_GPIO23 LVDS_MUX_SEL_GPUMAKE_BASE=TRUE

=LVDS_MUX_SEL_GPU

=LVDS_PD_L_DATA_N<0>

=LVDS_PD_L_CLK_N



=LVDS_PD_L_CLK_P


=LVDS_PD_U_CLK_P

GPU_DIGON

LVDS_PANEL_ENLVDS_VDDEN

LVDS_BKLTEN

LVDS_BKLTCTL

GPU_VARY_BL

INVERTER_BKLTON


=LVDS_PD_L_DATA_P<1>

=LVDS_PD_L_DATA_N<1>D3CPGOOD_PWROK

PP3V3_D3C

D3CPGOOD_2V5_DIV

D3CPGOOD_1V2_DIV

D3CPGOOD_1V8_DIV

PP2V5_D3C

79C6

79C6

79B3

76D7

76D7

76D7

76D7

76D7

76D7

76D7

76D7

76D7

76D7

76D7

76D7

76D7

76D7

76D7

76D7

79B6

79B3

26C3

79A4

79A4

79A4

79A4

79A4

79D3

79C5

76B2

76B2

76B2

76C2

76C2

76C2

76C2

76C2

76C2

76C2

76C2

76C2

76C2

76C2

76C2

76C2

76D7

76D7

76D7

76D7

76D7

76D7

76D7

76D7

76D7

76D7

76D7

76D7

76D7

65A3

79D5

79B6

79B6

79A3

65A3

22A6

13D5

13D5

75A3

75A3

76C3

76C3

65A3

26A1

64A2

65B6

65D6

74C3

65A3

6B3

6B3

6B3

65A3

79A3

65A6

76D3

65A6

6B1

6B1

6B1

6B1

6B1

6A1

6A1

6A1

6A1

6B1

6B1

6A1

6B1

6B1

6B1

6B1

75B3

75B3

75B3

75B3

75B3

75A3

75A3

75A3

75A3

75A3

75B3

75B3

75B3

13C5

13C5

13C5

13C5

13C5

13C5

13C5

13C5

13D5

13C5

13C5

13C5

13C5

13C5

13C5

13C5

6A3

79A4

64B1 6B3

71C5

6A3

64B2

76A8

79C4

64A2

21D5 79A4

6A3

6B3

6B3

6B3

6B3

6B3

6B3

74C3

76D4 13D5

13D5

13D5

74C3

76B8

6B3

6A3

6A3

65A3

65A6

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

Date - Radar # - Description Date - Radar # - DescriptionDate - Radar # - Description

DMS Release #01000

2006/05/26 - 4508681 - Release for Proto

2006/06/30 - 4566939 - Release for EVT

DMS Release #04000

2006/08/07 - 4607952 - Release for DVT

DMS Release #07000

DMS Release #0A000

2006/09/19 - 4726575 - Release for PVT

DMS Release #0C000

2006/09/27 - 4726575 - Release for PVT

051-7270 B

105100

BSYNC_MASTER=N/A SYNC_DATE=N/A

LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM











MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD








TABLE_SPACING_ASSIGNMENT_ITEM

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE



TABLE_PHYSICAL_RULE_ITEM



AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
























































TABLE_SPACING_ASSIGNMENT_ITEMTABLE_SPACING_ASSIGNMENT_ITEM












TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM




























DG says minimum spacing 50 mils to clocks

DG recommends at least 25 mils, >50 mils preferred

USB 2.0 Interface Constraints

Worst-case spacing is 2:1 within Data bus, with 3:1 spacing to the DSTBs.

DSTB complementary pairs are spaced 3:1, even in constraint areas.

Worst-case spacing is 2:1 within Addr bus, with 3:1 spacing to the ADSTBs.

FSB (Front-Side Bus) Constraints

Disk Interface Constraints

SOURCE: Napa Platform DG, Rev 0.9 (#17978), Sections 10.6 & 10.7.2

SOURCE: Napa Platform DG, Rev 0.9 (#17978), Sections 7.2, 9.2 & 10.5.2

PCI-Express / DMI Bus Constraints

Design Guide recommends FSB signals be routed only on internal layers.

SOURCE: Napa Platform DG, Rev 0.9 (#17978), Section 10.10.1.2

Internal Interface Constraints

SOURCE: Napa Platform DG, Rev 0.9 (#17978), Section 10.9.1

Audio Interface Constraints

SOURCE: Napa Platform DG, Rev 0.9 (#17978), Section 6.2

SOURCE: Napa Platform DG, Rev 0.9 (#17978), Sections 4.2 & 4.3

SOURCE: Napa Platform DG, Rev 0.9 (#17978), Sections 4.4, 4.6.2, & 5.8.2.4

Need to support MEM_*-style wildcards!

Some signals require 27.4-ohm single-ended impedance.

NOTE: Design Guide allows closer spacing if signal lengths can be shortened.

Design Guide recommends each strobe/signal group is routed on the same layer.

NOTE: Design Guide does not indicate FSB spacing to other signals, assumed 3:1.

All FSB signals with impedance requirements are 55-ohm single-ended.

CPU Signal Constraints

DDR2 Memory Bus Constraints

Most CPU signals with impedance requirements are 55-ohm single-ended.

Clock Signal Constraints

SOURCE: Napa Platform DG, Rev 0.9 (#17978), Section 10.17.1.1

=STANDARD=STANDARD=55_OHM_SE=55_OHM_SEY*CLK_SLOW_55S =55_OHM_SE

MEM_DQS *MEM_CMD MEM_CMD2MEM

* =2:1_SPACINGFSB_COMMON

* YDMI_100D =100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF

Y*PCIE_100D =100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF

CLK_SLOW * 10 MIL

=STANDARD=STANDARD=55_OHM_SE=55_OHM_SE=55_OHM_SEY*SPI_55S

MEM_CLK2MEM =4:1_SPACING*

*MEM_2OTHER 25 MIL

* =2:1_SPACINGMEM_CTRL2CTRL

=3:1_SPACING*MEM_CTRL2MEM

* *MEM_DQS MEM_2OTHER

**MEM_DATA MEM_2OTHER

* *MEM_CMD MEM_2OTHER

PCIE * 20 MIL

DMI * 20 MIL

AUDIO_55S * Y =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD

AUDIO * =1.8:1_SPACING

=STANDARD=STANDARD=55_OHM_SE=55_OHM_SE=55_OHM_SEY*SMB_55S

USB2 =4:1_SPACING*

USB2_2CLK * 25 MIL

=3:1_SPACING*SMB

CLK_MED * 20 MIL

=3:1_SPACING*FSB_ADDR2ADSTB

=3:1_SPACINGFSB_ADSTB *

=2:1_SPACINGFSB_ADDR2ADDR *

FSB_ADDR =3:1_SPACING*

=3:1_SPACING*FSB_DSTB

=2:1_SPACING*FSB_DATA2DATA

=3:1_SPACINGFSB_DATA *

=3:1_SPACING*FSB_DATA2DSTB

=27P4_OHM_SE* Y =27P4_OHM_SE =27P4_OHM_SE =STANDARD =STANDARDCPU_27P4S

CPU_2TO1 * =2:1_SPACING

*FSB_ADDR FSB_ADDR FSB_ADDR2ADDR

IDE_55S * Y =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD

SATA_100D Y* =100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF

Napa Platform ConstraintsSYNC_DATE=(MASTER)SYNC_MASTER=(MASTER)

051-7270 B

105101

FSB_DSTBFSB_DATA * FSB_DATA2DSTBIDE =1.8:1_SPACING*

=85_OHM_DIFF =85_OHM_DIFF* =85_OHM_DIFF=85_OHM_DIFFMEM_85D Y =85_OHM_DIFF

* *MEM_CLK MEM_2OTHER

**MEM_CTRL MEM_2OTHER

MEM_DATA * MEM_DQS2MEMMEM_DQS

FSB_ADDR2ADSTBFSB_ADDR FSB_ADSTB *

SATA * 20 MIL

Y*USB2_90D =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF

FSB_55S =55_OHM_SE* =55_OHM_SEY =55_OHM_SE =STANDARD =STANDARD

MEM_CLK MEM_CMD2MEM*MEM_CMD

MEM_CTRL MEM_CMD2MEMMEM_CMD *

MEM_CMD2CMDMEM_CMDMEM_CMD *

MEM_CTRL2MEM*MEM_CTRL MEM_DQS=3:1_SPACING*MEM_CMD2MEM

=1.8:1_SPACINGSPI *

Y* =100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFFCLK_FSB_100D =100_OHM_DIFF

Y* =100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFFCLK_PCIE_100D =100_OHM_DIFF

=STANDARD=STANDARD=55_OHM_SEY*CLK_MED_55S =55_OHM_SE=55_OHM_SE

CPU_55S =55_OHM_SE=55_OHM_SE* =55_OHM_SEY =STANDARD =STANDARD

=70_OHM_DIFFMEM_70D =70_OHM_DIFF =70_OHM_DIFF=70_OHM_DIFF* Y =70_OHM_DIFF

CLK_FSB * 25 MIL

CLK_PCIE * 20 MIL

=1.5:1_SPACING*MEM_CMD2CMD

* =3:1_SPACINGMEM_DATA2MEM

*MEM_DATA2DATA =1.5:1_SPACING

=3:1_SPACING*MEM_DQS2MEM

MEM_DATA *MEM_CLK MEM_CLK2MEM

MEM_DQS MEM_CLK2MEMMEM_CLK *

MEM_CTRL * MEM_CTRL2MEMMEM_DATA

MEM_CTRL MEM_DATA2MEMMEM_DATA *

MEM_CLKMEM_DATA MEM_DATA2MEM*

MEM_CMD *MEM_DATA MEM_DATA2MEM

MEM_DQS *MEM_DATA MEM_DATA2MEM

MEM_CTRL MEM_CTRL2MEM*MEM_CMD

MEM_CTRL MEM_CTRL2CTRL*MEM_CTRL

*MEM_CLK MEM_CTRL2MEMMEM_CTRL

* =STANDARD=45_OHM_SE =STANDARDMEM_45S Y =45_OHM_SE =45_OHM_SE

CPU_VCCSENSE * 25 MIL

CPU_COMP * 25 MIL

=55_OHM_SE =55_OHM_SE =STANDARD=STANDARDMEM_55S Y* =55_OHM_SE

*CPU_GTLREF 25 MIL

MEM_CMDMEM_DQS MEM_DQS2MEM*

MEM_CTRL * MEM_DQS2MEMMEM_DQS

MEM_CLK * MEM_DQS2MEMMEM_DQS

MEM_CLK MEM_CLK MEM_CLK2MEM*

MEM_CLK MEM_CTRL MEM_CLK2MEM*

MEM_CMD MEM_CLK2MEMMEM_CLK *

MEM_DATA MEM_CMD2MEMMEM_CMD * *MEM_DATA MEM_DATA MEM_DATA2DATA

MEM_DQSMEM_DQS MEM_DQS2MEM*

FSB_DATA2DATAFSB_DATA *FSB_DATA

=2:1_SPACING*CPU_ITP



















DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE




















ADDR/CTRL lines should route 35-ohms to T, then 55-ohms to each VRAM device.

NOTE: Layout Guide does not specify LVDS/TMDS spacing to other traces other than "do not run close"

Video Signal Constraints

GDDR3 (Frame Buffer) Memory Bus Constraints

SOURCE: ATI Layout Guide, Rev 0.5 (DSG-216MOBRADEON-05), Sections 7 & 8.1.2.

note

DQ/DQM/DQS lines are 40-ohm single-ended impedence.

CTRL lines are 55-ohm single-ended impedence.

LVDS and TMDS signals are 100-ohm +/- 10% differential impedence.

LVDS and TMDS pairs should be kept at least 25 mils apart.

Ground shields can be used around each pair if spacing cannot be met.

Ground shields recommended around VGA signals.

VGA should be routed as close to 75-ohms single-ended impedence as possible.

VGA signals should be kept at least 15 mils from other traces.

SOURCE: ATI Layout Guide, Rev 0.5 (DSG-216MOBRADEON-05), Sections 7 & 8.1.2.

NOTE: Layout Guide does not specify LVDS/TMDS spacing to other traces other than "do not run close"

High-Speed I/O Interface Constraints

PCI Bus Constraints

NOTE: CLK lines are specified in Layout Guide as 40-ohm single-ended. We treat as 75-ohm differential.

=3:1_SPACINGFW *

15 MIL*VGA

=3:1_SPACING*TMDS

* =3:1_SPACINGLVDS

FB_40S =40_OHM_SE* =STANDARD =STANDARD=40_OHM_SE=40_OHM_SEY

Y =55_OHM_SE =STANDARD=STANDARD=55_OHM_SE* =55_OHM_SEFB_55S

FB_CLK =2.5:1_SPACING*

=100_OHM_DIFFTMDS_100D * Y =100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF

=STANDARD* Y =STANDARD=75_OHM_SE =75_OHM_SE =75_OHM_SEVGA_75S

*FB_ADCTRL =2.5:1_SPACING

*LVDS_PAIR2PAIR 25 MIL

*TMDS_PAIR2PAIR 25 MIL

=3:1_SPACINGENET *

=100_OHM_DIFFLVDS_100D Y* =100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF

FB_75D =75_OHM_DIFF=75_OHM_DIFF=75_OHM_DIFF=75_OHM_DIFF=75_OHM_DIFFY*

LVDS * LVDS_PAIR2PAIRLVDS

*PCI =2:1_SPACING

PCI_55S =55_OHM_SE* =55_OHM_SE =STANDARD =STANDARD=55_OHM_SEY

FB_35S_TO_55S =35_55_OHM_SE =STANDARD=STANDARD* Y =35_OHM_SE =55_OHM_SE

=2.5:1_SPACING*FB_DATA

* Y =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFFFW_110D

ENET_100D =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF* Y

TMDS TMDS_PAIR2PAIR*TMDS

051-7270 B

105102

More System ConstraintsSYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)












TABLE_PHYSICAL_ASSIGNMENT_ITEM


PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPETABLE_PHYSICAL_ASSIGNMENT_HEAD

OVERRIDEOVERRIDE OVERRIDE OVERRIDE

TABLE_SPACING_RULE_OVERRIDE






































DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE




























TABLE_BOARD_INFO

VERSIONALLEGRO

(MIL or MM)BOARD UNITSBOARD LAYERS BOARD AREAS







OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE






































































M59 Board-Specific Spacing & Physical Constraints

Rules for "Topology #3" for FSB signals, Napa DG tables 4-7 & 4-12.

"Stale" physical / spacing types

Unsupported rule

Allow 0.1 MM on blind-to-buried via dogbones (layers 2 & 11)

ENET**ENETCONN

* *GND STANDARD

**I2C SMB

0.125 MM0.125 MM 0.125 MM0.125 MMY85_OHM_DIFF TOP,BOTTOM

0.125 MM0.101 MM0.101 MM* Y =STANDARD85_OHM_DIFF 0.125 MM

70_OHM_DIFF 0.125 MM0.125 MM0.185 MM0.185 MMYTOP,BOTTOM

TOP,BOTTOM Y 0.230 MM35_55_OHM_SE 0.100 MM

M59 Spacing & Physical Constraints


051-7270 B

105103

=STANDARD0.131 MM =STANDARD=STANDARDY*40_OHM_SE 0.100 MM

=STANDARD35_OHM_SE 0.165 MM0.165 MM =STANDARD=STANDARDY*

YTOP,BOTTOM 0.335 MM 0.335 MM27P4_OHM_SE

0.076 MM35_55_OHM_SE * Y =STANDARD =STANDARD0.165 MM =STANDARD

TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM MM 15.2NO_TYPE,BGA

0.077 MM0.077 MM 0.330 MM0.330 MM110_OHM_DIFF * Y =STANDARD

0.330 MM0.330 MM0.089 MM0.089 MMY110_OHM_DIFF TOP,BOTTOM

0.185 MM40_OHM_SE 0.185 MMYTOP,BOTTOM

TMDS_100D*TMDSCONN

=STANDARD =STANDARD=STANDARDY*45_OHM_SE 0.105 MM0.105 MM

0.090 MM =STANDARD0.090 MM50_OHM_SE =STANDARD=STANDARDY*

Y55_OHM_SE =STANDARD =STANDARD =STANDARD0.076 MM 0.076 MM*

0.100 MM55_OHM_SE Y 0.100 MMTOP,BOTTOM

DEFAULT =55_OHM_SE=55_OHM_SE 0 MM0 MMY* 30 MM

70_OHM_DIFF 0.125 MM0.125 MM0.149 MM0.149 MM* =STANDARDY

FSB_ADDR2ADDR =STANDARD*

FSB_ADSTB =2:1_SPACING*

FSB_ADDR2ADSTB * =2:1_SPACING

LVDS LVDS_100D*

* TMDS_100DTMDS

0.125 MM0.125 MM0.140 MM0.140 MM80_OHM_DIFF YTOP,BOTTOM

0.220 MMY 0.220 MM0.102 MM0.102 MM90_OHM_DIFF * =STANDARD

0.220 MM0.130 MM 0.220 MM0.130 MM90_OHM_DIFF YTOP,BOTTOM

0.200 MM0.080 MM 0.200 MM0.080 MM* Y =STANDARD100_OHM_DIFF

0.200 MM0.200 MM0.099 MM0.099 MM100_OHM_DIFF TOP,BOTTOM Y

75_OHM_SE 0.076 MM 0.076 MM =STANDARD=STANDARDY* =STANDARD

0.125 MM0.125 MMTOP,BOTTOM 0.161 MM0.161 MM75_OHM_DIFF Y

* 0.125 MM0.125 MM0.131 MM0.131 MM75_OHM_DIFF Y =STANDARD

0.125 MM80_OHM_DIFF * =STANDARD 0.125 MM0.111 MM0.115 MMY

* * FSB_COMMONFSB_P2MM

* FSB_COMMON*FSB_ANALOG

TMDS**TMDSCONN

*MEM_2OTHER 0.5 MM

=2:1_SPACING*FSB_DSTB

0.124 MM0.124 MM50_OHM_SE YTOP,BOTTOM

FSB_ADDR * =2:1_SPACING

BGA_P3MM * =DEFAULT

PCI_2PCIPCIPCI *

0.1 MMPCI_2PCI *

* * STANDARDFB_PP1V8

MEM_PP1V8_S3 ** STANDARD

VGA * VGA_75S

0.3 MM3:1_SPACING *

0.4 MM4:1_SPACING *

2.5:1_SPACING 0.25 MM*

0.15 MM1.5:1_SPACING *

1.8:1_SPACING * 0.18 MM

* 0.2 MM2:1_SPACING

=DEFAULT*BGA_P1MM

CLK_PCIE 0.1 MMISL2,ISL11

PCIE 0.1 MMISL2,ISL11

ISL2,ISL11 0.1 MMMEM_2OTHER

CLK_SLOW 0.1 MMISL2,ISL11

0.1 MMISL2,ISL11LVDS_PAIR2PAIR

CPU_VCCSENSE ISL2,ISL11 0.1 MM

ISL2,ISL11 0.1 MMDMI

CPU_COMP ISL2,ISL11 0.1 MM

CPU_GTLREF 0.1 MMISL2,ISL11

ISL2,ISL11 0.1 MMTMDS_PAIR2PAIR

0.1 MMISL2,ISL11VGA

CLK_MED ISL2,ISL11 0.1 MM

CLK_FSB ISL2,ISL11 0.1 MM

ISL2,ISL11 0.1 MMSATA

*STANDARD =DEFAULT

2.5:1_SPACING 0.1 MMISL2,ISL11

*MEM_45S 0.100 MM

0.240 MM =STANDARD=STANDARD0.240 MM27P4_OHM_SE =STANDARDY*

=STANDARDFSB_DATA2DATA *

BGA_P2MM*CLK_FSB BGA

0.230 MM0.230 MM35_OHM_SE YTOP,BOTTOM

=2:1_SPACINGFSB_DATA *

=DEFAULT =DEFAULT=DEFAULTSTANDARD * =DEFAULTY 12.7 MM

0.150 MM0.150 MM45_OHM_SE TOP,BOTTOM Y

MEM_70D 0.100 MM*

0.100 MMMEM_85D *

* BGA BGA_P2MMMEM_CLK

=DEFAULTBGA_P2MM *

BGA_P1MMBGA* *0.1 MM*DEFAULT

3:1_SPACING 0.1 MMISL2,ISL11

4:1_SPACING ISL2,ISL11 0.1 MM

* =2:1_SPACINGFSB_DATA2DSTB

1.8:1_SPACING 0.1 MMISL2,ISL11

BGAFSB_DSTB BGA_P3MMFSB_DSTB

* BGA BGA_P2MMFB_CLK

2:1_SPACING 0.1 MMISL2,ISL11

1.5:1_SPACING ISL2,ISL11 0.1 MM

BGA_P2MMCLK_MED BGA*

BGA_P2MMBGA*CLK_SLOW

* BGACLK_PCIE BGA_P2MM

GND

FSB_ANALOG

PCI_55SPCI

FB_PP1V8

MEM_PP1V8_S3

FSB_P2MM

I2C

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE

ELECTRICAL_CONSTRAINT_SET SPACING

NET_TYPE

PHYSICAL

I70

I71

I72

I73

M59 Net PropertiesSYNC_DATE=(MASTER)

051-7270 B

105104




TMDS_DATA_F_P<2..0>TMDSCONNTMDSCONN

TMDS_DATA_F_P<5..3>TMDSCONNTMDSCONN

TMDS_DATA_N<2..0>TMDSTMDS

TMDS_DATA_N<5..3>TMDSTMDS

TMDS_DATA_P<2..0>TMDSTMDS

TMDS_DATA_P<5..3>TMDSTMDS

TMDS_CLK_F_PTMDSCONNTMDSCONN

TMDS_CLK_F_NTMDSCONNTMDSCONN

FSB_LOCK_LFSB_COMMONFSB_55S

MEM_DQS MEM_85D

FB_CLK FB_75D

SATA SATA_100D

ENET ENET_100D

CPU_COMP<1>CPU_COMPCPU_55S

SMB SMB_55S

FSB_BPRI_LFSB_COMMONFSB_55S

CPU_XDP_CLK_NCPU_ITPCLK_FSB_100D

IMVP6_VSEN_PCPU_VCCSENSECPU_27P4S

CPU_INTRCPU_55S

FSB_ADSTB_L<3..0>FSB_ADSTBFSB_55S

FSB_D_L<63..0>FSB_DATAFSB_55S

FSB_DRDY_LFSB_COMMONFSB_55S

FSB_RS_L<2..0>FSB_COMMONFSB_55S

USB2 USB2_90D

FW FW_110D

CLK_FSB CLK_FSB_100D

FSB_TRDY_LFSB_COMMONFSB_55S

FSB_CPURST_LFSB_COMMONFSB_55S

FSB_DBSY_LFSB_COMMONFSB_55S

FSB_DSTBP_L<3..0>FSB_DSTBFSB_55S

FSB_DINV_L<3..0>FSB_DATAFSB_55S

FSB_DSTBN_L<3..0>FSB_DSTBFSB_55S

CPU_COMP<2>CPU_COMPCPU_27P4S

CPU_COMP<3>CPU_COMPCPU_55S

CPU_GTLREFCPU_GTLREFCPU_55S

PM_DPRSLPVRCPU_2TO1CPU_55S

CPU_IGNNE_LCPU_55S

CPU_DPSLP_LCPU_55S

CPU_A20M_LCPU_55S

CPU_NMICPU_55S

CPU_PWRGDCPU_55S

IMVP_DPRSLPVRCPU_2TO1CPU_55S

FSB_FERR_LCPU_55S

FSB_A_L<31..3>FSB_ADDRFSB_55S

CPU_VCCSENSE_NTHERM CPU_VCCSENSECPU_27P4S

IMVP6_VSEN_NCPU_VCCSENSECPU_27P4S

CPU_COMP<0>CPU_COMPCPU_27P4S

CPU_XDP_CLK_PCPU_ITPCLK_FSB_100D

XDP_BPM_L<5..0>CPU_ITPCPU_55S

FSB_BREQ0_LFSB_COMMONFSB_55S

FSB_ADS_LFSB_COMMONFSB_55S

MEM_CMD MEM_55S

MEM_CLK MEM_70D

MEM_CTRL MEM_45S

MEM_DATA MEM_55S

CPU_SMI_LCPU_55S

CPU_INIT_LCPU_55S

FB_ADCTRL FB_55S

FB_ADCTRL FB_35S_TO_55S

FB_DATA FB_40S

DMI DMI_100D

FSB_IERR_LCPU_55S

CPU_THERMTRIP_LCPU_2TO1CPU_55S

FSB_HIT_LFSB_COMMONFSB_55S

IDE IDE_55S

CLK_PCIE CLK_PCIE_100D

CLK_MED CLK_MED_55S

SB_ACZ_RST_LAUDIOAUDIO_55S

ACZ_RST_LAUDIOAUDIO_55S

ACZ_SDATAOUTAUDIOAUDIO_55S

SB_ACZ_SDATAOUTAUDIOAUDIO_55S

ACZ_SDATAIN<0>AUDIOAUDIO_55S

ACZ_SYNCAUDIOAUDIO_55S

TMDS_CLK_NTMDSTMDS

SB_ACZ_SYNCAUDIOAUDIO_55S

FSB_DEFER_LFSB_COMMONFSB_55S

FSB_HITM_LFSB_COMMONFSB_55S

FSB_BNR_LFSB_COMMONFSB_55S

TMDS_CLK_PTMDSTMDS

PCIE PCIE_100D

TMDS TMDS_100D

LVDS LVDS_100D

VGA VGA_75S

CPU_STPCLK_LCPU_55S

FSB_REQ_L<4..0>FSB_ADDRFSB_55S

FSB_DPWR_LFSB_COMMONFSB_55S

SPI SPI_55S

CLK_SLOW CLK_SLOW_55S

ACZ_BITCLKAUDIOAUDIO_55S

SB_ACZ_BITCLKAUDIOAUDIO_55S

CPU_VCCSENSE_PTHERM CPU_VCCSENSECPU_27P4S

CPU_VID<6..0>CPU_2TO1CPU_55S

CPU_VID<6..0>CPU_2TO1CPU_55S

ITPRESET_LCPU_ITPCPU_55S

12D6 12C6 12B6

12B4

12B4

12B4

77D6

77D1

77D6

77D1

7C4

7C4

7C4

7C4

12D4

77D1

77B6

77D1

77B6

77D8

77B8

77D8

77B8

12C4

7C3

7C3

7C3

7C3

12C4

12B4

77C6

77B5

77C6

77B5

77C8

77A8

77C8

77A8

77D1

77D1

12B4

7D8

7B4

12B4

12C4

12B4

7B4

7B4

7B4

59C8

7D8

12C4

12C4

12B4

47B3

47B6

47B6

47B6

77C8

12B4

12C4

77B8

12A4

47B6

84B6

84B6

77B5

77B3

77B5

77B3

76C7

76C7

76C7

76C7

77B6

77C6

7D6

12C4

34D3

21C4

7C8

7B3

7D6

12A4

12A4

11B5

7D6

7B3

7B3

7B3

23C3

21C4

21C4

21C4

21C4

21C4

7C8

59A1

34D3

11B3

7D6

7D6

21C4

21C4

7D6

21C7

21C7

21C7

21C7

76C7

12B4

7D6

7D6

76C7

21C4

7D8

12B4

21C7

59B1

9C2

9C2

77B3

77A6

77B3

77A6

75C3

75C3

75C3

75C3

77B5

77A5

5D5

7B3

7D6

11B3

59A3

7C8

5D5

5D5

5D5

7D6

7D6

7D6

5D5

5D5

5D5

5D5

7B3

7B3

7B4

14B7

7C8

7B3

7C8

7C8

7B3

59C7

5D5

8B6

59A3

7B3

11B3

7C6

5D5

5D5

7C8

7D6

7D6

5D5

21C6

5C1

5C1

21C6

5C1

5C1

75C3

21C6

7D6

5D5

5D5

75C3

7C8

5D5

7B3

5C1

21C6

8B6

8B7

8B7

11B3

DSIZE

OFSHT

DRAWING NUMBER






12345678

12345678

B

C

D

A

B

C

D

A

REV.


NONE



DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICALBOM options for crit. loc.Taiyo - non critical locations only

Note: all caps have CRITICAL BOM options regardless of location.

BOM options for non-crit. loc.

CAP22UF_MURACAP22UF_SAM_CRITCAP22UF_MURA_CRIT

3V42_G3H

Murata

Samsung

PP1V5_30_NB_VCCA_PLL

3V42_G3H

5V_S0,5V_S5,1V5_NB,1V5_S0

Low Acoustic Noise 22uF Ceramic Capacitor options

CAP22UF_TAIYO

CAP22UF_SAM

The vendors for 22uF ceramic capacitors are controlled on this page.The main BOMs must choose a vendor for critical and non-critical locations.

5V_S0,5V_S5,1V5_NB,1V5_S0


5V_S0,5V_S5,1V5_NB,1V5_S0

3V42_G3H


3V3_S5 (2V5_INPUT),2V5_S3,3V3_S3 (1V2_INPUT)


1V8_D3C

3V42_G3H

GPU_MISC

GPU_VIDEO

1V05_S0

1V8_S3

3V3_S5

3V3_S5

1V8_S3

GPU_VIDEO

GPU_MISC

1V8_D3C

3V42_G3H

1V05_S0

1V05_S0

3V42_G3H

GPU_MISC

GPU_VIDEO

1V8_D3C

1V8_S3

3V3_S5


CPU_VCORE

1V2_S3

GPU PCIE

GPU_CORE

VRAM_B

VRAM_A

CPU_VCORE

1V2_S3

GPU PCIE

GPU_VCORE,GPU_BB

GPU_CORE

VRAM_A

VRAM_B

GPU_VCORE,GPU_BB

22uF Capacitor BOM ConfigurationSYNC_MASTER=N/A

105

B051-7270

SYNC_DATE=N/A

105

CAP,CER,22UF,20%,6.3V,X5R,0805 CAP22UF_SAM138S0602 CRITICAL2 C7985,C7986

CAP,CER,22UF,20%,6.3V,X5R,0805 CAP22UF_SAM_CRITC8900,C8920,C8950,C89704 CRITICAL138S0602

CAP22UF_MURA_CRITCAP,CER,22UF,20%,6.3V,X5R,0805138S0603 20 CRITICALC0900,C0901,C0902,C0903,C0904,C0905,C0906,C0907,C0908,C0909,C0910,C0911,C0912,C0913,C0914,C0915,C0916,C0917,C0918,C0919

CAP22UF_MURACAP,CER,22UF,20%,6.3V,X5R,0805138S0603 CRITICAL2 C7846,C7847

CAP22UF_MURA_CRITCAP,CER,22UF,20%,6.3V,X5R,0805 C8400,C8405,C8410 CRITICAL3138S0603

CAP22UF_MURA_CRITCAP,CER,22UF,20%,6.3V,X5R,0805 CRITICAL9138S0603 C8600,C8601,C8630,C8650,C8651,C8652,C8653,C8690,C8695

CAP22UF_MURA_CRITCAP,CER,22UF,20%,6.3V,X5R,0805 CRITICAL4138S0603 C9000,C9020,C9050,C9070

CAP22UF_MURACAP,CER,22UF,20%,6.3V,X5R,0805 CRITICAL138S0603 8 C9100,C9110,C9115,C9120,C9125,C9130,C9135,C9140

CAP22UF_MURACAP,CER,22UF,20%,6.3V,X5R,0805138S0603 9 C9300,C9305,C9310,C9315,C9320,C9325,C9330,C9340,C9345 CRITICAL

CAP22UF_MURACAP,CER,22UF,20%,6.3V,X5R,0805 C7940,C79412 CRITICAL138S0603

CAP22UF_MURACAP,CER,22UF,20%,6.3V,X5R,0805 C78411 CRITICAL138S0603

CAP,CER,22UF,20%,6.3V,X5R,0805 C7940,C79412 CAP22UF_SAMCRITICAL138S0602

CAP,CER,22UF,20%,6.3V,X5R,0805 CAP22UF_SAM_CRIT5 CRITICAL138S0602 C8540,C8541,C8556,C8557,C8589

CAP22UF_SAM_CRITC9000,C9020,C9050,C90704138S0602 CRITICALCAP,CER,22UF,20%,6.3V,X5R,0805

CRITICALCAP,CER,22UF,20%,6.3V,X5R,0805 CAP22UF_SAMC78411138S0602

CAP,CER,22UF,20%,6.3V,X5R,0805 CAP22UF_SAM138S0602 CRITICAL1 C8015

CAP22UF_MURA_CRITCAP,CER,22UF,20%,6.3V,X5R,0805 C8540,C8541,C8556,C8557,C8589 CRITICAL5138S0603

CAP22UF_MURA_CRITCAP,CER,22UF,20%,6.3V,X5R,0805 C8900,C8920,C8950,C8970 CRITICAL4138S0603

CAP22UF_MURACAP,CER,22UF,20%,6.3V,X5R,0805138S0603 CRITICAL2 C7985,C7986

CAP22UF_MURA_CRITCAP,CER,22UF,20%,6.3V,X5R,08054 CRITICAL138S0603 C7755,C7756,C7758,C7759

CAP22UF_TAIYO138S0606 CAP,CER,22UF,20%,6.3V,X5R,0805 CRITICAL2 C7985,C7986

CAP,CER,22UF,20%,6.3V,X5R,0805 C78411 CRITICAL CAP22UF_TAIYO138S0606

CAP22UF_MURACAP,CER,22UF,20%,6.3V,X5R,0805138S0603 8 CRITICALC7616,C7617,C7650,C7651,C7671,C7672,C7690,C7691

CAP22UF_MURA2 CAP,CER,22UF,20%,6.3V,X5R,0805 CRITICAL138S0603 C1934,C1936

138S0602 CRITICAL20 C0900,C0901,C0902,C0903,C0904,C0905,C0906,C0907,C0908,C0909,C0910,C0911,C0912,C0913,C0914,C0915,C0916,C0917,C0918,C0919CAP,CER,22UF,20%,6.3V,X5R,0805 CAP22UF_SAM_CRIT

CAP,CER,22UF,20%,6.3V,X5R,0805 C9300,C9305,C9310,C9315,C9320,C9325,C9330,C9340,C9345 CRITICAL9 CAP22UF_TAIYO138S0606

C9100,C9110,C9115,C9120,C9125,C9130,C9135,C9140CAP,CER,22UF,20%,6.3V,X5R,08058 CRITICAL CAP22UF_TAIYO138S0606


CAP,CER,22UF,20%,6.3V,X5R,0805 C7940,C7941 CRITICAL2 CAP22UF_TAIYO138S0606

CAP22UF_TAIYO138S0606 CRITICALCAP,CER,22UF,20%,6.3V,X5R,08052 C7846,C7847

CAP22UF_TAIYO138S0606 6 C7700,C7709,C7710,C7711,C7751,C7752CAP,CER,22UF,20%,6.3V,X5R,0805 CRITICAL

CAP,CER,22UF,20%,6.3V,X5R,08058 C7616,C7617,C7650,C7651,C7671,C7672,C7690,C7691 CRITICAL CAP22UF_TAIYO138S0606


CAP,CER,22UF,20%,6.3V,X5R,0805 C1934,C1936 CAP22UF_TAIYO138S0606 CRITICAL2

CAP22UF_MURACAP,CER,22UF,20%,6.3V,X5R,0805 C80151 CRITICAL138S0603

CAP22UF_MURACAP,CER,22UF,20%,6.3V,X5R,0805138S0603 CRITICALC7700,C7709,C7710,C7711,C7751,C77526

CAP22UF_MURA138S0603 CAP,CER,22UF,20%,6.3V,X5R,08051 C5802 CRITICAL

CAP22UF_SAMCRITICALC9300,C9305,C9310,C9315,C9320,C9325,C9330,C9340,C93459138S0602 CAP,CER,22UF,20%,6.3V,X5R,0805

CAP22UF_SAM8 CAP,CER,22UF,20%,6.3V,X5R,0805 CRITICAL138S0602 C9100,C9110,C9115,C9120,C9125,C9130,C9135,C9140

CAP,CER,22UF,20%,6.3V,X5R,0805 CAP22UF_SAM_CRIT9138S0602 CRITICALC8600,C8601,C8630,C8650,C8651,C8652,C8653,C8690,C8695

CAP22UF_SAM_CRITCAP,CER,22UF,20%,6.3V,X5R,08053138S0602 CRITICALC8400,C8405,C8410

CAP,CER,22UF,20%,6.3V,X5R,0805 C58021138S0602 CRITICAL CAP22UF_SAM

138S0602 6 CAP,CER,22UF,20%,6.3V,X5R,0805 CRITICAL CAP22UF_SAMC7700,C7709,C7710,C7711,C7751,C7752

CAP,CER,22UF,20%,6.3V,X5R,0805 C7846,C78472138S0602 CRITICAL CAP22UF_SAM

C1934,C19362 CRITICAL138S0602 CAP22UF_SAMCAP,CER,22UF,20%,6.3V,X5R,0805

4 C7755,C7756,C7758,C7759138S0602 CRITICALCAP,CER,22UF,20%,6.3V,X5R,0805 CAP22UF_SAM_CRIT

C7616,C7617,C7650,C7651,C7671,C7672,C7690,C76918 CAP,CER,22UF,20%,6.3V,X5R,0805 CRITICAL CAP22UF_SAM138S0602

Documents

8 7 6 5 4 3 2 1 SCHEM,MLB-PRQ,M59...Yukon Power P.39 P.57-64,69 P.56 Fan SMBus x5 TSB83AA22 FireWire P.43 PHY Power Controller Yukon Gig-E P.39 P.37-38 Controller Connectors SMBus