SSN COLLEGE OF ENGINEERING, IT HIGHWAY, KALAVAKKAM- 603 110

DEPARTMENT OF ELECTRICAL & ELECTRONICS

ENGINEERING

LAB RECORD

131452- LINEAR AND DIGITAL INTEGRATED CIRCUITS LABORATORY

DEC 2011-APRIL 2012

NAME: _____________________________________

REGISTER NO.: ______________________

YEAR: II SEM: 4 SEC: A DEPT: EEE

SYLLABUS

131452-LINEAR AND DIGITAL INTEGRATED CIRCUITS LABOR ATORY

1. Study of Basic Digital IC’s. (Verification of truth table for AND, OR, EXOR, NOT , NOR, NAND, JK FF, RS FF, D FF)

2. Implementation of Boolean Functions, Adder/ Subt ractor

circuits. 3. a. Code converters, Parity generator and parity checking,

Excess 3, 2s Complement, Binary to gray code using suitable IC’s. b. Encoders and Decoders: Decimal and Implementatio n of 4-bit shift registers in SISO, SIPO, PISO, PIPO modes using suitable IC’s.

4. Counters: Design and implementation of 4-bit mo dulo counters

as synchronous and asynchronous Types using FF IC’s and specific counter IC.

5. Shift Registers: Design and implementation of 4- bit shift

registers in SISO, SIPO, PISO, PIPO Modes using sui table IC’s. 6. Multiplex/ De-multiplex- Study of 4:1; 8:1 multi plexer and Study

of 1:4; 1:8 demultiplexer 7. Timer IC applications: Study of NE/SE 555 timer in Astable,

Monostable operation. 8. Application of Op-Amp-I:- Slew rate verification s, inverting and

non-inverting amplifier, Adder, comparator, Integra tor and Differentiator.

9. Study of Analog to Digital Converter and Digital to Analog

Converter: Verification of A/D conversion using de dicated IC’s. 10. Study of VCO and PLL ICs

i. Voltage to frequency characteristics of NE/ SE 5 66 IC. ii. Frequency multiplication using NE/SE 565 PLL IC .

131452 LINEAR AND DIGITAL INTEGRATED CIRCUITS LABORATORY

LIST OF EXPERIMENTS

Expt.

No. Name of the Experiment

1 Study of Logic Gates & Flipflops

2 Implementation of Boolean Functions: Adder & Subtractor circuits

3 Realization of Code converters

4 Testing of Encoders and Decoders

5 Design and Implementation of Counters

6 Testing of Shift Registers

7 Realization of multiplexer-demultiplexer functions using direct IC’s

8 Realization of Astable & monostable modes of 555 timer IC

9 Verification of Op-Amp IC characteristics

10 Op-Amp IC applications –Design and Testing of Inverting amplifier, Non-

inverting amplifier, Summer, Subtractor, Integrator & Differentiator

11 Square & Triangular wave generators using IC741

12 Study of Analog to Digital Converter and Digital to Analog Converter

13 Study of VCO and PLL ICs

ADDITIONAL EXPERIMENTS

A1 Simulation of basic applications of op-amp: Inverting Summer,

Subtractor, Integrator & Differentiator.

A2 Simulation of Waveform generators: Square wave & Triangular wave

generators

A3 Simulation of Monostable & Astable modes of IC 555 timer

A4 Simulation of counters: Binary up & down counters

INDEX

S. NO. DATE EXPERIMENT Page

No.

MARKS/ EXPT. (10)

SIGN. OF THE

STAFF 1 Study of Logic gates & Flip-Flops

2 Implementation of Boolean Functions: Adder & Subtractor circuits

3 Realization of Code converters

4 Testing of Encoders and Decoders

5 Design and Implementation of Counters

6 Testing of Shift Registers

7 Realization of multiplexer-

demultiplexer functions using direct IC’s

8 Realization of Astable & monostable modes of 555 timer IC

9 Verification of Op-Amp IC characteristics

10

Op-Amp IC applications –Design and Testing of Inverting amplifier, Non-

inverting amplifier, Summer, Subtractor, Integrator & Differentiator

11 Square & Triangular wave generators using IC741

12 Study of Analog to Digital Converter and Digital to Analog Converter

13 Study of VCO and PLL ICs

A1 Simulation of basic applications of op-amp: Inverting Summer, Subtractor,

Integrator & Differentiator.

A2 Simulation of Waveform generators:

Square wave & Triangular wave generators

A3 Simulation of Monostable & Astable modes of IC 555 timer

A4 Simulation of counters: Binary up & down counters

COMPLETED / INCOMPLETE / LATE SUBMISSION

TOTAL MARKS:

EXPT NO: DATE:

STUDY OF LOGIC GATES & FLIPFLOPS

AIM:

To realize logic functions using gates & verify the operation of flip-flops. APPARATUS REQUIRED:

S.No Apparatus Range Type Quantity 1

IC 7404 (NOT), IC 7432 (OR), IC 7402 (NOR, IC 7408 (AND),

IC 7400 (NAND), IC 7486 (EX-OR)

1 each

2 IC 7411 (3 Input AND gate), IC 7402 (NOR gate)

1 each

3 Digital IC trainer Board 1 4 Connecting wires

THEORY: A. Gates: 1. NOT Gate

It is called so because its output is not the same as its input. It is also called an Inverter, because it inverts the input signal. It has one input & one output. If A is an input, then Y= A’ is its output. 2. OR Gate

The OR gate has an output of 1 when either A or B or Both are 1.In other words, it is an any-or-all gate because an output occurs when any or all inputs are present. The OR gate truth table, may be defined as a table, which give the output state for all possible input combinations. If A and B are inputs, then the output is Y = A+B. 3. NOR Gate

This is NOT-OR gate. It can be made out of an OR gate by connecting an inverter in its output. A NOR gate will have an output of 1 only when all its inputs are 0. If any one of the input is 1, then output is 0. In a NOR gate, the output is true only all inputs are false. If A & B are inputs, then output Y = (A+B)’ 4. AND Gate

The AND gate gives an output only when all its inputs are present. The AND gate has output 1 if both A & B are 1. Hence this is an all-or-nothing gate whose output occurs only all its inputs are present. The output Y= A . B. 5. NAND Gate

This is NOT-AND gate. It can be made out of an AND gate by connecting an inverter in its output. A NAND gate will have an output of 1 when all its inputs are 0. If any one of the input is 1, then output is 1. In a NAND gate, the output is true only all inputs are false. If A & B are inputs, then output Y = (A.B)’ 6. EX-OR Gate

In this gate, output is one if its input but not both is 1.In other words, it has an output 1 if its inputs are different. The output is 0, if its input is same. It is also called Inequality Comparator. The output Y= A’ B + A B’

7. Universal Gates The Universal gates are NAND and NOR gates because the logic gates like

NOT, OR and AND can be realized using these gates.

B. Flip-flops: Flip Flops is a bi-stable multivibrator circuit that has two stable states. The FF

can be used as memory device since it can maintain a binary state indefinitely (as long as power is delivered to the circuit) until directly by an input signal to switch states. It forms the heart of all sequential digital circuits. The FF is often called a latch, since it will hold, or latch in either stable state. The FF has two outputs; one for the normal valve and another one for the complement value of the bit stored in it.

Binary information can enter a flip-flop in a variety of ways, a fact which gives rise to different types of Flip-Flops. The different types of Flip Flops are RS FF, Clocked RS FF, D FF, JK FF and T FF. The major differences among various types of FFs are in the number of input they possess and in the manner in which the inputs affect the binary state. The important applications of FFs are

• Storage register • Shift register • Frequency divider • Counters

1. RS Latch

RS latch is an asynchronous sequential circuit because the cross-coupled connection from the output of one gate to the input of other gate constitutes a feedback path. This Circuit can be constructed from NAND gates or two NOR gates. It has 2 inputs, Reset and Set and two outputs, Q & Q’.

To analyze the operation of the circuit Fig-1, we must remember that the output of a NOR gate is 0 if any input is 1, and the output is 1 only when all inputs are 0.

As a starting point, assume that the set input is 1 and the reset input is 0.Since the gate 2 of input is 1, its output Q’ is 0 which puts both inputs of gate 1 at 0,so that he output Q is 1.

When the set input is returned to 0, the output remains the same, because the output Q remains 1, leaving one input of gate 2 at 1. That causes output Q’ to stay at 0, which leaves both inputs of gate number 1 at 0, so that output Q in a 1. In the same manner it is possible to show that a 1 in the reset input changes output Q to 0 and Q’ to 1. When the reset input returns to 0, the outputs do not change.

When a 1 is applied to both the set and the reset inputs, both Q and Q’ outputs go to 0. This condition violates the fact that outputs Q and Q’ are the compliments of each other. In normal operation this condition must be avoided by making sure that 1’s are not applied to both inputs simultaneously.

2. Clocked RS Flip-Flop:

The operation of the basic FF can be modified by providing an additional control input that determines when the state of the circuit is to be changed. The clocked RS flip-flop shown in fig consists of a basic flip-flop circuit and two additional NAND gates.

The clock pulse input acts as an enable signal for the other two inputs. The outputs of NAND gates 3 and 4 stay at the logic 1 level as long as the clock input (abbreviated CP) remains at 0.This is the quiescent condition for the basic FF.

When the clock pulse input goes to 1, information from the S or R inputs is allowed to reach the output. The set state is reached with S=1, R=0, and

CP=1. This causes the output of gate 3 to go to 0,the output of gate 4 to remain at 1,and the output of the FF at Q to go to1.

To change to the reset state, the inputs must be S=0, R=1, and CP=1.In either case, when CP returns to 0, the circuit remains in its previous state

When CP=1 and both the inputs S and R are equal to 0, the state of the circuit does not change.

An indeterminate condition occurs when CP=1 and both the inputs S=1, R=1. This condition places 0’s in the outputs of gates 3 and 4 and 1’s in both outputs Q and Q’. When the clock pulse goes back to 0 (while S=R=1), it is not possible to determine the next state, as it depends on whether the output of gate 3 or gate 4 goes to 1 first. This indeterminate condition makes this circuit difficult to manage and it is seldom used in practice. Nevertheless, it is important circuit because all other flip-flops are constructed from it.

3. Delay Flip Flop

The RS FF has two data inputs and therefore, generation of two signals to drive a FF is a disadvantage in many applications. One way to eliminate the undesirable condition of the indeterminate state in the clocked RS FF is to ensure that inputs S and R are never equal to 1at the same time. This has lead to the D FF, a circuit that needs only single data input.

The D input goes directly to the S input, and its complement, through gate 5, is applied to the R input. As long as the clock pulse input is at 0, the output of gates 3 and 4 are at the 1 level and the circuit cannot change state regardless of the value of D. This conforms to the requirement that the two inputs of a basic NAND flip flop remain initially at the 1 level.

The D input is sampled during the occurrence of a clock pulse. If D is 1, the output f gate 3 goes to 0, switching the flip-flop to the set state. If D is 0, the output of gate 4 goes to 0, switching the flip-flop to the clear state.

The D FF receives the designation from its ability to hold data into its internal storage. When the clock input goes high, input data is loaded into the FF and appears at the output. Then when the clock pulse goes low, the output retains the data.

The characteristic equation shows that the next state of the flip-flop is the same as the D input and is independent of the value of the present state.

4. J-K Flip Flop

A JK flip flop is a refinement of the RS flip flop in that the indeterminate state of the RS type is defined in the JK type. Inputs J and K behave like inputs S and R to set and clear the flip-flop respectively. When both inputs J=K=1 simultaneously the flip-flop switches to its complement state, that is if Q=1, it switches to Q’ =0 and vice versa.

A clocked JK flip-flop is shown in fig -5. Output Q is AND-ed with K and CP inputs so that the flip-flop is cleared during a clock pulse only if Q was previously 1. Similarly, output Q’ is AND-ed with J and CP inputs so that the flip-flop is set with a clock pulse only if Q’ was previously 1.

When both J and K are 1, the clock pulse is transmitted through one AND gate only. The one whose input is connected to the flip-flop output which is presently equal to 1. Thus if Q=1, the output of the upper AND gate becomes 1 upon application of a clock pulse, and the flip-flop is cleared. If Q’=1, the output of the lower AND gate becomes a 1 and the flip-flop is set. In either case, the output state of the flip-flop is complemented.

It is very important to realize that because of the feedback connection in the JK FF, a clock pulse that remains in the 1 state while both J=K=1 will cause the output to complement again and repeat complementing until the clock pulse goes back to 0.this is called Race-around condition in the FF.

To avoid this indeterminate condition, clock pulse must have time duration that is shorter than the propagation delay time of FF. This is a restrictive requirement, since the operation of the circuit depends on the width of the pulses. For this reason, JK flip-flop are never constructed.

The restriction on the pulse width can be eliminated with a mater- slave or edge-triggered flip flop.

The same reasoning applies to the T flip-flop.

5. Toggle Flip Flop The Toggle flip-flop is a single input version of the JK flip-flop. The T flip flop

is obtained from a JK type if both inputs are tied together. The designation T comes from the ability of the flip-flop to “toggle” or

complement its state. Regardless of the present state of the flip-flop complements its output when the clock pulse occurs while input T is logic-1.

The characteristic equation shows that when T=0, Q (T+1)=Q, that is next state is same as the present sate and no change occurs. When T=1, Q (T+1)=Q’ that is the state of FF is complemented.

PROCEDURE: A. Gates:

• In a digital IC trainer board, Fix the IC s firmly and the connections are made as per the circuit diagram.

• Apply +5 V to the 14th pin of IC s 7404, 7432, 7402, 7408, 7400 & 7486 and connect ground to the 7th pin of IC s.

• Apply inputs to the circuit & verify the outputs with Truth table. • To realize a particular gate using Universal gates, Connect the IC s as shown

in logic diagram and verify the truth table for that particular gate, Repeat the same for other gates.

B. Flip-flops:

• Fix the IC s firmly in a digital IC trainer board and the connections are made as per the logic diagram.

• Apply +5 V to the 14th pin of IC’s 7411, 7402 & 7404 and connect ground to the 7th pin of all the IC’s.

• Apply the proper input (i.e. data and clock inputs) to the Logic circuit and Check all the conditions stated in its function table

RESULT:

Thus the logic functions are realized using different gates & verify the operation of different flip-flops.

TTL Gate Pin Details:

LOGIC DIAGRAM & FUNCTION TABLE OF DIFFERENT TYPES O F GATES:

LOGIC DIAGRAM & FUNCTION TABLE OF DIFFERENT TYPES O F FLIP-FLOPS:

1. RS LATCH USING NOR GATE:

2. RS LATCH USING NAND GATE:

3. CLOCKED RS FLIP-FLOP:

4. D FLIP-FLOP:

5. J-K FLIPFLOP:

6. T FLIP-FLOP:

EXPT NO: DATE:

IMPLEMENTATION OF BOOLEAN FUNCTIONS: ADDER & SUBTRA CTOR

AIM:

To test the Half & Full adder and Half & Full subtractor circuits. APPARATUS REQUIRED:

S.No Apparatus Range Type Quantity 1

IC 7432 (OR), IC 7408 (AND), IC 7486 (EX-OR),IC7404(NOT)

1 each

2 Digital IC trainer Board 1 3 Connecting wires

THEORY: 1. Half Adder

It has 2 inputs for applying to the 2 binary digits to be added. Binary addition of 2 bits always produces 2 bit output data. One is sum & another one is Carry. For example, (1+1) gives a sum of 0 & a carry of 1. The sum output has the same logic pattern as X-OR ed with B. Also the carry output has the same logic pattern as when A is And ed with B. So the Half Adder can be formed from the combination of one X-OR gate and one AND gate. 2. Full Adder

It has three inputs and two outputs. It can add 3 digits at a time. The bits A and B which are to be added come from two registers and third input comes from the carry which is generated by the previous addition. It produces two outputs: Sum & Carry. A & B are the inputs from the respective digits of the registers to be added and C is the input for any carry generated by the previous stage. The sum output gives binary addition of A, B & C. The other generates the Carry Co to be added to the next stage. For example, A=B= 1& C=1, We get final Sum is 1 & Carry is 1. PROCEDURE:

• In a digital IC trainer board, Fix the IC s firmly and the connections are made as per the logic diagram.

• Apply +5 V to the 14th pin of IC s 7432, 7408 & 7486 and connect ground to the 7th pin of IC s.

• Check all the conditions from the Truth table by applying the proper input to the Logic diagram.

RESULT:

Thus the Half Adder & Full Adder Circuits are tested.

LOGIC DIAGRAM & FUNCTION TABLE: 1.Half Adder

2. Full Adder

INPUT OUTPUT

A

B

C Sum S =

A@B@C

Carry C=AB+BC+C

A 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1

3.Half Subtractor

4.Full Subtractor

INPUT OUTPUT

A

B

Bin Difference

D Borrow

Bout 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1

Expt. No.: Date :

a) DESIGN OF CODE CONVERTERS AIM: To Design and implement a combinational logic circuit that converts

1. BCD Code to Excess -3 code 2. 4 Bit Binary Code to Gray Code.

APPARATUS REQUIRED: S.No Apparatus Required Range Type Quantity

1 Digital IC trainer Board - - 1 2 IC 7404, - - 1 3 IC 7408 - - 2 4 IC7432 - - 1 5 IC7486 - - 1 6 Connecting Wires.

THEORY:

The availability of a large variety of codes for the same discrete elements of information results in the use of different codes by different digital system. It is sometimes necessary to use the output of one system as the input to another. A conversion circuit must be inserted between the two systems if each uses different codes for the same information. Thus, a converter is a circuit that makes the two systems compatible even though each uses a different code. A combinational circuit performs this transformation by means of logic gates.

The BCD (binary coded decimal) is a straight assignment of the binary equivalent. It is possible to assign weights to the binary bits according to their positions. The weights in the BCD code are 8, 4, 2, 1.The bit assignment 0110, for example, can be interpreted by the weights to represent the decimal digit 6 because 0*8+1*4+1*2+0*1=6.A decimal code that has been used in some old computers is the excess-3 code. This is an un-weighted code; its code assignment is obtained from the corresponding value of BCD after the addition of 3.

General Design Procedure:

1. Derive the truth table for both the simple code converter including DON'T CARE conditions. 2. Minimize the resulting logic functions using Karnaugh Maps. Be sure to take

advantage of DON'T CARE conditions when possible. 3. Design an implementation of the simple code converter using the TTL parts

available to you. Summarize the total number of parts of each type needed in your design.

Procedure for BCD code to Excess-3 Code

1. List the bit combinations (truth table) for the BCD input code and Excess-3 output codes. Since each code uses four bits to represent a decimal digit, there must be four input variables and four output variables. Let us designate the four input binary variables by the symbols A, B, C and D, and the four output variables by w, x, y and z.

2. Four bit binary variables may have 16 bit combinations, only 10 of which are listed in the truth table. The six bit combinations not listed for the input variables are don’t care combinations. Since they will never occur, we have

the liberty to assign the output variables either a 1 or 0, whichever gives a simpler circuit.

3. The maps are drawn to obtain a simplified Boolean function for each output. Each of the four maps represents one of the four outputs of this circuit as a function of the four input variables. The 1’s marked inside the squares are obtained from the min-terms that make the output equal to 1.The 1’s are obtained from the truth table by going over the output columns one at a time.

4. The Boolean expressions obtained may be manipulated algebraically for the purpose of using common gates for two or more outputs. This manipulation, shown below, illustrates the flexibility obtained with multiple-output systems when implemented with three or more levels of gates. z =D’

y =CD +C’D’ = CD+(C+D)’

x =B’C+B’D+BC’D’ = B’(C+D) +BC’D’

=B’(C+D) +B(C+D)’

w =A+BC+BD =A+B(C+D)

5. The logic diagram that implements the above expression is shown below:

Similarly, the above said procedure is applied for converting 4 Bit Binary Code to Excess-3 Code.

1. BCD TO EXCESS -3 CODE CONVERSION

Truth table :

Karnaugh maps:

LOGIC DIAGRAM FOR BCD TO EXCESS -3 CODE CONVERTER

2. BINARY TO GRAY CODE CONVERSION Truth table:

BINARY TO GRAY CODE CONVERSION-Karnaugh’s Maps:

LOGIC DIAGRAM FOR BINARY TO GRAY CODE CONVERTER USI NG AND, OR

& NOT GATES

TTL GATE PIN DETAILS

RESULT: Thus the combinational circuit that converts BCD Code to Excess -3 code and 4 Bit Binary Code to Gray Code are designed and verified with the truth Table.

Expt. No.: Date:

TESTING OF ENCODERS and DECODERS

AIM:

To verify the operation of Octal to Binary inverting Priority Encoder (8 to 3 Encoder) using IC 74148 and Binary to Octal Decoder (3 to 8 Decoder) using IC 74138. APPARATUS REQUIRED: S.No Apparatus Required Range Type Quantity

1 Digital IC trainer Board - - 1 2 IC 74148 - - 1 3 IC 74138 - - 2 4 Patch Chords - -

THEORY:

An Encoder is a combinational logic circuit that converts an active input signal (i.e. decimal) into a binary coded output signal. An encoder has 2n (or less) input lines and ‘n’ output lines. The output lines generate the binary code for the 2n input variables.

Discrete quantities of information are represented in digital system with binary codes. A binary code of ‘n’ bits is capable of representing up to 2n distinct elements of the coded information.

A decoder is a combinational circuit that converts binary information form ‘n’ input lines to a maximum of 2n distinct elements of coded information. If the n-bit decoded information has unused or don’t combinations, the decoder output will have less than 2n outputs. The name decoder is also used in conjunction with some code converters such as a BCD to seven-segment decoder.

Working of 8 to 3 Priority Encoder Using IC- 7414 8:

IC 74148 octal to binary encoder accepts 8 input data lines and produces a 3 bit binary output code (octal), corresponding to the activated output. It is also a priority encoder because it gives priority to the highest order input data line. Here, both the data inputs and outputs are active LOW logic level. Cascading circuitry (an enable input EI and an enable output EO) has been provided to allow octal expansion without the need for external circuitry. This allows octal expansion without the need for an external circuitry. The enable input EI must be asserted to LOW state to enable the chip while the enable output EO goes to LOW state only when all its inputs are inactive (i.e. HIGH State). Also, there is one more output, namely GS, Which goes low whenever one of its inputs is active (i.e. LOW State). Its operation is explained in the function table-1.

A priority encoder includes the necessary logic to ensure that when two or more inputs are activated, the output code will correspond to the highest numbered input, For example, when both A3 and A5 are ‘LOW’, the output code will be 101(i.e.5). Similarly, when A6and A2, A0 are all LOW, the output code is 110 (i.e. 6). Working of 3 to 8 Binary to Octal Decoder Using IC -74138:

Figure(c) shows the logic diagram for IC 74138 decoder. By examining this diagram carefully, first notice that it has NAND gate outputs, so that output are active

LOW. Another indication is the labeling of the outputs as Ỹ7, Ỹ6, Ỹ5 and so on. The over bar indicates active LOW Outputs. Since NAND gate produces the AND operation with an inverted output, it becomes more economical to generate the decoder min-terms in their complemented form.

The input code is applied at A2, A1and A0, where A2 is the MSB. With three inputs and eight outputs; this is a 3 to 8 decoder, or equivalently a 1 to 8 decoder. E1, E2 and E3 are separate enable inputs that are combined in AND gate. In order to enable the output NAND gates to responds to the input code at A2 A1A0, this AND gate output must be HIGH. This will occur only when Ē1=Ē2=0 AND E3=1. In other words, E1 and E2 are active LOW, E3 is active HIGH, and all there must be in their active states to activate the decoder outputs. If one or more of the enable inputs is in the inactive state, the AND gate output will be LOW, which will force all NAND output to their inactive HIGH state regardless of the input code. This operation is summarized in the following truth table (a).

Tabulation (a)

Where ‘x’ is the don’t care condition.

8 to 3 Octal to Binary ENCODER- IC 74148

14

15

16

11

12

13

9

10

3

2

1

6

5

4

8

7

A2

D7

D6

Vcc

A1

D4

D0

A0GND

D5 EO

D1

GS

D2

D3

EI IC 7

4148

10

11

13

12

2

1

3

5

4

6

7

14

6

15

D0

D2

D1

D4

D3

D6

D5

EI

D7 GS

EO

A1

A0

A2

Fig (a) PIN DIAGRAM Fig (b) LOGIC SYMBOL

3 to 8 Binary to Octal DECODER -IC 74138

14

15

16

11

12

13

9

10

3

2

1

6

5

4

8

7

A2

E3

Y7

A0

E1

Y6GND

Vcc

A1

Y5

Y1

Y0

Y4

Y2

E2 Y3

IC 7

4138

A2

Y4

Y3

Y2

Y1

Y7

Y6

Y5

Y0

3

2

1

6

9

7

11

10

13

12

15

14

4

5

E1

A0

A1

E3E2

Fig (c) PIN DIAGRAM Fig (d) LOGIC SYMBOL

8 to 3 OCTAL TO BINARY PRIORITY ENCODER IC-74148

LOGIC DIAGRAM:

LOGIC DIAGRAM: 3 to 8 BINARY TO OCTAL DECODER IC -7 4138

FUNCTIONAL TABLE (2)

B .LOGIC FUNCTION IMPLEMENTATION USING DECODER (I) F(X, Y, Z) =π m (2, 3, 5) TRUTH TABLE:

74111

12213

Z

Y

X

F(X,Y,Z)4

3

0

7

1

2

6

5

(ii) F (X, Y, Z) =E m (0, 1, 4, 6) TRUTH TABLE:

4

3

0

7

1

2

6

5

74206

12

45

Z

Y

XF(X,Y,Z)

RESULT:

Thus, the working of Octal to Binary inverting Priority Encoder using IC 74148 and Binary to Octal Decoder using IC 74138 are verified and also logical expressions are implemented using decoder and logic gates.

INPUTS

OUTPUTS

E3

Ê2

Ê1

Ā2

Ā1

Ā0

Ỹ0

Ỹ1

Ỹ2

Ỹ3

Ỹ4

Ỹ5

Ỹ6

Ỹ7

X L X H H H H H H H H

X X H L L L L L L L L

H X X L L L L L L L L

X X X L L L L H H H H

X X X L L H H L L H H

X X X L H L H L H L H

H H H L H H H H H H H

H H H H L H H H H H H

H H H H H L H H H H H

H H H H H H L H H H H

H H H H H H H L H H H

H H H H H H H H L H H

H H H H H H H H H L H

H H H H H H H H H H L

X Y Z O/P 0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

1 1 0 0 1 0 1 1

X Y Z O/P

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

1 1 0 0 1 0 1 0

Expt. No: Date:

DESIGN & IMPLEMENTATION OF COUNTERS AIM: To design a mod-5 Synchronous Counter and 3-bit Asynchronous binary Counter using JK Flip-Flop and Verify their function with the truth table. APPARATUS REQUIRED: S.No Apparatus Required Range Type Quantity

1 Digital IC trainer Board - - 1 2 IC 7476 - - 2 3 IC 7432, IC 7408 - - 1(Each) 4 Patch Chords - -

THEORY:

A counter is one of the most useful and versatile subsystems in a digital system. A sequential circuit that goes through a prescribed sequence of states upon the application of input pulses is called a ‘counter’. The input pulses, called count pulses may be clock pulses, or they may originate from an external source and may occur at prescribed intervals of time or at random. In a counter, the sequence of states may follow a binary count or any other sequence of states.

Counter has a natural count of 2n where ‘n’ is the number of flip-flop in the counter. Modulus of a counter is the total number of states through which the counter can progress. For example mod-8 counter has 8 states.

Counter of any modulus can be constructed by incorporating logic, which causes certain states to be skipped over, or omitted. One technique for skipping counts is to steer clock pulses to certain FFs at the proper time-this is called steering logic. A second technique is to precondition the logic inputs to each FF in order to omit certain states. This is called look-ahead logic.

Logic can be included such that the counter can operate in either a count-up or count-down mode. Furthermore, logic gates can be designed to uniquely decode each state of a counter.

There are basically two different types of counters.

• Synchronous or parallel counter • Asynchronous or serial counter

An asynchronous or ripple counter in which each flip-flop is triggered by the output of the previous flip-flop and all the FF’s do not change states in exact synchronism with the applied clock pulses. The first flip flop must change state before it can trigger the second FF, and the second FF has to change state before it can trigger the third FF and so on. The triggers move through the flip-flop like a ripple in water. Because of this, the overall propagation delay time is sum of all the individual delays i.e. the total settling time is approximately equal to n ∗delay time of single FF, where ‘n’ is the total number of FF. Therefore the speed of operation is limited.

A synchronous counter in which all flip-flops change states simultaneously since all clock inputs are driven by the same clock and the settling time is equal to the delay time of a single flip-flop. Therefore the speed of operation can be increased.

The basic function of a counter is to “memorize” how many clock pulses have been applied to the input; hence in the most basic sense counters are memory systems. The important applications are (i) counting pulse, (ii) frequency division (iii) time measurement (iv) control and timing operations. Working of Three Bit Asynchronous Binary Counter 1. Up Counter: Up counter is one, which will count upward from zero to a maximum count. A binary 3-bit ripple counter can be constructed by using the clocked JK flip-flop. Let’s assume that all FF are in the logic ‘0’ states.

1. A clock pulse is applied only to the clock input of FF-A. Thus FF-A will toggle (change to its opposite state) each time the clock pulse make a negative (HIGH to LOW) transition. Note that J= K=1 for all the FF’s.

2. The normal output of FF-A acts as the clock input for FF-B, and so FF-B will toggle each time the FF-A output goes from 1 to 0. Similarly, FF-C will toggle when FF-B goes from 1to 0.

3. FF outputs C, B and A represent a 3-bit binary number with C as the most significant bit (MSB). The waveforms in fig 1 show that a binary counting sequence from 000 to 111 is followed as clock pulses are continuously applied.

4. After the NGT (negative going transition) of the seventh clock pulse has occurred the counter FF’s are in the 111 condition.

5. On the eighth NGT, the FF-A goes from 1 to 0 which causes FF-B to go from 1 to 0, and so on, until the counter is in the 000 state. In other words, the counter has gone through one complete cycle (000 through 111) and has recycled back 000, from where it will begin new a counting cycle as subsequent clock pulses are applied.

2. Down Counter: Down counter is one, which will count downward from a maximum count to zero. Let as examine the countdown sequence for a 3-bit binary down counter.

1. A, B and C represent the FF output states as the counter goes through its sequence. It can be seen that FF-A (LSB) changes states (toggles) at each step in the sequence just as it does in up counter. The FF-B changes states each time B goes from LOW to HIGH; C changes states each time B goes from LOW to HIGH. Thus, in a down counters each FF, except first, must toggle when the preceding FF goes from LOW to HIGH.

2. If the FFs have clock inputs that respond to negative transitions (HIGH to LOW), then an inverter can be placed in front of each FF clock input; however the same effect can be accomplished by driving each FF clock input from inverted output of preceding FF. this is illustrated in fig 2 for a Mod 8 down counter.

3. The input pulses are applied to the FF-A .The Ā output serves as the clock input for FF-B, the B’ output serves as clock for FF-C. The waveforms at A, B and C show that B toggles whenever A goes LOW to HIGH (so that Ā goes HIGH to LOW) and C toggles whenever B goes LOW to HIGH. This results in the desired down counting sequence at the C, B, and A outputs.

Applications: Down counters are not as widely used as up counters. Their major application is in situations where it must be known when a desired number of input pulses have occurred. In these situations the down counter is preset to desired number and then allowed to count down as the pulses are applied. When the counter reaches the zero state, a logic gate whose output then indicates that the preset number of pulses has occurred detects it. Design Of Mod-5 Synchronous Counter

Basic idea: In synchronous counters the FF’s entire are clocked at the same time. Before

each clock pulse, the input of each FF in the counter must be at the correct level to ensure that the FF goes to the correct state. Therefore, the process of designing a synchronous counter then becomes one of designing the logic circuits that decode the various states of the counter to supply the logic levels to each FF input. The inputs to these decoder circuits will come from the outputs of one or more of the FF’s. Design Procedure:

In order to design a MOD-5 counter the number of flip-flops required is three. This is found from the equation 2n ≥N, where N=5, the number states present in MOD-5 counter. Let us assume that the MOD-5 counter has five states 000, 001, 010, 011 and 100.The counter is to designed by treating the unused states 101,110 and 111 as don’t care condition. Step 1: State transition diagram The state diagram for Mod-5 counter can be drawn as shown in figure below here it is assumed that the state transition from one state to another takes place when the clock pulse is asserted; when the clock is unasserted, the counter remains in present state.

Fig. State transition diagram for mod-5 counter Step 2: State transition table Use the state transition diagram to setup a table that lists all present states and their next states. The undesired states 101, 110, and 111 are considered as don’t care condition.

PRESENT state NEXT state C B A C B A 0 0 0 0 1

0 0 1 1 0

0 1 0 1 0

0 0 0 1 0

0 1 1 0 0

1 0 1 0 0

Step 3: J-K flip-flop excitation table

FF EXCITATION

Inputs

PRESENT state Q(t)

NEXT state

Q(t+1) J K

0 0 1 1

0 1 0 1

0 1 x x

x x 1 0

Step 4: Circuit excitation table Our design uses 3 FFs, C, B and A of each one has J and k input. Therefore, we must add three new columns as shown in the table. This complete table is called circuit excitation table. The entries under each J and K are obtained from state transition table and JK FF excitation table.

Step 4: Excitation Maps Design the logic circuits to generate the levels required at each J and K input using Karnaugh’s map. The circuit excitation table, lists six J and K inputs, JC, KC, JB, KB and JA, KA .We must consider each of these as an output from its own logic circuit with inputs from flip-flops C, B and A. Then we must design circuit for each one.

PRESENT

State

NEXT State

FF EXCITATION INPUTS

C B A C B A JC KC

JB KB

KA JA

0 0 0 0 0 1 0 1 0 0 1 1 1 0 0

0 0 1 0 1 0 0 1 1 1 0 0 0 0 0

0 x 0 x 0 x 1 x x 1

0 x 1 x x 0 x 1 0 x

1 x x 1 1 x x 1 0 x

Fig. K-Mappin g For FF Excitation Inputs Step 5: Implement the final expressions The logic circuits for each J and K inputs are implemented from the expressions obtained from the K-Mapping. The complete synchronous counter design is implemented in fig 1. IC 7476 DUAL EDGE TRIGGERED ‘JK’ FLIP-FLOP

PIN DIAGRAM

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9

10

11

3

2

1

5

4

8

7

62 CLK

1CLR

2 PRE

1 CLK

1J

2Q

2 J 2 CLR

1 K

1 PRE

2Q

1Q

1Q

2K

GND

Vcc

LOGIC SYMBOL

LOGIC DIAGRAM: Three-Bit Asynchronous Binary Up-Cou nter

6

CL

K CL

K CL

K

K

JJJ

K K Q

Q

Q

Q

Q

Q

PRESE

T

CLEA

R

CLOC

K

HIG

H

4

1

2

9

1

4

1

5

1

1

1

0

1

4

1

5

1

6

4

CBA

FF-

C

FF-

B

FF-

A

38

2 7 2

3

1 16

PR

E PR

E

CL

R CL

R CL

R

PR

E

Timing diagram:

Truth table:

LOGIC DIAGRAM: Three-Bit Asynchronous Binary Down-C ounter

Outputs (Binary)

FF-C FF-B FF-A

Clear

Preset

Clock pulse Transition

C B A

Decimal Count

1 1 -- 0 0 0 0 1 1 1 0 0 1 1 1 1 2 0 1 0 2 1 1 3 0 1 1 3 1 1 4 1 0 0 4 1 1 5 1 0 1 5 1 1 6 1 1 0 6 1 1 7 1 1 1 7 1 1 8 0 0 0 0 1 1 9 0 0 1 1

6

CLK CLK CLK

K

J J J

K K Q

Q

Q

Q

Q

Q

PRESET

CLEAR

CLOCK

HIGH

4

12

9

14

15 11

10 14

15

16

4

C B A

FF-C FF-B FF-A

3 8

2 7 2

3

1 1 6

PRE PRE

CLR CLR CLR

PRE

Truth table:

Waveform:

Outputs (Binary) Clear

Preset

Clock pulse

Transition FF-C

C FF-B

B FF-A

A

Decimal Count

0 0 -- 0 0 0 0 1 1 1 1 1 1 7 1 1 2 1 1 0 6 1 1 3 1 0 1 5 1 1 4 1 0 0 4 1 1 5 0 1 1 3 1 1 6 0 1 0 2 1 1 7 0 0 1 1 1 1 8 0 0 0 0 1 1 9 1 1 1 7

Logic diagram: Mod-5 Synchronous Counter

Truth Table:

Waveform:

Outputs (Binary) Clear

Preset

Clock pulse

Transition FF-C

C FF-B

B FF-A

A

Decimal Count

1 1 -- 0 0 0 0 1 1 1 0 0 1 1 1 1 2 0 1 0 2 1 1 3 0 1 1 3 1 1 4 1 0 0 4 1 1 5 0 0 0 0 1 1 6 0 0 1 1 1 1 7 0 1 0 2

16

4

A B

C

FF-B FF-C FF-A

1 6

1

3 8

2

3

7

7408

1

2 3

2

CLR

CLK

CLK

CLK

PRE PRE PRE

CLRCLR

J J

K K

J

Q K

Q

Q

Q Q

Q

CLEAR

PRESET

+5v 12

4

14 16

9 11

15 15

14 10

CLOCK

PROCEDURE: 1. Give the circuit connections as per logic diagram. 2. Give the input signal (clear & preset inputs) and the clock pulse. 3. Observe the output and verify this with the truth table. 4. Draw the observed waveforms.

RESULT: Thus the Mod-5 Synchronous counters and 3-bit Asynchronous binary counter are designed and their workings are verified with the truth table.

EXPT NO: DATE:

TESTING OF SHIFT REGISTERS

AIM:

To design SISO and SIPO Shift Register using Delay flip-flop with 4 bit word 1101 and to verify the function with their truth table. APPARATUS REQUIRED:

S.No Apparatus Range Type Quantity 1 IC 7474 (D’FF 2 2 Digital IC trainer Board 1 3 Connecting wires

THEORY:

A register is a group of flip-flops that can be used to store a binary number. There must be one flip-flop for each bit in the binary number. An ‘n’ bit register has a group of ‘n’ FFs and is capable of storing any binary information containing ‘n’ bits. A group of flip-flops connected in such way that a binary number can be shifted into or out of the flip-flops is called shift register. There are two ways to shift data into a resister (i.e. serial or parallel) and similarly two ways to shift the data out of the register.Serial shifting involves shifting data 1 bit at a time in a serial fashion beginning with either the MSB or LSB. Parallel shifting involves shifting all the data bit simultaneously with single clock transition. Hence, the parallel shifting method is much faster than the serial shifting method. They are classified into following four types based on how binary information is entered or shifted out.

a) Serial-in Serial-out Shift Register (SISO) b) Serial-in Parallel-out Shift Register (SIPO) c) Parallel-in Serial-out Shift Register (PISO) d) Parallel-in Parallel-out Shift Register (PIPO)

Working of SISO Shift Register

Data was stored in as well as shifted out of the register at flip-flop in a serial fashion. Hence, it is called serial input and serial output shift register (SISO). This shift register can be built using D FF as shown in figure. The clock pulse is applied to all the FFs simultaneously. When the shift or clock pulse occurs, each FF is set or reset according to the data at the respective FF input. Let us illustrate the entry of 4 bit binary number 1101 in to a register beginning with LSB. Before apply the clock input, the register is cleared using CLEAR input and therefore the register holds A=0; B=0; C=0; D=0.

At clock pulse 1: first data bit ‘1’ is loaded into serial data input i.e. FF-A. The content of the register is shifted one flip-flop to the right. The register holds the bits A=1; B=0; C=0; D=0.

At clock pulse 2: Second data bit ‘0’ is applied into serial data input i.e. FF-A. The content of the register is shifted one flip-flop to the right. The register holds the bits A=0; B=1; C=0; D=0.

At clock pulse 3: third data bit ‘1’ is applied into serial data input i.e. FF-A. The content of the register is shifted one flip-flop to the right. The register holds the bits A=1; B=0; C=1; D=0.

At clock pulse 4: Last data bit ‘1’ is applied into serial data input i.e. FF-A. The content of the register is shifted one flip-flop to the right. The register holds the bits A=1; B=1; C=0; D=1.

This completes the serial entry of the 4-bit number 1101 into a shift register. Let us illustrate the retrieve of 4 bit binary number 1101 from a register beginning with LSB=1.

At clock pulse 5: the entire number is shifted one flip-flop to the right. A ‘0’ is shifted into FF-A and the LSB shifted out the right and lost. The register holds the bits ABCD=0110 and the second LSB (0) appear at D.

At clock pulse 6: the entire number is shifted one flip-flop to the right. A ‘0’ is shifted into FF-A and third LSB (1) appears at D. The register holds the bits ABCD=0011

At clock pulse 7: the entire number is shifted one flip-flop to the right. A 0 is shifted into FF-A and MSB (1) appears at D.The register holds the bits ABCD=0001

This completes the serial retrieve of the 4 bit number 1101 from a shift register.

Working of SIPO Shift Register:

In this type data is shifted in serially, but shifted out in parallel. In order to shift the data out in parallel, it is simply necessary to have all the data bits available as outputs at the same time. This is easily accomplished by connecting the output of each flip-flop to an output pin. Let us illustrate the entry & retrieve of 4 bit binary number 1101 in to a register beginning with LSB. Before apply the clock input, the register is cleared using CLEAR input and therefore the register holds A=0; B=0; C=0; D=0.

At clock pulse 1: first data bit ‘1’ is loaded into serial data input i.e. FF-A. The content of the register is shifted one flip-flop to the right. The register holds the bits A=1; B=0; C=0; D=0.

At clock pulse 2: Second data bit ‘0’ is applied into serial data input i.e. FF-A. The content of the register is shifted one flip-flop to the right. The register holds the bits A=0; B=1; C=0; D=0.

At clock pulse 3: third data bit ‘1’ is applied into serial data input i.e. FF-A. The content of the register is shifted one flip-flop to the right. The register holds the bits A=1; B=0; C=1; D=0.

At clock pulse 4: Last data bit ‘1’ is applied into serial data input i.e. FF-A. The content of the register is shifted one flip-flop to the right. The register holds the bits A=1; B=1; C=0; D=1.

Thus the data word is now made available in a parallel fashion.

Applications

• A register might be used to accept input data from an alphanumeric keyboard and then present this data at the input of a microprocessor chip.

• They are often used to momentarily store binary data at the output of a decoder.

• It can be connected to form a number of different types of counter. • The shift forms a very important link between main digital system and the

input –output channels. For example, a register could be used to accept output data from a microprocessor chip and then present this data on a CRT screen.

PROCEDURE:

• Give the circuit connections as per logic diagram. • Give the input and the clock pulse • Observe the output. Influence is made from the observation .

RESULT:

Thus the truth table of Shift registers (SISO & SIPO) & their functions are verified.

IC 7474 DUAL EDGE TRIGGERED ‘D’ FLIP-FLOP PIN DIAGRAM:

LOGIC SYMBOL :

Logic diagram: SERIAL IN – SERIAL OUT SHIFT REGISTE R

Truth table :

Waveform:

Logic diagram: SERIAL IN - PARALLEL OUT SHIFT REGIS TER

Truth table :

Waveform:

Expt. No:

Date:

REALIZATION OF MULTIPLEXERS – DEMULTIPLEXERS FUNCTI ONS USING DIRECT IC’s

AIM:

To verify the working of 8 to 1 Multiplexer using IC 74151 and 1 to 8 Demultiplexers using IC 74138.

APPARATUS REQUIRED: S.No Apparatus Required Range Type Quantity

1 Digital IC trainer Board - - 1 2 IC74151 - - 1 3 IC 74138 - - 1 4 Patch Chords - -

THEORY:

Multiplexing means transmitting a large number of information units over a smaller number of channels or lines. A digital multiplexer is a combinational circuit that selects binary information from one of many input lines and directs it to a single output line. The selection of particular input line is controlled by a set of selection lines. Normally, there are 2n input lines and n selection lines whose bit combinations determines which input is selected.

A multiplexer is called a data selector, since it selects one of many inputs and steers the binary information to the output line. A Strobe is also provided to allow the designer to disable all output data until a specified time. Then, by allowing the STROBE to go low, the proper lead can be selected. This feature is very useful where data might be changing the same time DATA SELECT leads change. It is a very useful Medium Scale Integration (MSI) function and has a multitude of applications. It is used for connecting two or more sources to a single destination among the computer units and it is useful for constructing a common bus system.

A decoder with an enable input can function as a demultiplexer.A Demultiplexer is a circuit that receives information on a single line and transmits this information on one of 2n possible output lines. The selection of specific output line is controlled by the bit values of n selection lines. The decoder and demultiplexer operations are obtained from the same circuit; a decoder with an enable input is referred to as a decoder / de-multiplexer. The Strobe lead can be used to active or de-active the entire IC, allowing time for the address lines to change the information is fed to the output. Demultiplexers are useful anytime information from one source must be fed several places. Working Of IC74151- 8 To 1 Multiplexer It is an 8 x 1 multiplexer with eight data inputs (D0-D7), three select input lines (S2-S0) and a single output (Y). It also has an enable input Ğ and provide both normal and inverted outputs (i.e. Y & Ў) and Since 23=8, three bits are required to select any one of the eight data bits. When Ē=0, the select inputs S2, S1, S0 will select one of the data input to pass through the output Y. When Ğ =1, the multiplexer is disabled. The enable input can be used to expand two or more multiplexer ICs to a

digital multiplexer with a large number of inputs. The logic symbol of IC 74151 is shown in Fig. (a) And its logic diagram is shown in Fig (e).

Logic Function Generation Using Multiplexer Multiplexers can be used to implement logic functions directly from a truth

table with out the need for simplification when a multiplexer is used for this purpose, the select inputs are used as the logic variables, and each data inputs is connected permanently HIGH or LOW as necessary to satisfy the truth table. The figure shown below illustrates how an 8 input multiplexer can be used to implement the given three variable logic functions, .The input variables A, B, C are connected to select inputs S0, S1, S2 respectively, so that the levels on these inputs determine which data input appears at output Z. According to the truth table, Z is supposed to be low when CBA=000. Thus, multiplexer input D0 should be connected LOW; likewise D2, D4, D6 and D7 should be low. The other sets of CBA conditions must produce Z=1, and so multiplexer input’s D1,D3, and D5 are connected permanently HIGH. This method of implementation is often more efficient than using separate logic gates.

Diagram for 8-input Multiplexer

Implementation of Four Variable Logic Function The circuit of figure shows how an 8-input MUX can be used to generate a 4 variable logic function. Even though the MUX has only three select inputs, three of the logic variables A, B and C are connected to select data inputs. The fourth variable ‘D’ and its inverse ‘D’ are connected to be selected. Data inputs of the MUX as required by desired logic function, the other MUX data inputs are connected to a low or a high as required by the function.

Working Of IC 74138- 1 To 8 Demultiplexer:

The 1to 8 demultiplexer has a single input (D), eight outputs (Ỹ0 toỸ7) and three select inputs (A2, A1 and A0). Figure (f) shows how 74138 IC can be used as a Demultiplexer.The enable inputĒ1 is used as the data input ‘D’ While the other two enable inputs are held in their active states .The A2, A1,A0 Inputs are used as select code. To illustrate the operation, lets assume that the select inputs are ‘000’. With this input code, the only output that can be activated is Ỹ0, while all other outputs are HIGH Ỹ0 will go LOW only if Ē1 goes LOW and will be HIGH if Ē1 goes HIGH .In other words , Ỹ0 will follow the signal on Ē1 (i.e. the data input) while all other outputs stay HIGH .In a similar manner, a different select code applied to A2,A1,A0 will cause the corresponding output to follow the data inputs ‘D’.

8 to 1 MULTIPLEXER -IC 74151

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D1

W

G

D3

D0

CGND

Vcc

D2

B

A

D5

D4

Y D7

D6

IC 74151

W

G BA C

D3

D5D6D7

D4

Y

D0D1D2

10 11 12

(14)

(15)

(1)

(2)

(3)

(4)

9

9

9

(12)

(13)

Fig (a) PIN DIAGRAM Fig (b) LOGIC SYMBOL

1 to 8 DEMULTIPLEXER –IC 74138

LOGIC INPUT VARIABLES Fig (h)

D6

D5

D4

D3

D2

D1

D0

E

D7

2

C A B D

+5 V

Fig (c) PIN DIAGRAM Fig (d) LOGIC SYMBOL LOGIC DIAGRAM: IC 74151 - 8 to 1 MULTIPLEXER

Truth Table for the Multiplexer

LOGIC DIAGRAM: 1 to 8 DEMULTIPLEXER IC-74138

Truth Table for the DeMultiplexer

INPUTS OUTPUTS E3

Ê2

Ê1

DATA I/P

Ā2

Ā1

Ā0

Ỹ0

Ỹ1

Ỹ2

Ỹ3

Ỹ4

Ỹ5

Ỹ6

Ỹ7

X L X H H H H H H H H

X X H L L L L L L L L

H X X D D D D D D D D

X X X L L L L H H H H

X X X L L H H L L H H

X X X L H L H L H L H

H H H D H H H H H H H

H H H H D H H H H H H

H H H H H D H H H H H

H H H H H H D H H H H

H H H H H H H D H H H

H H H H H H H H D H H

H H H H H H H H H D H

H H H H H H H H H H D

EXPT NO: DATE:

REALIZATION OF ASTABLE & MONOSTABLE MODES OF 555 TI MER IC

AIM:

To design & test the Mono stable & Astable modes of operation of IC 555 Timer. APPARATUS REQUIRED:

S.No Apparatus Range Type Quantity 1 IC 555 timer 1 2 Power supply (0-15) V 1 3 Capacitors 0.01uF, 1uF 1 each 4 Resistors 1kΩ, 10kΩ 1 each 5 Pulse generator 1 6 Bread board 1 7 Connecting wires 8 Cathode Ray Oscilloscope 1 9 Digital multimeter 1

THEORY: 1. Monostable Mode:

The Mono stable multi vibrator is one of the applications of IC 555 Timer. In the standby mode Control flip-flop is set such that Q =0 & Q’ = 1.As trigger passes through Lower comparator, FF is set i.e. Q =1 & Q’ =0, output is high, Discharging transistor Q1 is OFF & Capacitor is unclamped. Timing cycle begins. Capacitor is charging towards VCC ,but after time T , Capacitor voltage reaches 2VCC / 3, Upper comparator resets FF. Capacitor discharges rapidly to ground potential through Q1.Output at pin 3 becomes zero. VC = VCC[ 1- exp(-t / RC)] ……(i) At t=T , VC= 2VCC / 3, 2VCC / 3 = VCC[ 1- exp(-T / RC)], T=ln (1/3) RC, T=1.1RC

This shows timing interval is independent of the supply voltage and that once triggered, the output remains in the HIGH state until time T elapses, which depends only on R & C. Any additional pulse during this time will not change the output state. 2. Astable Mode:

Comparing to Monostable operation the timing resistor is split into two sections RA & RB. Discharging transistor is connected to the junction of RA & RB. When VCC is connected Capacitor charges towards VCC with a time constant (RA+RB)C. During this time Q =1 & Q’=0, output is high. When capacitor voltage is equal to 2VCC / 3 ,Upper comparator resets the FF, Q1 is ON & output is LOW.C discharges through Q1 & RB to ground potential with time constant RBC.AS C reaches the voltage VCC/3, Lower comparator is triggered and sets the FF. Thus Capacitor is charged & Discharged between VCC/3 & 2VCC/3. VC = VCC[ 1- exp(-t / RC)] ……(i)

At t=t1, VC = 2VCC/3 , 2VCC/3 = VCC[ 1- exp(-t 1/ RC)] , t1= 1.09 RC At t=t2, VC = VCC/3 , VCC/3 = VCC[ 1- exp(-t 2/ RC)] , t2= 0.405 RC tHIGH = t1- t2 = 0.69 RC , tHIGH = 0.69 ( RA + RB) C During discharging time, C discharges from 2VCC/3 to VCC/3.

VCC/3 = 2VCC/3 [ 1- exp(-t / RC)] , t= 0.69 RC , tLOW = 0.69 RB C T = tHIGH + tLOW = 0.69 ( RA + 2RB) C & D = [( RA + RB) / ( RA + 2RB) ] *100% The diode is added to make adjustable duty cycle. During the charging portion of the cycle, diode is forward biased & short circuiting RB so that, tHIGH = 0.69 RA C & t LOW = 0.69 RB C , T = tHIGH + tLOW = 0.69 ( RA + RB) C & D =[ RB / ( RA + 2RB) ] *100% FORMULAE: 1. Monostable Mode: -- T =1.1 RC 2. Astable Mode: -- T = 0.69 C ( RA + RB) & D = RB / (RA + RB). DESIGN: 1. Monostable Mode: T =1.1 RC, Here C= 0.1 µF, T = TON = 1 m Sec. R = T / 1.1 C = 1 m Sec / (1.1 * 0.1 µF) =9.09 KΩ. 2. Astable Mode: T = 0.69 C ( RA + RB), here T = 1 mSec, C= 0.1 µF 1 mSec = 0.69 * 0.1 µF ( RA + RB) ………(i) D = RB / (RA + RB ), here D= 0.7 0.7 = RB / (RA + RB ) ………..(ii) Solving (i) & (ii) RA = 4.37 KΩ & RB = 10.1KΩ. PROCEDURE:

• Give the connections as per circuit diagram. • Give the supply voltage at pin 8. • Note down the input & output waveforms on CRO at pins 2 & 3. • Also note down the capacitor voltage. • Plot the waveforms on a graph.

RESULT:

Thus the Mono stable & Astable modes of operations of IC 555 timer is designed & tested.

PIN DIAGRAM:

FUNCTIONAL DIAGRAM:

CIRCUIT DIAGRAM: 1. Monostable Multivibrator:

2. Astable Multivibrator:

MODEL GRAPH: 1. Monostable Multivibrator:

2. Astable Multivibrator:

TABULATION: 1. Monostable Multivibrator:

2. Astable Multivibrator:

Parameter Observed value Calculated value Output Vo (volts)

Capacitor Voltage (volts)

T HIGH (ms)

T LOW (ms)

Freq (Hz)

Duty Cycle

CALCULATION: 1. Monostable Multivibrator: 2. Astable Multivibrator:

Parameter Observed value Calculated value Trigger input

(i) T (ms) (ii) Ton (ms) (iii) Vi PP (v)

Output Vo (volts) Output pulse width (ms) Capacitor Voltage (volts)

EXPT NO: DATE:

VERIFICATION OF OPERATIONAL AMPLIFIER CHARACTERISTI CS

AIM:

To Study the IC 741 Op-Amp and measure its important characteristics.

APPARATUS REQUIRED:

S.No Apparatus Range Type Quantity 1 IC 741 1 2 Dual power supply (0-15) V 1 3 Capacitor 0.01uF 2 4 Potentiometer 10Kω, 50kΩ 1each 5 Resistor 200kΩ 1 6 Resistor 100kΩ, 10MΩ 2each 7 Resistor 100Ω,

1KΩ,1MΩ 1 each

8 Bread board/ Linear IC Trainer Kit 1 9 Connecting wires

10 Cathode Ray Oscilloscope 1 11 Digital multimeter 1 12 Function Generator 1

THEORY: Op-Amp Definition:

OP-AMP is a high gain direct coupled differential amplifier consisting of one or more differential amplifiers, followed by a level translator and an output stage. It is a versatile device used to amplify both ac and dc signal. OP-AMP is a linear integrated circuit and the most widely used type is IC 741.

Ideal Op-Amp Characteristics:

An OP-AMP is said to be ideal, only if it satisfies the following electrical characteristics.

Infinite voltage gain A. (i.e. open loop voltage gain AOL =0 Infinite input gain resistance Ri =µ, so that any of the input signal source can

drive it and there is no loading of the proceeding stage. Because of the Ri =µ, OP-AMP draws no current at both input terminals i.e. I1=I2=0.

Zero output resistance Ro = 0 so that output can drive an infinite number of other devices.

Zero output voltage when input voltage is zero. Infinite bandwidth, so that any frequency signal from 0 to infinite Hz can be

amplified without attenuation i.e BW= infinite. Infinite common mode rejection ratio so that the output common-mode

voltage is zero i.e. CMRR= infinite. Infinite slew rate, so that output voltage changes occur simultaneously with

input voltage changes.

DC characteristics of Op-Amp:

• Input bias Current: Input bias current IB is the average of the currents that flow into the inverting & non-inverting input terminal of the Op-Amp. The two input currents IB1 and IB2 are actually the base currents of the first differential amplifier stage. Practically, the input terminals conduct a small value of DC current to bias the input terminals.

• Input offset current: the difference between the input bias current at the inverting and non-inverting terminals is known as input offset current. Since the input transistors cannot be made identical, there will always be some small difference between IB+ and IB- leading to this offset current.

• Input Offset Voltage : Input offset voltage is the voltage that must be applied to the input terminals of an Op-Amp to nullify the output. Since it can be positive or negative, the maximum value is 6 mV.

• Thermal drift : bias current, offset current and offset voltage change with temperature. This is called drift. Offset current is expressed in nA/C and offset voltage drift in mV/C.

Ac characteristics of Op-Amp:

• Frequency response : An ideal op-amp has infinite bandwidth and infinite gain. The practical op-amp gain however decreases at higher frequencies. This is because; the charges in the capacitor decays and corresponding variation causes gain variation with the frequency. The open loop gain of the op-amp decreases at the rate of -20 db/decade at each break frequency. Bode plot is plotted to observe the changes and compensation by means of dominant pole or pole-zero compensation or internal compensation as in the case of IC 741, is provided.

• Stability : Op-amps are rarely used in open loop configuration because of its high gain and small bandwidth. Feedback increases the bandwidth but may cause instability. Stability is the ability of the op-amp to prevent oscillations and to provide maximum bandwidth and gain. An oscillation is the starting point of instability. For stable operation, the rate of closure between the closed loop gain projection and the open loop curve should not exceed -20 db/decade. At higher frequencies for lower closed loop gains, the feedback becomes significant and regenerative and may result in sustained oscillations.

• Slew Rate: This is the maximum rate of change of output voltage caused by a step input voltage, specified in V /µ sec. It is caused due to the presence of a capacitor within or outside the Op-Amp that prevents oscillation. An ideal slew rate is infinite which means that op-amps output voltage should change instantaneously in response to input step voltage. Practical IC op-amps have specified slew rates from 0.1v/us to well above 1000v/us.slew rate improves with higher closed loop gain and dc supply voltage. It is also a function of temperature and generally decreases with an increase in temperature. Slew rate limits the response speed of all large signal wave shapes.

• CMRR: Common Mode Rejection Ratio- The relative sensitivity of an Op-Amp to a difference signal as compared to a common mode signal is called Common Mode Rejection ratio (CMRR) and gives the figure of merit ρ for the differential amplifier. So, CMRR is given by,

ρ = MOD (Ad / Ac) and is usually expressed in decibels (db). The IC741 Op-Amp has a minimum CMRR of 70 dB and precision IC 741 Op-Amp has a minimum CMRR of 120 dB .So, higher the value of CMRR, better is the Op-Amp.

PROCEDURE: 1. Input offset voltage (Vio):

• Give the connections as per circuit diagram. • Give the ±15Vpower supply to the pin 7& 4 of the op-amp. • Note the output voltage using digital multimeter at terminal- 6 of the op-amp. • Calculate input offset voltage using the following equation :

Vio = [Ri / (Ri+Rf)]* Vo 2. Input bias current (IB) & input offset current (Iio) :

• Give the connections as per circuit diagram. • Allow the input bias currents IB1 and IB2 to flow through the two large

resistors. • RB >10MΩ, while the amplifier is connected as a unity gain non-inverting

amplifier. If resisters RB are selected so that IBRB> Vio, then the voltage created by the bias currents are much larger than Vio .If you select terminals A and B,, the measured output will be Vo=IB2RB.

• Similarly, the measured output will be Vo=-IB1RB, if we connect terminals C and D.

• The large Resistor RB is by passed with 0.01uf capacitors to reduce high frequency noise.

• The bias current is defined as the average of IB1and IB2, while the input offset current Iio is the difference IB1 –IB2 of the individual base currents.

3. Offset Voltage Adjustment:

• Give the connections as per circuit diagram. • Keeping the 10k POT in arbitrary position, measure the output voltage. • Adjust the10k POT until the output voltage reads the zero.

4. Determination of CMRR:

(a) Open Loop Voltage Gain (AOL= Ad):

• Give the connection as per circuit diagram • By varying 50k POT, the Vio is nullified; since the high amplification of this Vio

will result in output saturation. • The input excitation, which is variable DC voltage source, is applied to a

resistive attenuator circuit whose attenuation factor about 1/101. Then adjust input dc from zero, until the output reaches 5 Volts to ensure linear operations

• Measure the exact output voltage and Vs, then the open loop voltage gain is calculated by

AOL=Vo /Vi=Vo/Vs/101=101*Vo/Vs

(b) Common Mode Voltage Gain (ACM):

• Give the connection as per circuit diagram. • Give the input supply voltage and measure the corresponding output voltage. • Calculate common mode voltage gain =Vo /Vcm

5. Slew Rate:

• Give the connection as per circuit diagram • Apply the square wave input to the circuit using function generator. • Check whether the circuit acts as voltage follower. • Varying the frequency of input supply, measure the maximum rate of change

of output voltage. • The maximum rate of change of output voltage will give the slew rate.

RESULT:

Thus the characteristics of the Op-Amp has been found and tabulated below:

S.No Parameter Measured value Data sheet value 1 Input offset voltage 2 Input bias current 3 Input offset current 4 Offset voltage adjustment range 5 Differential mode gain 6 Common mode gain 7 Common mode rejection ratio

(CMRR)

8 Slew Rate

PIN DETAILS: IC -741 OP AMP

IC 741 Specifications : Supply Voltage : + / - 18 volts Input voltage : + /- 15 volts Power Dissipation: 500 mW Input Resistance : 2 MΩ Output Resistance: 75 Ω

SCHEMATIC CIRCUIT DIAGRAM FOR IC 741 OP-AMP:

CIRCUIT DIAGRAM:

1. Input offset Voltage (Vio):

2. Input Bias current (IB ) & Input Offset Current (Ii o)

3. Offset voltage adjustment:

4. Determination of CMRR: a. Open loop voltage gain

b. Common mode gain

5. Slew Rate:

MODEL GRAPH- for slew rate:

MODEL CALCULATION:

1. Input offset Voltage (Vio):

Vio=[R1/ (R1+RF)]* Vo; Where Vo is the measured output voltage.

2. Input Bias current (IB ) & Input Offset Current (Ii o)

IB1= VAB/RA = ___________________ (nA) IB2=VCD/RB = ___________________(nA)

Where VAB & VCD are calculated voltage drop

Input bias current IB = (IB1 + IB2 ) / 2 = ________________nA

Input Offset Current (Iio) = IB1 ˜ IB2 = _________________ nA

3.Determination of CMRR:

Differential mode gain A d= Vo/ Vi = _____________

Where input voltage Vi=[R2 /(R1+ R2)]*Vs ; Where Vo is the respective measured output voltage

Common mode gain A cm =Vo / Vcm = ____________ Where input voltage Vi=[R2 /(R1+ R2)]*Vs Where Vo is the respective measured output voltage

4. Slew Rate:

S.R = ∆V /∆t =______________ V/ µs. (From graph)

EXPT NO: DATE:

OP-AMP IC APPLICATIONS Design and testing of Inverting amplifier, Non-inve rting amplifier, Summer,

Subtractor, Integrator & Differentiator

AIM:

To design and test (i) Inverting amplifier, (ii) Non-inverting amplifier,

(iii) Summer, (iv) Subtractor, (v) Integrator & (vi) Differentiator and to verify the

outputs.

APPARATUS REQUIRED:

S.No Apparatus Range Type Quantity

1 IC 741 1 2 Dual power supply (0-15) V 1 3 Capacitors 0.01uF, 0.1uF 1 each 4 Resistor 1kΩ 5 5 Resistors 10kΩ ,9kΩ,0.5k 1 each 6 Bread board/ Linear IC Trainer Kit 1 7 Connecting wires 8 Cathode Ray Oscilloscope 1 9 Function generator 1 10 Digital multimeter 1

THEORY:

1. Inverting amplifier: In an Inverting amplifier, the output voltage Vo is fed back to the

inverting input terminal through the Rf - Ri network Where Rf is the feedback resistor. The input signal Vi is applied to the inverting input terminal through Ri and the non-inverting terminal is grounded. The gain Av = -(Rf / Ri), there is a 180o phase shift between Vo & Vi .The value of Ri must be larger to avoid loading effect, but this limits the gain of the circuit. 2. Non-Inverting amplifier:

In the non-inverting amplifier, the signal is applied to the non-inverting terminal & the output is fed to the inverting terminal, so the circuit amplifies without inverting the output. Since Rf & Ri form a potential divider network, Vi = VoRi / Ri+Rf). Since no current flows through the Op-Amp the voltage gain is given by Av=Vo / Vi = 1+(Rf / Ri). The input resistance of the non-inverting amplifier is very high since the Op-Amp draws negligible current from the signal source.

3. Summer:

A Summing amplifier is a circuit whose output is the sum of several input signals. It can be an inverting or a non-inverting summer. In an inverting summer, the output is inverted sum of input signals. In practical circuit R comp is provided which is parallel combination of input & feedback resistors. R comp is Ri in parallel with Rf.

4. Subtractor: A basic differential amplifier can be used as a subtractor .The output is

equal to subtraction between non-inverting input signals and inverting input signals.

5. Integrator:

In an integrator the output is -1/RfC1 times the integral of the input & RfC1 is the time constant of the integrator. The gain at low frequency can be limited to avoid saturation if the feedback capacitor is shunted by resistance Rf. The parallel combination dissipates power so it is a lossy integrator. Rf also limits the low frequency gain to Rf/R1 and thus gives DC stabilization.

6. Differentiator:

In the differentiator, the output waveform is the derivative of the input waveform. In a practical differentiator circuit, the high frequency noise & stability problems are avoided by the capacitor Cf across Rf. For good differentiation, the time period of the input signal T should be greater than or equal to RfC1.

DESIGN: 1. Inverting amplifier:

Vo /Vi = -(Rf / Ri ) Let A = 10,Ri = 1KΩ Vo / Vi = A = 10 = -( Rf / 1KΩ) Rf =10 KΩ 2. Non-inverting amplifier:

Vo /Vi = 1+(Rf / Ri ) Let A = 10,Ri = 1KΩ Vo / Vi = A = 10 =1+( Rf / 1KΩ) Rf =9 KΩ

3.Summer (Inverting): Let R1 = R2 = R3 =Rf , Rf =1KΩ & Gain = Vo / Vi =1

Vo / Vi = -Rf / Ri = 1 Ri =1 KΩ.

4. Integrator: Let Time constant T = 1 m Sec & R1 = 1 KΩ

T = R1 Cf Cf =1µF & Rf =10R1 Rf=10 KΩ. 5. Differentiator: fa = 1/2∏RfC1 , fb=1/ 2∏R1C1 ,RfCf = R1C1 & fb=10fa Let fa = 800Hz & C1 =0.1 µF Rf = 1/2∏faC1= 1.98 KΩ R1= 1/ 2∏ fbC1=198 Ω

R1 C1= Rf Cf Cf =0.01 µF.

PROCEDURE:

• Give the connections as per circuit diagram & apply the input voltage(s) • Measure the corresponding output on CRO / using multimeter. • Repeat the same for different values of frequencies / voltages. • Trace the input & output waveforms & tabulate the values.

RESULT:

Thus inverting amplifier, non-inverting amplifier, summer, subtractor, Integrator & Differentiator circuits are designed using IC 741 and their outputs are verified.

PIN DETAILS: IC -741 OP AMP

IC 741 Specifications: Supply Voltage : + / - 18 volts Input voltage : + /- 15 volts Power Dissipation: 500 mW Input Resistance : 2 MΩ Output Resistance: 75 Ω CIRCUIT DIAGRAM: 1. Inverting amplifier:

2. Non-Inverting amplifier:

3. Summer (Inverting):

4. Subtractor:

5. Integrator:

6. Differentiator:

TABULATION: 1. Inverting amplifier:

S.No. Vi in volts Vo(Practical in Volts) Vo = -Rf/Ri *Vi (Theoritical in Volts)

2. Non-Inverting amplifier:

S.No. Vi in volts Vo(Practical in Volts) Vo= (1+Rf/Ri) *Vi

(Theoretical in Volts)

3. Summer (Inverting):

Vi in volts S.No. V1 V2 V3

Vo(Practical in Volts) Vo =-(V1+V2+V3) (Theoritical in Volts)

4. Subtractor:

Vi in volts S.No. V1 V2

Vo(Practical in Volts) Vo =V1-V2 (Theoritical in Volts)

5. Integrator:

Vi Amplitude (volts)

Input Frequency (Hz)

Observed Vo(volts)

Calculated Vo(volts)

6. Differentiator:

(i) For Triangular wave input

Vi Amplitude (volts)

Input Frequency (Hz)

Observed Vo(volts)

Calculated Vo(volts)

(ii) For Square wave input

Vi Amplitude (volts)

Input Frequency (Hz)

Observed Vo(volts)

CALCULATION: Integrator: Differentiator:

MODEL GRAPH: 1.Integrator

2. Differentiator

EXPT NO: DATE:

SQUARE & TRIANGULAR WAVE GENERATORS USING IC741

AIM:

To design the Square & Triangular wave generators using IC 741 Op-Amp and verify their outputs. APPARATUS REQUIRED:

S.No Apparatus Range Type Quantity

1 IC 741 2 2 Dual power supply (0-15) V 2 3 Capacitors 0.1uF 2 4 Resistors 10kΩ 3 5 Resistors 5kΩ, 12kΩ,

2kΩ, 3kΩ, 100kΩ,

1 each

6 Bread board/ Linear IC Trainer Kit 1 7 Connecting wires 8 Cathode Ray Oscilloscope 1 9 Digital multimeter 1

THEORY: 1. Square Wave Generator

The principle generation of square wave output is to force an Op-Amp to operate in saturation. A fraction of output [β =R2 / (R1 + R2) ] is fed to the positive input terminal. Thus the reference voltage Vref is βVo and may take values as + βVsat or – βVsat. The output is also fed back to the inverting terminal after integrating by a low pass RC combination .Whenever the input at the inverting terminal just exceeds Vref; Switching takes place resulting in a Square wave output. In Astable multivibrator, both the states are quasi stable.

When the output is at + Vsat, the capacitor starts charging towards Vsat through resistance R. The voltage at the (+) input terminal is held at + βVsat by R 1 AND R2 combination. This condition continues as the charge on C rises, until it has just exceeded + βVsat, the reference voltage. When the voltage at the (-) input terminal becomes just greater than this reference voltage, the output is driven to -Vsat .At this instant, the voltage on the capacitor is + βVsat .It begins to discharge through R, i.e. charges towards + Vsat When the output voltage switches to -Vsat, the capacitor charges more and more negatively until its voltage just exceeds - βVsat .The output switches back to +βVsat .The cycles repeats itself. The frequency is determined by the time it takes the capacitor to charge from -βVsat to + βVsat and vice-versa. The voltage across the capacitor as a function of time is given by Vc(t)= Vf+ (Vi-Vf)e-t/RC. Where the final value Vf= + Vsat and the initial value, Vi=- βVsat. There fore Vc(t)= Vsat - Vsat (1+ β)e-t/RC At t=T1, the voltage across the capacitor reaches βVsat and switching takes place, Therefore, Vc(T1)= βVsat =Vsat - Vsat (1+ β)e-T1/RC .It gives T1=RC ln [(1+ β)/(1+ β)]. This gives only one half of the period. Total time period is T=2T1=RC ln [(1+ β)/(1+ β)]. And the output waveform is symmetrical.

If R1=R2, then β=0.5 T=2RC ln (3). and If R1=1.16 R2 T=2 RC ,so the frequency of oscillation is fo=1/ T= 1/2RC . 2. Triangular Wave Generator

A Triangular Wave is obtained by integrating a square wave. The frequency of the square & triangular waves is the same. The amplitude of square wave is constant at ±Vsat, but the amplitude of the triangular wave will decreases as frequency, increases. This is because the reactance of the capacitor C2 in the feedback circuit decreases at high frequencies. A resistance R4 is connected across C2 to avoid the saturation problem at low frequencies as in the case of practical integrator. FORMULAE: 1.Square Wave Generator

a) feed back ratio β =R2 / (R1 + R2) b) frequency of oscillation fo= 1 / 2RC ln [(1+β) / (1-β)] c) Time period of oscillation T= = 2RC ln [(1+β) / (1-β)]

2.Triangular Wave Generator

a) Feed back ratio β =R2 / (R1 + R2) b) Frequency of oscillation fo= 1 / 2 RC c) Time constant T= R3C2

DESIGN: 1. Square Wave Generator:

Equal pulse Width Let β =0.5 , f o= 1KHz R1 = 1.16 R2 & C = 0.1 µF Choose R2=10KΩ R1 =12kΩ f o = 1 / 2RC R = 5 kΩ 2.Triangular Wave Generator: Let β =0.5 , f o= 1knHz R1 = 1.16 R2 & C = 0.1µF Choose R2=10KΩ R1 =12kΩ f o = 1 / 2RC R= 5 kΩ Time period = 1/f o =1msec, T = R3 C2 Choose C2 = 0.1 µF R3 = 10 kΩ Then Rf = 10; R3 = 100 KΩ PROCEDURE:

• Give the connections as per circuit diagram. • Give ±15 V dual power Supply to the op-amp. • Observe the output waveform at Pin 6 and capacitor voltage waveform at

pin 2 using Cathode Ray Oscilloscope. • Measure these waveforms amplitude and frequency. • Plot these waveforms on a linear graph sheet.

RESULT:

Thus the square & triangular waveform generators are designed and their outputs are verified.

PIN DETAILS: IC -741 OP AMP

IC 741 Specifications: Supply Voltage : + / - 18 volts Input voltage : + /- 15 volts Power Dissipation: 500 mW Input Resistance : 2 MΩ Output Resistance: 75 Ω CIRCUIT DIAGRAM: 1. Square Wave Generator Equal pulse width

2. Triangular Wave Generator

MODEL GRAPH:

1. Square Wave Generator- Equal pulse width

2. Triangular Wave Generator

CALCULATION:

Expt. No.: Date :

DESIGN OF ADC AND DAC CONVERTERS AIM: To design a circuit for analog to digital signal conversion and digital to analog signal conversion using ICs and verify the output.

APPARATUS REQUIRED: S.No Apparatus Required Range Type Quantity

1 ADC IC- 0808 - - 1 2 RPS - - 1 3 II. igital IC Trainer - - 2 4 LED - - 8 5 MC-1408 - - 1 6 Capacitor 15pF 1 7 Resistor 2.5k 7 5K 2 8 IC-741 1

THEORY:

Connecting digital circuitry to sensor devices is simple if the sensor devices are inherently digital themselves. Switches, relays, and encoders are easily interfaced with gate circuits due to the on/off nature of their signals. However, when analog devices are involved, interfacing becomes much more complex. What is needed is a way to electronically translate analog signals into digital (binary) quantities, and visa-versa. An analog-to-digital converter, or ADC, performs the former task while a digital-to-analog converter, or DAC, performs the latter. PROCEDURE: 1. Analog to Digital conversion (ADC) 1.Give the circuit connections as per the circuit diagram. 2.Set the analog input to a certain voltage. 3.Using the formula given below, calculate the decimal output D = ( 2n –1/Vr) x Vin 4.Convert this to binary system and check with the LED. 5.thus the circuit is verified. 2.Digital to Analog Conversion( DAC) 1.Give the circuit connections. 2. Give the input. 3.Measure the output.

TABULAR COLUMN: 1.Unipolar DAC S.no Binary number Measured

Value(V) Calculated value(V)

2.Bipolar DAC S.no Binary number Measured

Value(V) Calculated value(V)

CIRCUIT DIAGRAM Analog to digital Converter

CIRCUIT DIAGRAM Digital to Analog Converter (Unipolar)

Digital to Analog Converter (Bipolar)

Analog to digital Conversion (ADC):

Calculated value (V)

S.no Binary number Measured Value (V)

Binary No

Decimal No

MODEL CALCULATIONS RESULT : Thus DAC & ADC converter circuits have been studied.

EXP NO: DATE :

STUDY OF PLL AND VCO AIM:

To study the function of phase-locked loops (PLL) with voltage controlled oscillator (VCO). THEORY: Phase-locked loops (PLL):

PLL stands for ‘Phase locked loop’ and is basically a closed loop frequency control system, which functioning is based on the phase sensitive detection of phase difference between the input and output signals of the controlled oscillator (CO). The basic block schematic of the PLL is shown below and consists of the following: 1. Phase detector/comparator. 2. A low pass filter. 3. An error amplifier. 4. A voltage controlled oscillator (VCO). Block Diagram

PLL goes through three stages: 1. Free running. 2. Capture. 3. Locked or tracking. Some of the vital definitions in relation to PLL are:

Lock-in Range: Once the PLL is locked, it can track frequency changes in the incoming signals. The range of frequencies over which the PLL can maintain lock with the incoming signal is called the lock-in range or tracking range. The range is usually expressed as a percentage of, the VCO frequency. Capture Range: The range of frequencies over which the PLL can acquire lock with an input signal is called the capture range. This parameter is also expressed as a percentage of f0.. Pull-in time: The total time taken by the PLL to establish lock is called the pull-in time .this depends on the initial phase and frequency difference between the two signals as well as on the overall loop gain and loop filter characteristics.

MONOLITHIC PHASE-LOCKED LOOPS: All the different building blocks of the PLL are available as independent IC packages and can be externally interconnected to make a PLL. Some of the commercially available monolithic PLL’s are SE/NE560,561,562,564,565 and 567 mainly differ in operating frequency range, power supply requirement, frequency and bandwidth adjustment ranges. Since 565 is the most commonly used PLL, we will discuss some of the important features of this IC chip. IC PLL 565: It is a 14-pin DIP package and as 10-pin metal can package. The pin configuration and the block diagram are shown below. PIN DIAGRAM:

The output frequency of the VCO is given by the equation,

f0 = 0.25/ R1C1 Hz

where R1 and C1 are the external resistance and capacitance connected to the pin 8 and pin 9. A value between 2Kohm and 20Kohm is recommended for the value of R1. A short circuit between pins 4 and 5 connects the VCO output to the phase comparator so as t0 compare fo with input signal fs. A capacitor C is connected between pin 7 and pin 10 to make a low pass filter with the internal resistance of the 3.6Kohm. The important electrical parameters of the 565PLL a re:

Circuit Diagram of LM565 PLL:

VOLTAGE CONTROLLED OSCILLATOR (VCO): A commonly used type of VCO available in IC form is Signetics NE/SE 566.The pin configuration and basic block diagram of 566 VCO are shown below.

Pin Diagram:

Basic Block Diagram:

Typical Connection Diagram: The timing capacitor C1 is linearly charged or discharged by a constant current source/sink. The amount of current can be controlled by changing the voltage Vc applied at the modulating input pin 5 or by changing the timing resistor R1 external to the IC chip. The voltage at the pin 6 is held at the same voltage as pin 5. Thus, if the modulating voltage at pin 5 is increased, the voltage at the pin 6 also increases, resulting in less voltage across R1 and thereby decreasing the charging current. The output frequency of the VCO is given by the equation,

Some Applications: 1. Data and Tape Synchronization 2. Modems 3. FSK Modulation 4. FM Demodulation 5. Tone Decoding

6. Frequency Synthesizer 7. SCA Demodulators (‘Hidden’ Radio) 8. Telemetry Receivers 9. Signal Regeneration 10. Coherent Demodulators 11. Satellite RESULT:

Thus the phase-locked loops were studied with the voltage controlled

oscillator briefly.

EXPT. NO: DATE:

SIMULATION OF BASIC APPLICATIONS OF OP-AMP: INVERTI NG SUMMER, SUBTRACTOR, INTEGRATOR & DIFFERENTIATOR.

AIM:

To simulate the basic application circuits of IC 741 using PSPICE.

APPARATUS REQUIRED:

PSPICE ORCAD VERSION 9.3.

THEORY:

SPICE is a general-purpose circuit program that simulates Electrical &

Electronic Circuits. SPICE is an acronym of Simulation Program With Integrated Circuit Emphasis. PSPICE is a PC version of SPICE developed by Microsim Corporation. The PC version needs 512 kilobytes of memory to run. It is possible to simulate circuits that contained both analog & digital devices using this package. It contains models for common circuit elements & it is capable of simulating most of the Electrical & Electronic Circuits. This software allows the designer to investigate the behavior of a circuit without having to actually breadboard the circuit in the laboratory. This allows for a considerable savings in the materials and labour. Also if the design needs to be modified, changes can be easily submitted to the computer for another look at the results. PSPICE allows various types of analysis.PSPICE is a simulation program that models the behavior of a circuit. It is a software-based breadboard of the circuit that can be used to test and refine the design.Information about Pspice is available from the OrCAD website: http://www.orcad.com. PROCEDURE:

Simulate the circuit using PSPICE by the instructions.

SIMULATIONS:

(i). Inverting Summer

PSpice Circuit:

R1

1k

V42Vdc

0

V

0

0

R2 1k

R4

1k

V215Vdc

0R6

1k

R71k

V

V

U2

uA741

3

2

74

6

1

5+

-

V+

V-

OUT

OS1

OS2

V115Vdc

0

0

V31Vdc

V53Vdc

Simulation Output:

Time

0s 0.2ms 0.4ms 0.6ms 0.8ms 1.0ms 1.2ms 1.4ms 1.6ms 1.8msV(V3:+) V(V4:+) V(V5:+)

0V

2.0V

4.0VV(U2:OUT)

-6.00004V

-6.00002V

-6.00000V

SEL>>

(ii). Subtractor

PSpice Circuit:

V

R3

1kV

0

0

V43Vdc

R4

1k

V215Vdc

U1

uA741

3

2

74

6

1

5+

-

V+

V-

OUT

OS1

OS2

0

0

V32Vdc

R2

1k

R1

1kV

0

V115Vdc

Simulation Output:

Time

0s 0.1us 0.2us 0.3us 0.4us 0.5us 0.6us 0.7us 0.8us 0.9us 1.0usV(R1:1) V(R3:1)

2.0V

2.5V

3.0VV(R2:2)

0.90V

0.95V

1.00V

SEL>>

(iii). Integrator

PSpice Circuit:

U1

uA741

3

2

74

6

1

5+

-

V+

V-

OUT

OS1

OS2

R1

1k

0

0

R2

1k

V115Vdc

V215Vdc

R3

1k

V

C1 0.1u

V3

TD = 0

TF = 0PW = 0.1mPER = 0.2m

V1 = -1

TR = 0

V2 = 1

V

0

0

Simulation Output:

Time

0s 0.2ms 0.4ms 0.6ms 0.8ms 1.0ms 1.2ms 1.4ms 1.6ms 1.8ms 2.0msV(U1:OUT)

-2.0V

0V

2.0VV(R1:1)

-1.0V

0V

1.0V

SEL>>

(iv). Differentiator

PSpice Circuit:

0

0

U1

uA741

3

2

74

6

1

5+

-

V+

V-

OUT

OS1

OS2

C2

0.01u

R31k

V3

TD = 0

TF = 0PW = 0.1m

PER = 0.2ms

V1 = -1

TR = 0

V2 = 1

V2

15Vdc

R1

1k

V

0

V1

15Vdc

R2

1k

C1

.01u

0

Simulation Output:

RESULT:

Thus the basic IC741 application circuits have been simulated using PSPICE.

EXPT. NO: DATE:

SIMULATION OF WAVEFORM GENERATORS: SQUARE WAVE & TR IANGULAR WAVE GENERATORS.

AIM:

To simulate the waveform generators using PSPICE.

APPARATUS REQUIRED:

PSPICE ORCAD VERSION 9.3.

THEORY:

SPICE is a general-purpose circuit program that simulates Electrical &

Electronic Circuits. SPICE is an acronym of Simulation Program With Integrated Circuit Emphasis. PSPICE is a PC version of SPICE developed by Microsim Corporation. The PC version needs 512 kilobytes of memory to run. It is possible to simulate circuits that contained both analog & digital devices using this package. It contains models for common circuit elements & it is capable of simulating most of the Electrical & Electronic Circuits. This software allows the designer to investigate the behavior of a circuit without having to actually breadboard the circuit in the laboratory. This allows for a considerable savings in the materials and labour. Also if the design needs to be modified, changes can be easily submitted to the computer for another look at the results. PSPICE allows various types of analysis.PSPICE is a simulation program that models the behavior of a circuit. It is a software-based breadboard of the circuit that can be used to test and refine the design.Information about Pspice is available from the OrCAD website: http://www.orcad.com. PROCEDURE:

Simulate the circuit using PSPICE by the instructions.

SIMULATIONS:

(i). Square wave generator

PSpice Circuit:

Simulation Output:

(ii). Triangularwave generator

PSpice Circuit:

Simulation Output:

RESULT:

Thus the waveform generators have been simulated using PSPICE.

EXPT. NO: DATE:

SIMULATION OF MONOSTABLE & ASTABLE MODES OF 555 TIM ER AIM: APPARATUS REQUIRED: THEORY: PROCEDURE: Simulate the circuit using PSPICE by the instructions. SIMULATIONS: (i). monostable mode PSpice Circuit: Simulation Output: (ii). Astable mode PSpice Circuit: Simulation Output: RESULT:

EXPT. NO: DATE:

SIMULATION OF COUNTERS AIM: APPARATUS REQUIRED: PSPICE ORCAD VERSION 9.3. THEORY: PROCEDURE: Simulate the circuit using PSPICE by the instructions. SIMULATIONS: (i). Binary Up counter PSpice Circuit: Simulation Output: (ii). Binary down counter PSpice Circuit: Simulation Output: RESULT: