7 State Dias

7/30/2019 7 State Dias

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So far we have not discussed any method fordesigning sequential circuits

We will only look at the design of synchronoussequential circuits in this course

State transition diagrams are a graphical way ofrepresenting the behaviour of a sequentialsystem

Consider the status of two LEDs counting a sequence:

Represents 01

If a one is added (input, say), the display moves to a new state

1

Represents 11

States can be represented by circles containing a symbol for the state, and

the value of the output associated with the state

A state can return to itself

The numbers represent the inputs that moved the state machine from 1state to another state.

a, 01 b, 11

1

On an input of 1, this devicegoes from state a to state b

0


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e.g. state transitiondiagramfor a 2 bit up counter

0 inputs leave the

state unchanged

The complete set ofstates and associatedoutputs can be shownin a state transition

table

a,00 b,01

d,11 c,10

d

cb

a

next state

i = 0

11ad

10dc01cb

00ba

outputnext state

i = 1

present

state

1

1

1

1

00

00

The next stage is to encode the states, thereare 4 so it can be done in 2 bits:

Given this, we can proceed to a stateassignment table, where everything isrepresented in terms of 1s and 0s:

11d

10c

01b

00a

codestate

10

1

0

01

0

1

10

1

0

10

1

0

11

0

0

next i = 0

n1 n0

01

1

0

next i = 1

n1 n0

1111

00

00

output

o1 o0

present

p1 p0

By taking the inputs (present state and input) and putting them in a

truth table we can develop logic expressions for the next state andoutputs:

0111101

0101001

1100111

1111011

1001110

1010010

0010100

0000000

O0O1N0N1IP0P1

a,00 b,01

d,11 c,10

1

1

1

1

00

00

This line indicates:

In state b, when the input is 1, thenext state is c and the output is 01

The next step is to develop the logic expressions for N1, N0 O1 O0 from

the truth table, either by algebra, inspection or Karnaugh map,whichever is easiest.

0111101

0101001

1100111

1111011

1001110

1010010

0010100

0000000

O0O1N0N1IP0P1

A judicious choice of state codesmakes the outputs straightforward:

O1 = P1 and O0 = P0

Maps for N1 and N0 appear on thenext slide


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111

110

10110100P1,P0

I

111

110

10110100P1,P0

I

Fill in the maps and derive expressions for N1 and N0

N1 N0

111

110

10110100P1,P0

I

111

110

10110100P1,P0

I

Solution:

N1 = P1.P0.I + P1.I + P1.P0

N0 = P0.I + P0.I

N1 N0

A General Sequential machine consists of two main blocks edge triggered register to hold present state

logic circuits to derive the next state and outputs using thepresent state and external inputs

Machine changes state on active clock edge

next statelogic circuit

clk

NextState

PresentState

register

PresentState

Inputs

Outputs

Combinationalcircuit to

determineoutputs

In some cases the next state andoutput logic might be combined inthe same block of, eg PAL logic).

In the case of our simple binary counter:

clock

On the clock edge, theregister changes to thenext stage present onthe inputs,

registerfor present state

logic determiningoutputs and next states

presentstate

next

state

N1 = P1.P0.I + P1.I + P1.P0

N0 = P0.I + P0.I

in this caseactual outputs

match present state

O1 = P1 and O0 = P0


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The next few slides have blanks for you to fill in asthe lecture progresses.

This example takes us through the process needed todesign any sequential circuit.

The example is a two bit counter that can count up ordown, depending upon the input, U.

U = 1, count up, U = 0, count down

Stage 1, construct the state transition diagramshowing 4 possible states (a, b, c, d), the outputsat each stage and the two possible inputs (1 or 0)that moved the machine from state to state:

a,00 b,01

d,11 c,10

0

1

U = 1, count up, U = 0, count down

Completethe state

table

11acd

10dbc

01cab

00bda

OutputNext

U = 0 U = 1Present

!"

Probably it will simplify things i f the present state codeis made equal to the output code for that state.

11001011

10110110

01100001

00011100

Output

Next

U = 0 U =1

Present

11d

10c

01b00a

codestate


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At this stage wewill take theinputs as presentstate (A and B),input U andoutputs are thenext state (C andD and the outputrequired P andQ). These canbe put in a truthtable.

11001111101011

0111101

0110001

1001110

1000010

0010100

0011000

QPDCUBA

"via Karnaugh maps or otherwise determine expressions for outputsC, D, P and Q

1

0

10110100A,B

U

1

0

10110100A,B

U

C D

1

0

10110100A,B

U

1

0

10110100A,B

U

P Q

C = A.B.U + A.B.U + A.B.U + A.B.U

D = B

P = A

Q = B

Determine the logic expressions from the K Map.

B

QPD

U

C

A

D Q

Q

D Q

Q

nextstate

logic

circuit

A

B

C

D

A

B

clk

P

Q

Nextstatelogic

circuit

Combinational logic block obtained from expressions.Implemented here in programmable AND, fixed ORcircuit (PAL).


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!#

A method has been presented for the design ofgeneral state machines The stages were:

Construct a state transition diagram for the problem

construct a state table

construct a state assignment table

Implement machine

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7 State Dias