63505504 Electronics Projects

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January

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C O N S T R U C T I O N

AR U P KU M AR S EN

TABLE I

Orientation Test socket Test socket Test socket Base-Id Base-Id Collector-Id forNo. terminal 3 terminal 2 terminal 1 for npn for pnp pnp and npn

1 C B E 02 05 042 C E B 01 06 043 E C B 01 06 024 E B C 02 05 015 B E C 04 03 016 B C E 04 03 02

B= Ba se C= Collector E= Emitter Note: All bits of higher nibble are set t o zero.

TABLE II

Q2 (MSB) Q1 Q0 (LSB)

0 0 1

0 1 01 0 0

TABLE I II. S ET 1

Q2 Q1 Q0

0 0 10 1 01 0 0

TABLE IV. SET 2

Q2 Q1 Q0

1 1 01 0 1

0 1 1

T ransistor lead identification is cru-cial in designing a nd servicing. A cir-cuit designer or a serviceman must be

fully conversant with the types of tran-

sistors used in a circuit. Erroneous lead

identification may lead to malfunctions,

and, in extreme cases, even destructionof the circuit being designed or serviced.

Though transistor manufacturers en-

capsulate their products in different pack-

a ge outlines for identification, it is im-

possible to memorise the outlines of in-

numerable transistors manufactured by

t h e i n d u s t r y . A l t h o u g h a n u m b e r o f

manuals are published, which provide pin

details, they may not always be acces-

sible. Besides, i t is not always easy to

find out the details of a desired transis-

tor by going through the voluminous

manua ls. But , a ha ndy gadget, called tran-

sistor lead identifier, makes the job easy.

All one has to do is place the transistor

in the ga dget’s socket to instant ly get the

desired information on its display, irre-

spective of the type and package-outline

of the device under t est.

A manually controlled version of the

present project ha d been published in J une

’84 issue of EF Y . The present model is to-

ta lly microprocessor contr olled, an d h ence

all manually controlled steps are replaced

by software commands. A special circuit,

shown in Fig. 1, which acts a s an interface

to an 8085-based microprocessor kit, has

been developed for the purpose.

Base an d type id en t i f i ca t i on . When a

semiconductor junction is forw a rd-biased,

conventional current flows from the source

into th e p-layer a nd comes out of the junc-

t ion through the n-layer . By applying

proper logic volta ges, th e ba se-emitter (B -

E ) or base-collector (B -C) junction of a bi-

polar transistor may be forward-biased.

As a result, if the device is of npn type,

current enters only through the base. B ut,

in case of a pnp device, current flows

through the collector as well as the emit-

ter leads.

Dur ing tes t ing , when l eads o f the

‘transistor under test ’ are connected to

terminals 1, 2, and 3 of the test socket(see Fig.1), each of the leads (collector,

base, and emitter) comes in series with

one of the current directions indicating

LE D s (D2, D4, and D6) as shown in Fig. 1.

Whenever the current flows t oward a par-

ticular junction through a particular lead,

the LE D connected (in proper direction) to

tha t lead glows up. So, in case of an npn-

device, only the LE D connected to the base

lead glows. However, in case of a pnp-

device, the other two LE D s are lit. Now, if

a glowing LE D corresponds to binary 1, an

LE D that is off would correspond to binary

0. Thus, depending upon the orientation

of the transistor leads in the test socket,

we would get one of the six hexadecimal

numbers (taking LE D connected to termi-

nal 1 as LS B ), if we consider all higher

bits of the byte to be zero. The hexadeci-

mal numbers thus generated for an npn

and pnp transistor for all possible orien-

tations (six) are shown under columns 5

and 6 of Table I. Column 5 reflects the

B CD weight of B (base) position while col-

umn 6 represents 7’s complement of the

column 5 number.

We may call this 8-bit hexadecimal

number base identi fication num ber or, in

short, base-I d . Comparing the base-Id,

generated with Table I, a microprocessor

can easily indicate the type (npn or pnp)

and the base of the device under test ,

with respect to the test socket terminals

marked as 1, 2, and 3. The logic num-

bers, comprisin g logic 1 (+ 5V) and logic 0

(0V), applied to generate the base-Id, arethree bit numbers—100, 010, and 001. Thes e

numbers are applied sequentially to the

leads thr ough the testing socket.

Col lecto r iden t i f i ca t ion . When the

ba se-emitter junction of a t ra nsistor is for-

wa rd-biased a nd it s ba se-collector junction

is reverse-biased, conventional current

flows in t he collector-emitt er/emit ter -col-

lector path (referred to as C-E path in sub-

sequent text), the magnitude of which de-

pends upon the magn itude of the ba se cur-

rent and the beta (current amplification

factor in common-emitter configura tion) ofthe tra nsistor. Now, i f the t ran sistor is bi-

ased a s a bove, but with the collector a nd

emitter leads interchanged, a current of

much reduced strength would still flow in

the C-E path. So, by comparing these two

currents, the collector lead can be easily

identified. In pra ctice, we can a pply proper

bina ry numbers (as in case of the ba se iden-

tification st ep mentioned earlier) to the ‘de-

vice under test’ to bias the junctions se-

quentially, in both of the aforesaid condi-

RUPANJANA

— — —

— — —

6


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F i g

. 1 : S c h e m a t i c c i r c u i t d i a g r a m

o f t h e t r a n s i s t o r l e a d i d e n t i f i e r

tions. As a r esult, the LE Ds con-

nected to the collector and emit -

ter leads sta rt fl ickering alter-

nately wi th di f ferent bright-

ness. By inserting a resistor in

series with the base, the LE D

glowing with lower brightnesscan be extinguished.

In the case of an NP N de-

vice (under normal bias ing

condition), conventional cur-

rent flows from source to the

collector layer. Hence, the LE D

connected to the collector only

would f l icker brighter , i f a

proper resistor is inserted in

series with the base. On the

other hand, in case of a pnp

device (under normal biasing

condition), current flows fromsource to the emitt er layer. S o,

only the LE D connected to the

e m i t t e r l e a d w o u l d g l o w

brighter. As th e type of device

is already known by the base-

Id logic, the collector lead can

be easily identified. Thus, for

a particular base-Id, position

of the collector would be indi-

cated by one of the two num-

bers (we may call it collector-

Id) as shown in column 7 of

Table I.

E r r o r p r o cessi n g . Dur-

ing collector identification for

a pnp- or an npn-device, if the

junction voltage drop is low

(viz, for germanium transis-

tors), one of the two currents

in the C -E pa th (exp la ined

above) cannot be reduced ad-

equately and hence, the data

may contain two logic-1s. On

the other hand, if the device

beta is too low (viz, for power

transis tors) , no appreciable

current flows in the C-E pa th ,

and so the data may not con-

tain any logic-1. In both the

cases, lead configuration can-

not be established. The rem-

edy is to adjust the value of

the resistor in series with the

base. There ar e three resistors

(10k, 47k, and 100k) to choose

from. These resistors are con-

nected in series with the test-

ing terminals 1, 2, and 3 re-

spectively. The user has to ro-

tate the transistor, orienting

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Fig. 2: Effective biasing of PNP transistors using set 1 binary numbers

Fig. 3: Effective biasing of NPN transistors using set 2 binary numbers

the ba se in different t erminals (1, 2, or 3)

on the socket, until th e desired results are

obtained. To alert the user about this ac-

tion, a message ‘Adjust LE D ’ blinks on the

display (refer error processing routine in

the software program).

The b i na r y numbe r genera to r . In this

section, IC 1 (an NE 555 timer) is used as a

clock pulse generat or, oscillat ing a t a bout

45 Hz. The output of IC 1 is a pplied to clock

pin 14 of IC 2 (4017-decade counter). As a

result, the counter advances sequentially

from decimal 0 to 3, ra ising outputs Q0, Q1,

and Q2 to logic-1 level. On reaching the

next count , pin 7 (output Q3) goes high an d

it resets t he counter. S o, the three outputs

(Q0, Q1, and Q2) jointly produce three bina ry

numbers, continuously, in a sequential

ma nner (see Ta ble II).

Q0 through Q2 outputs of IC 2 are con-

nected to in-

puts of I C 3

(7486, quad 2-

input E X-O R

ga te) . Ga tes

of IC 3 are so

w i r e d t h a tthey function

as controlled

E X-OR g a t e s .

The outputs

o f I C 3 a r e

controlled by

the logic level

a t p i n 1 2 .

Thus, we ob-

tain two sets

o f o u t p u t s

(marked Q0,

Q1, and

Q2)from I C 3 a s

g i v e n i n

T a b l e s I I I

(for pin 12 a t

logic 1) and

IV (for pin 12

at logic 0) re-

spectively.

One o f

t h e s e t w o

sets would be

chosen for

the output by

the software,

b y c o n t r o l -

ling the logi-

c a l s t a t e o f

pin 12. Set-1 is used to identify the base

and type (npn or pnp) of the ‘transistor

under test,’ whereas set-2 is exclusively

used for identification of the collector lead,

if the device is of npn type.

Th e in te r face. The three data out-

put l ines, carrying the sta ted binary num-

bers (coming from pins 3, 6, and 8 of IC 3),

are connected separately to three bi-di-

rectional analogue switches SW1, SW2, and

SW3 inside IC 5 (CD 4066). The other sides of

the switches are connected to the termi-

na ls of the test socket t hrough some other

components shown in Fig. 1. The control

line of IC 3 (pin 12) is connected to the

analogue switch SW4 via pin 3 of IC 5. The

other side of SW4 (pin 4) is grounded. If

switch SW4 i s closed by the software,

set-1 binary numbers are applied to the

device under test, and when it is open,

set-2 binary numbers a re a pplied.

To clearly understand the function-

ing of the circuit, let us assume that the

‘tra nsistor under t est’ is inserted w ith its

collector in slot-3, the base in slot-2, and

the emit ter in slot-1 of the t esting socket.

Initially, during identification of the

base and type of the device, all the ana-

logue switches, except SW4, are closed by

the software, applying set-1 binary num-bers to the device. Now, if the device is of

pnp type, each time the binary number

100 is generated at the output of IC 3, the

B C junction is forward-biased, and hence,

a conventional current flows through the

junction as follows:

Q2 (logic 1)SW3R9internal LE D of

IC 4slot3collector leadCB junction

base lead slot-2D 3 pin 10 of

IC 5SW2Q1 (logic 0).

Similarly, when the binary number 001

is generated, another current would flow

through theB E

junction and the internalLE D of IC 7. The number 010 has no effect,

as in this case both the BC and BE junc-

tions become r eversed biased.

From the above discussion it is ap-

parent that in the present situation, as

the internal LE DS of IC 4 and that of IC 7 a re

forward-biased, they would go on produc-

ing pulsating optical signals, wh ich would

be converted into electrical voltages by

the respective internal photo-transistors.

The amplified pulsating DC voltages are

available across their emitter resistors R7

and R17 respectively. The emitter follow-

ers configured around transistors T1 a nd

T3 ra ise the power level of the opto-

coupler’s output, while capacitors C3 a nd

C5 minimise the ripple levels in the out-

puts of emitt er followers.

During initia lisation, 8155 is configured

with port A as a n input a nd ports B and C

as output by sending control word 0E(H)

to its control register.

Taking output of t ransis tor T1 a s

MSB(D2), and tha t of T3 a s LSB(D0), the data

that is formed during the base identifica-

tion, is 101 (binary). The microprocessor

under the software control, receives this

data through port A of 8155 P P I (port num-

ber 81). Since all the bits of the higher

nibble are masked by the software, the

data become 0000 0101= 05(H). This data is

stored at location 216A in memory and

termed in the software as base-Id.

Now, if the device is of npn type, the

only binary number that would be effec-

tive is 010. Under the influence of this

number both BC and B E junctions would

be forward-biased simultaneously, and

hence conventional current would flow in

the following two paths:

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Fig. 4: Schematic circuit of special display system

(i)

Fig. 5: Flowcharts for the main program and various subroutines

(ii) (iii)

1. Q1 (logic 1)SW2R1 4in ternal

LE D (IC6)slot-2base leadB C junction

collector leadslot-3D1S W3Q2

(logic 0)

2. Q1 (logic 1)SW2R1 4in ternal

LE D (IC6)slot-2base leadB E junction

emi t ter l ead

s lot 1

D5

S W1

Q0(logic 0)

Thus, only the internal LE D of I C 6

would start fl ickering, and the data that

would be formed at the emitters of the

transistors is also 010. Accordingly, the

base-Id that would be developed in this

case is 0000 0010= 2(H).

Since, under the same orientation of

the transistor in the socket, the base-Ids

are different for a pnp and an npn device,

the software can decode the type of the

device.

In a similar way we can justify theproduction of the other base-Ids, when

their collector, base, and emitter are in-

serted in the testing socket differently.

Once the base-Id is determined, the

software sends the same number for a

pnp-device (here= 05(H)) through port C

(port number 83) , wi th the bi t format

shown in Table V.

As a result, the control input of SW2

(pin 12 of IC 5) gets logic 0. So the switch

opens to insert resistor R5 in series with

the base circuit. This action is neces-

sary to identify the emitter (and hence

the collector) lead as described earlier

under ‘Principle’ sub-heading.

On the contrary, since an npn-de-

LT543

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Fig. 5 (v)

Fig. 5 (iv)

vice uses the set-2 binary numbers for

identification of the collector (hence the

emitter), the same number (base-Id) ob-

tained during base identification cannot

be sent through port C, if the device un-

der test is of npn type. The base-Id found

must be EX-ORed first with OF (H). Since

the base-Id found here is 02 (H), the data

to be sent through port C in this case

would be a s shown in Table VI.

Note that P C3 becomes logic-1, which

would close switch SW4 to get the set-2

binary numbers.

Once resistor R5 is inserted in the ba se

circuit, and set-1 binary numbers are ap-

plied to the device (pnp type), it would be

biased sequentially in three distinct ways,

of which only two would be effective. The

same are shown in Fig. 2.

In case of binary number 100, the cur-

rent through the internal LE D of IC 4 w ould

distinctly be very low compared to the

c u r r e n t f l o w i n g d u r i n g n u m b e r 00 1,

through the internal LE D of IC 7. If R5 is of

sufficiently high value, the former cur-

rent may be reduced to such an extent

that the related LE D would be off. Hence,

the data that would be formed at t he emit-

ters o f t r ans i s tors T1-T3

would be 001. It would be

modified by the software to

0000 0001= 01(H). This is

termed in the software as

emitter-Id and is stored at

memory location 216B .

On the other hand, if

the device is of npn type,

set-2 binary numbers are

to be applied to it, and the

transistor would be biased

as shown in Fig. 3. Here,

only the internal LE D of IC 4

would flicker. So, the data

a t t h e o u t p u t w o u l d b e

100= 04(H). This is termed in

the softwa re a s collector-Id,

an d is stored in memory lo-

cation 216C. (In case of pnp-

device, the collector-Id is determined

mathematically by subtracting the Base-

Id from the emitter-Id.)

So the result could be summarised as:

pnp type:

Ba se-Id = 05(H), Collector-Id = 01(H).

npn type:

Ba se-Id = 02(H), Collector-Id = 01(H).

DISPLAY ROUTINE USING ALTERNATIVE CIRCUIT OF FIG. 4

TABLE V

P C7 P C6 P C5 P C4 P C3 P C2 P C1 P C00 0 0 0 0 1 0 1

TABLE VI

P C7 P C6 P C5 P C4 P C3 P C2 P C1 P C00 0 0 0 1 1 0 1

With this result, the software would

point to configuration CB E in the da t a

table, and print the same on the display.

By a similar analysis, lead configuration

for any other orientation of the device in

the test socket would be displayed by the

software, after finding the related base-

and collector-Id.

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PARTS LIST

Semiconductors:

IC1 - NE 555, t imerIC3 - C D 4017, deca de count er-de-

coderIC3 - 7486, qua d E X-OR ga tesI C4,I C6,I C7 - MC T2E , opt ocoupler

IC5 - CD4066, qua d bila tera l sw itchIC8 - L M 7805, 3-t er m in a l + 5V

regulatorT1,T2,T3 - B C147, npn t ra nsist orD1,D3,D 5 - 1N34, point cont act diodeD2,D 4,D6 - L ED, 5mmD7,D8 - 1N4002, rect ifier diode

Resistors (All ¼ watt +/ - 5% metal/ carbon f i l m

un less stated otherw ise)

R1,R9,R10,R14,R15,R19,R20 - 1 kilo-ohmR2 - 33 kilo-ohmR5 - 47 kilo-ohmR4,R11,R16,R21 - 10 kilo-ohmR3,R6,R7,R12,R17 - 100 kilo-ohmR8,R13,R18 - 680 ohm

Capacitors:

C1 - 0.5µF polysterC2 - 0.1µF polysterC3-C5 - 220µF/12V elect rolyt icC6 - 0.22µF polysterC7 - 1000µF/12V elect rolyt ic

Miscellaneous:

X1 - 230V/9V-0-9V, 250mA pow ertransformer

Fig. 6: Actual-size, single-sided PCB layout for the circuit in Fig. 1

Fig. 7: Component layout for the PCB

Th e Di sp la y . The display procedure

described in this article is based on IC

8279 (progra mma ble keyboard/display in -

terface) which is used in the microproces-

sor kit. The unique feature of the 8279-

based display system is that, i t can run

on its own. You just have to dump the

data to be displayed on its internal RAM,

and your duty is over. 8279 extracts this

data from its RAM and goes on displaying

the same without taking any help or con-

suming the time of the microprocessor in

the kit .

Unfortunately, not all the micropro-

cessor kits present in the market are fit-

ted with this IC . Instead, some of them

use a soft-scan method for display pur-

pose. Hence, the stated procedure cannot

be run in those kits. Of course, if the

monitor program of the kit is to be used,

which may have an in-built display rou-

tine to display the content of four spe-

cific memory locations—all at a time, the

same may be used in place of the present

display procedure.

Note: Display subroutine at address

20 FC used at EF Y, maki ng use of the moni -

tor program of the Vin yt ics 8085 kit , dur -

ing program test ing, is l isted t owards the

end of the softwar e pr ogram given by the

aut hor. To m ake use of the author ’ s dis-

play subroutine, please change the code

against ‘ CALL DISPLAY ’ in st ruct ion (code

CDFC 20 ) ever yw here i n the p r ogr am to

code CD 40 21 for 8279 based d isplay or

code CD 07 21 for al tern ate display r eferr ed

in the next paragraph .

Alternat ively, one can construct a spe-

cial display system using four octal D-

type latches (74373) and four seven-seg-

ment LE D displays (LT543). Only one latch

and one display has been shown in the

schematic circuit of Fig. 4 along with its

interface lines from 8155 or 8255 of the

kit. To drive this display, a special soft-

scan method explained in the following

para has t o be used.

Th e sof t scan d i sp l ay pr ocedu r e.

The procedure extracts the first data to

be displayed from memory. The s tart

memory address of the data to be dis-

played is to be supplied by the calling

program. This data (8-bit) is output from

port B of 8155/8255 P P I (after proper coding

for driving the seven-segment displays),

used in the kit. Data lines are connected

in parallel to all the octal latches. But

only one of the four latches is enabled

(via a specific data bit of port C of 8155/

8255) to receive the data and transfer the

sam e to its output to drive the correspond-

ing seven-segment LE D display. To enable

a particular la tch, a logic 1 is sent t hrough

a particular bit of port C (bit 4 here, for

the first data) by the software. Subse-

quently, logic 0 is sent through that bit

to latch the data transferred. The pro-

gram then jumps to seek the second data

f r o m m e m o r y , a n d s e n d s t h e s a m e

through port B a s before. However, in th is

case logic 1 is sent through bit 3 of port

C , to latch the data to the second seven-

segment LE D display, and so on.

Register B of 8085 is used as a counter,

and is initially stored with the binary

number 00001000 (08H). Each time a data is

lat ched, the logic 1 is shifted right by one

place. So, after the fourth da ta is latched,

the reg. B content would be 0000 0001. Shift-

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2087 E607 ANI 07H Checks only first three bits2089 EAA021 J P E E RR I f 2 bit s a re a t logic-1 jumps to 21A0208C 326C21 STA 216CH Store the No. (Collector-Id)into mem.

208F C39220 J MP P 4 J umps to select lea d configura t ion

;Lead configuration selection program

2092 216A21 P4: LXI H ,21 6AH Ext ract s B ase-Id from memory l oca t ion2095 7E MOV A,M 216A to the a ccumula tor2096 FE05 CP I 05H If the number is 05,

2098 CAB A20 J Z P 4A jumps to subrout ine 4A209B FE 06 CP I 06H If the number is 06,209D CAD020 J Z P 4B jumps to the subrout ine 4B

20A0 FE 03 CP I 03H If the number is 03,20A2 CAE 620 J Z P 4C jumps to the subroutine 4C

20A5 FE 02 CP I 02H If the number is 02,20A7 CAB A20 J Z P 4A jumps to the subroutine 4A

20AA FE01 CP I 01H If the number is 06,20AC CAD020 J Z P 4B jumps to the subroutine 4B

20AF FE04 CP I 04H I f the number is 04,20B 1 CAE 620 J Z P 4C jumps to the subroutine 4C20B 4 CDFC20 M: CALL DISPLAY Jumps to display the lead configurat ion

selected in P4A or P4B or P4C20B 7 C30020 J MP MAIN J umps ba ck to st a rt

;Lead configuration selection (Base Id.=05 or 02)

20B A 216C21 P 4A: LXI H ,216CH E xtra ct s Collect or-Id from memorylocation

20B D 7E MOV A,M 216C to the a ccumula tor20B E FE01 CP I 01H If it is = 01, jumps to 20CA20C0 CACA20 J Z E If it is = 04, points t o lea d

configuration “Eb C ”20C3 217521 LXI H ,2175H in da t a t able

20C6 C3B 420 J MP M J umps to displa y the lea dconfiguration pointed

20C9 00 NOP NOP20CA 217121 E: L XI H ,2171H P oin ts t o le ad con fig .”Cb E ” and jumps20CD C3B 420 J MP M displa y the configura t ion


20D0 216C21 P4B: L XI H , 216C H E x tr a ct s C ol le ct or -I d f r om m e mo rylocation

20D3 7E MOV A,M 216C to the a ccumula tor20D4 FE02 CP I 02H I f it is STE02, jumps to 20E0

20D6 CAE020 J Z B I If it is = 04, point s to lea d20D9 217D21 LXI H ,217DH configura t ion “bE C ” in data ta ble20DC C3B 420 J MP M J umps to displa y the lead

configuration pointed20DF 00 NOP No oP era t ion

20E0 217921 B: L XI H ,2179H P o in t s t o l ea d con fi gu r a ti on “bC E ”20E 3 C3B 420 J MP M a nd jumps displa y the configura t ion


20E 6 216C21 P4C: L XI H , 216C H E x tr a ct s C ol le ct or -I d f r om m e mo rylocation

20E 9 7E MOV A,M 216C to the a ccumula tor20EA FE01 CP I 01H If it is = 01, jumps to 20F620E C CAF620 J Z C If it is = 02, point s to lea d

20EF 218121 LXI H ,2181H configura t ion “EC b” in data ta ble20F2 C3B 420 J MP M J umps to displa y the lea d

20F5 00 NOP configura t ion pointed; no opera t ion20F6 218521 C: L XI H ,2185H P o in t s t o l ea d con fi gu r a ti on “CE b”20F9 C3B 420 J MP M and jumps to displa y the configura t ion

;Display routine using 8279 of the kit (if present)

2140 0E04 MVI C,03 S et s the counter t o count 4 cha ra cters

2142 3E90 MVI A,90 Set s cont .8279 to a uto-incr . mode2144 320160 STA 6001 Address of 8279 cont . reg.= 60012147 7E MOV A,M Moves 1st da ta cha ra cter from mem.

Loc. pointed to by calling instruction.2148 2F CMA Invert s da t a (refer note below )2149 320060 STA,6000 S tores da ta in 8279 da ta reg.

(addr= 6000)214C 0D DCR C Decrement s counter214D CA5421 J Z 2154 Returns t o ca lling progra m if count= 02150 23 INX H Increment s memory pointer2151 C34721 J MP 2147 J umps to get next cha ra cter from

memory

2154 C9 RET Returns t o the ca lling progra m

Note: In the microprocessor kit used, data is inverted before feeding the 7-seg display.

;Alternative Display Subroutine to be used with interface circuit of Fig. 4

2107 0608 MVI B ,08H Store 0000 1000 in reg.B

2109 3E 00 MVI A,00H Out 00H through P ort C t o la t ch da t ain all

Memory Map And Software listing in 8085 Assembly LanguageR AM L oca t ion s u se d f or pr og ra m :2000H - 21B B H

Stack pointer init ia lised :2FFFHMonitor P rogra m :0000H - 0FFFH

Displa y Da ta Ta ble :2160H - 219AHC ont rol/S ta tus Reg ist er of 8155 :80H

P ort A (Input ) of 8155 :81HP ort B (Output) of 8155 :82HP ort C (Output) of 8155 :83H

Address Op Code L abel Mnemonic Comments

;Initialisation, base and type identification

2000 31FF2F MAIN: LXI SP ,2FFFH In it i a li sa t i on of th e por t s . A a s th e2003 3E0E MVI A,0EH input a nd C a s the output port .2005 D380 OU T 80H Sends 07 through port C t o ma ke SW1,

2007 3E 07 MVI A,07H S W2, SW3 ON a nd SW4 OFF.2009 D383 OU T 83H Time dela y should be a llow ed before

200B CD3320 CALL DELAY mea suring the logic volt a ges a cross200E CD3320 CALL DELAY ca pa citors C1, C2, a nd C3, so tha t

2011 CD3320 CALL DELAY they cha rge t o the pea k va lues.2014 AF XRA A Clea rs the a ccumula tor

2015 DB 81 IN 81H Input da t a from interfa ce through.portA 2017E607 ANI 07H Test only first 3 bit s, masking others

2019 326A21 STA 216AH Stores the number in memory.201C CA2A20 J Z P I f the number is zero jumps to 202A

201F EA3D20 J P E P 2 If the number ha s even no. of 1s,jumps to 203D (refer note 2)

2022 E26820 J P O P 3 If the number ha s odd no. of 1s, jumpto 2068 (refer n ote 1)

2025 00 NOP No opera t ion

2026 00 NOP No opera t ion2027 00 NOP No opera t ion

2028 00 NOP No opera t ion2029 00 NOP No opera t ion

202A 218921 P: L XI H, 2189H P oi nt s t o m es sa g e “P U S H ” in datatable

202D CDFC20 CALL DISP LAY Displa ys the message2030 C30020 J MP MAIN J umps to st a rt .

;Delay sub-routine

2033 11FFFF DELAY: L XI D ,F FF FH L oa ds DE w it h F FF F2036 1B DCX D Decrement s DE2037 7A MOV A,D Moves result into Acc.

2038 B 3 ORA E OR E w ith Acc.2039 C23620 J NZ 2036 If not zero, jumps to 2036203C C9 RET Returns to ca lling program

;Collector identification program for PNP transistors

203D 216A21 P2: L XI H ,216AH P o in t s of B a se -I d in da t a t a bl e2040 7E MOV A,M Ext ra ct s the number to the

accumulator2041 D383 OU T 83H Send the number t o the interfa ce

2043 216021 LXI H ,2160H P oint s t o messa ge ‘P nP ’ in data table2046 CDFC20 CALL DISP LAY Displa ys the messa ge2049 CD3320 CALL DELAY Wa it s for few moments

204C CD3320 CALL DELAY Wa its for few moments204F CD3320 CALL DELAY Wa its for few moments

2052 AF XRA A Clea rs the a ccumula tor2053 DB 81 IN 81H Seeks da t a from the interfa ce

2055 E607 ANI 07H Ma sks a ll bits except bits 0,1 a nd 22057 EAA021 J P E ERR If the da t a conta ins even no. of 1s

jumps to error processing routine205A 326B 21 STA 216B H Stores the da ta (Emit ter-Id) in memory

205D 47 MOV B ,A Moves the Emit t er-Id. to B regist er

205E 3A6A21 LDA 216AH Ext ract s B ase-Id from memory2061 90 SU B B Subt ra cts Emit t er-Id from B a se-Id

2062 326C21 STA 216CH Stores the result(Collector-Id)in mem.

2065 C39220 J MP P 4 J umps to select lea d configura t ion

;Collector identification program for NPN transistors

2068 216A21 P3: L XI H ,216AH P o in t s t o B a s e-I d in da t a t a bl e206B 7E MOV A,M Extra ct the number to the a ccumula tor

206C FE07 CP I 07H Refer note 1

206E CAB 621 J Z ER J umps to error processing rout ine

2071 EE0F XRI 0FH Refer note 2

2073 D383 OU T 83H Send the number t o the interfa ce

2075 216421 LXI H ,2164H P oint s to the messa ge “nP n”2078 CDFC20 CALL DISP LAY Displa ys the same207B CD3320 CALL DELAY Wa its for few moments

207E CD3320 CALL DELAY Wa its for few moments2081 CD3320 CALL DELAY Wa it s for few moments

2084 AF XRA A Clea rs the a ccumula tor2085 DB 81 IN 81H Seeks da t a from the interfa ce

Address Op Code L abel Mnemonic Comments

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210B D383 OU T 83H 74373s. (no da t a w ould move to O/P s)210D 7E MOV A,M Moves the 1st cha r. Of the da t a

pointed, to the a ccumulator (mem.address given by

210E D382 OU T 82H ca lling progra m)

2110 78 MOV A,B B y moving out reg.B da t a throgh port

C

2111 D383 OU T 83H a specific la t ch is ena bled.2113 1F RAR Logic 1 of counter da t a moves right 1

bit

2114 FE00 CP I 00H Checks to see logic 1 moves out from

acc.

2116 CA2121 J Z 2121H (All 4 da t a digit s la tched)to return to

the calling program.

2119 47 MOV B ,A Else stores ba ck new counter da ta to B

reg.

211A CD3320 CALL DELAY

211D 23 INX H Memory pointer incremented by 1

211E C30921 J MP 2109H J umps to the next cha ra cter from the

table

2121 C9 RET Returns t o the ca lling progra m

;Error Sub-routine

21A0 219121 ERR: L XI H ,2191H P oin ts to t he m es sa g e“Adj.” in memory21A3 CDFC20 CALL DISP LAY Ca lls the displa y rout ine to displa y the

same21A6 CD3320 CALL DELAY Wa it s

21A9 CD3320 CALL DELAY Wa it s

21AC 219621 LXI H ,2196H P oints to the messa ge “LEAd ” in

memory

21AF CDFC20 BAD: CALL DISPLAY Cal ls the display rout ine to display21B 2 C30020 J MP MAIN J umps ba ck to st a rt

21B 5 00 NOP No opera t ion

21B 6 218D21 ER: L XI H, 218D H P oin ts t o m es sa g e “bAd” in the datatable

21B 9 C3AF21 J MP B AD J umps to displa y the message

Data table:

Addr. Da t a Display Addr. Da ta Displa y Addr. Da t a Displa y

2160 37 P 2179 C7 b 2189 37 P

2161 45 n 217A 93 C 218A E3 U

2162 37 P 217B 97 E 218B D6 S

2163 00 217C 00 218C 67 H

2164 45 n 217D C7 b 218D C7 b

2165 37 P 217E 97 E 218E 77 A

2166 45 n 217F 93 C 218F E5 d

2167 00 2180 00 2190 00

216A B a se-id (store) 2181 97 E 2191 7 a

216B Emit ter-id (store) 2182 93 C 2192 E5 d

216C Collector-id (store) 2183 C7 b 2193 E1 J

2171 93 C 2184 00 2194 002172 C7 b 2185 93 C 2196 83 L

2173 97 E 2186 97 E 2197 97 E

2174 00 2187 C7 b 2198 77 A

2175 97 E 2188 00 2199 E5 D

2176 C7 b 219A 00

2177 93 C

2178 00

Address of routines/labels:

MAIN 2000 P 202A DELAY 2033 D 2036

P 2 203D P 3 2068 P 4 2092 M 20B 4

P 4A 20B A E 20CA P 4B 20D0 B 20E0

P 4C 20E 6 C 20F6 DISP LAY 20FC ERR 21A0

B AD 21AF ER 21B 6

Notes:

1. During Ba se identification, if the data found ha s odd parity, only then the program

jumps to this routine (starting at 2068 at P3:) for collector identification. A single logic-1denotes a good tra nsistor, whereas three logic-1 (i.e. Base-Id = 07) denote a bad t ransistor

with shorted leads. Hence the program jumps to error processing routine to display the

message “bAd”.

2. The purpose of sending the Ba se-Id number to the interfa ce through P ort-C, is t o

insert a resistor in series with the Base (as indicated in the principle above). The logic-1(s) of

the Ba se-Id, set the sw itches connected with the collector and emitter leads t o“ON ”, and that

with the base to “OFF ”. The result is, the resistor a lready present in the base circuit (10K,

47K or 100K which one is applicable), becomes active. To achieve this result, the Base-Id

found for an NP N device is to be inverted first.

;Display subroutine used by EFY using monitor program of Vinytics kit.

20FC C5 DISP LAY: P U SH B

20FD 3E00 MVI A,0H

20FF 0600 MVI B ,0H

2101 7E MOV A,M

2102 CDD005 CALL 05D0H

2105 C1 P OP B

2106 C9 RET

Address Op Code L abel Mnemonic Comments Addr. Da ta Displa y Addr. Da t a Displa y Addr. Da t a Displa y

TABLE VII

; Modification to Collector Identification Program for pnp Transistors

Address Op Code Label Mnemonic Comments

203D 216021 P2: LXI H ,2160H P oint s t o messa ge ‘P nP ’in data ta b le2040 CDFC20 CALL D ISP LAY D ispla ys the messa ge2043 216A21 LXI H ,216AH P oints to B a se-Id in da t a t a ble2046 7E MOV A,M Extra ct the number to the a ccumula tor2047 D383 OU T 83H Send number via port C to interfa ce

TABLE VIII

; Modification to Collector Identification Program for npn TransistorsAddress Op Code Label Mnemonic Comments

2068 216421 P3: LXI H ,2164H P oint s t o t he messa ge ‘nP n ’206B CDFC20 CALL DISP LAY Displa ys the sa me on displa y.206E 216A21 LXI H ,216AH P oints to B a se-Id in DATA ta ble2071 7E MOV A,M E xtra ct the number to the a ccumula tor2072 FE07 CP I 07H Refer note.1 (see origina l progra m.)2074 CAB 621 J Z ER J umps to error processing rout ine2077 E E0F XRI 0FH Refer note.2 (see origina l progra m.)2079 D383 OU T 83H Send number to interfa ce (via port C)

ing operation is done after first moving

the da ta from the register to the a ccumu-

lator, and then storing the result back

into the register once again if the zero

flag is not set by the R AR opera t ion.

Now, with the reg. B content = 0000 0001,

one more shifting of the bits towa rds right

would make the accumulator content =

0000 0000, w h i c h w o u l d s e t t h e z e r o

flag. And hence the program would jump

back to the calling one. It would be inter-

esting to note the same reg. B content (a

binary number comprising a logic 1) is

sent through port C to enable the particu-

lar latch.

Since the base Id numbers and the

code to enable a specific latch are sent

through the same port (port C) in the

alternate display, the base Id must be

sent first for displaying the message P nP /

nP n . Therefore changes or modifications

are required in the original program per-

ta ining t o collector identificat ion progra m

for pnp transistors (at locations 203D

through 2048) and npn transistors (at lo-

cations 2068 through 207A) as given in

Tables VII and VIII r espectively.

Sof twa r e f l ow cha r t s . Software flow

charts for main program and various sub-

routines are shown in Fig. 5.

P CB and parts list are included only

for the main interface diagram of Fig. 1.

The actual-size, single-sided P CB for the

same is given in Fig. 6 while its compo-

nent la yout is shown in Fig. 7. ❏

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The analogue technology is giving

way to the digital technology as

the latter offers numerous advan-

tages. Digital signals are not only free

from distortion while being routed from

one point to another (over various me-

dia ), but error-correct ion is also possible.

Digital signals can also be compressed

which makes i t possible to store huge

amounts of data in a small space. Thedigita l technology ha s a lso made remark-

able progress in the field of audio and

video signal processing.

Dig i t a l s i gna l process ing i s be ing

widely used in audio and video CD s and CD

playing equipment. These compact disks

have brought about a revolution in the

field of a udio and the video technology. In

audio CD s, analogue signals are first con-

verted into digital signals a nd th en stored

on the CD . During reproduction, the digi-

tal data, read from the CD , is reconverted

into analogue signals. In case of video sig-

nals, the process used for recording and

reproduction of data is the same as used

for audio CD s. However, there is an addi-

tional step involved—both during record-

ing as well as reproduction of the digital

video signa ls on/from th e compa ct disk.

This additional step relates to the com-

pression of da ta before recording on th eCD a nd its decompression wh ile it is being

read. As video data requires very large

storage space, it is first compressed using

MPEG - (Motion P icture E xpert G roup) com-

patible softwa re and then recorded on th e

CD . On reading the compressed video data

from the CD , it is decompressed a nd pa ssed

to th e video processor. Thus wit h t he help

of the compression technique huge a mount

of video data (for about an hour) can be

stored in one CD .

PARTS LIST-1Semiconductors: I C1 - L M7805 volt a ge r eg ula tor + 5 V

Resisters (All ¼W, ±5% metal/ carbon fi lm ,

unl ess stated otherwi se):

R1 - 68 ohmR 2, R 3 - 1 kilo-oh mVR 1 - 100 oh m ce rm et (v a ria b le re si st or )

Capacitors:

C1 - 1µF pa per (unipola r)C2 - 10µF , 16V elect rolyt ic

M iscell aneous:

X1 - 230 V AC pr im a r y t o 12V-0-12 V, 1A s ec.transformer

S 1, S 2 - P u s h-t o-on ta ct i le s w it ch- MPE G decoder card (Sony Digital Tech.)- TV modulator (optional)- AF plugs/jacks (with screened w ire)- Co-axial connectors, male/female- Co-axial cable

G.S. SAGOO

An audio CD player, which is used to play

only audio CD s, can be converted to play

the video CD s as well. Audio CD players

ha ve all t he required mechanism/functions

to play video CD s, except an M PEG card ,

which is to be added to the player. This

M PEG card is readily available in the mar-

ket. This MPEG ca rd decompresses the da ta

a vailable from the a udio CD player and con-

verts it into proper level of video signals

before feeding it to th e television.

Step-by-step conversion of audio CD playerto video CD player is described with refer-

ence to Fig. 1.

Step 1. Connection of MPEG cardto TV and step-down power trans-former to confirm proper working of the MPEG card. Connect IC 7805, a 5-volt regula tor, to the

MPEG card. Please check for correct pin

assignments. Connect audio and video outputs of the

Fig. 1: Complete schematic layout and connection diagram for conversion of Audio CD to Video CD player Fig 2: Photograph of TV scene

P U NER J OT S ING H M ANGAT

14


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MPEG car d t o the a udio/video input of TV

via jacks J 7 and J 11 respectively. Use

only shielded wires for th ese conn ections. Check to ensure that the step-down

transformer provides 12-0-12 volts at

1 ampere of load, before connecting it

to the MPEG card. Connect it to the MPEGcard via jack J 1. Switch on the TV to a ud io/video m ode

of operation. Adjust the 100-ohm pre-

set connected at the video output of

MPEG card to mid position. Switch on the MPEG card by switching

on 230 volts main supply to the 12-0-

12 volt transformer. If everything works right, ‘Sony Digital

Technology’ will be displayed on the

television. The TV screen will display

this for about 5 seconds before going

blank. Adjust the 100-ohm preset forproper level of video signals.

Step 2. Connections to audio CDplayer after confirmation of properfunctioning of MPEG card duringstep1. Open your aud io CD player. Do th is very

carefully, a voiding a ny jerks to the au-

dio CD player, as these may damage the

player beyond repair. Look for the IC number in Table II (on

page 47) that matches with any IC in

your au dio CD player. After finding the right IC , note its RF

EF MIN pin number from the Table I. Follow the P CB t ra ck which leads awa y

form RF EF M in pin of the IC and find

an y solder joint (land ) on t his P CB track.

Solder a wire (maximum ha lf meter) to

this solder joint carefully. Other end of

this wire should be joined to RF jack J 2

of the MPEG card.

Caution: U np l ug t he sol de r i ng i r on form the mai ns before sold eri ng th is wire because any leakage in the sol-

deri ng ir on m ay damage the audio CD

player . Another w ire should be joined betw een

the ground of the audio CD player and

the gr ound of jack J 2 of the MPEG card. This finish es t he connection of the MPEG

card to the audio CD player.

Step 3. Playing audio and videoCDs. Switch on the power for the audio CD

player and the M PEG card.

Put a videoCD

in the audioCD

playerand press i ts play button to play the

video CD . After a few seconds the video picture

recorded on the CD will appear on the

television. The play, pause, eject, rewind, forward,

track numbers, etc buttons present on

the audio CD can be used to control the

new video CD player.

Now your audio CD player is capable

of playing video CD s as well. You can con-

nect a power amplifier to the M PEG card

to get a high-quality stereo sound. The

author tested this project on many audio

players including Thompson Diskma n a nd

Kenwood Diskman. A photograph of one

of the scenes in black and white is in-

cluded as Fig. 2. (Please see its coloured

clipping on cover page.)

No special P CB is required and hence

the same is not included.

The author has perferred to use SonyDigital Technology Card (against KD 680 RF -

35C of C-Cube Technology) becaus e of ma ny

more functions it provides.

Additional a ccessibility fea tur es of this

card (Sony Digital Technology), as shown

in Table I can be invoked by adding two

push-to-on swit ches betw een jack 8(J 8) a nd

ground via 1K resistors (Fig 1). These will

enhance the already mentioned functions

and facilities available on this card, even

though it has not been possible to exploit

the card fully due to non-availability of

technical details. I hope these additions

will help the readers get maximum mile-

age from their efforts.

TABLE I

POSSIBLE EXTRA FUNCTIONS

S1 (mode switch) S2 (function switch)

Slow —Discview —P a l/NTSC P a l NTSCVol+ Volume U p

Vol- Volume Dow nKey+ Left volume dow nKey- Right volume downL/R/C H Left , Right , Mute, S t ereoP la y/P a use —

and backward scan facil i ty with 9-view

pictures, slow-motion play, volume and

tone control and R/L (righ t/left ) voca l.

Want to convert your audio com-

pact disk play er into video com-

pac t d i sk p l ayer . Here i s a

simple, economical but efficient a dd-on cir-

cui t des ign tha t conv er t s your aud io

CD player to video CD player.

Decode r c a r d . The add-on circuit is

based on VCD decoder card, KD 680 RF -3S c,

also known as M PEG card adopting MPEG -

1 (Motion Picture Expert Group) stan-

dard, the internat ional stan-

dard specification for compress-

ing the moving picture and a u-

dio, comprising a DS P (digital

signal processor) IC chip, CL 860

from C-cube (Fig. 3). The VCD

decoder card fea tures smal l

size, high reliability, and low

power consumption (current

about 300ma) and real and ga y

colours. This decoder card has

two play modes (Ver. 1.0 and

Ver. 2.0) and also the forward

Note:The above mentioned functions can also be accessedusing remote control.

Fig. 3: Layout diagram of MPEG card from c-cube

K.N. GHOSH

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put (AV in) facility in their TV, can make

use of a pre-assembled audio-video to RF

convert er (modula tor) module of 48.25MHz

or 55.25 MHz (channel 2 or channel3),

which is easily available in the market

(refer Fig. 4). The a udio an d video signa ls

from the decoder card are suitably modu-l a t e d a n d c o m b i n e d a t t h e f i x e d TV

channel’s frequency in the RF modulator.

The output fr om the m odulator can be con-

nected to antenna connector of a colour

television.

Power supp l y un i t : The VCD decoder

card and the RF modulator requires + 5V an d

+ 1 2V r e g u l a t e d p o w e r s u p p l y

r e s p e c -

tively. Sup-

p l y d e s i g n

uses tw o lin-

ear regula-to rs7805 a nd

7812 (Fig. 5).

The voltage

r e g u l a t o r s

f i t t ed w i th

TO 22 0-type

h e a t s i n k

s h o u l d b e

mounted on

the C D

p l a y e r

enclosure’s

rea r pa nel The circuit

can be wired on a gen-

eral-purpose P CB .

I n s t a l l a t i o n

steps:

1 . F ind su i t ab le

place in th e enclosure

of the aud io CD player

for fixing the decoder card, RF modulator,

and the power supply unit . Make appro-

priate diameter holes an d fix them firmly.

2. Make holes of appropriate dimen-

sions on the rear panel for fixing sockets

for power supply and RF output.

3. Refer to Ta ble II (Combined for P ar t-

I and II) and confirm DS P chip type of the

existing au dio CD player for EF M (eight to

fourteenth modula tion)/RF Signa l (from op-

tical pick-up unit of the audio CD player)

pin number, connect E FM in wire to this

pin.

4. Make a ll the connections as per Fig.

6.

Text of ar ti cles on th e above pr oject

r eceived separ ately fr om th e tw o author s

have been been r epr oduced above so as to

make the informa ti on on th e subject as

exha usti ve as possibl e. We ar e fu r th er

TABLE II

DSP ICs and their EFM RF pin numbers

DSP IC EFM DSP IC EFM/RF Pin /RF Pin

C XA 1372Q 32, 46C XA 1471S 18, 27C XA 1571S 18, 35

AN 8370S 12, 31AN 8373S 9, 35AN 8 80 0SC E 1 2AN 8 802 SEN 9TDA 3308 3LA 9200 35L A 9200 NM 36LA 9211 M 72HA 1215 8 NT46, 72S AA 7210 3, 25(40 pin)SAA 7310 32(44 pin)S AA 7341 36, 38SAA 7345 8SAA 7378 15TC 9200 AF 56TC 9221 F 60

TC 92 36 AF 5 1, 56TC 9284 53YM 22 01 /F K 7 6YM 3805 8YM 7121 B 76YM 7402 4, 71HD 49215 71HD 49233 19AFSUPD 6374 CU 23UPD 6375 CU 46M 50422 P 15M 50427 FP 15, 17M 504239 17M 515679 4M 51598 F P 20MN 35510 43M 65820 AF 17

M 50423 F P 17CX 20109 20, 9S AA7311 25M50122P 15M50123 F P 17M50127 F P 17U P D 6374 C V 3N M2210F K 76YM2210FK 76

cuit, digital to analogue converter, micro

computer interface, video signal proces-

sor, and error detector, etc. Audio and

video signa ls stored on a CD are in a high-

density digital format. On replay, the digi-

tal information is read by a laser beam

and converted into analogue

signals.

One can also use another

VCD decoder card comprising a n

M PEG IC 680, from Technics, and

a DS P IC chip, CXD 2500, with pow-

er fu l e r ro r-cor rec t ion f rom

Sony. Similarly, another card,

K D 2000-680R F c o m p r i s i n g a n

M PEG IC chip, CL 680 from Tech-

nics and a DS P IC chip, MN6627

from C-cube.

RF modu l a t o r . For those

wh o do not ha ve au dio-video in-

KS 5950 5KS 5990, 5991 5KS 9210 B 5

KS 92 11 B E , 9 21 2 5KS 9282 5, 66KS 9283 66KS 9284 66CXD 1125 QX 5CXD 1130 QZ 5CXD 1135 5CXD 1163 Q 5CXD 1167 R 36C XD 1167 Q/QE 5CXD 20109 9, 20C XD 25 00 AQ /B Q 2 4CXD 2505 AQ 24

CXD 2507 AQ 14

CXD 2508 AQ 36CXD 2508 AR 36

CXD 2509 AQ 34CXD 2515 Q 36, 38CXD 2518 Q 36LC 7850 K 7LC 7860 N/K /E 7, 8LC 7861 N 8LC 7862 30LC 78620 11LC 78620 E 11LC 7863 8LC 7865 8

LC 7866 E 7, 8LC 7867 E 8LC 7868 E 8LC 7868 K 8LC 78681 8MN 6617 74

MN 6222 11MN 6625 S 41MN 6626 3, 62MN 6650 6MN 66240 44MN 66271 RA 44, 52MN 662720 44CXA 72S 18, 46CXA 1081Q 2, 27

PARTS LIST-2

Semiconductors:

I C1 - L M78L 05, volt ag e r eg ula t or + 5 V

I C2 - 78L 12, volt a ge r eg ula t or + 12V

D 1, D 2 - 1N 4001, r e ct if ie r d iod e

Capacitors:

C 1 - 2200µF , 35V elect rolyt ic

C 2 ,C 3 - 1 00 µF, 1 6V e le ct r ol yt i c

M iscell aneous:

- 230V AC primar y t o 18V-0-18V,

1A sec. transformer

- MPEG decoder card (C-cube DigitalTech.)

- TV modulator (optional)

- AF plugs/jacks (wit h screened wire)

- Co-axia l connectors, male/female

- Co-ax ia l cable

The decoder card converts your CD play-

ers or video games to VCD player to give

almost DV D-quality pictures.

The decoder card mainly consists of

sync signal separator, noise rejection cir-

Fig. 4: Layout of TV RF modulator

Fig. 5: Power supply to cater for MPEG card and RF modulator

Fig. 6: Block diagram of connections to decoder card and codulator

16


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serv ed th at f r equent l y, th e pi ctur e/

frames froze on the CTV screen and the

power to th e MPEG convert er card had to

be switched off and on again. Thi s fault

was attr ibuted to inabil ity of 7805 regu-

la t o r to del i ver t he requ i red cu r r en t

(about 300 mA) to the MPEG card. Th e regulator cir cuit w as therefore modifi ed

as shown i n F ig. 7 to provide a bypass

path for curr ent above 110 mA (approxi-

mat ely). A step-down t ran sform er of 9V-

0-9V, 500mA is adequate if th e modul a-

tor has it s own power supply ar ran ge-

ment (r efer par agra ph 4 below).

4. RF modulator for TV channels E 2

and E 3 are availabl e in the mark et com-

plete wi th step-down t ran sform er, hence

th ere may n ot be any n eed to w ir e up a

12V regulator cir cuit of part II .

5. Apar t fr om the facil i t ies (availabl e in t he MPEG decoder car d KD 680 RF - 3 SC from

C-cube) as expla in ed by t he auth or, th ere

ar e other facil it ies such as IR r emote con-

tr ol of the card functi ons (via J ack J 5 )

and reali sation of change-over betw een

N TSC and PAL m odes (via jack J 4 –no

connections means PAL mode). Sim ilar ly,

Jack J 1 is meant for extern al au di o and

vid eo inpu t f rom exchange and connec-

t i o n of aud i o and v i deo ou tpu t s t o

CTV . The foregoin g inform ation i s avail-

ab le on d ocum en t accompany i ng th e

MPEG decoder card . H owever , the detail ed

appl icat ion/ inform ation is not provided

and as such we have not tested these

faci l i t ies.

6. EFM i s a techn iqu e used f or encod-

in g digital samples of audi o signals into

seri es of pi ts and land s int o the disc sur-

face. Dur in g pl ayback t hese are decoded

in to digit al r epresentat ion of audio sig-

nal and converted to analogue form us-

in g digi tal -to-analogue convert er f or even-

tu al feedi ng to th e loud speakers.

7. For th ose ent hu siasts who wi sh to

ri g-up their own video modul ator, an ap-

pl icat ion circuit fr om Nati onal Semi con-

ductor L td , m aki ng use of I C L M 2889 ,

wh i ch is p in for p i n compa t ib le wi th

LM 1889 ( RF section), is given in Fi g 8.

—Tech Editor

player part. T he DSP chip, more often th an

not, would be a mu lt ipi n SM T device. I n

the AIWA system we located t wo such chi ps

( LA9241 M and LC 78622 E both fr om Sanyo).

Th ei r data-sheets, p icked u p fr om th e

I ntern et, r evealed th e form er chi p to be an

ASP (anal ogue sign al pr ocessor) and lat ter one ( LA78622 E ) is th e CD player DSP chip for

which EFM IN is not found in T able I. For

thi s chip EFM IN p i n is pin 10 whil e pin 8 is

the nearest d igit al gr ound pi ns–wh ich w e

used.

2. Of th e tw o conver ter card s

(one d isp lay ing ‘Sony Dig i ta l

Techn ology' an d th e other d is-

p lay ing ‘C-cube Techno logy ’

on the CT V screen), t he la t ter

card's resoluti on and colour qual-

i t y wa s foun d t o be ver y good

when tested by us. The C-cube card needs a single 5V DC supply

for i ts operat ion.

3. During testing it was ob-

Fig. 8: Two channel video modulator with FM sound

Fig. 7: Modified 5V regulator for enhancing current capability

adding the fol lowing information which

we have been abl e to gather du ri ng th e

pr actical t estin g of th e pr oject at EFY .

1. Th er e may be more th an one PCB

used i n an audi o CD player (i.e addi tional

for FM r adi o and tape record er functions)

and even the DSP chips r eferr ed in Tabl e1,ma y not fi gur e on it. For example, we coul d

not fi nd the subject IC used i n AIWA audio

CD pl ayer. T he PCB , wh ich i s located clos-

est un der t he laser system, i s related to CD

www.electronicsforu.coma portal dedicated to electronics enthusiasts

17


18/205

C I R C U I T I D E A SCIRCUIT IDEAS

This add-on device for telephones

can be connected in para llel to the

telephone inst rument . The circuit

provides audio-visual indication of

on-hook, o f f -hook, and r ing ing

modes. It can also be used to con-

nect the telephone to a CI D (caller

identification device) through a re-

lay and also to indicate tapping or

misuse of telephone lines by sound-

ing a buzzer.

In on-hook mode, 48V DC supply

is maintained across the telephone

lines. In this case, the bi-colour LE D

glows in green, indicating the idle

state of the telephone. The value of

resistor R1 can be changed some-

what to adjust the LE D glow, with-

out loading the telephone lines (by

trial a nd error).

In on-hook mode of the hand-

set, potentiometer VR1 is so adjusted

that base of T1 (B C547) is forward bi-

ased, w hich, in tur n, cuts off transistor T2

(B C108). While ad justing potmeter VR1, en-

sure that the LE D glows only in green and

not in red.

When the hand-set is lifted, the volt-

age drops to around 12V DC . When this

ha ppens, the voltage a cross tra nsistor T1’s

base-emitter junction falls below its con-

duction level to cut it off. As a result t ra n-

sistor pair T2-T3 starts oscil lating and the

piezo-buzzer starts beeping (with switch

S 1 in on position). At the same time, the

bi-colour LE D glows in red.

In ringing mode, the bi-colour LE D

flashes in green in synchronisation with

the telephone ring.

A CI D can be connected using a relay.

The relay driver tra nsistor can be con-

nected via point A as shown in the cir-

cui t . To use the c i rcui t fo r warningaga inst misuse, switch S1 can be left in

on position to activate the piezo-buzzer

when anyone tries to tap the telephone

line. (When th e telephone line is tapped,

it’s like the off-hook mode of the tele-

phone hand-set.)

Two 1.5V pencil cells can provide Vcc1

power supply, wh ile a sepa ra te power sup-

ply for Vcc2 is recommended to avoid

draining the battery. However, a single

6-volt supply source can be used in con-

junction with a 3.3V zener diode to cater

to both Vcc2 and Vcc1 supplies.

The circuit described here is of an

electronic combination lock for

daily use. It responds only to the

right sequence of four digi ts that are

keyed in remotely . I f a wrong key is

touched, it resets the lock. The lock code

can be set by connecting the l i ne wires to

the pads A, B , C , and D in the figure. For

example, if the code is 1756, connect line

1 to A, line 7 to B , line 5 to C , line 6 to D

a nd r est of th e lines—2, 3, 4, 8, and 9—to

the reset pad a s shown by dotted l ines in

the figure.

The circuit is built around two CD 4013

dual-D flip-flop IC s. The clock pins of the

four flip-flops are connected to A, B , C ,

RANJ ITH G . P ODU VAL

YASH D. DOSHI

and D pads. The correct code sequence for

energisation of relay RL 1 is realised by

clocking points A, B , C , and D in that or-

der. The five remaining switches are con-

nected to reset pad which resets all the

flip-flops. Touching the key pad switch A/

B /C/D briefly pulls the clock input pin high

and the state of flip-flop is altered. The Q

output pin of each flip-flop is wired to D

input pin of the next flip-flop while D pin

of the first flip-flop is grounded. Thus, if

correct clocking sequence is followed then

low level appears at Q2 output of IC 2 which

energises the relay through relay driver

G.S. SAGOO

G.S. SAGOO

18


19/205

C I R C U I T I D E A S

transistor T1. The reset keys

are wired to set pins 6 and

8 of each IC . (P ower-on-reset

capacitor C1 has been added

at EFY during testing as the

state of Q output is indeter-

minate during switching onoperation.)

This circuit can be use-

fully employed in cars so

that the car can star t only

when the correct code se-

quence is keyed in via the

key pad. The circuit can a lso

be used in various other ap-

plications.

This circuit is used to a utomate t he

working of a bath room light. It is

designed for a bathroom fi t ted

with an automatic door-closer, where the

manual verification of l ight status is dif-

ficult. The circuit also indicates whether

the bathroom is occupied or not. The cir-

cuit uses only two IC s and can be oper-

ated from a 5V supply. As it does not use

any mechanical contacts i t gives a reli-

able performance.

One infrared LE D (D1) a nd one infrared

detector diode (D2) form the sensor part of

the circuit . Both the infrar ed LE D and the

detector diode are fitted on the frame of

a reference potential set by preset VR1.

The preset is so adjusted as to provide

a n optimum th reshold volta ge so tha t out-

put of IC 2(a) is high when the door is

closed and low when the door is open.

Capacitor C1 is connected at the output

to fi lter out unw ant ed tra nsitions in out-

put voltage generat ed at t he time of open-

ing or closing of the door. Thus, at point

A, a low-to-high going voltage transition

is available for every closing of the door

after opening it. (See waveform A in Fig.

2.)

The second comparator IC 2(b) does th e

reverse of IC 2(a), as the input terminals

are reversed. At point B , a low level is

available when the door is closed and it

J AYAN A.R .

the door with a small sepa-

r a t i o n b e t w e e n t h e m a s

shown in Fig. 1. The radia-

tion from IR LE D is blocked

by a small opaque strip (fi t-

ted on the door) when the

door is closed. Detector di-

ode D2 has a resistance in

the ra nge of meg-ohms wh en

it is not activated by IR rays.

When the door is opened,

the strip moves along with

it. Radiation from the IR LE D

turns on the IR detector di-

ode and the voltage across

it drops to a

low level.

C o m -

p a r a t o r

LM 358 IC 2(a )

c o m p a r e s

the vol tage

a c r o s s t h e

photodetec-

t o r a g a i n s tFig. 1

Fig. 2

G.S. SAGOO

19


20/205


switches to a high level when

the d oor is opened. (See wa ve-

form B in Fig. 2.) Thus, a low-

to-high going voltage transi-

tion is available at point B for

every opening of the door ,

from the closed position. Ca-pacitor C2 is connected at the

output to fi l ter out unwanted

transitions in the output volt-

age generated at the time of

closing or opening of the door.

IC 7474, a rising-edge-sen-

sitive dual-D flip-flop, is used

in the circuit to memorise the

occupancy status of the bath-

room. I C 1(a) memorises the

state of the door and acts as

an occupancy indicator while

IC 2(b) is used to control the re-

lay to turn on and turn off the bathroom

light. Q output pin 8 of IC 1(b) is tied to D

input pin 2 of IC 1(a) whereas Q output pin

5 of IC 1(a) is tied to D input pin 12 of

IC 1(b).

At the time of switching on power for

the first time, the resistor-capacitor com-

bination R3-C3 clears the two flip-flops. As

a result Q outputs of both IC 1(a) and IC 1(b)

are low, and the low level at the output

of IC 1(b) activates a relay to turn on the

bathroom light. This operation is inde-

penden t of t he door st a tu s (open/closed).

Most of the fluid level indicator

circuits use a bar graph or a

seven-segment display to indi-cate the fluid level. Such a display using

LE D s or digits may not make much sense

to an ordinary person. The circuit pre-

sented here overcomes this flaw and dis-

plays t he level using a seven-segment dis-

play—but w ith a difference. It shows each

level in meaningful English letters. It dis-

plays the letter E for empty, L for low, H

for half, A for above average, and F for

full ta nk .

The circuit is built using CMOS IC s.

CD 4001 is a quad. NOR gate and CD 4055 is a

B CD to seven-segment decoder and dis-

play driver IC . This decoder IC is capable

of producing some English alphabets be-

sides the usual digits 0 through 9. The

BC D codes for various displays are given

in Table I. The B CD codes are generated

by NOR gates because of their intercon-

nections as the sensing probes get im-

mersed in water. Their operation being

self-explana tory is n ot included here.

Note that there is no display pattern

like E or F available from the IC . There-

fore to obtain the pattern for letters E

and F , transistors T1 and T2 are used.

These transistors blank out the unneces-

sary segments from the seven-segment

display. It can be seen that letter E is

generat ed by blanking ‘b’ an d ‘c’ segments

of the seven-segment display while it de-

codes digit 8. Letter F i s obtained by

blanking segment ‘b’ while it decodes let-

ter P .

As CMOS IC s are used, the current con-

The occupancy indicator red LE D (D3) is off

at this point of t ime, indicating that the

room is va cant.

When a person enters the bathroom,

the door is opened and closed, which pro-

vides clock signals for IC 1(b) (first) and

IC 1(a). The low level at point C (pin 5) is

clocked in by IC 1(b), at the time of open-

ing the door, keeping the l ight st at us un-

changed.

The high level point D (pin 8) is

clocked in by IC 1(a), turning on the occu-

pancy indicator LE D (D3) on at the time of

closing of the door. (See waveform C in

Fig. 2.)

When the person exits the bathroom,

the door is opened again. The output of

IC 1(b) switches to high level, turning off

the bathroom light. (See waveform D in

Fig. 2.) The closing of the door by the

door-closer produces a low-to-high transi-

tion at the clock input (pin 3) of IC 1(a).

This clocks in the low level at Q output

of I C 1(b) point D to Q output of I C 1(a )

point C , thereby turning off the occupancy

indicator.

TABLE I

D C B A DISPLAY

L L L L 0L L L H 1— — — — 2— — — — 3— — — — 4— — — — 5— — — — 6— — — — 7H L L L 8H L L H 9H L H L LH L H H HH H L L PH H L H AH H H L —

H H H H B L ANK

THOMMACHAN THOMAS

RUPANJANA

Fig. 3

20


21/205


sumption is extremely low. This makes it

possible to power the circuit from a bat-

tery. The input sensing current through

the fluid (with all the four probes im-

mersed in water) is of the order of 70 µA,

which results in low rate of probe dete-

rioration due to oxidation as also low lev-

els of electrolysis in t he fluid.

No t e : Thi s c i rcui t should no t be

used with inflamm able or highly reactive

fluids.

Thi s i s an e f fec t i v e and use fu l

project for educat ional inst i tu-

tions. In most schools and col-

leges, the peon rings the bell after every

period (usually of a 40-minute duration).

The peon ha s to depend on his w rist w at ch

or clock, and sometimes he can forget to

ring the bell in time. In the present sys-

tem, the human error has been el imi-

nated. Every morning, when the school

starts, someone has to just switch on the

system and it thereafter work automati-

cally.

The automatic microprocessor con-

trolled school bell system presented here

h a s b e e n t e s t e d b y t h e a u t h o r o n a

Vinytics’ microprocessor-8085 kit (VMC -

8506). The kit displays

the period number on

two most significant

digits of address field

and minutes o f the

period elapsed on the

next tw o digits of the

a d d r e s s f i e l d . T h e

data field of the kit

displays seconds con-

tinuously.

T h e i d e a u s e d

here is very simple.

The programmable peripheral interfacing

(P P I ) Intel-8255-I chip present in the micro-

processor kit has been used. It has three

8-bit w ide input /output ports (port A, port

B , and port C). Control word 80 (hex) is

used to initialise all ports of 8255-I as out-

put ports. B it 0 of port A (P A0) is connected

to the base of transistor BC 107 through a

10-kilo-ohm resistor as shown in the fig-

ure. It is used to energise the relay when

P A0 pin of 8255-I is high. A siren, hooter,

or any bell sound system with an audio

amplifier of proper wattage (along with 2

or 3 loudspeakers) may be installed in

the school campus. The relay would get

energised after every 40 minutes for a

Dr D.K. KAUSHIK

RUPANJANA

PAO

21


22/205


few seconds. The program (software) and

data used for the purpose are given be-

low in mnemonic and ma chine code forms.

The progra m is self-explana tory.

The program and data have been en-

tered at specific memory locations. How-

ever, the readers ar e at l iberty to use anyother memory area in their kits, depend-

ing on their convenience. Two monitor

programs (stored in kit’s ROM /EPRO M) a t

locations 0347H (for clearing the display)

and 05D OH ( for displaying contents o f

memory locations 2050H through 2055 in

the address and data fields respectively)

have been used in the program. Please

note that before calling the display rou-

tine, registers A and B are required to be

initia lised with either 00 or 01 to indicat e

to the monitor program as to where the

contents of above-mentioned memory lo-

cations are to be displayed (e.g. addressfield or data field), and whether a dot

is to be displayed at the end of address

field or not. (Readers should refer to th eir

kit’s documentation before using the dis-

play routine.) In Vinytics’ kit , i f register

A contents are 00, the address field is

used for display , and i f i t i s 01, the

data field is used for display. Similarly,

i f register B contains 00 then no dot

is displayed at the end of address field,

else i f B c o n t e n t s a r e 0 1 , a d o t i s

displayed.

When the program is executed on the

microprocessor kit, a bell sound would beheard for a few seconds. The address and

dat a fields would initial ly display :

01 00 00

01 indicates start of first period with 00

as elapsed minutes a nd 00 seconds in t he

data field. The data field (seconds) are

continuously incremented.

Address Op-code Label Mnemonic Comments

20 FC 3E 80 MVI A, 80H I nit ia lise 8255-I a s output port20 F E D E 03 OU T 03 H2100 31 FF 27 L XI SP , 27FF H I nit ia lise t he st a ck poin t er2103 C D 47 03 C AL L 0347H C lea rs t he displa y

2106 C 3 69 21 J MP TT J um p t o r ing the bell2109 AF AA XRA A P ut A= 0210 A 47 MOV B , A P ut B = 0210 B 21 50 20 L XI H , 2050 H S ta r t ing a ddress of displa y210 E C D D0 05 C AL L 05D 0H C a ll output rout ine t o displa y per iod

no. & minutes to address field21 11 3E 01 MVI A, 01H A= 0121 13 06 00 MVI B , 00H B = 0021 15 21 54 20 L XI H , 2054H C ur rent sec.21 18 C D D 0 05 C AL L 05D 0H Address of L SD of current sec.21 1B 21 55 20 L XI H , 2055H21 1E 7E MOV A, M Move the L S D of curr en t sec. t o a cc.21 1F C 6 01 AD I 01 H Add 01 t o a cc.21 21 FE 0A C P I 0AH C om pa re L S D of sec. w ith 0AH (10

decimal)21 23 C A 36 21 J Z RR If L S D com pletes 09 jum p t o RR21 26 77 MOV M, A Move t he a cc. cont ent t o 20 55 H

location

21 27 06 02 D D MVI B , 02H D ela y21 29 11 00 F A YY L XI D , FA00H S ub-21 2C C D 00 25 C ALL 2500H Rout ine21 2F 05 D CR B F or21 30 C 2 29 21 J NZ YY 1 second21 33 C 3 09 21 J MP AA After dela y of 1 sec.

J ump to AA for display the t ime21 36 3E 00 RR MVI A, 00H A= 021 38 77 MOV M, A S t ore Acc. To m em ory loca t ion21 39 2B D C X H D ecrem ent H L pa ir content21 3A 7E MOV A, M Move t he MS D of sec to a cc.21 3B C 6 01 AD I 01H Add 01 to Acc.21 3D FE 06 C P I 06H C om pa r e MS D of sec w ith 06H21 3F C A 46 21 J Z U U I f sec. com plet e 59 m ove to U U21 42 77 MOV M, A S t ore a cc. cont ent to m em ory

location21 43 C 3 27 21 J MP D D J um p for dela y of 1 sec.21 46 3E 00 U U MVI A, 00 P ut A= 00 a ft er com plet ing 59

seconds21 48 77 MOV M,A21 49 2B D C X H21 4A 7E MOV A,M Move current L S D of m inut es t o a cc.21 4B C 6 01 AD I 01H Add 01 t o a cc.21 4D FE 0A C P I 0A C om pa r es a cc. to 0A H21 4F C A 56 21 J Z VV J um p to VV if LS D of m inutes

completes 0921 52 77 MOV M,A Move a cc. to m em or y loca t ion21 53 C 3 27 21 J MP D D J um p for dela y of 1 sec.21 56 3E 00 VV MVI A,00H21 58 77 MOV M,A21 59 2B D C X H D ecrem ent H -L pa ir content21 5A 7E MOV A,M Move MS D of m inut es t o a cc.21 5B C 6 01 AD I 01H Add 01 t o a cc.21 5D FE 04 C P I 04H C om pa re a cc. cont ent w it h 04 H21 5F C A 66 21 J Z S S I f m inutes 40 then jum p t o SS21 62 77 MOV M,A

21 63 C 3 27 21 J MP D D J um p for dela y of 1 sec

Address Op-code Label Mnemonic Comments

21 66 3E 04 S S MVI A, 04 P ut A= 421 68 77 MOV M, A21 69 AF TT XRA A A= 021 6A 47 MOV B ,A B = 0

21 6B 21 50 20 LXI H , 2050H21 6E C D D 0 05 C AL L 05D 0H D ispla y the period no. a nd m inut es

in a ddress fie ld21 71 3E 01 MVI A, 01H A= 121 73 06 00 MVI B , 00H B = 021 75 21 54 20 LXI H , 2054 H21 78 C D D 0 05 C AL L 05D 0 H D ispla y t he seconds in da ta field21 7B 3E 01 MVI A, 01H21 7D D 3 00 OU T 00H E xit e t he 8255:1 for engergising t he

relay (r ings the bel l)21 7F 21 55 20 LXI H , 2055H21 82 3E 00 MVI A, 00H S tor es 00 t o m em ory loca t ion21 84 77 MOV M, A 2055 to21 85 2B D C X H 2052 H21 86 77 MOVM, A21 87 2B D C X H21 88 77 MOV M, A21 89 2B D C X H

21 8A 77 MOV M,A21 8B 2B D C XH21 8C 7E MOV A, M B rings t he LS D current period

no. to acc21 8D C 6 01 AD I 01 Add 1 to it com pa re w it h OA21 8F FE 0A C P I 0A21 91 C A 98 21 J Z XX I f L S D of period no. com plete 09 t hen

jump to XX21 94 77 MOVM, A E lse st ore it t o m em ory loca t ion21 95 C 3 A0 21 J MP XY J um p to XY21 98 3E 00 XX MVI A, 00H A= 021 9A 77 MOV M,A S t or e it t o m a in loca t ion21 9B 2B D C X H21 9C 7E MOV A, M S t ore MS D of per iod no. t o a cc21 9D C 6 01 AD I 01H Add 1 t o it21 9F 77 XXX MOV M,A S t ore it m em or y loca t ion21 A0 06 02 XY MVI B , 0221 A2 11 00 F A XYZ L XI D , FA 00H P rogra m 1 sec displa y

21 A5 C D 00 25 C ALL 2500 H21 A8 05 D C R B21 A9 C 2 A2 21 J NZ XYZ21 AC AF XRA A= 021 AD 47 MOV B ,A B = 021 AE 21 50 20 LXI H , 2050H21 B 1 C D D 0 05 C AL L 05D 0H21 B 4 3E 01 MVI A, 0IH21 B 6 06 00 MVI B , 00H P rogr a m to displa y21 B 8 21 54 20 L XI H , 2054 H The period no.21 B B C D D 0 05 C AL L 05 D 0 H Minut es a nd second21 B E 21 55 20 LXI H , 2055H21 C 1 7E MOV A, M L SD of st or ed cur rent second t o a cc21 C 2 C 6 01 AD I 01H Add 1 t o it21 C 4 F E 06 C P I 06H C om pa re w it h 0621 C 6 C 2 9F 21 J NZ XXX If not 06 jum p to XXX21 C 9 3E 00 MVIA, 00H A= 021 C B D 3 00 OU T 00H Out put t o 8255 t o de-energise

the relay

22


23/205


RUPANJANA

Address OP CODE LABEL Mnemonic Comments

21 C D C 3 09 21 J MP AA Repea t for next period

DELAY SUBROUTINE25 00 1B NE XT D CX D25 01 7A MOV A, D25 02 B 3 ORA E25 03 C 2 00 25 J NZ NE XT

25 06 C9 RE T

Address OP CODE LABEL Mnemonic Comments

DATA20 50 00 MS D of period no.20 51 00 LS D of period no.20 52 00 MS D of m inut es20 53 00 L S D of m inut es20 54 00 MS D of seconds20 55 00 L S D of seconds

Radio frequency probe is used to

directly measure the level of RF

RMS voltage present across twopoints. It is one of the most useful test

instruments for home brewers as well as

for commu nica tion equ ipment service/de-

sign labs.

RF voltage level being measured pro-

vides useful information only when the

probe has been designed for use with a

specific multimeter. The design of RF

probe is a function of the meter we in-

tend to use i t with. If a meter with a

different input resistan ce is used with the

probe, the rea ding will be incorrect. The

value of RX (refer figure) is so chosen tha twhen this resistor is connected in paral-

lel with input resistance of the multim-

eter, the peak value is about 1.414 times

the RMS voltage. Resistor RX has to drop

this excess voltage so that meter indica-

tion is accurate. If we know the input

resistance of the meter, we can calculate

the value of RX with the help of the fol-

lowing relationship:

Let meter DC input resistance

X 1.414 = RY

Then RX = R

y – meter DC input resis-

t anceFor example, i f meter input resis-

tance is 20 meg-ohm, Ry = 28.28 meg-

ohm and RX = 8.28 meg-ohm.

We can convert the RF voltage level

N.S. HARISANKAR, VU3NSH

(E) so mea-s u r e d

a c r o s s a

g iv en load

r e s i s t a n c e

(R ) to R F

watts (W)

u s i n g t h e

f o l l o w i n g

r e l a t i o n -

ship:

Power P

= E 2 / R

watts (W)For example, if RF probe voltage read-

ing across a load resistance of 50 ohms is

found to be, sa y, 15.85 volts, t he power in

th e load = 15.85 x 15.85 /50 = 5W approx.

In other words, for 5-watt power in a

50-ohm load, the voltage across the load

is 15.85 volts.

The rectified DC voltage at the cath-

ode of diode D1 is at about the peak level

of the RF voltage at the tip of the probe.

Use shielded cable in between the probe

output and meter . I t wi l l act as feed-

through capacitance and thus avoid RF i n-

terference. The maximum RF input volt-age level depends on the peak inverse volt-

age (P IV ) of diode D1. The shielded lead

length is too large to give accurate re-

sults at U HF . Please refer Tables I and II

for ready conversion of RF voltage level (RMS) to

equivalent power across a 50-ohm load and deduc-

tion of RX value for a given meter’s DC input resis-

tance respectively.

Table II

Meter DC Impedence R x

20 Meg-ohm 8.25 Meg-ohm10 Meg-ohm 4.14 Meg-ohm1 Meg-ohm 41.4 kilo-ohm20 kilo-ohm 8.28 kilo-ohm

TABLE I

Voltage to Watts Conversionfor 50 ohms Termination

RMS (V) RF Power (W)

2.24 0.13.88 0.35.0 0.57.08 112.25 315.90 520.0 822.4 1038.75 2541.85 3550.0 50

23


24/205


25/205


This project describes the software

and hardware necessary to moni-

tor and capture in real t ime the

speed of any rotating object. The speed

ma y be defined/st ored/displa yed in a ny of

th e th ree unit s: RPM (rev./minut e), R P S

(rev./second ), or RP H (rev./hou r). The s ys -

tem uses a sampling time of two seconds

an d can st ore up to 16 minutes of data per

file. The x a nd y a xes can be scaled to read

a ny speed and t he x-axis can be ‘stret ched’

to observe clustered points .

The hardware mainly comprises a

proximity switch whose output is con-

nected to the printer

(LP T1) port of t he com-

puter through a n opto-

coupler. The proximity

s w i t c h i s u s e d a s a

speed-sensor. The pro-

gram is wri t ten in C+ +

and has effective error

han dling capability a nd

a help facility. This sys-

t e m c a n b e u s e d t o

monit or the speed of ro-

tating parts in the in-

dustry or to read and

record w ind speeds.

The hardware interface circuit is given

in F ig. 1. A 230V AC prim a ry t o 0-9V,

250mA secondary transformer followed

by IC 7805 is used for cat ering t o th e

power supply requirement for proximity

switch and the opto-coupler. The proxim-

ity switch, as shown in Fig. 2, is a 3-wire

sw itch (e.g. PG Electronics’ ED P 101)

which operates at 6V to 24V DC.

The inductive type proximity switch

senses any metal surface from a distance

of about 5 mm to 8 mm. Thus, a gear or

fan blade is ideal for counting the number

of revolutions. The number of teeth that

trigger (switch-on) the proximity switch

during every revolution are to be known

for the software to calculate the speed of

G.S. SAGOO

SANTHOSH J AYARAJ AN

the machinery. The output of the circuit,

available across resistor R2, is fed to the

P C via 25-pin ‘D’ connector of pa ra llel port

LP T1. Pin 11 pertains t o data bit D7 of the

input port 379(hex) of the LPT1 port hav-

ing base address 378(hex), and pin 25 is

connected to PC ground. (In fact, pins 18

thr ough 25 of the para llel port a re stra pped

toget

Documents

63505504 Electronics Projects