620 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 3 ...eeic7.sogang.ac.kr/paper file/international journal/JSSC10_A 12 bit 50... · 622 IEEE JOURNAL OF SOLID-STATE CIRCUITS,

620 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 3, MARCH 2010

A 12 bit 50 MS/s CMOS Nyquist A/D Converter Witha Fully Differential Class-AB Switched Op-Amp

Young-Ju Kim, Hee-Cheol Choi, Gil-Cho Ahn, and Seung-Hoon Lee

Abstract—A 12 bit 50 MS/s 1.8 V pipelined CMOS analog-to-dig-ital converter (ADC) based on a fully differential class-AB switchedoperational amplifier achieves low power consumption with a dif-ferential input voltage of 2.4 Vp-p. A global-loop dynamiccommon-mode feedback circuit enables fully differential class-ABoperation with dynamic current switching for power reduction.The prototype ADC shows a peak signal-to-noise-and-distortionratio of 64.0 dB and a peak spurious-free dynamic range of 76.6dB for a 31 MHz input signal at 50 MS/s while the measureddifferential and integral nonlinearities are within 0.26 LSB and

0.72 LSB, respectively. The prototype ADC in a 0.18 m 1P6MCMOS process consumes 18.4 mW at 50 MS/s and 1.8 V occupyingan active die area of 0.26 mm�.

Index Terms—Analog-to-digital converter (ADC), class-AB,fully differential, low power, sample-and-hold amplifier(SHA)-free, switched operational amplifier (op-amp).

I. INTRODUCTION

L OW POWER consumption is a key specification in bat-tery-powered systems such as wireless communication

and mobile imaging applications, and the high-performanceA/D converter (ADC) is one of the most essential buildingblocks for those systems. However, the required linearity for12 bit-level high-speed ADCs is difficult to be implementedwith thin-oxide digital CMOS technologies due to the re-duced voltage headroom and low intrinsic output resistanceof transistors while the linearity of some circuits relies onpost-fabrication component trimming, cascaded and/or cas-coded gain stages, and complicated digital calibration [1]–[3].Nevertheless, the state-of-the-art mobile multimedia systemsfor digital audio and video broadcastings have demandedhigh-performance high-resolution ADCs with an input band-width over the Nyquist frequency and a high signal swing range[4]. In those ADCs, the most critical circuit building block todetermine the maximum achievable accuracy and samplingrate with low power dissipation is an op-amp. Typical op-ampsrequire a proper slewing and settling time for a signal to reachthe target level within the required time, and the most widelyemployed class-A op-amp consumes static currents constantlyduring both of the slewing and settling periods. Althoughsome inventive power-saving schemes such as switched bias,op-amp sharing, and op-amp current reuse techniques minimize

Manuscript received August 24, 2009; revised November 30, 2009. Currentversion published February 24, 2010. This paper was approved by AssociateEditor Jan Craninckx. This work was supported in part by the IDEC of KAIST,Korea.

The authors are with the Department of Electronic Engineering, Sogang Uni-versity, Seoul 121-742, Korea (e-mail: [email protected]).

Digital Object Identifier 10.1109/JSSC.2009.2039534

power consumption [5]–[9], achievable signal ranges tend to belimited. The well-known class-AB op-amp mostly consumesdynamic currents during the slewing period and dissipates onlysmall quiescent currents during the next settling period. Eventhough a class-AB design cannot possibly achieve the samemaximum speed as a class-A design in the same technology,additional power reduction can be obtained along with arail-to-rail output swing by replacing the class-A type op-ampwith the class-AB type [10]–[12]. Moreover, the class-ABop-amp tends to have a relatively small transistor size anddie area at the same operating speed compared to the class-Aop-amp [13].

This work proposes a low-power 12 bit 50 MS/s 1.8 Vpipelined CMOS ADC based on a fully differential class-ABswitched op-amp [14]. The proposed two-stage class-ABop-amp with a floating current source and a global-loop dy-namic common-mode feedback (CMFB) circuit can processsignals with a much higher swing range than the conventionalfully differential class-A op-amps. The sample-and-hold am-plifier (SHA)-free input sampling network composed of onlygate-bootstrapping switches and capacitors samples high-swingwideband signals exceeding the Nyquist frequency without se-rious distortion at 12 bit level. The proposed ADC architectureis discussed in Section II and the op-amp topology is describedin Section III. Circuit design techniques with a fully differentialclass-AB op-amp are discussed in Section IV. The measuredresults of the prototype ADC are summarized in Section V.Finally, conclusion is given in Section VI.

II. PROPOSED ADC ARCHITECTURE

The proposed 12 bit 50 MS/s CMOS ADC consists of fivepipelined stages, a 3 bit back-end ADC, a current and amp-bias generator, a clock generator, and a digital correction logic(DCL) block, as shown in Fig. 1. Each pipelined stage is com-posed of a multi-bit multiplying D/A converter (MDAC) and asub-ranging flash ADC, generating 2 bit and 3 bit coarse digitaloutputs for the first stage and the remaining stages, respectively.The 3 bit MDAC amplifies a reconstructed residue signal byrather than to correct decision errors digitally in the DCL[15]. Two reference voltages for sub-ranging flash ADCs andMDACs are externally supplied in this version of the prototypeADC.

The proposed ADC employs a SHA-free input scheme toachieve not only low power consumption but also high SNRwith the same input capacitance by eliminating one of thethermal noise sources in the analog signal path. Since analoginputs are directly sampled in the first pipelined stage ratherthan a SHA, a sampling time mismatch between the MDAC1

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KIM et al.: CMOS NYQUIST A/D CONVERTER WITH A FULLY DIFFERENTIAL CLASS-AB SWITCHED OP-AMP 621

Fig. 1. Proposed ADC architecture with a SHA-free input network.

and flash ADC1 may produce a difference between sampledvoltages in each block, limiting the input signal bandwidth. TheSHA-free input sampling network proposed in Fig. 1 allowsa precisely matched input sampling for the MDAC1 and flashADC1 without any performance degradation at high frequency.The undesirable sampling time mismatch is minimized byusing a single bootstrapped clock ( ) for the switchesconnected to the input side of each capacitor in the MDAC1and flash ADC1. In addition, each flash ADC is based on thecapacitor-divided reference voltages instead of the conven-tional resistor ladder-based voltages. The latter can cause a gainerror in the ADC due to a voltage drop of references throughinterconnection line currents [16].

III. TOPOLOGY OF THE OP-AMP

A. Operations of Class-A and Class-AB Op-Amps

An op-amp is commonly the most power-hungry analogbuilding block in high-performance ADCs and the class-Aop-amps of folded-cascode and telescopic types have beenwidely employed with current switching or op-amp sharingtechniques to reduce power consumption [5]–[9]. The class-Aop-amp topologies consume constant currents during theslewing and settling periods. On the other hand, the class-ABop-amps show higher power efficiency than the class-Aop-amps, since the required currents can be optimized duringthe slewing period. The conceptual current flows of the class-Aand class-AB op-amps are described in Fig. 2.

In the case of the class-A type described in Fig. 2(a) and (b),output branches show a constant current flow of during theslewing and settling periods, since bias circuits always forcethe current sources to have a constant current. On the otherhand, in the class-AB type, one push or pull current source isconnected to a capacitive load and the other is turned off in

Fig. 2. Fully differential op-amp current flows: (a) Slew mode of the class-Atype, (b) settling mode of the class-A type, (c) slew mode of the class-AB type,and (d) settling mode of the class-AB type.

the slewing period as illustrated in Fig. 2(c). As a result, theclass-AB op-amp consumes only dynamic currents instead ofstatic currents during the slewing period. The dynamic currentsare changed into a small amount of quiescent currents during



Fig. 3. Rail-to-rail output stage with a floating class-AB control.

the next settling period as observed in Fig. 2(d). In the slewingperiod, if the dynamic currents of the class-AB op-amp are thesame as the static currents of the class-A op-amp, the slewingtime of the class-AB op-amp is twice as faster than that of theclass-A op-amp.

B. Rail-to-Rail Output Stage With a Floating Class-AB Control

For class-AB amplifiers, some extra class-AB control circuitssuch as a capacitive level shifter [10], [11], a cross-coupledpush-pull circuit [12], and a capacitance-coupling input stage[17] are essential to achieve the push-pull operation. However,the class-AB control schemes need additional chip area andpower dissipation. Especially in the capacitive level shifter, thesize of level shifting capacitors should be sufficiently larger thanthe gate capacitance of the class-AB output transistors to avoidthe overall DC gain reduction. In addition, the capacitance-cou-pling push-pull amplifier is sensitive to an input common-modevoltage shifting [17]. The proposed ADC employs the floatingclass-AB control topology as shown in Fig. 3 [18]. It consists ofcontrol transistors, M1 and M2, and output transistors, M3 andM4, which are directly driven by two in-phase signal currents,I3 and I4. Two current sources, I1 and I2, supply bias currents toM1 and M2. Two gate voltages of the class-AB control transis-tors, VB1 and VB2, are generated with diode-connected transis-tors. By maintaining a constant voltage difference between thegates of M3 and M4, the class-AB operation can be achieved.When the in-phase signal currents, I3 and I4, are pushed into theclass-AB output stage, the current of M1 increases while that ofM2 decreases by the same amount. Consequently, the gate volt-ages of both M3 and M4 move up and the output stage pullscurrents from the output node. This action continues until thecurrent through M1 is equal to I1, and then the current of M1is kept at a specific value, which can be set by the aspect ratioof M1 and M2 [13]. A similar discussion can be applied when

input signals are pulled from the class-AB output stage. Thisscheme also permits a rail-to-rail output swing by removing thecascoded current sources in the class-AB output branch.

C. Concept of the Proposed Fully Differential Class-ABOp-Amp

The power dissipation, chip area, and phase margin are af-fected by the amplifier topology, while the amplifier bandwidthis little related to the employed amplifier topology. In this work,two-stage amplifiers rather than single-stage amplifiers are em-ployed considering the required DC gain of 12 bit level, highenough output swing range of 2.4 Vpp, and high capacitanceloads of the following pipelined stage. The simplified designconcept of the proposed op-amp is described in Fig. 4. Thiscircuit is the extended one from the single-ended two-stageclass-AB op-amp in [13]. The proposed fully differentialop-amp employs a folded-cascode topology for the first stageand a class-AB amplifier for the second stage. Transistors,M15, M16, M17, and M18 are added for the floating class-ABcontrol. The overall DC gain of the proposed op-amp in Fig. 4is calculated as

(1)In (1), and are the trans-conductance of input transis-tors, M1 and M3, in the complementary input stage, andand are the output resistance seen at nodes, T2 and T4. Forexample, is the parallel resistance observed from the drainof M10, the source of M16, and the drain of M18. Likewise,

is the parallel resistance of the drain of M12, the drainof M16, and the source of M18. When the same common-modevoltage is applied to the inputs of the op-amp, and , allthe transistors operate in the saturation region and a static cur-rent at T2, flowing through pMOS transistor M16 and nMOStransistor M18, is evenly divided. When a little bit higher inputvoltage is applied to the and a little bit lower voltage isapplied to the , the node voltage at T2 is decreased by thecurrent variation. It decreases the current through M16 and in-creases the current through M18, resulting in a voltage decre-ment at T4. From the view point of a negative feedback config-uration, the voltages of and are almost the same, re-sulting in evenly divided currents through M16 and M18 regard-less of the op-amp output. Thus, the voltage difference betweenthe gates of output transistors, M20 and M22, is kept constant,while the floating node voltages of T2 and T4 are moved to-ward the same direction. For this reason, the source impedanceof M16 and the drain impedance of M18 are considered to bealmost infinite, leaving only the output impedance of M10 to bethe total output impedance. In summary, the output resistancesat T2 and T4 are simplified to (2) and (3), and the overall DCgain of the first stage amplifier with a floating class-AB controlcircuit shows the same DC gain as the conventional folded-cas-code topology.

(2)

(3)



Fig. 4. Concept of the proposed fully differential class-AB op-amp.

Fig. 5. Proposed fully differential class-AB switched op-amp.

IV. CIRCUIT IMPLEMENTATION

A. Fully Differential Two-Stage Op-Amp With a SwitchedClass-AB Output Stage

The proposed fully differential class-AB op-amp using aswitched op-amp technique, as shown in Fig. 5, is employed inall the MDACs to amplify a residue voltage in each pipelinedstage. The proposed op-amp consists of four functional circuit

blocks, which are complementary input stage, cascoded gainstage with a floating class-AB control circuit, switched-currentclass-AB output stage, and floating current source with a CMFBcircuit.

Although, the rail-to-rail input stage is not mandatory forthis work, the proposed ADC employs a complementary inputstage to conveniently implement the structure of Fig. 3. A majordrawback of the previously implemented class-AB op-amps



is that the quiescent currents of output transistors are severelyaffected by supply voltage variations due to finite outputimpedance of the output push-pull transistors. To overcome thesupply sensitivity of quiescent currents, the bias circuits for thecurrent sources of the class-AB op-amp should have the samesupply voltage dependency as the class-AB control. Thus, thefloating class-AB control nodes, T1 to T4, are controlled by thefloating current sources, which have the same circuit schemeas the floating class-AB control circuit. Additional transistors,M24 and M30, are added for a specific CMFB operation, whichwill be described in the following section in details.

On the other hand, capacitors, C1 to C4, are needed for thecascoded-Miller frequency compensation, which shows a lagerbandwidth than the Miller compensation [19]. Transistors,M31 to M38, are employed for the current switching of outputstages to reduce power consumption. During the samplingphase, these switches are turned off and both differential outputnodes, and , are set to an output common-modevoltage, VCOM. The gates of M19 and M20 are connected toT5 while the gates of M21 and M22 are connected to T6 toachieve a fast op-amp signal settling during the next amplifica-tion phase. At the next amplifying phase, switches are turned onto amplify a residue signal. During these on and off operations,a timing delay may happen between the control signals forpMOS and nMOS devices and can result in pedestal errors.The pedestal errors and the settling time of the amplifier can beminimized by aligning the control signals properly for pMOSand nMOS devices. Although there is a switching time delay,the timing mismatch commonly does not generate any problemsince the device unity gain frequency is much higher than theop-amp bandwidth itself. As a result, the proposed switchedop-amp technique minimizes the static currents consumed inthe output stages and reduces the power dissipation of the entireop-amp without degrading the total signal settling time.

B. Global-Loop CMFB Circuit

One of the most important blocks of a fully differentialop-amp is a CMFB circuit, and the maximum available swingrange of the op-amp is severely restricted due to signal distor-tion when the CMFB circuit does not properly work. In manyADCs, a fully differential multi-stage op-amp employs a dedi-cated CMFB circuit in each stage [2], [4], [6], [10], [12]. On theother hand, the proposed fully differential two-stage op-ampadopts a single CMFB circuit with a global feedback loop,since the output stage consists of push-pull transistors operatedby a floating class-AB control circuit. The proposed CMFBcircuit composed of common-mode control circuits, invertingamplifiers, and output common-mode voltage detection circuitsis illustrated in Fig. 6. In this global-loop CMFB circuit, theinversion of current direction is essentially required betweenthe common-mode voltage detection and control circuits for anegative feedback operation. When an output common-modevoltage stirs due to current mismatch, the voltages of theTC2 and TC4 nodes move in the same direction as the outputcommon-mode voltage with level-shifting operation. At thesame time, the voltages of the TC1 and TC3 nodes move inthe opposite direction to the output common-mode voltage.By connecting TC1 and TC3 to the upper and lower floating

Fig. 6. Proposed global-loop CMFB circuit.

current sources of the first-stage amplifier, the globally con-nected feedback loop adjusts the output common-mode voltageappropriately.

The detailed CMFB circuit is implemented in the fully dif-ferential class-AB op-amp of Fig. 5, where inverting ampli-fiers with a floating current source are inserted at the gates ofM7, M8, M13, and M14, for a negative feedback loop. The in-verting amplifiers employ two current sources, which consist ofM23-M24 and M29-M30. Dynamic feedback currents are gen-erated by M24 and M30, which gates are connected to the dy-namic CMFB blocks. Static currents are generated by M23 andM29, which operate as a floating current source.

C. Op-Amp Requirements for the MDAC Operation

The 2.5 bit MDACs in this work adopt the commutative feed-back capacitor switching technique to obtain a higher capacitormatching accuracy [20] by changing a feedback capacitor ac-cording to input levels. In addition, the proposed MDAC ampli-fies a residue voltage by rather than with the switched-ca-pacitor based closed-loop circuit containing the fully differen-tial class-AB op-amp to correct non-linear errors caused by theoffset voltages of the MDACs and the flash ADCs in the DCL.The proposed MDAC1 is shown in Fig. 7 where and aredefined as the sampling and feedback capacitors, respectively.

The transfer function of the 2.5 bit MDAC1 employing anop-amp with a finite open-loop DC gain of is derived as (4).The output of the MDAC1 is required to maintain more thana 10 bit accuracy for the overall 2.5 b/stage pipelined ADC toachieve a 12 bit resolution, as summarized in (5) and (6).

(4)

(5)

(6)

The exponent in (5) and (6) should be 10 and the requiredop-amp DC gain for the MDAC1 should be larger than 74.2 dB.



Fig. 7. Proposed MDAC1 scheme.

The DC gain variation of the proposed two-stage class-ABop-amp depending on output voltage swing ranges is simulatedand summarized in Fig. 8. The proposed op-amp maintains anoverall DC gain exceeding 74.2 dB up to an output swing rangeof 2.4 Vpp, which is a target in this work. Although the DCgain requirements of the amplifiers in the remaining pipelinedstages are gradually reduced, the proposed ADC employs thesame amplifier topology in each pipelined stage to verify thefunctionality of the proposed class-AB circuit. However, thesampling capacitor and bandwidth of the amplifier in each stageare scaled down to reduce power dissipation and chip area.The sampling capacitances in the first and second pipelinedstages are 960 fF and 360 fF, respectively, while the remainingpipelined stages employ a sampling capacitance of 240 fF con-sidering the thermal noise requirement and matching accuracy.Considering only the and amplifier thermal noise in theprototype ADC, the maximum achievable SNR is estimated tobe 78 dB. The simulated thermal noise at the MDAC1 output is55.8 uVrms and the effective input-referred noise is divided bythe closed-loop gain. It means that the total device noise sumresides within the targeted 12 bit-level quantization noise.

In two-stage amplifiers, the slew rate is generally determinedby the available driving current of the input-stage amplifier( ) and the compensation capacitor ( ). Even though theproposed amplifier employs a class-AB output stage, the firststage still uses a class-A topology. Thus, the maximum drivingcurrent of the first-stage amplifier is determined by its tailcurrent source. By considering the small-signal analysis andloop stability, the slew rate can be expressed with the availabledriving current of the input-stage amplifier ( ), the inputtransconductance ( ), and the second most dominant pole( ), as (7). To achieve a high slew rate, the current drivingcapability of the input-stage amplifier and the second polelocation need to be increased. In this work, the proposed 12 bitADC operates at a sampling rate of 50 MS/s and the calculatedslew rates of the proposed class-AB amplifier in the MDAC1 is

Fig. 8. Op-amp DC gain variation versus output swing range.

6.01 kV/us, which does not restrict the overall MDAC1 settlingtime at all, while the reduced static current of the class-ABoutput stage results in less power consumption. This calculatedslew rate can be improved with the cascoded compensationtechnique [13].

(7)

V. ADC IMPLEMETATION AND MEASUREMENTS

The prototype 12 bit 50 MS/s pipelined ADC is implementedin a 0.18 m single-poly six-metal CMOS process and con-sumes 10.2 mA at 50 MS/s with a 1.8 V power supply. Theactive die area of the ADC is 0.26 mm ( m m)as shown in Fig. 9 where the areas marked as a rectangle repre-sent the proposed class-AB op-amps employed in the MDACs.In typical high-resolution and high-speed pipelined ADCs, sam-pling capacitors and wideband op-amps occupy almost all ofthe chip area. However, as demonstrated in the proposed 12 bitADC of Fig. 9, the area of all the MDACs is similar to the areaoccupied by all the flash ADCs. When the signal swing rangeis increased with the noise power stayed the same, the SNR isincreased that much. It means that the area occupied by on-chipcapacitors and op-amps is reduced as much as the increasedvoltage swing range as long as the same SNR is maintained.As a result, the chip area of the prototype ADC can be substan-tially reduced by the proposed class-AB op-amp with little per-formance degradation.

The measured differential nonlinearity (DNL) and inte-gral nonlinearity (INL) in Fig. 10 are withinand , respectively, demonstrating a 12 bit lin-earity with an input swing range of 2.4 Vp-p. The measuredsignal-to-noise-and-distortion ratio (SNDR) and spurious-freedynamic range (SFDR) with the 16384-point FFT are 64.0 dBand 74.9 dB, respectively, at a sampling frequency of 50 MHzwith a 2.4 Vp-p input sinusoidal signal of 4 MHz, as shown inFig. 11. The measured FFT spectrum of Fig. 12 demonstratesthe SNDR and SFDR of 64.0 dB and 76.6 dB, respectively, withan input frequency of 31 MHz at a sampling rate of 50 MS/s.



Fig. 9. Die micrograph of the proposed 12 bit ADC.

Fig. 10. Measured DNL and INL.

Fig. 11. Measured FFT spectrum (�� MHz, �� MHz).

The proposed ADC properly processes input signals exceedingthe Nyquist frequency, based on the proposed SHA-free inputsampling network. The prototype ADC employing the pro-posed fully differential class-AB op-amp shows no abruptperformance degradation even though the sampling frequencyis increased to 100 MHz, twice a target sampling frequencyof 50 MHz, as shown in Fig. 13. The current consumptionof analog circuits in the prototype ADC is measured to be aconstant level of 4.4 mA up to 5 MS/s. The currents tend to be

Fig. 12. Measured FFT spectrum (�� MHz, �� MHz).

Fig. 13. Measured SNDR and SFDR versus sampling frequency.

Fig. 14. Current consumption of analog circuits versus sampling frequency.

gradually increased depending on a sampling clock frequencydue to the proposed class-AB amplifier operation, as illustratedin Fig. 14. The figure of merits (FoM), defined as (8), is 0.28pJ/conversion-step. The overall ADC performance is summa-rized in Table I and the recently reported 12 bit CMOS ADCsoperating above 40 MS/s are compared with the proposed ADCin Fig. 15.

(8)



Fig. 15. Performance comparison of recently reported 12 bit CMOS ADCsoperating above 40 MS/s.

TABLE IPERFORMANCE SUMMARY OF THE PROPOSED ADC

VI. CONCLUSION

This work proposes a 12 bit 50 MS/s CMOS Nyquist ADCbased on a fully differential class-AB switched op-amp for bat-tery-powered portable applications. The proposed ADC adoptsa 2.5 bit/stage pipelined architecture except the first stage witha 2 bit resolution to optimize chip area and power consumption.The proposed SHA-free input sampling network properly ma-nipulates high-swing wideband analog signals exceeding theNyquist frequency without serious timing errors or distortion.The prototype ADC implemented in a 0.18 m 1P6M CMOStechnology demonstrates a measured DNL and INL within

and , respectively. The prototype ADCshows a maximum SNDR and SFDR of 64.0 dB and 76.6 dB,respectively, a power consumption of 18.4 mW at 1.8 V and50 MS/s, and an active die area of 0.26 mm .

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Young-Ju Kim received the B.S. and M.S. degreesin electronic engineering from Sogang University,Seoul, Korea, in 2005 and 2007, where he is cur-rently pursuing the Ph.D. degree.

His current interests are in the design of high-res-olution low-power CMOS data converters and veryhigh-speed mixed-mode integrated systems. From2009 to 2010, he interned in the analog and mixedsignal development group at Broadcom Corporation,Irvine, CA.

Mr. Kim received the HumanTech Thesis ContestSilver Award from Samsung Electronics Corporation in 2007.



Hee-Cheol Choi was born in Seoul, Korea. He re-ceived the B.S., M.S., and Ph.D. degrees in electronicengineering from Sogang University, Seoul, Korea, in1994, 1996, and 2009.

From 1996 to 2006, he worked as a senior engi-neer at Samsung Electronics. He is currently a se-nior engineer with Aptina Korea. His work focusesmainly on sensor chip design and his current inter-ests are high-resolution low-power CMOS data con-verters and analog front-ends for video signal pro-cessing.

Gil-Cho Ahn received the B.S. and M.S. degreesin electronic engineering from Sogang University,Seoul, Korea, in 1994 and 1996, respectively, and thePh.D. degree in electrical engineering from OregonState University, Corvallis, in 2005.

From 1996 to 2001, he was a Design Engineer atSamsung Electronics, Kiheung, Korea, working onmixed analog and digital integrated circuits. From2005 to 2008, he was with Broadcom Corporation,Irvine, CA, working on mixed-mode interface cir-cuits design. Currently, he is an Assistant Professor

in the Department of Electronic Engineering, Sogang University. His researchinterests include high-speed, high-resolution data converters and low-voltage,low-power mixed-signal circuits design.

Seung-Hoon Lee received the B.S. and M.S. degreeswith honors in electronic engineering from Seoul Na-tional University, Seoul, Korea, in 1984 and 1986,respectively, and the Ph.D. degree in electrical andcomputer engineering from the University of Illinoisat Urbana-Champaign in 1991.

From 1990 to 1993, he was with Analog DevicesSemiconductor, Wilmington, MA, as a Senior DesignEngineer. Since 1993, he has been with the Depart-ment of Electronic Engineering, Sogang University,Seoul, Korea, where he is now a Professor. His cur-

rent research interest is in the design and testing of high-resolution high-speedCMOS data converters, CMOS communication circuits, integrated sensors, andmixed- mode integrated systems.

Dr. Lee has been serving as the chief editor of the IEEK Journal of Semicon-ductor Devices, Circuits, and Systems and a TPC member of many internationaland domestic conferences including the IEEE Symposium on VLSI Circuits.


Documents

620 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 3 ...eeic7.sogang.ac.kr/paper file/international journal/JSSC10_A 12 bit 50... · 622 IEEE JOURNAL OF SOLID-STATE CIRCUITS,