6-Bit Pipeline ADCPRESENTED BY: BHAWNA SHIWANI & ADITYA RAJ VERMA

ADC Architecture

Sampling Unit

Pre-Amplifier

Pre-Amp Phase-Gain plot

Pre-Amp Transient Response at 10KHz

Pre-Amp Transient Response at 100KHz

Sample & Hold

Charge Pump

Problem of Clock Feedthrough

Problem of Clock Feedthrough

Sample & Hold Transient Response

6-Bit Pipeline Quantizer

Unit Pipeline Circuit

Pipeline Unit Charateristics

DC Response of Quantizer

DC Response of Quantizer-Zoom In

Worst case Transient Response of QuantizerBit Transition 011111 [ 990mV ] to 100000 [ 1010mV ]

ADC Transient Response without output Latch

Transition Pattern 011111 -> 111111 -> 101111 -> ….. -> 100000

ADC Transient Response without output Latch

ADC Transient Response with output Latch

High Low Transition time mismatch of Latch

References

1. Understanding State of the Art in ADCs by Brad Brannon and Jon Hall, Analog Devices, Inc.

2. G.E. Moore, “Cramming more components onto integrated circuits,” Electronics, Vol. 38, No. 8, Apr. 1965.

3. G. E. Moore, “No exponential is forever: but “forever” can be delayed!,” IEEE ISSCC, Dig. Tech. Papers, San Francisco, CA, Feb. 2003, pp. 20–23.

4. Comparator-Based Switched-Capacitor Circuits for Scaled CMOS Technologies John K. Fiorenza, Student Member, IEEE, Todd Sepke, Student Member, IEEE, Peter Holloway, Charles G. Sodini, Fellow, IEEE, and Hae-SeungLee, Fellow, IEEE

5. Trends in high speed ADC design by Akira Matsuzawa, Department of Physical Electronics Tokyo Institute of Technology

6. “Pushing the State of the Art with Multichannel A/D Converters” By Rob Reeder, Mark Looney and Jim Hand