5.GB_SS42_E2_1 ZXG10 IBSC Structure and Principle (1G) 118

ZXG10 iBSC Structure and Principles

Course Objectives

After learning this course, you will: Understand the functions, features and specifications of ZXG1

0 iBSC Master the hardware structure of ZXG10 iBSC and the working

principles of its shelves and boards Master the interface design and logical units of ZXG10 iBSC Master signal streams on the control plane and the user plane

of ZXG10 iBSC Master the internal cable connections of ZXG10 iBSC

Contents

iBSC System Overview iBSC Hardware Structure iBSC Board Principles iBSC Interface Implementation and Logical Units Signal Flow on iBSC Control Plane and User Plane iBSC Internal Cable connection

SGSN GGSN

NodeB

RNC

NodeB

BTS

BSC

BTS

MSC/VLR GMSC

Inter-PLMN

PSTN

MGW GMGW

Gb

IuPs

IuCs

A

Mc

Nb

Nc

Iur-g

Network Structure

What does "i" stand for?

intelligentintelligent identification of wirelessaccess intelligent error self-correction

integrationintegrates multi-interfacesE1/STM-1/IP integrates multi transmission supported

immensitylarge capabilitysupports 3072 TRX and 15000 Erl with only two racks

intensifyintensified designsupports FR/EFR/HR/AMR/WB-AMR,innovative NetSpeed wireless enhanced technology

IPAll-IP platform

supports IP bearer

iBSC

Based on V3 universal hardware platform All IP hardware architecture Large capacity and strong processing capabilities Modular design with good scalar Separation of control streams from media streams Supporting Flex A and Flex Gb Coding scheme: FR/HR/EFR/FR-ARM/HR-AMR Transmission interface: E1/T1/FE/STM-1 Easy and smooth upgrade Flexible networking modes High integration and low power consumption

ZXG10 iBSC Product Features

Universal Hardware Platform

All IPAll IPSmoothUpgradeSmoothUpgrade

ModularityModularity

GSM / WCDMA

NGN

TD-SCDMA

CDMA 2000

Totally 16 boards

Universal All IP Hardware Platform

Modular Design

Boards Different software can be used to define diffe

rent functions for the same board. AIU, BIU, PCU and TCU are logical units; All

interface units are in the resource shelf.

RACK1

BCTC

BGSN

BPSN

BGSN

BGSN

BGSN

BGSN

BGSN

RACK2RACK1

BCTC

BGSN

BPSN

BGSN

Easy Scalability The system can be e

xpanded via adding RCBUs.

3 RCBUs/2 racks.

Multiple Access Modes and Smooth Evolution

iBSC supports multiple access modes E1/T1 STM-1 FE/GE

Evolution

BSC

BSC

RNC

RNC

RNC&BSC

RNC&BSC

RNC&BSC

RNC&BSC

BSC

BSC

BSC

iBSC iBSC iBSC

Advantages• Saves 20% space when 2G and 3G modules are integrated into the same site.• Shares cabinets, spare parts, transmission and OMM.• Saves power consumption• Saves engineering and network upgrade cost

Advantages• Saves 20% space when 2G and 3G modules are integrated into the same site.• Shares cabinets, spare parts, transmission and OMM.• Saves power consumption• Saves engineering and network upgrade cost

ZXG10 iBSC Interfaces

No.Logical Interfa

ceLink Object Interface Type

1. A MSC STM-1, E1, FE/GE

2. Gb SGSN E1, FE/GE

3. Abis BTS E1, STM-1, FE/GE

4. Ater iTC STM-1, E1

A-Interface E1(T1) A STM-1 A IP A

Abis Interface

CabinetNumber of

CarriersInterface Capa

city

Number of Carri

ersInterface Capacity

Number of Carriers

Interface Capacity

E1(T1) Abis

A Single Cabinet

1024Abis:208 E1(T1)

1024Abis:208 E1(T1)

1024Abis:208 E1(T1)

A:188E1(T1) A:4 pairs of STM-1 A:1 pair of GE

Dual Cabinets 3072Abis:624 E1(T1)

3072Abis:624 E1(T1)

3072Abis:624 E1(T1)

A:700E1(T1) A:11 pairs of STM-1 A:2 pairs of GE

STM_1 Abis

A Single Cabinet

1024

Abis:3 pairs of STM-1 1024

Abis:3 pairs of STM-11024



Dual Cabinets 3072

Abis:9 pairs of STM-1 1024




IP Abis

A Single Cabinet

1024Abis:1 pair of GE

1024Abis:1 pairs of GE

2048Abis:1 pair of GE


Dual Cabinets 3072

Abis :2 pairs of GE 3072

Abis:2 pairs of GE3072

Abis:2 pairs of GE


IPoE Abis (EIPI+DTB)

A Single Cabinet

1024Abis:160 E1(T1)

1024Abis:160 E1(T1)

1024Abis:160 E1(T1)


Dual Cabinets 3072Abis:480 E1(T1)

3072Abis:480 E1(T1)

3072Abis:480 E1(T1)


IPoE Abis (EIPI+SDTB2)

A Single Cabinet

\\

1024Abis:3 pairs of STM-1

1024Abis:3 pairs of STM-1

\ A:4 pairs of STM-1 A:1 pair of GE

Dual Cabinets \ \ 3072 11 pairs of STM-1 3072 A:2 pairs of GE

ZXG10 iBSC Interface Specifications

Item Specification

Dimensions (H*D*W) (mm) 2,000 * 800 * 600

Weight<270Kg(1 rack)<540Kg(2 rack)

Power Consumption

All E1:2,558W per rack, 6,368W/2 racksAll IP: 2,542W per rack, 3,808W/2 racks

Power Source Requirements -48V DC (-40V DC to -57V DC)

Operating Temperature

Long-term temperature: 0°C–40°C.

Short-term temperature: -5°C–45°C.

Operating Humidity:Long-term humidity: 20–90%.

Short-term humidity: 5%–95%.

ZXG10 iBSC Physical Specifications

The all-IP architecture conforms to the trend towards an IP-

based network

Large capacity and strong processing capabilities

Supports E1, T1, STM-1 and IP interfaces and flexible netw

orking modes

Item Specification

BHCA 4,200K

Maximum traffic 15000 Erl

Maximum throughput over Gb interface

E1 Gb: 256Mbps

IP Gb: 600Mbps

Maximum TRXs supportedOne Rack: 1,024

Two Rack: 3,072

ZXG10 iBSC Performance Specifications

Contents


Hardware Architecture Introduction Work Planes

Control Plane & User Plane

Major Interfaces Abis – IP over E1, E1, IP A – TDM (E1, STM-1), IP Gb – TDM (E1), IP (Ater)

Levels of Shelves Shelf Types Control shelf (BCTC), resource shelf (BGSN), switch shelf (BPS

N)

Boards

(BPSN)Switch Shelf

(BGSN)Resource Shelf

(BCTC)Control Shelf

(BGSN)Resource Shelf

Control Shelf (BCTC)

System control and management

Clock capture and distribution

Processing of control plane signaling

System operation and maintenance

Resource Shelf (BGSN)

System external access

Processing of universal services

Switch Shelf (BPSN)

Large-capacity IP switch platform on the user plane

ZXG10 iBSC Shelves

Shelf Board Full Name Functions

BCTC

UIMCUniversal Interface Module for Control plane

Level 2 switch of control plane signaling

CMP Control Main Processor Control and management of CS and PS services, processing of BSSAP and BSSGP protocols, and resource management of the system

CHUB Control HUB Switch and convergence of control plane signaling

OMP Operation Main Processor Operation and maintenance, system control, management and monitoring

SBCX X86 Single Board Computer O&M server

CLKG Clock Generation Clock generation and distribution

ICM Integrated Clock Module Clock generation and distribution (with GPS)

BPSNGLI Gigabit Line Interface Level 1 switch, interface with the resource shelf

PSN Packet Switch Network Provides bi-directional user plane data switch with a capacity of 40 Gbps on each direction

BGSN

SPB2 Signaling Processing Board Signaling processing, interface board (16 E1 lines for A/Gb, eight E1 lines for Abis)

GUIM Giga bit User Interface Module Level 2 switch between the control plane and the user plane, resource shelf management

GUP2 GSM Universal Processing Processing of user plane protocols, such as TC, PCU and RTP

DTB Digital Trunk Board Provides 32 E1/T1 trunk interfaces

SDTB2 Sonet Digital Trunk Board 2 Provides two STM-1 interfaces

GIPI GE IP Interface Provides four FE interfaces or one GE interfaces for Abis/A/Gb

EIPI E1 IP Interface provides E1 or T1 based IP connection

ZXG10 iBSC Boards

Physical Board

Logical Board Functions

GIPI

IPBBCompletes IP access over the Abis interface, and sever the control plane from the user plane

IPICompletes IP access over the A interface, and sever the control plane from the user plane (signaling from service)

IPGBCompletes IP access over the Gb interface, and sever the control plane from the user plane

GUP2

BIPB2Search 20 ms TRU frames according to the channels and form IP packetsFor IP access over the Abis interface, it also processes RTP.

AIPB It processes RTP and forms IP packets

UPPB2 User plane protocol processing in the PS field

DRTB2Completes the transcoding and rate adaptation of TRAU frames, and provides FR, EFR, AMR and TFO functions

SPB2

LAPD2 LAPD signaling processing

SPB2 MTP2 protocol processing

GIPB2Provides Gb interface functions, and processes the FR, NS and partial BSSGP of GPRS.

Physical and Logical Boards of ZXG10 iBSC

No. Board Name Number Slot No. Backup

1 OMP 2 11–12 1+1

2 CMP 2~4 1~4 1+1

3 CHUB 2 15~16 1+1

4 ICM 2 13~14 1+1

5 UIMC 2 9~10 1+1

6 SBCX 2 5， 7 1+1

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

Rear B

oard

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

Front

Board

Control Shelf

BCTC

CMP

CMP

CMP

CMP

SBCX

SBCX

RSVB

RSVB

UIMC

UIMC

RUIM2

RUIM3

OMP

OMP

RMPB

RMPB

ICM

ICM

RCKG1

RCKG2

RCHB1

RCHB2

CHUB

CHUB

Introduction to BCTC Completes the global operation

and maintenance of the system, provides the global system clock, manages the control plane, and responsible for the switch between the control plane and the Ethernet

Each iBSC must be configured with one control shelf, which is located in Shelf 2 in Rack 1

BCTC Working Principles The clock generation board (IC

M) distributes clock signals to the switch shelf and resource shelves through cables.

OMP and SBCX boards are connected to the iOMCR through the hub to sever intranet segments from Internet segments.

The CHUB acts as the control stream convergence center for the control streams from the switch shelf, the resource shelf and the control shelf.

CHUB

CMP

UIMC

OMP

ICM

BCTC

Outside network

UIMC

BPSN

GUIM

BGSN

8K/16M

Ethernet

HUB

SBCX

HUB


1 GUIM 2 9~10 1+1

2 GIPI - 1-8,11-17 1+13 GUP2 - 2-8,11-16 -4 DTB 0-8 1-8,11-14,17 -5 SDTB2 - 1-8,11-16 1+16 SPB2 - 1-8,11-17 -

7 EIPI - 1-8,11-17 -

RGUM1

RDTB

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

Rear B

oard

SPB2

GUIM

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

Front B

oard

Gigabit Resource Shelf

BGSN

DTB

GUIM

RGUM2

EIPI

GUP2

RSPB

GUP2

RSPB

RDTB

SPB2

SPB2

RSPB

GUP2

DTB

Introduction to BGSN Provides system external inter

faces. Processes universal services. Acts as the Level 2 switch cen

ter. The BGSN is configured in Sh

elf 1 and Shelf 3 of the main rack. When a single shelf constitutes an office, it is configured in Shelf 2.

BGSN Working Principles

The GUIM board is the convergence and switch center for various data in the resource shelf. It completes the information exchange between modules.

The GUIM board interconnects with the GLI board in the packet switch shelf to carry out level 1 switch between different resource shelves.

DTBs and SPBs provide E1 interfaces, and SDTBs provide STM-1 access.

GIPI boards provide FE and GE access.

Processes universal services (conversion from TC and TDM to IP packets, processing of user plane protocols).

GUIM

STM-1

BGSN

GLI

BPSN BCTC

ICMCHUB

E1 FE

SDTB2 DTB SPB2 GIPI

E1 GE

GUP2 GUP2

RUIM2

RUIM3

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

Rear B

oard

GLI

GLI

GLI

GLI

PSN

PSN

UIMC

UIMC

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

Front B

oard

Packet Switching Shelf

BPSN

GLI

GLI

CMP

CMP

CMP

CMP


1 PSN 2 7~8 Load sharing

2 GLI 2~6 1~6 Load sharing

3 CMP 0~2 11~14 1+1

4 UIMC 2 15~16 1+1

Introduction to BPSN Interconnects BGSNs and Lev

el 1 switch centers on the user plane.

Each iBSC should have one BPSN, which is configured in Shelf 4.

If the iBSC has two BGSNs, then the BPSN is not mandatory. However, this can affect the capacity expansion of the system.

BPSN Working Principles

The GLI board receives user plane data from the GUIM board.

The PSN provides 40Gbps data switch capacity.

The UIMC receives clock and control signals from the control shelf and distributes control & management interfaces and clock signals in the shelf.

PSN UIMC

GLI GLI

GUIM GUIM

CHUB

ICM

BPSN BCTC

BGSN BGSN

fiber

......

LVDS

FE

Shelf Configuration (1)

GUIM

GUIM

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

PWRD

FAN

FAN

FAN

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

PWRD

FAN

FAN

FAN

SPB

GUP

D

TB

D

TB

2 2

D

TB

GUP

D

TB

D

TB

2

GUP

SPB

2 2

D

TB

D

TB

GUIM

GUIM

D

TB

SPB

GUP

2 2

RSPB

GUP2

GUI

GUI

D

TB

D

TB M M

D

TB

D

TB

SPB

D

TB

2

GUP2

SPB2

RDT

RDT

B

B

RDT

RDT

B B

RDT

RDT

B B

RDTB

RSPB

RSPB

RDTB

RDTB

RSPB

RDT

RDT

B B

RDT

RDT

B B

RSP

RSP

B B

RSPB

D

TB

SPB2

SPB2

SPB2

GUP

GUP

2 2

D

TB

D

TB

GUP2

D

TB

D

TB

GUP2

D

TB

D

TB

GUP

GUP

2 2

D

TB

SPB2

D

TB

D

TB

GUIM

GUIM

D

TB

GUP

GUP

2 2

D

TB

D

TB

GUP2

D

TB

D

TB

GUP2

D

TB

D

TB

GUP

GUP

2 2

RDT

RSP

B B

RDTB

RDTB

RDTB

RDT

RDT

B B

RDTB

RDTB

RDTB

RDTB

RDTB

RDTB

RDTB

RDT

RDT

B B

RDTB

RDTB

RSPB

GUIM

GUIM

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

PWRD

FAN

GL

I

GL

I

GL

I

GL

I

FAN

FAN

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

PWRD

FAN

FAN

FAN

RUIM2

RUIM3

SPB

GUP

D

TB

D

TB

2 2

D

TB

GUP

D

TB

D

TB

2

SPB

DTB

DTB2

GUP

SPB

SPB

2 2 2

GIPI

/

SPB2

GIPI

/

C

MP

C

MP

C

MP

C

MP

UIMC

SBCX

SBCX

UI

MC

CHU

CHU

O

MP

O

MP B B

IC

IC

M M

SPB

GUP

2 2

RSP

GUP

B2

GUP2

GUI

GUI

D

TB

D

TB M M

D

TB

D

TB

GUP

D

TB

2

D

TB

D

TB

GUP

GUP

2 2

SPB2

GL

I

GL

I

PS

N

PS

N

CM

P

CM

P

UIM

UIM

C C

RUIM2

RUIM3

RSV

RDT

B

B

RDT

RDT

B B

RDT

RDT

B B

RDTB

RDT

RDT

B B

RSPB

RSVB

RMP

RMP

B B

RCKG1

RCKG2

RCHB1

RCHB2

RSPB

RDT

RDT

B B

RDT

RDT

B B

RSPB

RGER

/

RSPB

RGER

/

RDT

RDT

B B

RSP

RSP

B B

BIU

AIU

PCU

TCU

RGUM

RGUM

1 2

RGUM

RGUM

1 2

RGUM

RGUM

1 2

RGUM

RGUM

1 2

RGUM

RGUM

1 2

RGUM

RGUM

1 2

Abis Interface E1

A-Interface E1

Abis Interface IP

A-Interface IP

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

PWRD

FAN

FAN

FAN

RGER

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

PWRD

FAN

FAN

FAN

RGUM

RGUM

RUIM2

RUIM3

RGER

RUIM2

RUIM3

RSVB

RGER 1 2

RSVB

RMP

RMP

B B

RCKG1

RCKG2

RCHB1

RCHB2

RGER

RGUM

RGUM

1 2

RMI

RMI

N N

RGER

RGUM

RGUM

1 2

RGER

RGER

RGER

RGER

GUIM

GUIM

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

PWRD

FAN

FAN

FAN

GUIM

GUIM

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

PWRD

FAN

GL

I

GL

I

GL

I

GL

I

FAN

FAN

GIP

GIP

I I

GUP2

GUP

GUP

2 2

C

MP

C

MP

C

MP

C

MP

UIMC

SBCX

SBCX

UIMC

CHU

CHU

O

MP

O

MP B B

I

C

M

GIP

GIP

I I

GUP2

GIPI

GUI

GUI

M M

GUP2

GUP

GUP

2 2

PS

N

PS

N

CM

P

CM

P

UIM

UIM

C C

BIU

AIU

PCU

TCU

GUP

GUP

2 2

GUP2

GUP2

GIP

GIP

I I

GIPI

GUP2

GIP

GIP

I I

GUP2

GIP

GIP

I I

GUP2

GUP2

GUP2

GUP2

GUP2

C C

RGER

I

C

M

Cabinet Configuration (2)

Cabinet Configuration (3)

Abis Interface IPoE

A-Interface IP

GUIM

GUIM

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

PWRD

FAN

FAN

FAN

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

PWRD

FAN

FAN

FAN

GUP

SPB

22

GUIM

GUIM

SPB2

GUP2

RDTB

RDT

RDT

B B

RDTB

RSPB

RDT

RDT

B B

RDTB

RSPB

SPB2

SPB2

GUP2

SPB2

RSP

RSP

B B

RDTB

RSPB

GUIM

GUIM

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

PWRD

FAN

GLI

GL

I

GL

I

GL

I

FAN

FAN

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

PWRD

FAN

FAN

FAN

RUIM2

RUIM3

EIPI

D

TB

D

TB

D

TB

D

TB

D

TB

SPB2

SPB

GUP

GUP

2 2 2

GIPI

/

SPB2

GIPI

/

C

MP

C

MP

C

MP

C

MP

UIMC

SBCX

SBCX

UIMC

CHU

CHU

O

MP

O

MP B B

ICM

RGER

GUI

GUI

M M

GLI

GL

I

PSN

PS

N

CMP

CM

P

UIM

UIM

C C

RUIM2

RUIM3

RSV

RDT

B

B

RSVB

RMP

RMP

B B

RCKG1

RCKG2

RCHB1

RCHB2

RDT

RDT

B B

RDT

RDT

B B

RSPB

RGER

/

RSPB

RGER

/

RSPB

BIU

AIU

PCU

TCU

RGUM

RGUM

1 2

RGUM

RGUM

1 2

RGUM

RGUM

1 2

RGUM

RGUM

1 2

RGER

GIPI

GIPI

GIPI

GIPI

GUP2

GUP2

GUP2

GUP2

GUP2

GUP2

GUP2

GIPI

GIPI

RGER

RGER

RGER

RGER

EIPI

GUP2

GUP2

EIPI

D

TB

D

TB

D

TB

D

TB

D

TB

EIPI

GUP2

EIPI

D

TB

D

TB

D

TB

D

TB

D

TB

EIPI

GUP2

GUP2

GUP2

RDTB

RDTB

GUP2

ICM

Contents


OMP

The OMP board processes the global procedure, performs O&M related control of the entire system (including O&M proxy), and connects to the OMM through the 100M Ethernet.

As the processing core of iBSC operation & maintenance, the OMP board can directly or indirect monitor and manage all boards in the system. It provides two links (Ethernet interface and RS485) for configuration management of system boards.

OMP CPU A is responsible for global operation & maintenance. CPU B is the Router Processing Unit (RPU). The HD Disk is a 2G hard disk to store system data, for example,

board software version files, configuration files and logs.

What are the functions of the R

PU?

What are the functions of the R

PU?

1. Enables intranet addresses within the BSC to communicate with each other.2. Provides routes for the operation and maintenance of the BTS.

1. Enables intranet addresses within the BSC to communicate with each other.2. Provides routes for the operation and maintenance of the BTS.

RS485,RS232

Logic UnitPower

Management

RS232

CPU B

OMC2CPU Core

HD Disk

CPU A

CPU Core RS485

EthernetOMC1

RS232

RS485

DEBUG 2-232

GPS485

PD 485RS232

DEBUG1-232

CP FE

Ba

ck B

oa

rd

Ethernet

CP FE

RS485,RS232

CMP

The CMP board controls and manages service calls in the PS and CS fields, and manages the resources of BSSAP, BSSGP and the system.

Its physical board is MPx86/2, the same as the OMP, but the memory capacity is slightly different: 1GB/CPU for the OMP, and 2GB/CPU for the CMP, and the OMP has a hard disk).

UIMC

The UIMC is responsible for Ethernet Level 2 switch within the BCTC and the BPSN and the management of the BCTC.

The UIMC provides the clock drive function inside the BCTC and the BPSN. It inputs 8K and 16M signals, which are sent to different slots in the BGSN after phase lockup to provide 16M and 8K clocks for the boards.

The UIMC provides management interfaces for the BCTC and the BPSN; it also provides board resetting and resetting signal collection functions for the BCTC and the BPSN.

UIMC The UIMC provides one internal GE interface that is connected to the

CHUB.

DEBUG 232

DEBUG FE

Inner Bus

Logic Unit CPU

Ethernet Switch Unit

User Plane Switch

Control Plane Switch

CP FE 1~10

Clock Unit

CLKIN

RS

485

Inner Bus

Bac

k B

oard

CP FE, CP GE

CHUB

The CHUB works together with the UIMC/GUIM to be responsible for control plane data stream exchange and convergence in the system.

The control plane data from each shelf is sent to the Ethernet switching unit of CHUB board through the Ethernet cables on the control plane.

The data is then sent to UIMC board of the BCTC through GE for level-2 switch, and then distributed to each CMP board for processing.

CHUB The RCHB1 board has three FE buses, on which FE interfaces are grouped as F

E1–8, FE9–16 and FE17–24. The RCHB2 board has three FE buses, on which FE interfaces are grouped as F

E25–32, FE33–40 and FE41–46.

CPU

Inner Bus

Logic UnitDEBUG FE/232

CP GE

FE1

Ethernet Switch

Ethernet Switch


FE1 FE1 FEn

Bac

k B

oard

ICM Responsible for system clock supply and external synchron

ization. The board extracts clock reference via the A interface and drives multiple channels of clock reference signals for use by each interface unit.

It receives GPS satellite signals and extract 1PPS signals and related TOD messages. The 1PPS signals are used as reference for phase lockup in order to create PP2S,19.6608MHz and 8 K clock references for iBSC.

Supports background or manual selection of clock references, including BITS, line (8 K), GPS, local (Level 2 or Level 3); supports software shielding of manual switchover.

Supports four work modes: CATCH, TRACE, HOLD and FREE.

ICM 8 K reference input， when DTB/SDTB2 provides the clock reference, it con

nects with the 8KOUT/DEBUG-232 interface of RGIM1.When SPB2 provides the clock reference, it connects with the 8KOUT/CPU1-RS232 interface of RSPB.

One CLKOUT interfaces outputs a one-to-six cable; one shelf has two UIM/GUIM boards with two clock sockets, so one CLKOUT interface can connect with three shelves. The RCKG1 board has two CLKOUT interfaces providing six clock output lines, that is , it can connect with six shelves.

CLKOUT

Reference Selection Unit

CPU

8 K , 16 M, 32 M , 64 M

Oscillastor

RS232

GPS

2Mbps/2MHz

PP2S/16CHIP

GPS Unit

PLL Unit

8KIN

RS

485

Inner Bus

SBCX The SBCX board is the server board. It mounts the server o

n the rack. It provides the keyboard, the mouse and the VGA interface. Uses Sossaman dual-path dual-core CPU with a frequency

of 2G Hz. Supports multiple operating systems, including Windows XP

/2000/2003, Linux and Solaris. Provides three FE interfaces, two GE interfaces and one RS

232 serial port. Provides four universal USB interfaces. Supports boot from hard disk and boot from USB drive.

SBCX OMC1(eth3) is set to an external network address to communicate wit

h NetNumen M31 server. OMP1(eth6) is set to an intranet address to communicate with the OM

P.

OMC1

CPU

KeyBoard(KB)

VGA

SAS HD1

USB

SAS Controller

SAS

Dual Core

HD2

Outside Interface

Outside Interface

Mouse(MS)

OMC2

OMP1

RS232

USB

DTB

Provides 32 E1/T1 links for external connections. Supports extraction of 8K synchronization clock from the li

nes, which is transferred to the CLKG/ICM board through the cable as clock reference.

Supports 120/75 Ω impedance selection for E1 cables, and supports coaxial cables and twisted-pair cables.

Supports 100 Ω twisted-pair T1 cables.

DTB

CPU

Clock Unit

Bac

k B

oard

Interface Unit

CP FE ，RS232，RS485

Clock

Logic Unit

Circuit Switch Unit

HW

8KOUT/DEBUG-232

E1/T1 1~32

DTP DIP Switches

X23

ONS11

S10 ONS8 ON

ONS7

S2ON

ON

S4

S6

ON

ON

S12

S9ON

ON

S5

S3

ON

ON

S1

DTP DIP SwitchesDIP Switch

Purpose

Switch Configuration Default Location

Mode 1 2 3 4 1 2 3 4

S1~S6 S9 S12

Used to set the resistances that match the impedances of different E1 paths to 75 Ω or 120 Ω.

75 Ω ON ON ON ON

ON ON ON ON

120 Ω OFF OFF OFF OFF

S7 S8

Used for indicating the receiving matching impedance of corresponding E1 chip to the CPU.

75 Ω ON ON ON ON

ON ON ON ON

120 Ω OFF OFF OFF OFF

S10 S11

Used for reporting the long/short wire status of each E1 chip to the CPU.

SHORT HAUL

ON ON ON ON

ON ON ON ONLONG HAUL

OFF OFF OFF OFF

RDTP Jumpers On the RDTB, the E1 cable work

s in the 75 Ω unbalanced coaxial transmission mode by default.

If the E1 line uses 120 Ω balanced transmission mode, the short-circuit block at X9–X16 on the RDTB needs to be removed.

The sending end is grounded through the jumper. The receiving end is connected to a capacitor and then grounded through the jumper. Jumpers X9–X16 are used to complete such settings.

RDTP Jumpers

X9-X16 Pin Connection Definitions

1-2 Connect E1_TX（ N） -R to the protection ground (Path N)

3-4 Connect E1_RX（ N） -R to the protection ground (Path N)

5-6Connect E1_TX（ N+1） -R to the protection ground (Path N+1)

7-8Connect E1_RX（ N+1） -R to the protection ground (Path N+1)





SDTB2

The SDTB2 acts as the digital trunk interface board. It provides two 155M STM-1 standard interfaces.

Supports CAS and CCS, and provides an access processing capacity equal to 126 E1 lines or 168 T1 lines.

Outputs one path of differential 8 K synchronous clock signals for the reference of the clock board

SDTB2

CPU

Clock Unit

Ba

ck B

oard

Interface Unit

CP FE ，RS232，RS485

Clock

Logic Unit

Circuit Switch Unit

HW

8KOUT/DEBUG-232

STM-1

STM-1

SPB2 According to its functions, the SPB2 board can be classified into the L

APD processing board (LAPD2), the signaling processing board (SPB2) and the Gb interface processing board (GIPB2).

The LAPD2 board processes LAPD signaling. LAPD signaling data from the BTS are received by the DTB/SPB/SPB2 board, and then switched to the LAPD2 board through the circuit switching net on the UIM board in the local resource shelf or the GUIM board in the local Gigabit resource shelf. The LAPD2 completes the processing of LAPD signaling data.

The SPB2 board processes MTP2 and X.25 protocols. It supports extraction of 8 K synchronization clock from the lines, which is transferred to the CLKG board through the cable as clock reference.

The GIPB2 board processes the FR, NS and partial BSSGP protocols for the GPRS, and provides Gb interfaces.

SPB2

CPU 1

Clock Unit Bac

k B

oard

Interface Unit

CP FE

RS232，RS485

Clock

Logic Unit

Circuit Switch Unit

HW

8KOUT/CPU1-RS232

E1/T1 1~16

CPU 2

CPU 3

CPU 4


CPU2-RS232

CPU3-RS232

CPU4-RS232

UP FE

SPB2

Interface unit, which connects with the switching unit and provides E1 interfaces.

Circuit switch unit, which implements the switching between interface unit circuits and backplane circuits.

CPU, which implements signaling processing, board management and internal connection control.

Ethernet Switch Unit, which implements control plane and user plane data switch and provides FE interfaces.

Clock Unit, which extracts line clock signals and sends them to the ICM board.

Each SPB2 board contains four CPUs.

Each SPBs board provides 16 E1/T1 interfaces.

GIPI The GIPI board provides IP interfaces between iBSC and the

BTS, the SGSN and the MSC/MGW. Implements Layer 3 protocol interface processing, separates

control plane data from user plane data, and sends the data respectively to the Ethernet interfaces on the internal control plane and user plane.

According to functions, GIPI can be classified into four functional boards:Abis interface Gigabit IP interface board(IPBB)

A interface Gigabit IP interface board IPAB(Signaling)

A interface Gigabit IP interface board IPI （ signaling and service）Gb interface Gigabit IP interface board(IPGB)

GIPI

Processing Unit

Interface Unit

Logic Unit

Bac

k B

oard

GE1

CPU

CP FE, UP GE

RS232

GE2

DEBUG1-232

DEBUG2-232

The Interface Unit receives data and sends it to the service processing unit, which separates user plane data from control plane data. User plane data is then sent to the GUP2 through the user plane switch network, and control plane data is sent to the CMP through the control plane switch network.

The GIPI board can choose RGER (providing one GE interface) or RMINIC (providing four FE interfaces) as its rear board.

EIPI The EIPI board provides E1 or T1 based IP connection and

works together with the DTB. It has no external interface and no rear board. One EIPI works together with two DTBs to provide up to 64 E1 or T1 ports.

EIPI The interface unit receives HW data and sends it to the HPS daughter

card. The data is then processed according to the HDLC protocol and then sent to the service processing unit. It sends user plane data through the user plane switch network to the GUP2 for processing, and sends control plane data through the control plane switch network to the CMP for processing.

Processing Unit

Interface Unit

Logic Unit

Back

Boa

rd

CPU

CP FE, UP GE, HW

RS232

HPS SubcardHW

GUIM The GUIM performs Ethernet Level 2 switching between the control p

lane and the user plane in the Gigabit resource shelf, the CS field timeslot multiplexing slot switching and Gigabit resource shelf management. It also provides external interfaces for the Gigabit resource shelf.

It has the capability of 16 K circuit switching, and provides an internal circuit switching network for the GE resource shelf.

It provides the clock drive in the resource shelf. It inputsPP2S, 8K and 16M signals, which are sent to different slots in the resource shelf after phase lockup to provide 16M, 8 K and PP2S clocks for resource modules in this shelf.

The UGIM board performs Gigabit resource shelf management and provides RS485 management interfaces in the Gigabit resource shelf; It also provides board resetting and in-slot signal collection functions.

GUIM

DEBUG 232

Inner Bus

Logic Unit CPU


User Plane Switch

Control Plane Switch

Clock Unit

CLKIN

RS

485

Inner Bus

Bac

k B

oar

d

HW

Circuit Switch Unit

UP

GE 4*1 Gbps optical for UP

CP FE 1~6

CP

FE

GUP2

According to functions, GUP2 boards are classified into five functional boards: Abis interface processing board BIPB2, A interface processing board AIPB, user plane processing board UPPB2, dual rate transfer board DRTB2 and Ater interface processing board TIPB2.

Over the STM-1 or E1 Abis interface, CS and PS services from the BTS are switched to the BIPB2 board through the UIM board in the local resource shelf or the GUIM board in the local Gigabit resource shelf. The BIPB2 board searches 20ms TRU frames or PCU frames and form them into IP packets, which are sent to the TCU or the UPU for processing. Over the IP Abis interface, the BIPB2 board is also used to process RTP.

The DRTB2 implements code conversion, finishes TRAU frame conversion and rate adaptation, and provides FR/EFR/HR/AMR/TFO function.

The AIPB board processes RTP and forms data into IP packets over the A interface.

The UPPB2 processes user plane protocols such as BSSGP, PDCP and GTP_U under the A/Gb mode.

GUP2 Each GUP2 board has 15 DSPs.


DSP Unit

CPU PDSP

PDSP

Clock Unit

UP GE

CP FE

Logic Unit

…

Circuit Switch Unit

HW

Bac

k B

oard

GUP2 CPU: responsible for board management, and provides c

ontrol plane FE interfaces for external connection. DSP: processes universal services, including functions of

BIPB2, AIPB, DRTB2, UPPB2 and TIPB2. Circuit Switch Unit: connects the serial ports of multiple-c

hip DSP with the circuit switching network. Ethernet Switch Unit: implements the Ethernet connection

s for multiple-chip DSP and provides the user plane FE interface for external devices.

Clock Unit: provides necessary clock signals for the units on the board.

GLI The GB Line Interface (GLI) board is located at level 1 swi

tching subsystem of iBSC. It finishes physical layer adaptation, IP package query, segmentation, forwarding, and flow management functions, processes bi-directional 2.5Gbps forwarding, and implements the interfaces to different resource shelves and external interface functions.

GLI Interface Unit: provides GE optical interface and supports physical ba

ckup. SD1–SD2, SD3–SD4, SD5–SD6 and SD7–SD8 are backup groups.

Processing Unit: implements bi-directional IP packet table look-up, fragmenting, forwarding and traffic management.

Queue Management Unit: implements bi-directional queue management.

The GE optical interface receives user plane data from the GUIM and sends it through the backplane to the PSN board for user plane data exchange.

SD1~SD8 (GE Optical)Optical&Ethernet

Interface UnitProcessing Unit

Queue Management Unit

Logic Unit CPU

Bac

k B

oard

CP FE

PSN

Provides bi-directional user plane data switch with a capacity of 40 Gbps on each direction

The data from each GLI board is sent to the Matrix Switching Unit through the high-speed serial links on the backplane. It is switched and then sent to the destination GLI board.

LVD

S

Inner bus

Matrix Switch Unit

CP FECPU

Logic Unit

Ba

ck B

oar

d

Peripheral Monitor Unit (PMU)

Includes the PWRD board and the alarm box PWRD is responsible for collecting some peripheral and envir

onment board information within the cabinet, including the power distributor and fan status as well as some environment alarms like temperature/humidity, smog, water and infrared alarms. Each cabinet has one PWRD board.

The Alarm Box (ALB) can report system alarms at different levels according to system fault grades to facilitate timely interference and handling by equipment management personnel.

Board Summary 1

Board Summary 2

Board Summary 3

Control Plane and User Plane Interconnection

BGSN

UIMU(UIM_2)

BGSN

UIMU(UIM_2)

BCTC BPSN

GUIM

PSN

GLI

GUP2

CHUB

UIMC

CMP

OMP

SPB2 DTBSDTB2 GUP2

GLI

UIMC

User plane

Control plane

GUIM

User plane

Control plane

Abis/A /Gb

STM-1E1

iOMCR Client

Circuit Circuit

SBCX

HUB

GIPI

IP

Active/Standby Board Design

BCTC

BPSN

BGSN

GUIM (Main)

Control Plane

User Plane

GUIM (Standby)

Control Plane

User Plane

GLI/PSN

GLI/PSN

CHUB

CHUB

UIMC

UIMC

UIMC

UIMC

OMP/CMP (Standby)

OMP/CMP (Main)

Key boards have 1+1 backup. Key interface boards such as GIPI and SDTB can have 1+

1 backup if necessary. GLI and PSN boards work in the load sharing mode.

General Description of Boards

Front board and rear board Rear boards are passive boards that provides cabling fr

om the backplane (such as E1 and network cables) in order to work together with corresponding front boards.

Front boards are physical boards that process resources. All system optical cables are led from the front board panels.

All front boards have four indicators on their panels (RUN, ENUM, ACT, ALM) to indicate board status.

Indicators on Board Panels

Indicator Color Meaning Description

RUN GreenRunning indicator

Flashing at 1 Hz: the board is running normally

Flashing at 5 Hz: version downloading is in process.

ALM RedAlarm indicator

Flashing at 5 Hz: version download fails; board self test fails because of inconsistency between board and configuration

ENUM YellowBoard extraction indicator

Solid on: the microswitch is opened; the board is not in position; or version files are not downloaded.

Flashing at 5 Hz (quickly): the microswitch generates an alarm because it is opened when the board is still running.

Flashing at 1 Hz (slowly): the board can be extracted. The microswitch is opened when the board is running, and the board is in standby mode or release the resource.

Solid off: the microswitch is normal.

ACT GreenActive/standby status indicator

On: the board is active.

Off: the board is standby.

Contents


iBSC Logical View

Power and Fans

CMPU

O&M Unit

PMU

ZXG10 iBSC

BTS

MSC

SGSN

TC Unit

UPU

Access

Unit

Switch

Unit

iBSC External Physical Interfaces

DTB/SDTB2/GIPI SPB2/GIPI

DTB /SDTB2/GIPI DTB/SDTB2 SBCX GIPI

BTS iTC NetNumen OMCB MR

MSC/ MGW SGSN

Abis Ater

A Gb

iBSC

STM -

FE

E1

- 1

Access Unit–Abis Interface Unit (BIU)

E1 Abis E1 borne TDM link

IP Abis FE/GE borne IP link

IPoE Abis E1 borne IP link

BIU - E1 AbisThe interface board can be the DTB or SDTB2 board. The access capacity of SDTB2 is four times that of the DTB.

E1/ T1 HW

1

2

32

BIU

LAPD2

E 1 Abis

T

User Plane Switching Network

Control Plane Switching Network

InternalEthernet

to TCU or UPU

to CMP

DT

B

GU

P2

BIPB2

SP

B2

GU

IM

BIU - IP Abis

网

BIU

UPU

TCU

IP Abis



SCTP

UDP

to CMP

IPBB BIPB2

GIP

I

GU

P2 G

UP

2G

UP

2

HWInternalEthernet

ExternalEthernet

BIU - IPoE Abis

BIU

UPU

TCU

HWInternalEthernet

SCTPIP

to CMP

1

2

32

E1/T1

IPoE Abis

PPPHDLC

UDP

UDP



BIPB2

DT

B

EIP

I

ML/MC -PPP

RTPc UDP

RTPc UDP

GU

P2 G

UP

2G

UP

2

Access Unit- A Interface Unit (AIU)

E1 A E1 borne TDM link

IP A FE/GE borne IP link

AIU - E1 A

E1/ T1 HW

12

32

TCU

MTP2

1

2

16

AIU

STM -1


InternalEthernet

E 1 A

DT

BS

PB

2

GU

P2

User Plane Swi tching Network

GU

IM

AIU - IP A

AIU

AIPB

HWInternalEthernet

ExternalEthernet

SCTP

to CMP

BIPB2

UDP



IP A

IPI

GIP

I

GU

P2

RTPUDP

RTPUDP

GU

P2

Access Unit–Gb Interface Unit (GIU)

E1 Gb E1 borne TDM link

IP Gb FE/GE borne IP link

GIU - E1 Gb

E1/ T1

12

16

UPPB2

12

16

GIU


E 1 Gb

to CMP

UDP


SP

B2

GU

P2

Internal Ethernet

SP

B2

GIU - IP Gb


GIU

UPPB 2

UDP

to CMP

UDP

BIPB2

UDP

IP Gb


IPGB

GIP

I

GU

P2

GU

P2

HWInternalEthernet

ExternalEthernet

O&M Unit

OMP Board System operation and maintenance; Connects to the iOMCR; System management and monitoring

P

OMP

H

U

B

-R

100 M Ethernet

SVB

OMP

OMP

H

U

B

LMT

Sw

itchin

g U

nit

100 M Ethernet

SBCX

Operation and Maintenance Networking

The networking mode of SBCX is as follows: iBSC and SBCX(OMP1) form a subnetwork, and SBCX(OMC1)+NetNumen for a subnetwork. The local OMM usually consists of the SBCX and the SBCX client (LMT).Usually, LMT and the OMM client are installed on the same PC. The PC is then put in a different equipment room. The network interfaces of SBCX are connected to the switches of each iBSC, and then connected to the router. Then the cables are connected to the remote NetNument using WAN connection.

When the iBSC needs to manage SDR BTSs, the OMCB server manages all SDR configurations (physical, transmission and radio configurations), links, alarms and versions. The OMCB program is installed on the SBCX and a pair of GIPI boards must be configured.

Operation and Maintenance Networking

Processing Units & Monitoring Units

Processing Unit - CMPU CMP Board PS/CS Service Call and Control Management BSSAP, BSSGP and System Resource Management

Monitoring Unit - PMU PWRD board The PWRD board collects the environment monitoring i

nformation of peripheral devices, including temperature and humidity, smoke, water and infrared alarms.

UPU & TCU

Processing Unit – UPU UPPB2: Processes PS protocols

TransCoder Unit – TCU DRTB2: code transfer and rate adaptation

Level 1 switch: GLI and PSN, 40G large-capacity user plane data switch. Level 2 switch: UIMU,GUIM, UIMC, and CHUB, responsible for the switch an

d convergence of control plane and user plane data in the system.

IP Switch Unit (PSU)

2*GE

GE

1st Switch Subsystem 2nd Switch Subsystem

FE

BGSN 1 BGSN N

Switch Control

2nd Switch Subsystem 2nd Switch Subsystem

FE

If there are only two resource shelves, the Level-1 switch subsystem is not needed on the user plane. The two resource shelves can be directly interconnected using Gigabit optical interfaces.

IP Switch Unit (PSU)

FE

BGSN 1 BGSN 2

Control

2*GE

2nd Switch Subsystem

2nd Switch Subsystem 2nd Switch Subsystem

GE

FE

Contents

iBSC System Overview iBSC Hardware Structure iBSC Board Principles iBSC Interface Implementation and Logical Units Signal Flow on iBSC Control Plane and User Pla

ne iBSC Internal Cable connection

User Plane Signal Flow in the CS Domain

BIU

User plane switch network AIU

A Interface

GIU

CMP OMP

UPU TCU

1

2

Control plane switch network

Gb Interface

Abis Interface

The BIU severs user plane data from control plane data, and then sends user plane data to the TCU, which processes such data and then sends it to the AIU. Signal flow 1→2.

User Plane Signal Flow in the PS Domain The BIU severs CPU frames from all frames and sends them to th

e UPU(UPPB2) through the user plane switching network. The UPU then separates PS field user plane data from CPU frames received for further processing. After data processing is complete, the data is sent to the GUI through the user plane switching network.

BIU

User planeSwitching network AIU

GIU

1

CMP OMP

UPU TCU

2

Control planeSwitching network

A Interface

Gb Interface

Abis Interface

Control Plane Signal Flow in the CS Domain Abis interface signal flow Abis interface unit (BIU) sends signaling in the L

APD channel to the CMP board as control plane data. The CMP processes such data and sends some of it directly back to the BIU (flow direction: 1→1). Some signaling data will be sent to the AIU in the form of A-interface signaling flow (flow direction: 1→2).

A-interface signal flow: The AIU processes the MTP2 part of A-interface signaling, and then sends it to the CMP to complete the processing of MTP3 and layers above. Some global processes need the participation of the OMP. The data flow direction is 2→3→3→2 or 2→2.

BIU

AIU

GIU1

2

CMP OMP

3

UPU TCU

User planeSwitching network

A Interface

Gb Interface

Abis Interface


Control Plane Signal Flow in the PS Domain

BIU

AIU

GIU1

4

CMP OMP

6

UPU TCU

2

35

A Interface

Gb Interface

Abis Interface

User planeSwitching network


For some control plane signaling in the PS field, the system requests resources from the CMP board, and then sends the signaling to the UPPB2 for processing.

When the MS is processing PS services, control plane signaling should be separated from UPPB2 and then sent to the CMP for processing.


Abis interface signaling flow The Abis interface unit (BIU) sends control plane data in

the LAPD channel to the CMP board. The CMP processes such data and sends some of it directly back to the BIU (flow direction: 1→1). Some data, such as packet assignment messages, is sent to the UPU, which processes the data and then sends it to the BIU through the user plane switch network (flow direction: 1→3→2).

Data from the Abis interface unit is sent to the UPU through the user plane switch network. The UPU processes the data and separates control signaling packets, which are sent to the control plane processing board (CMP).The data flow direction is: 2→3→3→2.


Gb interface signaling flow The GIU sends BVC channel data as control plane data to the activ

e CMP. The CMP processes the data and sends some of it (such as PTP BVC restart) to other CMPs and some (such as signaling BVC restart) to the OMP. The CMP or the OMP processes the data and some signaling generates the Abis signaling traffic, such as paging messages in the PS or CS field, whose data flow is 5→1 or 5→3→2; other signaling, such as PTP BVC restart acknowledgement and signaling BVC restart acknowledgement, is sent to the Gb interface through the GUI, with the data flow as 5→5 or 6→6.

The GUI routes data from other BVC channels to the user plane processing unit, which separates control plane data and sends it to the CMP. The CMP processes the data and some signaling, such as PTP paging messages, is sent to the Gb interface through the GIU with the data flow as 4→3→5; some signaling generates the Abis signaling flow, such as location messages, with the data flow as 4→3→1.

User Plane Board Signal Flow in the CS Domain

BGSN

UIMU ( UIM _ 2)

BGSN

UIMU ( UIM _ 2)

BCTC BPSN

GUIM

GLI

BIPB2

CHUB

UIMC

CMP

OMP

LAPD2

GLI

UIMC

UP CP

GUIM

CP

E1 Abis

iOMCR Client

SBCX

HUB

SPB2 DTB

A

E1 A

Circuit

DTB

PSN

CircuitUP

DRTB2

E1 Abis, E1 A

The BIU severs user plane data from control plane data, and then sends user plane data to the TCU, which processes such data and then sends it to the AIU.

Signal flow 1→2.

Control Plane Board Signal Flow in the CS Domain

BGSN

UIMU ( UIM _ 2)

BGSN

UIMU ( UIM _ 2)

BCTC BPSN

GUIM

PSN

GLI

BIPB2

UIMC

CMP

OMP

DRTB2

GLI

UIMC

UP CP

GUIM

UP CP

iOMCR Client

Circuit

SBCX

HUB

SPB2 DTB

E1 Abis E1 A

CHUB

Circuit

LAPD2 DTB

E1 Abis, E1 A

The Abis interface unit (BIU) sends signaling in the LAPD channel to the CMP board as control plane data. The CMP processes such data and sends some of it generates the A interface signaling flow to the AIU.

Signal flow 1→2.

User Plane Board Signal Flow in the CS Domain

BGSN

UIMU ( UIM _ 2)

BGSN

UIMU ( UIM _ 2)

BCTC BPSN

GUIM

PSN

GLI

BIPB2

CHUB

UIMC

CMP

OMP

GLI

UIMC

UP CP

GUIM

UP CP

IP Abis

iOMCR Client

Circuit

SBCX

HUB

IP A

IPBB

Circuit

AIPB IPI

IP Abis, IP A

The BIU severs user plane data from control plane data, and then sends user plane data to the TCU, which processes such data and then sends it to the AIU.

Signal flow 1→2.

Control Plane Board Signal Flow in the CS Domain

BGSN

UIMU ( UIM _ 2)

BGSN

UIMU ( UIM _ 2)

BCTC BPSN

GUIM

PSN

GLI

BIPB2

CMP

OMP

AIPB

GLI

UIMC

UP CP

GUIM

UP CP

iOMCR Client

Circuit

SBCX

HUB

IPBB

Circuit

IPI

UIMC

CHUB

IP Abis IP A

IP Abis, IP A

The Abis interface unit (BIU) sends signaling in the LAPD channel to the CMP board as control plane data. The CMP processes such data and sends some of it generates the A interface signaling flow to the AIU.

Signal flow 1→2.

User Plane Board Signal Flow in the PS Domain

BGSN

UIMU ( UIM _ 2)

BGSN

UIMU ( UIM _ 2)

BCTC BPSN

GUIM

PSN

GLI

BIPB2

CHUB

UIMC

CMP

OMP

LAPD2 UPPB2

GLI

UIMC

UP CP

GUIM

UP CP

E1 Abis

iOMCR Client

Circuit

SBCX

HUB

E1 Gb

Circuit

DTB GIPB2

E1 Abis, E1 Gb

The BIU severs CPU frames from all frames and sends them to the UPU(UPPB) through the user plane switching network. The UPU then separates PS field user plane data from CPU frames received for further processing. After data processing is complete, the data is sent to the GUI through the user plane switching network.

Signal flow 1→2.

Control Plane Board Signal Flow in the PS Domain

BGSN

UIMU ( UIM _ 2)

BGSN

UIMU ( UIM _ 2)

BCTC BPSN

GUIM

PSN

GLI

BIPB2

CMP

OMP

GLI

UIMC

UP CP

GUIM

UP CP

iOMCR Client

Circuit

SBCX

HUB

GIPB2

E1 Abis E1 Gb

UIMC

CHUB

Circuit

LAPD2 DTB UPPB2

E1 Abis, E1 Gb

The Abis interface unit (BIU) sends control plane data in the LAPD channel to the CMP board. The CMP processes such data and sends some of it to the UPU (such as packet assignment message). The UPU processes such data and then sends it to the BIU through the user plane switch network.

Signal flow 1→3→2.


BGSN

UIMU ( UIM _ 2)

BGSN

UIMU ( UIM _ 2)

BCTC BPSN

GUIM

PSN

GLI

BIPB2

CMP

OMP

LAPD2

GLI

UIMC

UP CP

GUIM

UP

iOMCR Client

Circuit

SBCX

HUB

E1 Abis E1 Gb

UIMC

CHUB

CPCircuit

DTB UPPB2 GIPB2

E1 Abis， E1 Gb

The GIU sends BVC channel data as control plane data to the main CMP. The CMP processes the data and some signaling generates the Abis signaling flow, such as paging messages in the CS field


User Plane Board Signal Flow in the PS Domain

BGSN

UIMU ( UIM _ 2)

BGSN

UIMU ( UIM _ 2)

BCTC BPSN

GUIM

PSN

GLI

BIPB2

CHUB

UIMC

CMP

OMP

GLI

UIMC

UP CP

GUIM

UP CP

IP Abis

iOMCR Client

Circuit

SBCX

HUB

IP Gb

IPBB

Circuit

IPGBUPPB2

IP Abis, IP Gb

The BIU severs CPU frames from all frames and sends them to the UPU(UPPB) through the user plane switching network. The UPU then separates PS field user plane data from CPU frames received for further processing. After data processing is complete, the data is sent to the GUI through the user plane switching network.

Signal flow 1→2.


BGSN

UIMU ( UIM _ 2)

BGSN

UIMU ( UIM _ 2)

BCTC BPSN

GUIM

PSN

GLI CHUB CMP

OMP

GLI

UIMC

UP CP

GUIM

UP CP

iOMCR Client

Circuit

SBCX

HUB

IPBB

Circuit

IPGB

UIMC

UPPB2BIPB2

IP Abis IP Gb

IP Abis, IP Gb

The Abis interface unit (BIU) sends control plane data in the LAPD channel to the CMP board. The CMP processes such data and sends some of it to the UPU (such as packet assignment message). The UPU processes such data and then sends it to the BIU through the user plane switch network.



BGSN

UIMU ( UIM _ 2)UIMU ( UIM _ 2)

BCTC BPSN

GUIM

PSN

GLI CMP

OMP

GLI

UIMC

UP CP

GUIM

UP

iOMCR Client

Circuit

SBCX

HUB

Circuit

IPGBUPPB2

IP Abis IP Gb

CP

UIMC

BIPB2 IPBB

BGSN

CHUB

IP Abis, IP Gb

The GIU sends BVC channel data as control plane data to the main CMP. The CMP processes the data and some signaling generates the Abis signaling flow, such as paging messages in the PS or CS field


IP over E1 Signal Flow

IPoE User Plane Signal Flow IPoE Control Plane Signal Flow

BGSN

UIMU ( UIM _ 2)GUIM

BIPB2

UP CP

IPoE Abis

Circuit

DTBEUIP

BGSN

UIMU ( UIM _ 2)GUIM

BIPB2

UP CP

IPoE Abis

Circuit

DTBEUIP

Contents


PWRD

CLKG

SPB

MNIC

DTB

VTCD

SDTB

GUI

M

CMP

OMC-R

RS485 Ethernet

CHUB

GLI

PSN

UI

MC

OMP

System Interconnection Modes Most boards are managed by the OMP via the internal control plane. The CLKG/ICM board are connected to the UIMC via the RS485 bus, and

then managed by the OMP. The PWRD board is directly managed by the OMP via the RS485 bus.

BPSN BCTC in 1# Rack

CLKG

BGSN1

GUIM

BGSN2

GUIM

User Plane Ethernet

Circuit Switch Shelf

PWRD in Each Rack

485 Signal

GLI UIMC CHUB CLKG

UIMC OMP

Control Plane

Ethernet

User Plane

Ethernet

UIMC

Internal Communications Management

System Clock Capture and Distribution Principles The CLK board is responsible for

supplying clock signals and external synchronization functions.

Clock level: Level 3 clock The board extracts clock referenc

e via A Iu interface and drives multiple channels of timing reference signals for use by each interface shelf after intra-board synchronization.

Level 2 forwarding of the UIM board

DTB, SDTB2 and SPB2 can be used to extract line reference

The BPSN does not need a clock reference

BGSN

BCTC

ICM/CLKG

GUIM

DTB

8K，16MDifferential signals

BITS interface，Line 8K reference GPS reference

BPSN

UIMC

GLI GLI

8K，16MDifferential signals

E1 STM-1

SDTB2

8K referenceDifferential signals

SPB2

Intra-shelf Cable Connection

Clock extraction and distribution cables; Control plane and Ethernet interconnection cables; User plane optical cable connection; Monitoring cable.

Clock Extraction and Distribution Cables

UIMC

OMP

ICM

CHUB

Power distribution subrack

BGSN

BGSN

BCTC

BPSN

Fan subrack

GUI

M

GUI

M

UI

MC

The clock extraction cable connects the 8KOUT interface on the DTB rear board to the 8KIN interface on the ICM.

The ICM can also extract GPS signals as the clock reference.

The clock distribution cables connect the CLKOUT interface on the ICM rear board to the CLKIN interfaces on UIM boards in each shelf.

Control Plane and Ethernet Interconnection Cables

GUIM

UIMC

OMP

ICM

CHUB

GUIM

UIMC


Fan subrack

BGSN

BGSN

BCTC

BPSN

The FE interfaces of the CHUB rear boards connect to the FE interfaces of the UIM boards in each shelf.

Internal GE connection is used inside the BCTC.

User Plane Optical Cable Connection

GUI

M

UI

MC

OMP

ICM

CHUB

GUI

M

UI

MC

GLI


Fan subrack

BGSN

BGSN

BCTC

BPSN

The optical interface on the GUIM front panel in the BGSN connects to the optical interface on the PLI front panel.

Supports physical backup.

Monitoring CablesSensor

GUI

M

UI

MC

OMP

ICM

CHUB

GUI

M

UI

MC

GLI

Cabinet-top fan


Fan subrack

Fan subrack

Fan subrack

BGSN

BGSN

BCTC

BPSN

The cables between fans to PWRD boards are usually 120 ohm twisted-pair cables that are connected to the FANBOX interfaces to monitor fan running status.

The environment monitoring sensor is connected to the SENSORS interface on the PWRD board to collect environment alarms.

The door access sensor is connected to the DOOR interface on the PWRD board to monitor door access status.

The PWRD board reports monitoring information to the OMP board via RS485 cables.

Documents

5.GB_SS42_E2_1 ZXG10 IBSC Structure and Principle (1G) 118