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x. y. Carry-in. c. Sum. s. Carry-out. c. i. i. i. i. i. +1. 0. 0. 0. 0. 0. 0. 0. 1. 1. 0. 0. 1. 0. 1. 0. 0. 1. 1. 0. 1. 1. 0. 0. 1. 0. 1. 0. 1. 0. 1. 1. 1. 0. 0. 1. 1. 1. 1. 1. 1. x. y. c. +. x. y. c. +. x. y. c. +. x. y. c. s. - PowerPoint PPT Presentation
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si =ci +1 =
Figure 6.1. Logic specification for a stage of binary addition.
13
7+ Y
1
00010
1
1
00110
11
0
01101001
0
0
0
0
1
1
1
1
00001111
Example:
10= = 0
01 1
11 1 0 0
1
1 1 10
Legend for stage i
xi yi Carry-in ci Sum s i Carry-out ci+1
X
Z
+ 6 0+xiyisi
Carry-outci+1
Carry-inci
xiyicixiyicixiyicixiyici x i yi ci =+ + +
yicixicixiyi+ +
Please see “portrait orientation” PowerPoint file for Chapter 6
Figure 6.2. Logic for addition of binary vectors.
Add/Subcontrol
n-bit adder
x n 1- x1 x 0
cn
sn 1- s1 s0
c0
y n 1- y 1 y0
Figure 6.3. Binary addition-subtraction logic network.
Please see “portrait orientation” PowerPoint file for Chapter 6
Figure 6.4. 4-bit carry-lookahead adder.
Figure 6.5. 16-bit carry-lookahead adder built from 4-bit adders (see Figure 6.4b).
Carry-lookahead logic
4-bit adder 4-bit adder 4-bit adder 4-bit adder
s15-12
P3IG3
I
c12
P2IG2
I
c8
s11-8
G1I
c4
P1I
s7-4
G0I
c0
P0I
s3-0
c16
x15-12 y15-12 x11-8 y11-8 x7-4 y7-4 x3-0 y3-0
.
G0II P0
II
Please see “portrait orientation” PowerPoint file for Chapter 6
Figure 6.6. Array multiplication of positive binary operands.
Please see “portrait orientation” PowerPoint file for Chapter 6
Figure 6.7. Sequential circuit binary multiplier.
Figure 6.8. Sign extension of negative multiplicand.
1
0
11 11 1 1 0 0 1 1
110
110
1
0
1000111011
000000
1100111
00000000
110011111
13-
143-
11+( )
Sign extension isshown in blue
Figure 6.9. Normal and Booth multiplication schemes.
0
1
0
0 0
1 0 1 1 0 1
0
0 0 0 0 0 01
00110101011010
10110101011010
0000000000000
011000101010
0 1 0 1 1 1
0000
00000000000000
0
00
1 1 1 1 1 1 1 0 1 0 0 100
0
0 0 0 1 0 1 1 0 10 0 0 0 0 0 0 0
0110001001000 1
2's complement ofthe multiplicand
0
0
00
1+ 1-
1+ 1+ 1+ 1+
00
0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 00 0 0 0 0 0 0
Figure 6.10. Booth recoding of a multiplier.
001101011100110100
00000000 1+ 1-1-1+1-1+1-1+1-1+
Figure 6.11. Booth multiplication with a negative multiplier.
010
1 1 1 1 0 1 10 0 0 0 0 0 0 0 0
000110
0 0 0 0 1 1 01100111
0 0 0 0 0 0
01000 11111
1
10 1 1 0 11 1 0 1 0 6-
13+( )
78-
+11- 1-
Multiplier
Biti Biti 1-
Version of multiplicandselected by bit i
0
1
0
0
01
1 1
0 M
1+ M
1 M
0 M
Figure 6.12. Booth multiplier recoding table.
Figure 6.13. Booth recoded multipliers.
1
0
1110000111110000
001111011010001
1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
0
000000000000
00000000
1- 1- 1- 1- 1- 1- 1- 1-
1- 1- 1- 1-
1-1-
1+ 1+ 1+ 1+ 1+ 1+ 1+ 1+
1+
1+1+1+
1+
Worst-casemultiplier
Ordinarymultiplier
Goodmultiplier
Please see “portrait orientation” PowerPoint file for Chapter 6
Figure 6.14. Multiplier bit-pair recoding.
Please see “portrait orientation” PowerPoint file for Chapter 6
Figure 6.15. Multiplication requiring only n/2 summands.
FA FA FAFA
FA FA FAFA
FA FA FAFA
p7 p6 p5 p4 p3 p1 p0p2
0 m3q0
m3q1
(a) Ripple-carry array (Figure 6.6 structure)
m2q1
m2q0 m1q0
m1q1 m0q1
m3q2 m2q2 m1q2 m0q2
m3q3 m2q3 m1q3 m0q3
0
0
0
m0q0
FA FA FAFA
FA FA FAFA
FA FA FAFA
p7 p6 p5 p4 p3 p1 p0p2
0 m3q0
m3q1
(b) Carry-save array
m2q1
m2q0 m1q0
m1q1 m0q1
m2q3 m1q3 m0q3 0
0
0
m2q2 m1q2 m0q2m3q2
m3q3
m0q0
Figure 6.16. Ripple-carry and carry-save arrays for the
multiplication operation M x Q = P for 4-bit operands.Figure 6.16. Ripple-carry and carry-save arrays for the multiplication operation M Q = P for 4-bit operands.
Figure 6.17. A multiplication example used to illustrate carry-save addition as shown in Figure 6.18.
100 1 11
100 1 11
100 1 11
11111 1
100 1 11 M
Q
A
B
C
D
E
F
(2,835)
X
(45)
(63)
100 1 11
100 1 11
100 1 11
000 1 11 111 0 00 Product
Please see “portrait orientation” PowerPoint file for Chapter 6
Figure 6.18. The multiplication example from Figure 6.17 performed using carry-save addition.
Figure 6.19. Schematic representation of the carry-save
C2
ABE D CF
addition operations in Figure 6.18.
Level 1 CSA
S2 C1 S1
C2 C3 S3
C4 S4
+Product
Level 2 CSA
Level 3 CSA
Final addition
Figure 6.19. Schematic representation of the carry-save addition operations in Figure 6.18.
Figure 6.20. Longhand division examples.
1101
1
1314
26
21
274 100010010
10101
1101
1
11101101
10000
13 1101
qn 1-
mn 1-
-bit
Divisor M
Controlsequencer
Dividend Q
Shift left
adder
an 1- a0 q0
m0
a n
0
Add/Subtract
Quotientsetting
n 1+
Figure 6.21. Circuit arrangement for binary division.
A
Please see “portrait orientation” PowerPoint file for Chapter 6
Figure 6.22. A restoring-division example.
Please see “portrait orientation” PowerPoint file for Chapter 6
Figure 6.23. A nonrestoring-division example.
Please see “portrait orientation” PowerPoint file for Chapter 6
Figure 6.24. IEEE standard floating-point formats.
0 1 1 00 1 0 0 0 0 1 0 1
(a) Unnormalized value
(b) Normalized version
0 1 0 0 0 1 0 0 0 0 0 1 0 1 1 0 ...
(There is no implicit 1 to the left of the binary point.)
Value represented 0.0010110 29+=
...
Value represented 1.0110 26+=
Figure 6.25. Floating-point normalization in IEEE single-precision format.
excess-127 exponent
Please see “portrait orientation” PowerPoint file for Chapter 6
Figure 6.26. Floating-point addition-subtraction unit.
Representation Examples
Sign and magnitude
9' s complement
10' s complement
0526
0526
9473
9474
0070
0070
9929
9930
Figure P6.1. Signed numbers in base 10 used in Problem 6.3.
+526 526 +70 70
12 bits
5 bitsexcess-15exponent
6 bitsfractionalmantissa
1 bit for sign of number
Figure P6.2. Floating-point format used in Problem 6.25.
+0 signifies-1 signifies
Figure P6.3. 1's-complement addition used in Problem 6.36.
(3) 101
00 0
01 1 0 0
1
1 1 10
+ ( + 0
0
1 1 10
3
(6) 101
00 1
11 0 0 0
0
0 0 01
+ ( + 1
1
0 0 11
5- )
2-
3- )