5558 IEEE SENSORS JOURNAL, VOL. 17, NO. 17, SEPTEMBER 1, …analog.snu.ac.kr/publications/copy_of__ASCInterfacewith... · 2017-12-06 · 5558 IEEE SENSORS JOURNAL, VOL. 17, NO. 17,

5558 IEEE SENSORS JOURNAL, VOL. 17, NO. 17, SEPTEMBER 1, 2017

An SC Interface With Programmable-GainEmbedded �� ADC for MonolithicThree-Axis 3-D Stacked Capacitive

MEMS AccelerometerJaehoon Jun, Student Member, IEEE, Cyuyeol Rhee, Student Member, IEEE,

Sangwoo Kim, and Suhwan Kim, Senior Member, IEEE

Abstract— This paper presents a switched capacitor interfacecircuit for a monolithic three-axis capacitive micro-electro-mechanical system (MEMS) accelerometer. The MEMS sensorand the interface circuit of our system-in-package-type MEMSaccelerometer are 3-D stacked to optimize integration densitywith a small package footprint. The proposed fully integratedinterface circuit includes a capacitance-to-voltage converter fol-lowed by a �� analog-to-digital converter (ADC). To optimizesystem power and area, the programmable-gain functionality isembedded to the second-order �� ADC without any stabilitydegradation. The offset and 1/ f noise of the fully differentialinterface circuit are mitigated by a correlated double samplingtechnique. The rest of the low-frequency error from systemmismatch is also suppressed by calibration using fine metal–oxide–semiconductor capacitor array. The measurement resultsof our MEMS accelerometer show a 13.7-b maximum effectiveresolution with the 197-μg/

√Hz noise floor in a conversion time

of 1 ms with a maximum nonlinearity of 1.09%. Implementedin a standard 0.18-μm CMOS technology, the fabricated chipconsumes only 247-μA current from a 3.3-V supply, and 37-μAcurrent from a 1.8-V supply.

Index Terms— 3-Axis acceleration sensing system, interfacecircuit, delta-sigma ADC, MEMS, �� modulators,programmable-gain ADC (PGADC).

I. INTRODUCTION

ACCELROMETERS are now common in mobile devicessuch as cellular phones and tablet PCs [1]. The internet

of things (IoT) has also increased the demand for high-sensitive and low price accelerometers. Nowadays, automotiveapplications, vibration monitoring system, military applica-tions, and other GPS-assisted operating systems require moreaccurate accelerometer. Low-cost micro-electro-mechanicalsystem (MEMS) accelerometers have the merit of satisfyingthese requirements with its easy integration characteristicwith semi-conductor based interface circuits. The capacitive

Manuscript received May 31, 2017; revised July 5, 2017; acceptedJuly 5, 2017. Date of publication July 11, 2017; date of current versionAugust 9, 2017. The associate editor coordinating the review of this paper andapproving it for publication was Dr. Arindam Basu. (Corresponding author:Suhwan Kim.)

J. Jun, C. Rhee, and S. Kim are with the Inter-University SemiconductorResearch Center, Department of Electrical and Computer Engineering,Seoul National University, Seoul 08826, South Korea (e-mail:[email protected]; [email protected]; [email protected]).

S. Kim is with Crepas Technologies, Seoul 08826, South Korea (e-mail:[email protected]).

Digital Object Identifier 10.1109/JSEN.2017.2725486

MEMS accelerometer with a CMOS interface circuit has manyadvantages compared to previous classical accelerometers withdifferent types [2]–[4]. The MEMS sensors have the merit ofsubminiature size, low price with mass production, and highreliability.

Fig. 1 shows the simplified structure of a typical capacitiveMEMS accelerometer sensor. The MEMS sensor is composedof an electrically conductive proof mass, fixed electrodes,springs, and dampers. The proof mass is suspended on thespring, and the external acceleration can move the proof massfrom the balanced steady state. The deviated location of theproof mass from the nominal location generates an unbalanceddistance from the mass to differential fixed electrodes, whichleads to differential capacitive variation (±�CS).

An interface circuit is one of the critical componentsfor capacitive MEMS accelerometer. It is used for measur-ing the imbalance of the differential capacitive half-bridgeand digitizing with minimum data loss for post-processing.Recently, there exist various approach to read out the sensor’soutput precisely using discrete components or highly-complexcircuits [5], [6]. However, discrete components on a printedcircuit board (PCB) are clearly undesirable, and complicatedICs require extra electrodes and a large chip area [4], [7]–[12].

A demand for better performance of interface circuitsin a smaller size is being increased along with theadvance of semiconductor lithography and MEMS technology.However, the amplitude of sensor’s output is very small ingeneral [13], [14]; typically, it is less than a few femto-farads for capacitive MEMS structure. The low sensitivityof a MEMS makes the following interface circuit difficultto achieve a high resolution with low power consumption.The additional gain stage with programmable gain controlfunction has previously been applied to various sensing appli-cation systems [15]–[17]. However, the programmable-gainamplifier (PGA) needs to have low noise characteristic tomaintain the performance of the digitization stage. Thus,the gain amplification block typically consumes more energythan following blocks, which results in poorly optimizedsensing system in aspects of power consumption and chiparea. A recent implementation proposes a programmable-gain analog-to-digital converter (PGADC) to alleviate thechallenges mentioned above [18]. However, the PGADC ofthe previous work consists of a first-order closed-loop, and

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JUN et al.: SC INTERFACE WITH PROGRAMMABLE-GAIN EMBEDDED +�� ADC 5559

Fig. 1. (a) Simplified structure of a capacitive MEMS sensor, and (b) its equivalent model.

it achieves only 7.60-bit effective resolution (ER), which isnot sufficient for precise sensor applications. In the caseof implementing multi-pole closed-loop systems for highresolution, the loop stability cannot be maintained in theprocess of coefficient modification. The proposed interfacecircuit includes a power-efficient second-order �� PGADCemployed with a switched-capacitor topology. The proposedPGADC is a stable architecture incorporating the functionalityof a PGA into an ADC. The programmable-gain embeddedPGADC is beneficial for overall system performance includingpower consumption, chip area, noise performance, etc.

This paper describes the design of a system-in-packagetype 3-axis acceleration sensing system including a precisioninterface circuit and a capacitive MEMS accelerometer sensor.The interface circuit consists of a capacitance-to-voltage (C/V)converter and a PGADC, which are implemented in switched-capacitor topology. The C/V converter and ADC are used tomeasure an imbalance in the MEMS sensor and digitize themeasured data, respectively. The proposed sensing system hasno additional digital feedback to the proof mass to reducesystem complexity and parasitic capacitances. The parasiticcapacitances should be minimized due to the signal degra-dation caused by unwanted offset [19], [20]. The parasiticcapacitance issue is further reduced by the 3-D stackingtechnique, which can be implemented with relatively shorterbonding wire in comparison with side-by-side integration [21].The remained asymmetry between the differential capacitorsin the MEMS sensor can be compensated using precision DCoffset trimming technique. The DC offset trimming capac-itors can be elaborately adjusted in a unit of hundreds ofattofarads.

The proposed interface circuit for a system-in-package typeMEMS accelerometer is implemented in a standard 0.18-μmCMOS technology. The prototype achieves 197 μg/

√Hz noise

floor which is equivalent to a 13.7-bit ER in a conversion timeof 1 ms.

This paper is organized as follows. Section II describesthe architecture of the 3-axis acceleration sensing sys-tem. Section III discusses and analyzes the design of theMEMS sensor and the interface circuit. Section IV is a sum-mary of the proposed system. The experimental results arepresented in Section V, and the paper ends with conclusionsin Section VI.

Fig. 2. Simplified signal path block diagram of the proposed accelerationsensing system.

Fig. 3. A capacitive MEMS sensor interface.

II. SYSTEM ARCHITECTURE

Fig. 2 shows a simplified single-axis block diagram ofthe proposed interface circuit with the capacitive MEMSsensor. The input of the MEMS sensor of the accelerometeris an external acceleration, and the output is a variation indifferential capacitance, which is changed to a differentialvoltage by the C/V converter. This differential voltage outputis amplified and digitized by the PGADC. The designed inter-face circuit is implemented in a fully-differential switched-capacitor topology, so the gain of the analog circuits is welldefined by the ratio of capacitances, which is much moreaccurate than other methods, such as open-loop gain setting,passive resistors, trans-conductance cells, etc.

Because the proof mass moves through a very small distance(tens-of-nanometer in this case), the variation in capacitanceis no more than a few femtofarads. Large gain in analogfront-end is therefore required to achieve wide dynamic rangeof the system. The gain of the interface circuit also shouldbe programmable to accommodate a wide range of externalaccelerations (>± 16-g). The gain of the C/V converters and,


Fig. 4. Schematic diagram of the MEMS sensor and C/V converter with the associated timing.

of course, the PGADC both can be adjusted. The 2-stageprogrammable-gain embedded interface circuit is integratedwith the MEMS sensor in 3-D stacked structure. The approachof vertically stacking in a package is to minimize packagefootprint and parasitic capacitances [21]. It is very impor-tant to have a symmetric wiring with the shortest bondingwires. For this configurations, the I/O pads of the interfacecircuit are carefully arranged considering connections to theMEMS sensor. The residual parasitic capacitances are digitallycompensated by a fine offset calibration utilizing an array ofmetal-oxide-semiconductor (MOS) capacitors.

The detailed operation and circuitry of the system arediscussed in the following sections.

III. IMPLEMENTATION DETAILS

A. MEMS Sensor and Interface Circuits

The sensor interface is implemented in a fully-differential,and a square driving pulse is supplied to the proof mass,as shown in Fig. 3 [22]. A fully differential interfacehas several important advantages, such as voltage swingrange improvement, second order nonlinearities reduction and,in particular, sensitivity reduction to system noise includingpower-supply noise, substrate noise, and other common-modesystem noise [23].

A driving pulse from the electrical IC is applied to theproof mass of the MEMS sensor, while the fixed electrodes areconnected to the differential interface circuit through bondingwires. Fig. 4 shows a schematic diagram of the MEMSsensor and the C/V converter with the associated timing. Theamplitude of the voltage pulse to drive the MEMS structure isequal to the analog supply voltage of 3.3 V to achieve the highsystem signal-to-noise ratio (SNR) at the output stage of theelectrical IC with maximized signal amplitude. Any capacitiveimbalance in the MEMS sensor causes different amounts ofcharge to flow from each output to the interface circuit. Thecharge difference �Q, in response to the voltage step VM isgiven by

�Q = Q1 − Q2 = 2�CS × VM (1)

Fig. 5. Single-ended representation for charge to voltage conversion at(a) reset phase (P2) and (b) signal transfer phase (P1).

where Q1 and Q2 are charge on the differential capacitorsof the MEMS sensor. Because the charge difference shouldbe converted to a voltage with high reliability, and switched-capacitor circuits are robust to capacitor mismatch, variousswitched-capacitor ICs are proposed [24], [25]. The operationclock frequency of the designed switched-capacitor based C/Vconverter is 256 kHz, and the bottom plate sampling techniquewith complementary switches using non-overlapping clockis applied to minimize the charge injection and the clockfeedthrough [26]. Single-ended representations of the twophase of the process are shown in Fig. 5. After solving thecharge conservation equations utilizing (1), the differentialoutput voltage �VOUT is given by

�VOUT = −2�CS

CF× VM (2)

where CF is the variable feedback capacitor in C/V converter.The feedback capacitor CF (250 fF, 500 fF, 1 pF, and 2 pF) canbe adjusted by a 2-bit digital control signal. The smallest valueof the CF (250 fF) is suitable for MEMS sensor applications toobtain a maximum electrical signal, except for exceptionallylarge acceleration input cases, which can aggravate systemstability.


Fig. 6. Simplified schematic diagram (at signal transfer phase P2) of the signal path of a single axis, including the 8-bit offset calibration.

Some mismatch between the differential MEMS capacitorsis inevitable, and this can cause an unwanted DC offset ofdifferential electrical signals. To compensate the undesiredDC offset, high-precision offset trimming circuits are required.In many cases, gate connected MOS capacitor is well used,however, an extrinsic parasitic capacitance of a minimumsize PMOS device is used to implement fine capacitor lessthan a femtofarad. The minimum increment of the capacitorarray for offset calibration is about 600 aF. In this work,8-bit capacitor array is chosen to ensure ±50% capac-itive mismatch compensation between the two nominalcapacitor C0, which is about 250 fF. The offset calibrationcircuits are fully differential, and the linearity of the fine DCoffset trimming using MOS capacitors is proved and shownwith measurement results in Section IV.

Fig. 6 shows the schematic diagram of the signal pathincluding the offset calibration at signal transfer phase. Flickernoise and offset produced by the operational amplifier in theC/V converter cause an additional error, which is suppressedby a correlated double-sampling (CDS) technique [27], [28].The value of CCDS is chosen to 1 pF for negligible additionalthermal noise generation. The CDS method operates in twophases, a noise sampling phase, and a noise subtraction phase.Noise sampling is performed during the P2 phase when theamplifier’s output is in reset mode. During the P1 phase,the sampled noise is subtracted from the signal, suppressingboth the flicker noise and any offset.

The design parameter x (=2Rongm) of the C/V converter isabout 3.5 [29], where Ron is the on-resistance of the switches,and gm is the trans-conductance of the OTA. It means thatthe noise fraction of the OTA is less than 20 % of the C/Vconverter thermal noise. The amplifier of the C/V converter isimplemented in a fully-differential folded cascade operationaltrans-conductance amplifier (OTA) with a wide-swing cascadestructure for wide operating range [30]. The OTA has a unit-gain bandwidth (UGB) of 8 MHz with 1 pF load capacitor forenough settling.

B. Programmable-Gain �� Modulator

A discrete-time �� ADC is a very suitable candidatefor high-fidelity sensor applications with noise-shaping andoversampling technique to reduce the electrical quantization

Fig. 7. A �� PGADC employing 1-bit internal ADC.

and thermal noise. Fig. 7 shows the block diagram of theprogrammable-gain �� ADC, which consists of an analog�� modulator and a digital decimation filter. A loop filter inthe �� modulator provides integration and scaling with a pro-grammable coefficient. The negative feedback loop is formedby a loop filter, an internal quantizer (coarse ADC), and afeedback digital-to-analog converter (DAC). A 1-bit quantizeris applied because it is suitable for sensor applications due toits inherent linearity.

The speed of the clock in a �� modulator exceed thenyquist sampling frequency by the oversampling ratio (OSR),which divides the noise power in the band of interest.Furthermore, the �� modulator shapes the quantization noiseby the noise-transfer function (NTF), which enables the ADCto achieve high ER. The modulator output Y is 1-bit digitaldata-stream. The down-sampling process through the decima-tion filter produces multi-bit outputs at the nyquist samplingrate.

Fig. 8 shows a block diagram of the �� modulator, inwhich a single comparator is used as the internal quantizer.The gain of the 1-bit comparator is not fixed value andcan degrade the stability of the �� loop by altering thetransfer functions of the system. The coefficient c2 and thevariable gain of the comparator can be considered in a mergedcoefficient K . The signal transfer function (STF) and the NTFcan be expressed as (3) and (4) respectively:

STF YX(z) = K b1c1

z2 + (ka2 − 2)z + (1 − K a2 + K a1c1)(3)

NTF YE(z) = (z − 1)2

z2 + (K a2 − 2)z + (1 − K a2 + K a1c1), (4)


Fig. 8. Block diagram of a programmable-gain �� modulator.

Fig. 9. Schematic diagram of the second-order �� modulator.

Thus STF for z = 1 can be expressed as following:

STF YX(z = 1) = b1

a1. (5)

The loop filter in the �� modulator must itself be program-mable for implementing PGADC, and consequently, eithera1 or b1 in (5) should be variable. However, a1 affects thelocation of the NTF poles, which alter the noise shapingprovided by the loop filter, and the undesired change ofthe poles can compromise system stability. In this work,the programmable gain capability is realized with b1, whichis independent of the NTF [31]. The values of the coefficientsof the loop filter are presented in Table I.

Fig. 9 is a schematic diagram of the proposed PGADC. Thenon-overlapping clock timing is matched by the associatedclock in the C/V converter, shown in Fig. 4. In many cases,the sampling capacitors CS1 and CDAC1 are implemented

TABLE I

VALUES OF COEFFICIENTS IN THE PGADC DESIGN

as a single shared capacitor for area optimization. But theshared DAC structure produces a signal-dependent currentfrom the reference voltage [32], which can result in severeodd-harmonic distortion. In addition, �� modulators using ashared DAC can only have a loop filter with a signal gain


TABLE II

NUMERICAL VALUES OF THE PROGRAMMABLE COEFFICIENT

of unity, which means a1 and b1 must be same. Therefore,we introduce a programmable- gain loop filter with a separatefeedback DAC, and the numerical values of the programmablecoefficient are listed in Table II.

In order not to compromise the noise performance of thesensor and the analog front-end interface, the PGADC shouldbe the lowest noisy block with high power-efficient. The CDStechnique applied to the C/V converter is also applied to thefirst integrator of the �� modulator to suppress low-frequencyflicker noise. At a cost-efficient point of view, the CDStechnique is not applied to the second integrator, as its flickernoise is shaped by the first integrator. The OTAs of 1st and2nd integrators have the same structure that of C/V converter,and consume only 37 uA and 12 uA, respectively.

The other significant type of noise is thermal noise, whichcan be analyzed based on [29]. The input-referred noise (IRN)of the first integrator is the most influential, and can be derivedas follows:

IRN ≈ 4kT

CS(1 + CDAC

CS)/OSR

= 4kT

CS(1 + a1

b1)/OSR (6)

where k is the Boltzmann constant (1.38 × 10−23 J/K ), andT is the temperature in Kelvin. Ignoring the negligible quan-tization noise suppressed by �� modulation technique, thesignal-to-noise ratio (SNR) of the PGADC can be expressedas follows:

SNR (dB) � 10 log

⎛⎜⎝ PSIGNAL

4kTCS×OSR (1 + 1

STF YX

(z=1) )

⎞⎟⎠ (7)

where PSIGNAL is the input signal power, and the SNR isrelated to the DC gain of the STF. The SNR accounts for thenoise caused by applying separate feedback DAC topology.The IRN and SNR of the PGADC vary with the gain of thePGADC, following (6) and (7), but the SNR equals or exceedsthat of a conventional ADC at all gains [31].

C. Decimation Filter

The decimation filter converts the 1-bit stream output ofthe �� modulator to 16-bit digital data by low-pass filteringwith down-sampling. The decimation filter is implemented asa sinc3 filter to optimize the performance of the interfacecircuit including second-order �� ADC with a hardwareefficiency [33]. The frequency response of the designed sinc3

filter is given by

∣∣∣H (e jw)∣∣∣ =

(1

M× sin(π M f / fS)

sin(π f / fS)

)3

(8)

where M is the down-sampling ratio of the decimation filter,and fS is the over-sampled clock frequency of the switched-capacitor analog blocks. The values of M and fS used inthis filter are 256 and 256 kHz respectively, which gives anoutput data-rate (ODR) if 1 kHz. The decimation filter hasspectral notches at multiples of the decimated clock frequency,which are the zeros of (8). Hardware-inefficient finite-impulseresponse (FIR) filter for droop compensation which requiresmulti-bit multiplier and additional operations is omitted dueto its slow data rate.

IV. SYSTEM-LEVEL SUMMARY

Fig. 10 is the system-level block diagram of the 3-axisaccelerometer chip including the capacitive MEMS sensorand the interface circuit, which are fabricated in a monolithicchip. The full on-chip interface circuit includes an oscillator,a band-gap reference (BGR), a low-dropout regulator (LDO),a power-on reset (PoR), a clock generator, a C/V converter,and a PGADC. The main analog signal path is fully differentialwith 8-bit offset calibration of the asymmetric capacitance ofthe MEMS sensor, and 2-bit gain control of both stages. Thegain control functions are embedded in the C/V converterand the programmable-gain �� modulator to save powerconsumption. The digitized 16-bit values for each axis arepassed through a serial interface.

V. EXPERIMENTAL RESULTS

The prototype is fabricated in a 0.18 μm CMOS tech-nology. To verify an effective performance of the designedinterface circuit, the system-in-package type accelerometeris implemented with 3-D stack technique. Fig. 11 showsa microphotograph of the die with a layout of the analogcore circuits, which has an area of 1.18 mm2. As shownis fig. 12, the on-chip 3-axis MEMS sensor is 3-D stackedon the electrical IC, which is connected by bonding wires.The nominal voltages supplied to the analog and digital are3.3 V and 1.8 V, respectively. The directions of the 3-axisaccelerometer with the photograph of the custom-designedPCB for the fabricated chip can be figured out in Fig. 13.

A. Linearity MeasurementsThe measured digitized output from the 16-bit ADC is

plotted against the gain of the PGADC in Fig. 14. The top halfplane corresponds to an acceleration of + 1-g gravitationalforce of the Earth, and the bottom half plane to a −1-gacceleration. The each output code value in the graph withvertical mirror characteristic is an averaged over 212 samples.The graph from the averaged output code shows a linearrelationship with PGADC gain mode for accelerations in bothdirections. The mass of the z-axis responds to a verticalacceleration, meanwhile x, and y-axes to a horizontal accel-eration. The vertical movement of the mass is difficult dueto physical constraints, so the capacitance variation of thez-axis is smaller than other axes, which results in relatively


Fig. 10. System-level block diagram of the fabricated chip (gray-colored blocks (OSC, PoR, BGR, LDO) are shared for 3-axis interface circuit).

Fig. 11. Microphotograph of fabricated interface circuit with a magnifiedlayout of its core.

small signal amplitude. The difference of the amplitude canbe matched using digital gain correction.

To verify the dynamic characterization of the proposed inter-face circuit, a laboratory shaker (Brüel & Kjær Type 4808) anda standard reference accelerometer (Brüel & Kjær Type 8305)are used for tests. Fig. 15 is the measured results of thex-axis in response to 20 Hz sinusoidal acceleration input(0.8-g and 1.6-g) on top of the 1-g gravitational force of theEarth. Fig. 16 shows the measured code of the accelerom-eter with the maximum gain mode of C/V converter andthe PGADC after digital gain calibration. The default 1-g acceleration input is from the Earth’s gravitational force,and the additional acceleration is from the shaker. The mea-sured maximum nonlinearity in Fig. 16 is 1.09 % using the

Fig. 12. Photograph of the fabricated read-out IC with bonding wireconnected 3-D stacked MEMS sensor.

Fig. 13. Photograph of the custom-designed PCB with fabricated 3-axisMEMS acceleration sensing chip.

nonlinearity definition as follows [34]:

Nonlinearity(%) = Error

FSR× 100 (9)


Fig. 14. Measured digital output versus gain of the PGADC with themaximum gain of the C/V converter.

Fig. 15. Measured output code of the x-axis for 0.8-g and 1.6-g 20 Hzsinusoidal acceleration on top of a 1-g gravitational force of the Earth.

where FSR is the full-scale range, which is shownin Table II.

Fig. 17 shows the relationship between DC offset trimmingcode and measured digital output code. . The trend lineexhibits linear characteristic with 0.9997 of the coefficientof determination, which means the systemic offset can beprecisely calibrated with the 8-bit digital code.

B. Noise Measurements

The C/V converter and the PGADC both have the pro-grammable gain capability, and so the distribution of noiseacross the system can be obtained by solving two simul-taneous equations. The two simultaneous equations can bederived from the measured output noise values for differentgain condition of the system. In this case, the maximumgain difference (18 dB) of the C/V converter and the unity-gain PGADC are used to make the simultaneous equations,which are obtained by (10) and (11):√

V 2N + V 2

N,ADC = 1.87 LSB (10)√

(8 × VN)2 + V 2N,ADC = 4.90 LSB (11)

Fig. 16. Measured output code response to the accelerations.

Fig. 17. Measured offset calibration linearity using differential 8-bit DCoffset trimming code.

where VN is the MEMS mechanical noise combined with theelectrical noise of the C/V converter referred to the input ofthe C/V converter, and VN,ADC is the IRN of the PGADC oper-ating with unity gain. The right-hand sides of equations (10)and (11) are the measured output ref erred noise (ORN) ofthe x-axis sensor system corresponding to the minimum andmaximum gain of the C/V converter, respectively, as shownin Fig. 18 and Fig. 19. Solving equations (10) and (11), theroot-mean-square (RMS) noise values of VN and VN,ADC canbe computed, which are 0.57 least significant bit (LSB) and1.78 LSB, respectively. The noise analysis method that is usedto the x-axis can also be applied to the y-axis and z-axis. Theresults of noise measurements and analysis are summarizedin Table III.

Fig. 20 shows the measured variation in the decimal outputcode of the PGADC supplied directly with an external input.The measured RMS output noise is about 1.8 LSB, which isvery similar to the calculated value in Table III. The solutionof (10) and (11) can be used to obtain other noise values,such as the ORN of the x-axis sensor system for various gainof PGADC with maximum C/V converter gain, which can be


Fig. 18. Measured output code histogram of the x-axis accelerometer, mea-sured over 212 samples (minimum C/V converter gain, unity-gain PGADC).

Fig. 19. Measured output code histogram of x-axis accelerometeron 212 samples (maximum C/V converter gain, unity-gain PGADC).

TABLE III

SUMMARY OF NOISE MEASUREMENTS WITH UNITY-GAIN PGADC

expressed as follows:

ADCG ·√

(8 × VN)2 + V 2N,ADC = ADCG · 4.90 LSB (12)

where ADCG is the value of the designed PGADC. The noisevalue obtained from (12) is compared with the measured noisein Fig. 21, showing that error between calculated and measurednoise is less than 1 LSB for all gain settings.

Fig. 20. Measured output code histogram of ADC on 212 samples with anexternal input.

Fig. 21. Measured and calculated output RMS noise versus gain of PGADC.

Fig. 22. Measured power spectral density of the designed x-axis accelerationsensing system.

Fig. 22 shows the measured output power spectrumdensity (PSD) of the decimated 16-bit digital output. Thethermal noise dominant PSD of 0 g input shows that thereis no DC offset or 1/ f noise below 1 mHz. The attenuationabove 0.1 Hz is an effect of notch generated by the digitalsinc3 filter.


TABLE IV

COMPARISON WITH OTHER REPORTED ACCELERATION MEASURING CHIPS

Fig. 23. Noise budget.

C. Performance Summary

The noise budget obtained using (10) and (11) is shownin Fig. 23. The proportion pie chart shows that the mechanicalnoise from the MEMS and the electrical noise from the C/Vconverter occupy about three quarters in the total noise budgetof the designed acceleration sensing system. The remainedportion of the noise budget is for ADC, which is a few morethan a quarter, and the estimated quantization noise portionis 20% of the ADC noise budget.

The performance of the accelerometer is summarizedin Table IV and compared to other acceleration sensingsystems [3], [4], [12], [17], [19], [24], [25]. The proposedmonolithic chip effectively achieves 3-D stacked 3-axis accel-eration sensing system with high resolution. The ER can becalculated as follows:

ER = log2

(FSR

RMS Noise

)(13)

The system-in-package type 3-axis accelerometer achieves themaximum ER of 13.7-bits with the maximum nonlinearity of1.09 %. The average current consumptions from 3.3 V and1.8 V are 247 μA and 37 μA, respectively, in a conversiontime of 1 ms.

VI. CONCLUSION

An interface circuit for a monolithic 3-axis capacitiveMEMS accelerometer has been realized in a 0.18 μm CMOStechnology. The fabricated prototype consists of a MEMS sen-sor and the interface circuit with an embedded programmable-gain delta-sigma ADC. The accelerometer is implementedto system-in-package type using 3-D stack technique forarea optimization and offset minimization with small para-sitic capacitances of bonding wires. The remaining offset issuppressed by the CDS technique and sub-femtofarad finecalibration scheme. The performance of the system has beenverified with histogram and PSD.

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Jaehoon Jun (S’16) received the B.S. degreesin electrical and computer engineering from SeoulNational University, Seoul, South Korea, in 2013,where he is currently pursuing the Ph.D. degree inelectrical engineering and computer science.

He is currently focusing on the design of low-power high-resolution readout interface circuits withanalog-to-digital converters for sensor applications.His research interests include the design of CMOSsmart temperature sensors, humidity sensor interfacecircuits, precision dc measurement interface circuits

for bridge transducers, and other MEMS sensor application interface circuits.

Cyuyeol Rhee (S’16) received the B.S. degreein electrical engineering from the University ofToronto, Toronto, Canada, in 2010.

He is currently pursuing the Ph.D. degree withSeoul National University, Seoul, South Korea. Hisresearch interests are in analog and mixed-signalintegrated circuits and systems.

Sangwoo Kim received the M.S. degree in electricalengineering from Seoul National University, Seoul,South Korea, in 2004.

From 2004 to 2011, he was with Samsung Elec-tronics, South Korea, where he was involved in thedesign of display driver IC and Touch Control IC.From 2011 to 2014, he was with Hyundai Autron,South Korea, where he was involved in the design ofpressure and ultrasonic sensor IC. In 2014, he joinedCrepas Technologies, South Korea, and is now incharge of the ROIC Design Team and focuses on

architecture design and signal processing for sensor ROIC.

Suhwan Kim (S’97–M’01–SM’07) received theB.S. and M.S. degrees in electrical engineeringand computer science from Korea University, Seoul,South Korea, in 1990 and 1992, respectively, and thePh.D. degree in electrical engineering and computerscience from the University of Michigan, Ann Arbor,MI, USA, in 2001.

From 1993 to 1999, he was with LG Electronics,Seoul, Korea. From 2001 to 2004, he was a ResearchStaff Member with the IBM T. J. Watson ResearchCenter, Yorktown Heights, NY, USA. In 2004, he

joined Seoul National University, Seoul, where he is currently a Professorof electrical and computer engineering. His research interests include high-performance and low-power analog and mixed-signal integrated circuits, high-speed I/O circuits, and power electronics.

Dr. Kim received the 1991 Best Student Paper Award of the IEEE KoreaSection and the First Prize (Operational Category) in the VLSI Design Contestof the 2001 ACM/IEEE Design Automation Conference. He has served as theGeneral Co-Chair and the Technical Program Chair of the IEEE InternationalSystem-on-Chip (SoC) Conference. He also served as a Guest Editor of theIEEE JOURNAL OF SOLID-STATE CIRCUITS Special Issue on the IEEE AsianSolid-State Circuits Conference. He has participated multiple times on theTechnical Program Committees of the IEEE International SoC Conference,the International Symposium on Low-Power Electronics and Design, the IEEEAsian Solid-State Circuits Conference, and the IEEE International Solid-StateCircuits Conference.

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