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5.0.1 – JEDEC Moisture sensitivity Update P.1
JEDEC / JEITA Joint Meeting #19 in Kyoto, Japan, September 2015
Steve Martell (Sonoscan)
5.0.1 Moisture Sensitivity Update
by JEDEC
5.0.1 – JEDEC Moisture sensitivity Update P.2
JEDEC / JEITA Joint Meeting #19 in Kyoto, Japan, September 2015
Outline Outline
• J-STD-020E – J-STD-020E Officially Published December 2014
• Changes incorporated in 020E version
– Potential Future Change list
• J-STD-033D – Last published February 2012
– Planned changes to J-STD-033D
• J-STD-075 – Published August 2008
– Planned changes to J-STD-075
• Future Topics to be Considered
5.0.1 – JEDEC Moisture sensitivity Update P.3
JEDEC / JEITA Joint Meeting #19 in Kyoto, Japan, September 2015
J-STD-020E Published Dec. 2014 J-STD-020E Published Dec. 2014
5.0.1 – JEDEC Moisture sensitivity Update P.4
JEDEC / JEITA Joint Meeting #19 in Kyoto, Japan, September 2015
J-STD-020E Published Dec. 2014 J-STD-020E Published Dec. 2014
5.0.1 – JEDEC Moisture sensitivity Update P.5
JEDEC / JEITA Joint Meeting #19 in Kyoto, Japan, September 2015
J-STD-020E Published Dec. 2014 J-STD-020E Published Dec. 2014
5.0.1 – JEDEC Moisture sensitivity Update P.6
JEDEC / JEITA Joint Meeting #19 in Kyoto, Japan, September 2015
J-STD-020E Published Dec. 2014 J-STD-020E Published Dec. 2014
5.0.1 – JEDEC Moisture sensitivity Update P.7
JEDEC / JEITA Joint Meeting #19 in Kyoto, Japan, September 2015
J-STD-020E Published Dec. 2014 J-STD-020E Published Dec. 2014
5.0.1 – JEDEC Moisture sensitivity Update P.8
JEDEC / JEITA Joint Meeting #19 in Kyoto, Japan, September 2015
J-STD-020E Published Dec. 2014 J-STD-020E Published Dec. 2014
5.0.1 – JEDEC Moisture sensitivity Update P.9
JEDEC / JEITA Joint Meeting #19 in Kyoto, Japan, September 2015
J-STD-020E Published Dec. 2014 J-STD-020E Published Dec. 2014
5.0.1 – JEDEC Moisture sensitivity Update P.10
JEDEC / JEITA Joint Meeting #19 in Kyoto, Japan, September 2015
J-STD-020E Published Dec. 2014 J-STD-020E Published Dec. 2014
5.0.1 – JEDEC Moisture sensitivity Update P.11
JEDEC / JEITA Joint Meeting #19 in Kyoto, Japan, September 2015
J-STD-020E Published Dec. 2014 J-STD-020E Published Dec. 2014
5.0.1 – JEDEC Moisture sensitivity Update P.12
JEDEC / JEITA Joint Meeting #19 in Kyoto, Japan, September 2015
J-STD-020E Published Dec. 2014 J-STD-020E Published Dec. 2014
5.0.1 – JEDEC Moisture sensitivity Update P.13
JEDEC / JEITA Joint Meeting #19 in Kyoto, Japan, September 2015
J-STD-020E Published Dec. 2014 J-STD-020E Published Dec. 2014
5.0.1 – JEDEC Moisture sensitivity Update P.14
JEDEC / JEITA Joint Meeting #19 in Kyoto, Japan, September 2015
J-STD-020E Published Dec. 2014 J-STD-020E Published Dec. 2014
5.0.1 – JEDEC Moisture sensitivity Update P.15
JEDEC / JEITA Joint Meeting #19 in Kyoto, Japan, September 2015
J-STD-020E Published Dec. 2014 J-STD-020E Published Dec. 2014
5.0.1 – JEDEC Moisture sensitivity Update P.16
JEDEC / JEITA Joint Meeting #19 in Kyoto, Japan, September 2015
J-STD-020E Published Dec. 2014 J-STD-020E Published Dec. 2014
5.0.1 – JEDEC Moisture sensitivity Update P.17
JEDEC / JEITA Joint Meeting #19 in Kyoto, Japan, September 2015
J-STD-020E Published Dec. 2014 J-STD-020E Published Dec. 2014
5.0.1 – JEDEC Moisture sensitivity Update P.18
JEDEC / JEITA Joint Meeting #19 in Kyoto, Japan, September 2015
Future Topics for 020 Future Topics for 020
Flip Chip and CSP Failure Criteria & Soak Requirements Open
Stacked Die Failure Criteria & Soak Requirements Open
Heat Spreader Failure Criteria & Soak Requirements Open
Socket mounted components to be included? Plus, Sockets themselves? (Add clause
about removing socketed devices w/o MSL qualification should be removed before rework
should be added to rework section)
Sockets covered by ECIA.
SMD/socketed ICs are covered by J-
STD-020 as any other component, if
ICs are intended only for socket
applications do not need MSL. Is
this covered by current J-STD-020?
ECIA is working
on EIA364-56 to
cover sockets as
per Curtis
Grosskopf
May be more of a consideration for J-STD-
033, rather than J-STD-020. Ife will see what
Intel does for socket only SMDs.
Review of A-113F for time above liquidous range, which may affect J-STD-020 & other
issues that may have to be updated in J-STD-020 based on A113 work.
Discussed @ June 2011 Curt Grosskopf Collecting data for A113F - Oct 2008 revision
before making any changes for
preconditioning profile. (June 2012)
Clean "no clean fluxes", any issue with MSL classification Discussed @ June 2011 Jeff Jarvis Need comments from Jeff to proceed further
How can we cover MSL for Wave Solder? J-STD-020, J-STD-075 or A111? Discussed ay May 2013 Ted Kruger At minimum a note to clarify that J-STD-020
does not cover wave solder MSLs.
Component manufacturers would like a guideline for MSL
classification for flip chip/ WLCSP with redistribution
layers using laminate based substrates.
APEX 2014 Mumtaz Bora Next version of 020
Chip on wafer MSL Discussed at May 2014 Steve Martell Next version of 020
ILD MSL Discussed at May 2014 Steve Martell Next version of 020
WLP, Flip Chip, etc. testing and criteria Discussed at May 2015 Bob Knoell NXP paper on WLP absorption & desorption
from ESREF2015
Review LOC & potentially COL wording in section 6.2.1.1 B E-mail & discussed at May 2015 Francis Classe Next version of 020
5.0.1 – JEDEC Moisture sensitivity Update P.19
JEDEC / JEITA Joint Meeting #19 in Kyoto, Japan, September 2015
J-STD-033C Published Feb 2012 J-STD-033C Published Feb 2012
5.0.1 – JEDEC Moisture sensitivity Update P.20
JEDEC / JEITA Joint Meeting #19 in Kyoto, Japan, September 2015
J-STD-033D Planned Changes J-STD-033D Planned Changes The Committee wants to address what you do with longer term storage. Discussed @ June 2008.
This should be a
separate standard
through JEDEC.
JEDEC completed
JEP160
JEP160 completed, need to at least add a reference
and appropriate place within 033D like 020E
Add/transfer packaging and labeling requirements from J-STD-075 Do we need a "PSL"
label?
Discussed at Sept 2010
JEDEC Meeting
Add to Rev 033D Add to Rev 033D
HIC - Consider adding a non-reversable 60%RH dot to the card to notify user to discard the
HIC
Discussed at January 2012 Add to Rev 033D Add to Rev 033D
Clarification that you can use an HIC with more than 3 dots Discussed at January 2012 Add to Rev 033D Add to Rev 033D
For passive devices, appendices for bake drying times would be added. Coordinate with J-STD-075 Feedback from ECA
It was noted that for bake times when parts on reels at level 2 that have been exposed to
moisture, they will take 8 days to get them back to level 2 again. This is because reels
cannot withstand higher temperatures they have to be baked at 40 degrees C. (Need to verify
with tape & reel suppliers and possibility of higher temperature bake)
Do we need to add another
bake-out temperature
between 40 and 90 C or
recommendations for
alternative handling
procedures for higher
temperature back-out
Looked at Adding 60
- 70C bake, but data
from IDC was not
adequate.
The existing derating table in Section 7.1 does not apply to flip chip. Adding something
stating that the document only covers wire bond packages was proposed. It was decided that
this will wait until the next revision. Some material was presented by IBM on the floor time
derating tables that they have measured. Agere then showed the existing table 7.1 and noted
that the thickness makes all the difference—it is a critical number. The thinner you make it
the shorter the time. Knowing the distance from the outside area of the chip to the first bump
would help to revise the calculations. IBM agreed to make a few more soak evaluations to get
some more data. A task group was created to work on flip chip derating. Bill Guthrie will lead
it, and its members were Shook, Newman, McCullen and Susko. (Xuejun Fan (Intel) papers
on this subject)
How to derate Flip Chip,
Stacked Die and other
types of packages and
definitions of the various
package types. Bring
examples to show others
the construction. (SRM to
contact Robin, Keith & cc
Jack)
JEDEC TG on Flip
Chip (Ash)
Evaluate derating tables for substrate based packages. See above JEDEC TG on Flip
Chip (Ash)
Concern about alternative methods for determining the bakeout time tables other than the
methods provided in J-STD-020 or 033 (Modify Table 4-1 Note 1 and Section 4)
Discussed @ Jan 2009 Keith approved
removal via e-mail
1/29/15
Meaning of "Dry" package for dry bake times Discussed @ January
2009
Keith approved
removal via e-mail
1/29/15
How do you label & handle "socket only" SMDs? Discussed at APEX 2012
5.5.1.1 - Remove 5% RH spot indicates "dry" to cover column 2 condition of table 3-2 Discussed at January 2013 Enrico e-mail - IPC
question
Consider adding the word "minimum" in front of "12 months" on Figure 3-4 Moisture-Sensitive
Caution Label
Discussed at January 2013 Nick Lycoudes
3.3.5.2.1 - Consider adding or something similar to "“ A HIC card where the 10% spot
indicate wet CAN STILL re-used, unless the bag will be opened and the HIC inspected
within 48 hours" prior to the exisiting sentence.
Discussed at January 2013 Nick Lycoudes Closed due to potential HIC could be 15 to 55%RH
HIC - Valid beyond two (2) years? Data needed from Clariant, etc. for Sept 2014 meeting Discussed at May 2014 Nick Lycoudes via
SRM
Desiccant - Valid life time based on MBB vapor transmission rate? Data needed from
Clariant, etc., for Sept 2014 meeting
Discussed at May 2014 Steve Martell Not a limiting factor. No need to add.
Labels added to annex and reference within 033 & remove JEP113 reference Discussed at May 2014 Steve Tisdale &
Curtis Grosskopf
Convert and add to J-STD-033 as an Annex.
Shelf Life - review definition for moisture/reflow only? Discussed at May 2014 Group Review for comparison to JEP160
Bake times for packages <1mm in thickness E-mail from Jin 6/2/14 J. Kim (Samsung)
MSL1 - Bake recommendations if exceed 30C/85% RH floorlife &/or storage. Per Table 5-1 (J-
STD-033 & 020)
Question via IPC site Dec
2014 & Discussed at Jan
2015 meeting
SRM for IPC inquiry
Non-reversable 60% spot for HIC Discussed at May 2015 Mark (Clariant) &
Group
Non-reversable or other flag to indicate that 60%RH
was reached at some point.
MSL4, 5 & 5a pause clock clarification in section 4.1.2.2 e-mail & discusssion at
May 2015
SRM for IPC inquiry
Clarification of when 12 month clock starts. Bag seal date, etc. on label Discussed at May 2015 Ash Kumar
5.0.1 – JEDEC Moisture sensitivity Update P.21
JEDEC / JEITA Joint Meeting #19 in Kyoto, Japan, September 2015
J-STD-033D Planned Changes J-STD-033D Planned Changes
The Committee wants to address what you do with longer term storage. Discussed @ June 2008.
This should be a
separate standard
through JEDEC.
JEDEC completed
JEP160
JEP160 completed, need to at least add a reference
and appropriate place within 033D like 020E
Add/transfer packaging and labeling requirements from J-STD-075 Do we need a "PSL"
label?
Discussed at Sept 2010
JEDEC Meeting
Add to Rev 033D Add to Rev 033D
HIC - Consider adding a non-reversable 60%RH dot to the card to notify user to discard the
HIC
Discussed at January 2012 Add to Rev 033D Add to Rev 033D
Clarification that you can use an HIC with more than 3 dots Discussed at January 2012 Add to Rev 033D Add to Rev 033D
For passive devices, appendices for bake drying times would be added. Coordinate with J-STD-075 Feedback from ECA
It was noted that for bake times when parts on reels at level 2 that have been exposed to
moisture, they will take 8 days to get them back to level 2 again. This is because reels
cannot withstand higher temperatures they have to be baked at 40 degrees C. (Need to verify
with tape & reel suppliers and possibility of higher temperature bake)
Do we need to add another
bake-out temperature
between 40 and 90 C or
recommendations for
alternative handling
procedures for higher
temperature back-out
Looked at Adding 60
- 70C bake, but data
from IDC was not
adequate.
The existing derating table in Section 7.1 does not apply to flip chip. Adding something
stating that the document only covers wire bond packages was proposed. It was decided that
this will wait until the next revision. Some material was presented by IBM on the floor time
derating tables that they have measured. Agere then showed the existing table 7.1 and noted
that the thickness makes all the difference—it is a critical number. The thinner you make it
the shorter the time. Knowing the distance from the outside area of the chip to the first bump
would help to revise the calculations. IBM agreed to make a few more soak evaluations to get
some more data. A task group was created to work on flip chip derating. Bill Guthrie will lead
it, and its members were Shook, Newman, McCullen and Susko. (Xuejun Fan (Intel) papers
on this subject)
How to derate Flip Chip,
Stacked Die and other
types of packages and
definitions of the various
package types. Bring
examples to show others
the construction. (SRM to
contact Robin, Keith & cc
Jack)
JEDEC TG on Flip
Chip (Ash)
Evaluate derating tables for substrate based packages. See above JEDEC TG on Flip
Chip (Ash)
Concern about alternative methods for determining the bakeout time tables other than the
methods provided in J-STD-020 or 033 (Modify Table 4-1 Note 1 and Section 4)
Discussed @ Jan 2009 Keith approved
removal via e-mail
1/29/15
Meaning of "Dry" package for dry bake times Discussed @ January
2009
Keith approved
removal via e-mail
1/29/15
How do you label & handle "socket only" SMDs? Discussed at APEX 2012
5.5.1.1 - Remove 5% RH spot indicates "dry" to cover column 2 condition of table 3-2 Discussed at January 2013 Enrico e-mail - IPC
question
Consider adding the word "minimum" in front of "12 months" on Figure 3-4 Moisture-Sensitive
Caution Label
Discussed at January 2013 Nick Lycoudes
3.3.5.2.1 - Consider adding or something similar to "“ A HIC card where the 10% spot
indicate wet CAN STILL re-used, unless the bag will be opened and the HIC inspected
within 48 hours" prior to the exisiting sentence.
Discussed at January 2013 Nick Lycoudes Closed due to potential HIC could be 15 to 55%RH
HIC - Valid beyond two (2) years? Data needed from Clariant, etc. for Sept 2014 meeting Discussed at May 2014 Nick Lycoudes via
SRM
Desiccant - Valid life time based on MBB vapor transmission rate? Data needed from
Clariant, etc., for Sept 2014 meeting
Discussed at May 2014 Steve Martell Not a limiting factor. No need to add.
Labels added to annex and reference within 033 & remove JEP113 reference Discussed at May 2014 Steve Tisdale &
Curtis Grosskopf
Convert and add to J-STD-033 as an Annex.
Shelf Life - review definition for moisture/reflow only? Discussed at May 2014 Group Review for comparison to JEP160
Bake times for packages <1mm in thickness E-mail from Jin 6/2/14 J. Kim (Samsung)
MSL1 - Bake recommendations if exceed 30C/85% RH floorlife &/or storage. Per Table 5-1 (J-
STD-033 & 020)
Question via IPC site Dec
2014 & Discussed at Jan
2015 meeting
SRM for IPC inquiry
Non-reversable 60% spot for HIC Discussed at May 2015 Mark (Clariant) &
Group
Non-reversable or other flag to indicate that 60%RH
was reached at some point.
MSL4, 5 & 5a pause clock clarification in section 4.1.2.2 e-mail & discusssion at
May 2015
SRM for IPC inquiry
Clarification of when 12 month clock starts. Bag seal date, etc. on label Discussed at May 2015 Ash Kumar
5.0.1 – JEDEC Moisture sensitivity Update P.22
JEDEC / JEITA Joint Meeting #19 in Kyoto, Japan, September 2015
J-STD-033D Planned Changes
Example Discussion Point
J-STD-033D Planned Changes
Example Discussion Point
5.0.1 – JEDEC Moisture sensitivity Update P.23
JEDEC / JEITA Joint Meeting #19 in Kyoto, Japan, September 2015
J-STD-075 J-STD-075
5.0.1 – JEDEC Moisture sensitivity Update P.24
JEDEC / JEITA Joint Meeting #19 in Kyoto, Japan, September 2015
J-STD-075 MSL & PSL J-STD-075 MSL & PSL
5.0.1 – JEDEC Moisture sensitivity Update P.25
JEDEC / JEITA Joint Meeting #19 in Kyoto, Japan, September 2015
J-STD-075 - Future
• Changes needed since original release of J-STD-075
– Remove from scope connectors and point to equivalent connector
document
• EIA-364-56E, Resistance to Soldering Heat Test Procedure for Electrical
Connectors and Sockets
– Move marking requirements to J-STD-033
– Widen Scope of document to include solid state devices
– Add preheat requirements to solder wave profile
• 125C for 3 minutes (based on profiling from a few IBM cards)
– Add process flows for performing PSL classification
• Provide guidance for pass/fail criteria for passive commodities
– Update tables 13-1 and 14-1
• Base wave and base reflow solder process exceptions
– PTH “Selective Soldering” Processes
• Some of the PTH process conditions could be modified based on results
of the Pb-free solder wave/fountain survey currently being conducted
within JEDEC, ECIA, IPC, and iNEMI.
5.0.1 – JEDEC Moisture sensitivity Update P.26
JEDEC / JEITA Joint Meeting #19 in Kyoto, Japan, September 2015
Future Topics for 075
The idea for passives is that appendices to J-STD-020 would be created with criteria
included.
Plan to keep J-STD-020
for SMD IC criteria only.
Add criteria for passives
to J-STD-075 eventually.
ECA
criteria
needed
Clause 11, 3rd bullet, corrosive flux, (ph 1-2) change to (M and H per J-STD-004). Committee
agreed to remove (ph 1-2). Reference to J-STD-004 was left in. Committee wanted to consider
this for the next revision, because it was a technical change and will require further review.
Committee agreed in concept.
Discussed @ Apex 2008
Add a new section to address selective soldering (Solder fountain process for rework).
Committee noted this will be considered for the next revision. Pre-heat considerations
need to be added for through-hole PSL classification. (See item #19 below for Pb-
free Wave Profile)
Discussed @ Apex 2008 Curtis
How to test and notify about "washing limitations" to meet 075 E-mail inquiry Dec 2008
Request for alternative bakeout temperatures in addition to 125C due to temperature limits of
component carriers (i.e. Tape & Reel, etc.) Potential to use 60 - 70C for bakeout?
E-mail inquiry Jan 2009 IDC data inadequate for 60 to 70C bakeout.
Consider Outstanding Technical Comments for Next Revision:
Rework Processes
Flux references to J-STD-004
Inclusion of PTH “Selective Soldering” Processes
Classification Simplification (fewer buckets?)
Review Editorial Statement as to a “Reasonable” Process (Table 11-1, Note 1)
Expand on Connector Commodity Information / Participation
Additional Commodities
Discussed @ January
2009
Paul K.
Add failure criteria with input from ECIA Curt mentioned at Sept
2010 JEDEC meeting
Curtis
Transfer packaging and labeling requirements to J-STD-033D. Need "PSL" label? Curt mentioned at Sept
2010 JEDEC meeting
Curtis
Request from "Connector group" within ECIA has requested "connectors" be removed from J-
STD-075
Discussed @ June 2011
(ECIA completed their
doc)
Curtis
Reflow simulation profile diagram needed for A113 and 075 to show worst case conditions.
What can a "user" use? This will also require updates to JEDEC A113, B106, A111, J-STD-
075 and J-STD-020. Ideas for JEDEC September/October meeting (Curtis).
Discussed @ Jan 2012 Curtis
Consider changing the title and scope of 075 to "Process Sensitive" devices, meaning that it
may include ICs in the future for "PSLs"
Discussed @ Jan 2012 Curtis
Need to define what a "Reflow" actually is for a part/device. (Nearst Neighbor) Rework for
parts under large BGAs + sockets for LGAs (4 reflows may be needed) & In some cases less
than 3 reflows needed for other parts, since they do not see 3 peak temperatures. Should
there be a seperate profile for nearst neighbor parts that are "temperature/process sensitive".
Discussed at APEX 2012 Curtis
PB-free Wave Profile Standardized between B106, A111 & 075 (JEDEC TG starting July
2012 (July 2013)) The TG will be open to all who want to participate and is a priority
over other issues with 075 at this time.
Discussed at June 2012 Curtis
Additional tables into 075 from 020 - 1) Volume/area to peak temp 2) Discussed at January
2013
Curtis
5.0.1 – JEDEC Moisture sensitivity Update P.27
JEDEC / JEITA Joint Meeting #19 in Kyoto, Japan, September 2015
Future Topics for 075
The idea for passives is that appendices to J-STD-020 would be created with criteria
included.
Plan to keep J-STD-020
for SMD IC criteria only.
Add criteria for passives
to J-STD-075 eventually.
ECA
criteria
needed
Clause 11, 3rd bullet, corrosive flux, (ph 1-2) change to (M and H per J-STD-004). Committee
agreed to remove (ph 1-2). Reference to J-STD-004 was left in. Committee wanted to consider
this for the next revision, because it was a technical change and will require further review.
Committee agreed in concept.
Discussed @ Apex 2008
Add a new section to address selective soldering (Solder fountain process for rework).
Committee noted this will be considered for the next revision. Pre-heat considerations
need to be added for through-hole PSL classification. (See item #19 below for Pb-
free Wave Profile)
Discussed @ Apex 2008 Curtis
How to test and notify about "washing limitations" to meet 075 E-mail inquiry Dec 2008
Request for alternative bakeout temperatures in addition to 125C due to temperature limits of
component carriers (i.e. Tape & Reel, etc.) Potential to use 60 - 70C for bakeout?
E-mail inquiry Jan 2009 IDC data inadequate for 60 to 70C bakeout.
Consider Outstanding Technical Comments for Next Revision:
Rework Processes
Flux references to J-STD-004
Inclusion of PTH “Selective Soldering” Processes
Classification Simplification (fewer buckets?)
Review Editorial Statement as to a “Reasonable” Process (Table 11-1, Note 1)
Expand on Connector Commodity Information / Participation
Additional Commodities
Discussed @ January
2009
Paul K.
Add failure criteria with input from ECIA Curt mentioned at Sept
2010 JEDEC meeting
Curtis
Transfer packaging and labeling requirements to J-STD-033D. Need "PSL" label? Curt mentioned at Sept
2010 JEDEC meeting
Curtis
Request from "Connector group" within ECIA has requested "connectors" be removed from J-
STD-075
Discussed @ June 2011
(ECIA completed their
doc)
Curtis
Reflow simulation profile diagram needed for A113 and 075 to show worst case conditions.
What can a "user" use? This will also require updates to JEDEC A113, B106, A111, J-STD-
075 and J-STD-020. Ideas for JEDEC September/October meeting (Curtis).
Discussed @ Jan 2012 Curtis
Consider changing the title and scope of 075 to "Process Sensitive" devices, meaning that it
may include ICs in the future for "PSLs"
Discussed @ Jan 2012 Curtis
Need to define what a "Reflow" actually is for a part/device. (Nearst Neighbor) Rework for
parts under large BGAs + sockets for LGAs (4 reflows may be needed) & In some cases less
than 3 reflows needed for other parts, since they do not see 3 peak temperatures. Should
there be a seperate profile for nearst neighbor parts that are "temperature/process sensitive".
Discussed at APEX 2012 Curtis
PB-free Wave Profile Standardized between B106, A111 & 075 (JEDEC TG starting July
2012 (July 2013)) The TG will be open to all who want to participate and is a priority
over other issues with 075 at this time.
Discussed at June 2012 Curtis
Additional tables into 075 from 020 - 1) Volume/area to peak temp 2) Discussed at January
2013
Curtis
5.0.1 – JEDEC Moisture sensitivity Update P.28
JEDEC / JEITA Joint Meeting #19 in Kyoto, Japan, September 2015
Summary Summary
• J-STDs 020 – 020E Officially Published December 2014
• J-STD-033D – 033D Working Group has revision in process
• J-STD-075 – 075 Published August 2008
– Looking at potential future changes
• Other Future Considerations from JEITA ? – J-STD-020?
– J-STD-033?
– J-STD-075?
– Other?