40 Ei 4p2-Lic Lab Manual

8/17/2019 40 Ei 4p2-Lic Lab Manual

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/* 40 EI 4P2- Linear Integrated Circuits Laboratory*

/*KSRCT – DEPARTMENT OF EIE*/ 1

CIRCUIT DIAGRAM OF INVERTING AMPLIFIER:

CIRCUIT DIAGRAM OF NON-INVERTING AMPLIFIER:

R1

4.7kΩ

Vi

Vo

Rf

10kΩ

+V cc

-V cc

LM741

3

2

4

7

6

1

5 +

-

OU

T

CRO

R1

4.7kΩ

Vo

RF

10kΩ

+V cc

-V cc

LM741

3

2

4

7

6

1

5 +

-

OUT

Vi CRO


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Ex. No:DESIGN OF

INVERTING, NON-INVERTING AMPLIFIER USING OP-AMP

DATE:

AIM:

To design, construct and test an Inverting Amplifier for a given gain.

To design, construct and test a Non Inverting Amplifier for a given gain.

To measure CMRR of the differential Amplifier

APPARATUS REQUIRED:

S.No Name of the Apparatus Range Quantity

1. Function Generator 3 MHz 1

2. CRO 30 MHz 1

3. Dual RPS 0 – 30 V 1

4. Op-Amp IC 741 1

5. Bread Board 1

6. Resistors Based on Design Each 1

THEORY:

INVERTING AMPLIFIER:

The input signal Vi is applied to the inverting input terminal through R 1 and the non-inverting input

terminal of the op-amp is grounded. The output voltage Vo is fed back to the inverting input terminal through

the R f - R 1 network, where R f is the feedback resistor. The output voltage is given as,

Vo = - ACL × Vi

Here the negative sign indicates that the output voltage is 1800

out of phase with the input signal.

NON INVERTING AMPLIFIER:

The input signal Vi is applied to the non - inverting input terminal of the op-amp. This circuit amplifies

the signal without inverting the input signal. It is also called negative feedback system since the output is

feedback to the inverting input terminals. The differential voltage Vd at the inverting input terminal of the op-

amp is zero ideally and the output voltage is given as,

Vo = ACL × Vi Here the output voltage is in phase with the input signal


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CIRCUIT DIAGRAM OF COMMON MODE CONFIGURATION:

CIRCUIT DIAGRAM OF DIFFERENTIAL MODE CONFIGURATION:


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DESIGN:

DESIGN OF AN INVERTING AMPLIFIER WITH CLOSED LOOP GAIN - 2:

We know for an inverting Amplifier ACL = -R F / R 1

ACL = -R F / R 1 = 2

R F=2 R 1

Choose R 1=4.7k

Then R F=2x4.7k=9.4k

R F 10k

DESIGN A NON-INVERTING AMPLIFIER WITH CLOSED LOOP GAIN - 3:

We know for a Non-inverting Amplifier ACL = 1 + R F / R 1

ACL = 1 + R F / R 1 =3

R F=2 R 1

Choose R 1=4.7k

Then R F=2x4.7k =9.4k

R F 10k

CALCULATION:

In general, gain can be calculated by using the formula A= Adm/Acm

CMRR = Adm /Acm

Adm (Differential Mode Gain) = inV V 02

Acm (Common Mode Gain) = inV V 01

PROCEDURE:

1. Connections are given as per the circuit diagram.


5/94



2. + Vcc and - Vcc supply is given to the power supply terminal of the Op-Amp IC.

PIN DIAGRAM OF OP-AMP:

TABULATION:


S.No.

Input Output

GAIN

ACL = -R F / R 1 Amplitude

( No. of div x

Volts per div )

Time period

(No. of div x

Time per div )

Amplitude

( No. of div x

Volts per div )

Time period

(No. of div x

Time per div )

1.

2.

NON-INVERTING AMPLIFIER:

S.No.

Input Output

GAIN

ACL= 1+(-R F/ R 1) Amplitude

( No. of div x

Volts per div )

Time period

(No. of div x

Time per div )

Amplitude

( No. of div x

Volts per div )

Time period

(No. of div x

Time per div )

1.

2.


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3. By adjusting the amplitude and frequency knobs of the function generator, appropriate input voltage is

applied to the inverting input terminal of the Op- Amp for inverting amplifier and to non inverting

terminal for non inverting amplifier.

4. The output voltage is obtained in the CRO and the input and output voltage waveforms are plotted in a

graph sheet. Then the gain is calculated from the output and verified with designed gain.

5. Calculate the CMRR value of the differential amplifier in common mode and differential mode. CMRR

is expressed in db and for higher value of CMRR op amp is better.

6. Then the gain is calculated from the output and verified with designed gain.

MODEL CALCULATION:


NON-INVERTING AMPLFIER:


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MODEL GRAPH:

VIVA QUESTIONS:

1. What are the casues for offset voltage, offset current and bias current?

2. What are the assumptions made in delivering the closed loop gain of the amplifier circuits?

3. What is the negative feedback system?

4. What is the order of the input impedance of the non-inverting amplifier?

5. What is the output offset voltage?

6. How the offset voltage is reduced to zero in case of 741 Op amp?

7. What is the difference between DC voltage follower and AC voltage follower?

8. Explain the application of a differential amplifier for instrumentation and control applications?

9. What are the casues for offset voltage, offset current and bias current?


11. How the offset voltage is reduced to zero in case of 741 Op amp?

12. What are the ideal characteristics of op-amp?

13. What are the popular IC packages available in op – amp?

14. The negative sign in the output voltage of the inverting amplifier indicates what?

15. Define CMMR.

(V)

Vin

Vo

(V)

t(sec)

t(sec)

Inverting amp(V)

Vin

Vo

(V)

t(sec)

t(sec)

Non-Inverting amp


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RESULT:

Marks Allocation

DetailsMarks Allotted status

Marks

Awarded

Preparation 20

Conducting 20

Calculation / Graphs 15

Results 5

Basic understanding 15

Viva-Voice 15

Record 10

Total 100

Signature of faculty


9/94



CIRCUIT DIAGRAM OF NON-INVERITNG SUMMER:

DESIGN OF AN NON-INVERTING SUMMER:

03

3

2

2

1

1

R

V V

R

V V

R

V V aaa

)1( R

RV

f

O

When R 1= R 2= R 3= R= R f /2

V0= V1+V2+V3

TABULATION:

S.No V1(volts) V2(volts) V3(volts)

Designed Output

Voltage

V0=

V1+V2+V3(volts)

Obtained Output

Voltage

Vo=V1+V2+V3(volts)

R

Vo

Rf

+V cc

-V cc

LM741

3

2

4

7

6

1

5 +

- UT

CRO

R

R2

R3 V3

V1

V2

Va


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AIM:

To design, construct and test an Inverting and Non Inverting Summing Amplifier using op-amp.

To design, construct and test a Subtractor using op-amp.

To design, construct and test an Inverting and non inverting comparator.

To design, construct and test a Zero Crossing Detector.

APPARATUS REQUIRED:


1. CRO 30 MHz 1

2. Dual RPS 0 – 30 V 3

3. Op-Amp IC741 1

4. Bread Board - 1

5. Resistors Based on design As per requirement

6. Multimeter - 1


9. Single RPS 0-30 V 1

THEORY:

SUMMER:

Op-amp may be used to design a circuit whose output is the sum of several input signals. Such a circuit is

called a summing amplifier or a summer. For inverting summing amplifier the in[put voltages V1,V2 and V3 are

given through the input resistance to the inverting terminal of the op-amp. The non inverting terminal is

connected to the ground through the compensating resistor. The output of the inverting summing amplifier is

given below if R 1 = R 2 = R 3 = R

V0= - (V1+V2+V3 )

When R 1= R 2= R 3= 3R f

3

V3V2V1OV

Ex. No: DESIGN OF ADDER,SUBTRACTOR,COMPARATOR & ZEROCROSSING

DETECTOR USING OP-AMPDATE:


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CIRCUIT DIAGRAM OF INVERITNG SUMMER:

DESIGN OF AN INVERTING SUMMER:

03

3

2

2

1

1

f

o

R

V

R

V

R

V

R

V

When R 1= R 2= R 3= 3R f

3

V3V2V1OV

TABULATION:

S.No V1(volts) V2(volts) V3(volts)

Designed Output

Voltage

V0=

V1+V2+V3(volts)

Obtained Output

Voltage

Vo=V1+V2+V3(volts)

Vo

RCOMP = R1 R2 R3 R4

Rf

+V cc

-V cc

LM741

3

2

4

7

6

1

5 +

-

OUT

CRO

R1

R2

R3 V3

V1

V2

Va


12/94



For non inverting amplifier the input voltages are applied to the non inverting terminal of the op-amp.the

output is the sum of the input voltages.

When R 1= R 2= R 3= R= R f /2,

V0= V1+V2+V3

SUBTRACTOR:

A basic differential amplifier can be used as a subtractor. One of the input voltage is given to the

inverting terminal of the op-amp and other input is given to the non-inverting terminal of op-amp. The output

voltage is the difference between the two input voltages. If the input voltages are V1 and V2 means the output

voltage is given as

V0= V1- V2

NON INVERTERING COMPARATOR:

A fixed reference voltage Vref is applied to the inverting (-) input terminal and sinusoidal signal uin is

applied to the non-inverting (+) input terminal. When vin exceeds Vref the output voltage goes to positive

saturation because the voltage at the (-) input is smaller than at the (+) input. On the other hand, when v in is less

than Vref the output voltage goes to negative saturation. Thus output voltage Vout changes from one saturation

level to another whenever vin = Vref ,.as illustrated in figure. In short, the comparator is a type of an analog-to-

digital converter (ADC). At any given time the output voltage waveform shows whether vin is greater or less

than Vref . The comparator is sometimes referred to as a volt-level detector because for a desired value of V ref

the voltage level of the input voltage vin can be detected.

Diodes D1 and D2 are provided in the circuit to protect the op-amp against damage due to excessive

input voltage. Because of these diodes, the differential input voltage vd is clamped to either + 0.7 V or -0.7 V

hence the diodes are called clamp diodes. There are some op-amps with built-in input protection. Such op-amps

need not to be provided with protection diodes. The resistance R 1 in series with vin is used to limit the currentthrough protection diodes D1 and D2 while resistance R is connected between the inverting (-) input termina

and Vref to reduce the offset problem.

When the reference voltage Vref is negative with respect to ground, with a sinusoidal signal applied to

the non-inverting input terminal, the output voltage will be as illustrated in figure. Obviously, the amplitude of

vin must be large enough to pass through Vref for switching action to take place. Since the sinusoidal input signal

is applied to the non-inverting terminal, this circuit is called the non-inverting op-amp comparator.


13/94



CIRCUIT DIAGRAM OF SUBTRACTOR:

DESIGN OF SUBTRACTOR:

By using superposition principal,

To find the output V01 due to V1 alone, make V2 =0

11

01 )1(2

V V R

RV

Similarly the output V02 due to V2 alone,

V02= -V2, Thus, V0= V01+ V02 = V1- V2

TABULATION:

Sl.No V1(volts) V2(volts)

Designed Output

Voltage

V0= V1 - V2 (volts)

Obtained Output Voltage

V0= V1 - V2 (volts)

Vo R

R

+V cc

-V cc

LM741

3

2

4

7

6

1

5 +

-

OUT

CRO

R

V1

V2

Va

R


14/94



INVERTING COMPARATOR:

In an inverting op-amp comparator the sinusoidal input is applied to the inverting (-) input terminal to

the op-amp. The circuit for an inverting comparator in which the sinusoidal input signals v in is applied to the

inverting (-) input terminal while the reference voltage Vref is applied to the non-inverting (+) input terminal

show in figure. In this circuit V ref is obtained by the use of a potentiometer forming a potential divider

arrangement with dc supply voltage + Vcc and – VEE. As the wiper connected to (+) terminal is moved toward +

Vcc, Vref becomes more positive, while if it is moved toward – VEE, Vref becomes more negative. Comparators

are used in circuits such as discriminators, voltage level detectors, oscillators, digital interfacing, Schmitt trigger

etc.

ZERO CROSSING DETECTOR:

It is an applied form of comparator. The zero-crossing detector provided the reference voltage V ref is

made zero.The output voltage waveform indicates when and in what direction an input signal Vincrosses zero

volt. In some applications the input signal may be low frequency one (i.e. input may be a slowly changing

waveform). In such a case output voltage VOUT may not switch quickly from one saturation state to the other

Because of the noise at the input terminals of the op-amp, there may be fluctuation in output voltage between

two saturation states (+ Vsat and – Vsatvoltages). Thus zero crossings may be detected for noise voltages as well

as input signal vin. Both of these problems can be overcome, if we use regenerative or positive feeding causing

the output voltage vout to change faster and eliminating the false output transitions that may be caused due to

noise at the input of the op-amp.


15/94



CIRCUIT DIAGRAM OF NON-INVERITNG& INVERITNG COMPARATOR:

OUTPUT WAVEFORMS OF NON INVERTING COMPARATOR:

OUTPUT WAVEFORMS OF INVERTING COMPARATOR:


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PROCEDURE:

ADDER & SUBTRACTOR:

1. Connections are given as per the circuit diagram for adder.

2. Apply the input voltage to the corresponding resistors

3. The output voltage is obtained in the CRO and the input and output voltage waveforms are plotted in a

graph sheet. Repeat the above to get the different value of input voltage Same procedure can be adopted

to Subtractor but the output is the difference of input voltages

COMPARATOR:




applied to the corresponding terminals of Op-Amp.

4. Reference voltage to the comparator is fed with the single RPS.

5. The output waveform is obtained in the CRO and the input and output voltage waveforms are plotted in

a graph sheet. Then the gain is calculated from the output and verified with designed gain.

ZERO CROSSING DETECTOR:



3. Connect the non inverting terminal of the op-amp to grount and switch on the dual RPS.

4. Observe the output wave form from the CRO and draw the input and output waveform.


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CIRCUIT DIAGRAM OF ZERO CROSSING DETECTOR:

OUTPUT WAVEFORM OF ZERO CROSSING DETECTOR:

VIVA QUESTION:

1. What is comparator?

2. List the different types of comparator?

3. How the reference voltage to the comparator can be applied?

4. List out the application of comparator.

5. What is zero crossing detector?

6. What is a window detector?

7. What is meant by regenerative comparator?

8. Define upper threshold voltage and lower threshold voltage in Schmitt trigger.

9.

Define the term Gain of an op – amp.10. Explain how to measure the phase angle between two voltages.

11. Give the characteristics of an ideal op-amp:

12. How a non-inverting amplifier can be courted into voltage follower?

13. What is the necessity of negative feedback?

14. What are 4 building blocks of an op-amp?

15. What is the purpose of shunting C f across R f and connecting R 1 in series with the input signal?


18/94



RESULT:

Marks Allocation

DetailsMarks Allotted status

Marks

Awarded

Preparation 20

Conducting 20


Results 5


Viva-Voice 15

Record 10

Total 100



19/94



CIRCUIT DIAGRAM OF DIFFERENTIATOR:

CIRCUIT DIAGRAM OF INTEGRATOR:


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AIM:

To design and test a Differentiator circuit for the given operating frequency using op-Amp IC 741.

To design an Integrator circuit for the given operating frequency using op-Amp IC 741.

APPARATUS REQUIRED:



2. CRO 30 MHz 1

3. Dual RPS 0 – 30 V 1

4. Op-Amp IC 741 1

5. Bread Board - 1

6. Resistors Based on Design Each 1

7. Capacitors 0.55nF,0.01uF Each1

THEORY:

DIFFERENTIATOR:

The differentiator circuit performs the mathematical operation of differentiation: that is, the output

waveform is the derivative of the input waveform. The differentiator may be constructed from a basic inverting

amplifier if an input resistor R 1 is replaced by a capacitor C1. The expression for the output voltage is given as

Vo = - R f C1 (d Vi /dt)


out of phase with the input signal. A

resistor R comp = R f is normally connected to the non-inverting input terminal of the op-amp to compensate for

the input bias current. A workable differentiator can be designed by implementing the following steps:

1. Select f a equal to the highest frequency of the input signal to be differentiated. Then, assuming a value of

C1< 1 µF, calculate the value of R f .

2. Choose f b= 20 f a and calculate the values of R 1 and Cf so that R 1C1 = R f Cf .

Ex. No:DESIGN OF DIFFERENTIATOR & INTEGRATOR USING OP-AMP

DATE:


21/94



PIN DIAGRAM:

TABULATION:

DIFFERENTIATOR:

S.No Measurements Input Output

1.

Amplitude

( No. of div x Volts per div )

2.

Time period

( No. of div x Time per div )

3. Calculated Frequency

INTEGRATOR:


1.

Amplitude


2.

Time period




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The differentiator is most commonly used in wave shaping circuits to detect high frequency components

in an input signal and also as a rate – of – change detector in FM modulators.

INTEGRATOR:

A circuit in which the output voltage waveform is the integral of the input voltage waveform is the

integrator. Such a circuit is obtained by using a basic inverting amplifier configuration if the feedback resistor

R f is replaced by a capacitor Cf. The expression for the output voltage is given as,

Vo = - (1/R f C1) ∫Vi dt


out of phase with the input signal

Normally between f a and f b the circuit acts as an integrator. Generally, the value of fa < f b. The input signa

will be integrated properly if the Time period T of the signal is larger than or equal to R f Cf . That is,

T ≥ R f Cf

The integrator is most commonly used in analog computers and ADC and signal-wave

DESIGN:

DIFFERENTIATOR:

To design a differentiator circuit to differentiate an input signal that varies in frequency from 10 Hz to

about 1 KHz, a sine wave of 1 V peak at 1000Hz is applied to the differentiator, draw its output waveform.

Given f a = 1 KHz

We know the frequency at which the gain is 0 dB, f a = 1 / (2π R f C1)

Let us assume C1 = 0.01 µF:

Then

R f = 15.9k , since f b = 20 f a, f b = 20 KHz

We know that the gain limiting frequency f b = 1 / (2π R 1 C1)

Hence R 1 = 820 ,

Since R 1C1 = R f Cf =0.55Nf


23/94



MODEL GRAPH:

INTEGRATOR:

DIFFERENTIATOR:

Vin

Vo

t

t

Model graph

t

t

IV

Vin

Vo

t

t

-IV

Model graph

2V

-2V

IV

Vin

Vo

t

t

-IV

Model graph


24/94



INTEGRATOR:

To obtain the output of an Integrator circuit with component values

R f Cf = 0.335ms, R f = 10 R 1 and Cf = 0.01 µF

and also if 1 V peak square wave at 1500Hz is applied as input.

We know the frequency at which the gain is 0 dB, f b = 1 / (2π R 1Cf )

Therefore f b = 10 f a

Since f b = 10 f a, and also the gain limiting frequency f a = 1 / (2π R f Cf )

We get,

R 1 = 3.3k and hence R f = 33k

PROCEDURE:




applied to the inverting input terminal of the Op-Amp.

4.

The output voltage is obtained in the CRO and the input and output voltage waveforms are plotted in agraph sheet.


25/94



VIVA QUESTIONS:

1. How the differentiation can be performed in op amp circuits?

2. What are the applications of integrator and differentiator?

3. What is an inverting integrator?

4. What are the limitations of basic differentiator and integrator?

5. Write down the input and output relation for the differentiator and integrator?

6. Derive the design equations of the differentiator and integrator?

7. Why integrators are preferred over differentiator in analog computer?

8. What are the frequency compensation techniques available in op – amp?

9. What are the applications of Differentiator?

10. What do you mean by unity gain bandwidth?

11. What did you observe at the output when the signal frequency is increased above f a?

12. How would you eliminate the high frequency noise in integrator?

13. What are the main applications of the Integrator?

14. Is it possible to design an analog computer using integrator and differentiator?

15. What happens to the output of integrator when input signal frequency goes below f a?


26/94



RESULT:

Marks Allocation

Details Marks Allotted status

Marks

Awarded

Preparation 20

Conducting 20


Results 5


Viva-Voice 15

Record 10

Total 100



27/94



CIRCUIT DIAGRAM – ACTIVE CLIPPER:

MODEL GRAPH:

TABULATION:

ACTIVE CLIPPER:


1.Amplitude


2.

Time period




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/ * K S R C T - D E P A R T M E N T O F E I E * / 28

Ex. No:

DESIGN OF CLIPPER AND CLAMPER CIRCUITS USING OP-AMP

DATE:

AIM:

To design and test the operation of active diode (precisions circuits) with the help of clipper and

clamper circuits using Op-Amp.

APPARATUS REQUIRED:


1. IC 741 -- 1

2. Resistors 1kΩ,2.2kΩ,4.7kΩ 1

3. Capacitors 0.1 µF,0.01 µF 2

4. Diode IN4001 1

5. CRO -- 1

6. Power supply ±15 V,(0-30) V 1

7. Probe -- 2

8. Bread Board -- 1

THEORY:

ACTIVE CLIPPER:

Clipper is a circuit that is used to clip off (remove) a certain portion of the input signal to obtain a

desired output wave shape. In op-amp clipper circuits, a rectified diode may be used to clip off certain parts of

the input signal. The figure shows an active positive clipper, a circuit that removes positive parts of the input

signal. The clipping level is determined by the reference voltage Vref. With the wiper all the way to the left,

Vref is o and the non-inverting input is grounded. When Vin goes positive, the error voltage drives the op-amp

output negative and turns on the diode. This means the final output VO is 0 (same as Vref) for any positive

value of Vin. When Vin goes negative, the op-amp output is positive, which turns off the diode and opens the

loop. When this happens, the final output VO is free to follow the negative half cycle of the input voltage. This

is why the negative half cycle appears at the output. To change the clipping level, all we do is adjust Vref as

needed.

ACTIVE CLAMPER:

In clamper circuits, a predetermined dc level is added to the input voltage. In other words, the output is

clamped to a desired dc level. If the clamped dc level is positive, the clamper is called a positive clamper. On

the other hand, if the clamped dc level is negative, it is called a negative clamper. The other equivalent terms for


29/94



CIRCUIT DIAGRAM – ACTIVE CLAMPER:

MODEL GRAPH:

Input put Waveforms of Clamper for Different VREF

TABULATION:

ACTIVE CLAMPER:


1.

Amplitude


2.

Time period




30/94



clamper are dc inserter or dc restorer . A clamper circuit with a variable dc level is shown in figure. Here the

input wave form is clamped at +Vref and hence the circuit is called a positive clamper.

The output voltage of the clamper is a net result of ac and dc input voltages applied to the inverting and

non-inverting input terminals respectively. Therefore, to understand the circuit operation, each input must be

considered separately. First, consider Vref at the non-inverting input. Since this voltage is positive, is +VO is

positive, which forward biases diode D1. This closes the feedback loop and the op-amp operates as a voltage

follower. This is possible because C1 is an open circuit for dc voltage. Therefore VO = Vref. As for as voltage Vin

at the inverting input is concerned during its negative half-cycle D 1 conducts, charging C1 to the negative peak

value of the VP. However, during the positive half-cycle of Vin diode D1 is reverse biased and hence the voltage

VP across the capacitor acquired during the negative half-cycle is retained. Since this voltage V P is in series with

the positive peak voltage VP, the output peak voltage VO=2VP. Thus the net output is Vref+ VP, so the negative

peak of 2VP is at Vref. For precision clamping C1R d


31/94



VIVA QUESTIONS:

1. The clipper circuit can be called “go-no go detector”. Explain why it is called so?

2. In the Clipper circuit, if the POT is adjusted for Vref = -1V, what would be the output?

3. Set Vref = 0V in the clipper circuit and observe the output waveform and record your comments.

4. If the diode is reversed in the clipper circuit what would the output voltage be?

5. If the diode is reversed in clamper circuit what would the output be like?

6. State the difference between active and passive clippers.

7. List the advantages of clipper circuits.

8. Why the clamper circuit is called as DC Restorer?

9. Define CMRR.

10. Mention the non-linear applications of Op-Amp.

11. List the linear applications of Op-Amp.

12. Define Slew rate.

13. Infer the effects of slew rate in linear and non-linear applications.

14. Define Duty Cycle.

15. Define Time period and Frequency.


32/94



RESULT:

Marks Allocation

Details Marks Allotted statusMarks

Awarded

Preparation 20

Conducting 20


Results 5


Viva-Voice 15

Record 10

Total 100



33/94



CIRCUIT DIAGRAM OF INSTRUMENTATION AMPLIFIER

INPUT POWER SUPPLY DESIGN:


34/94



AIM:

To design and analyse the performance characteristics of instrumentation amplifier for the specified

gain value using op-Amp.

APPARATUS REQUIRED:


1. Dual RPS 0 – 30 V 2 Nos

2. Op-Amp IC 741 3 Nos

3. Bread Board - 1 No

4. Resistors 1 K ,100 K , 120 K ,10K 4 Nos

5. Decade Resistance Box - 1 Nos

THEORY: An instrumentation amplifier is typically the first stage in an instrumentation system. It is used to

amplify the signal produced by a transducer such as a thermocouple or a strain gauge. An instrumentation

amplifier is a difference amplifier i.e., it amplifies the voltage difference between its two input terminals,

neither of which is required to be a signal ground. An instrumentation amplifier should have the following

characteristics: high input resistance, high voltage gain, and high common-mode-rejection-ratio (CMRR).

The instrumentation amplifier depicted in Figure does not suffer from the disadvantages listed

above; it has high input resistance and high CMRR. It is clear from the circuit diagram that the input

resistance seen by the source is governed by the input resistance of the op-amps used in the circuit. The

input resistance of the instrumentation amplifier is thus very high.

The instrumentation amplifier consists of an input stage followed by a second stage (which is just a

basic difference amplifier). It is easily shown that the differential voltage gain of the first stage is (1 +

2R2/R1). We know that the differential gain of the second stage is R4/R3. The overall differential gain of the

instrumentation amplifier is thus

It is easily shown that the common-mode voltage gain of the first stage is unity. We know that the

common mode gain of the second stage is R4/ (R3 CMRRo). The overall common-mode gain of the

instrumentation amplifier is thus

Ex. No:DESIGN OF INSTRUMENTATION AMPLIFIER USING OP-AMP

DATE:


35/94



PRACTICAL CIRCUIT OF INSTRUMENTATION AMPLIFIER:

TABULATION:

S.No. THEORATICAL VALUE PRACTICAL VALUE

GAIN = Vout /(V1-V2) GAIN V1 (mV) V2(mV) V1-V2 Vout (mV)


36/94



The above two gives the CMRR of the instrumentation amplifier. We have

The CMRR of the instrumentation amplifier is thus greater than that of the op-amps by a factor (1 +

2R2/R1) which can be large. In fact, if we set R4 = R3, we see from Eq. 2-12 that this multiplying factor is the

(large) differential voltage gain of the instrumentation amplifier. In a number of instrumentation and consumer

applications one is required to measure and control the physical quantities. Some typical examples are

measurement and control of temperature, humidity, light, Intensity, water flow etc. These physical quantities are

usually measured with the help of transducer. The output of the transducer has to be amplified so that it can

derive the indicator or display system. The functions performed by an instrumentation amplifier are,

• High gain accuracy.

• High CMRR.

• High gain stability with low temperature coefficient.

• Low dc offset.

• Low input impedance.

These are specially designed op-amp such as VA725 to meet the above started requirement of a good

instrumentation amplifier. Monolithic instrumentation amplifiers are also available commercially such as

AD521, AD524, and AD624 by analog devices L40036, and L40037 by national semiconductors.

DESIGN:

V01= (1+R2/R1) V1− (R2/R1) V2,

V02 = (1+R2/R1) V2 − (R2/R1) V1

V0 = V02 − V01

= (V2−V1) (1+2R2/R1),

Gain = Vo/Vi => Vo / (V2−V1) => (1+2R2/R1

PROCEDURE:

1. Circuit connections are given as per the experimental setup.

2. The input signal is given.

3. The dual power supply is switched ON.

4. The input is varied in steps and the corresponding output readings are noted from CRO.

5. The practical gain is calculated from the readings


37/94



MODEL GRPAH:

VIVA - QUESTIONS:

1. What is the negative feedback system?

2. What is the order of the input impedance of the non-inverting amplifier?


4. Define the term Gain of an op – amp.

5. What is the necessity of negative feedback?

6. What are 4 building blocks of an op-amp?

7. What is the purpose of shunting Cf across Rf and connecting R1 in series with the input signal?

8. Mention any two specifications of a DAC.

9. Name any two types of ADC.

10. Define duty cycle ratio.

11. What is meant by quasi stable state?

12. How an Op-amp is used to generate square wave?

13. What are the changes to be done in a symmetric square wave generator to generate asymmetric square

wave?14. Write down the design equations of duty cycle and frequency of oscillations for astable circuit.

15. Mention the merits of Instrumentation Amplifier.


38/94



RESULT:

Marks Allocation


Awarded

Preparation 20

Conducting 20


Results 5


Viva-Voice 15

Record 10

Total 100



39/94



CIRCUIT DIAGRAM:

LOW PASS FILTER:

MODEL GRAPH:


40/94



Ex. No:

DESIGN OF FILTER CIRCUITS USING OP-AMP

DATE:

AIM:

To design and test the operation of active filters (Low Pass, High Pass) with the help of Op-Amp.

APPARATUS REQUIRED:

S.No. Name of the Apparatus Range Quantity

1. IC 741 -- 2

2. Resistors 1.6KΩ,10KΩ,5.86K Ω As per the need

3. Capacitors 0.1 µF 2

5. CRO -- 1


7. Probe -- 2

8. Bread Board -- 1

THEORY:

LOW PASS FILTER:

An active filter generally uses an operational amplifier (op-amp) within its design and in the Operational

Amplifier tutorial we saw that an Op-amp has high input impedance, low output impedance and a voltage gain

determined by the resistor network within its feedback loop.

Unlike a passive high pass filter which has in theory an infinite high frequency response, the maximum

frequency response of an active filter is limited to the Gain/Bandwidth product (or open loop gain) of the

operational amplifier being used. Still, active filters are generally much easier to design than passive filters, they

produce good performance characteristics, very good accuracy with a steep roll-off and low noise when used

with a good circuit design. This second order low pass filter circuit has two RC networks, R1 – C1 and R2 – C2

which give the filter its frequency response properties. The filter design is based around a non-inverting op-amp

configuration so the filters gain, A will always be greater than 1. Also the op-amp has a high input impedance

which means that it can be easily cascaded with other active filter circuits to give more complex filter designs.

The normalized frequency response of the second order low pass filter is fixed by the RC network and is

generally identical to that of the first order type. The main difference between a 1st and 2nd order low pass filter

is that the stop band roll-off will be twice the 1st order filters at 40dB/decade (12dB/octave) as the operating

frequency increases above the cut-off frequency ƒc, point as shown.


41/94



HIGH PASS FILTER:

MODEL GRAPH:


42/94



DESIGN:

LPF:

The gain magnitude equation of the Low – Pass filter can be obtained by converting equation into its

equivalent polar form, as follows. | Vo / Vin | = AF/√1+ (f / f l)4

Where

f H = => cut-off frequency of the filter

The operation of the low – pass filter can be verified from the gain magnitude equation. 1. At very low

frequencies, that is

1. f < fH | Vo/Vin | = AF

2. At f = fH, | Vo/Vin | = AF/√2 = 0.707 AF

3. At f > fH | Vo/Vin | < AF

1. Choose a value for the high cut-off frequency, f H(1 KHz).

2. To simplify the design calculations, set R2=R3=R and C2=C3=C. Then choose a value of C1μF

(0.0047 μF).

3. Calculate the value of R using the equation R=1/2Πf r C.

4. Finally, because of the equal resistor (R2=R3) and capacitor (C2=C3) values, the pass band voltage

gain AF = (1+) of the second-order low-pass filter has to be equal to 1.586.That is, Rf = 0.586R1. This

gain is necessary to generate Butterworth response. Hence choose a value of R1100KΩ (33 KΩ) and

calculate the value of Rf.

HIGH PASS FILTER:

The basic electrical operation of an Active High Pass Filter (HPF) is exactly the same as we saw for its

equivalent RC passive high pass filter circuit, except this time the circuit has an operational amplifier or op-amp

included within its filter design providing amplification and gain control.Like the previous active low pass filter

circuit, the simplest form of an active high pass filter is to connect a standard inverting or non-inverting

operational amplifier to the basic RC high pass passive filter circuit as shown.

Second Order High Pass Filter consists of RC networks for filtering. Second Order High Pass filter can

be constructed from a Second Order Low Pass filter simply by interchanging frequency determining

components R & C . Op-Amp is used in the non – inverting configuration. Resistor R1 and RF determine thegain of the Filter.

A first-order high pass active filter can be converted into a second-order high pass filter simply by using

an additional RC network in the input path. The frequency response of the second-order high pass filter is

identical to that of the first-order type except that the stop band roll-off will be twice the first-order filters at

40dB/decade (12dB/octave). Therefore, the design steps required of the second-order active high pass filter are

the same. Higher-order High Pass Active Filters, such as third, fourth, fifth, etc are formed simply by cascading


43/94



TABULATION:

LOW PASS FILTER:

Vin = 1V

S.NO.Input Frequency

f(Hz)

Output Voltage Vo(v)Gain Magnitude

|Vo/Vin|

Gain in dB

20 log |Vo/Vin|


44/94



together first and second-order filters. For example, a third order high pass filter is formed by cascading in

series first and second order f ilters, a fourth-order high pass filter by cascading two second-order filters together

and so on.

HPF:

The gain magnitude equation of the Low – Pass filter can be obtained by converting equation into its

equivalent polar form, as follows. | Vo / Vin | = AF/√1+ (f/f l) 4

Where

f H = => cut-off frequency of the filter

The operation of the low – pass filter can be verified from the gain magnitude equation. 1. At very low

frequencies, that is

1. f < fH | Vo/Vin | = AF

2. At f = fH, | Vo/Vin | = AF/√2 = 0.707 AF

3. At f > fH | Vo/Vin | < AF

1. Choose a value for the high cut-off frequency, f H(1 KHz).

2. To simplify the design calculations, set R2=R3=R and C2=C3=C. Then choose a value of C1μF

(0.0047 μF).

3. Calculate the value of R using the equation R=1/2Πf r C.

4. Finally, because of the equal resistor (R2=R3) and capacitor (C2=C3) values, the pass band voltage

gain AF = (1+) of the second-order low-pass filter has to be equal to 1.586.That is, Rf = 0.586R1

This gain is necessary to generate Butterworth response. Hence choose a value of R1100KΩ (33

KΩ) and calculate the value of Rf.PROCEDURE:

LOW PASS FILTER:

1. Connect the components/equipment as shown in the circuit diagram.

2. Switch ON the power supply.

3. Connect channel -1 of CRO to input terminals (Vin) and channel -2 to output terminals (Vo).

4. Set Vin = 1V & fin=10Hz using function generator.

5.

By varying the input frequency in regular intervals, note down the output voltage.6. Calculate the gain (Vo/Vin) and Gain in dB = 20 log (Vo/Vin) at every frequency.

7. Plot the frequency response curve (taking frequency on X-axis & Gain in dB on Y-axis) using Semi log

Graph.

8. Find out the high cut-off frequency, fH (at Gain= Constant Gain, Af – 3 dB) from the frequency

response plotted.

9. Verify the practical (fH from graph) and the calculated theoretical cut-off frequency (fH = 1/2πRC).


45/94



TABULATION:

HIGH PASS FILTER:

Vin = 1V

S.NO.Input Frequency

f(Hz)Output Voltage Vo(v)

Gain Magnitude

|Vo/Vin|

Gain in dB

20 log |Vo/Vin|


46/94



HIGH PASS FILTER:

1. Connect the components/equipment as shown in the circuit diagram.

2. Switch ON the power supply.

3. Connect channel -1 of CRO to input terminals (Vin) and channel -2 to output terminals (Vo).

4. Set Vin = 1V & fin=10Hz using function generator.

5. By varying the input frequency in regular intervals, note down the output voltage.

6. Calculate the gain (Vo/Vin) and Gain in dB = 20 log (Vo/Vin) at every frequency.

7. Plot the frequency response curve (taking frequency on X-axis & Gain in dB on Y-axis) using Semi log

Graph.

8. Find out the low cut-off frequency, fL (at Gain= Constant Gain, Af – 3 dB) from the frequency response

plotted.

9. Verify the practical (fL from graph) and the calculated theoretical cut-off frequency (fL = 1/2πRC).


47/94



VIVA-QUESTIONS:

1. How filters are classified? Give one example for each classification.

2. What is an active filter and why it is called so?

3. How an active filter differs from a passive filter?

4. What are the advantages of active filters over passive filters?

5. Draw the circuit diagrams of active filters LPF and HPF.

6. Draw the frequency response of all filters (LPF, HPF, BPF, BRF and All-pass).

7. What is the gain roll off rate for a 1st order and 2nd order filter?

8. What is the formula for cut-off frequency?

9. What is a 3 dB frequency and why it is called so?

10. What are the other names for 3 dB frequency?

11. Define UGB.

12. Why 3dB line is used to determine the bandwidth of the device.

13. Mention the merits of active filters.

14. Define magnitude and phase of filter.

15. List the demerits of active filter.


48/94



RESULT:

Marks Allocation


Awarded

Preparation 20

Conducting 20


Results 5


Viva-Voice 15

Record 10

Total 100



49/94



0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5-1

-0.5

0

0.5

1

time

a m p l i t u d e

sine wave

CIRCUIT DIAGRAM:

RC PHASE SHIFT OSCILLATOR:

MODEL GRAPH:


50/94



Ex. No:

DESIGN OF OSCILLATOR CIRCUITS USING OP-AMP

DATE:

AIM:

To design and test the functioning of RC phase shift and Wien Bridge Oscillator circuit with the help of

Op-Amp.

APPARATUS REQUIRED:

S.No. Name of the Apparatus Range Quantity

1. IC 741 -- 2

2. Resistors 1kΩ,1.2kΩ,50k Ω,4.7k Ω,1,5k Ω As per the need

3. Capacitors 0.1 µF,o.001 µF As Per the need

5. CRO -- 1


7. Probe -- 2

8. Bread Board -- 1

THEORY:


RC phase shift oscillator is a sinusoidal oscillator used to produce sustained well shaped sine wave

oscillations. It is used for different applications such as local oscillator for synchronous receivers, musicalinstruments, study purposes etc. The main part of an RC phase shift oscillator is an op amp inverting amplifier

with its output fed back into its input using a regenerative feedback RC filter network, hence the name RC

phase shift oscillator.

By varying the capacitor, the frequency of oscillations can be varied. The feedback RC network has a

phase shift of 60 degrees each, hence total phase shift provided by the three RC network is 180 degrees. The op

amp is connected as inverting amplifier hence the total phase shift around the loop will be 360 degrees. This

condition is essential for sustained oscillations. We have already discussed about RC phase shift oscillator using

transistor.

The feedback network offers 180 degrees phase shift at the oscillation frequency and the op amp is

configured as an Inverting amplifier, it also provide 180 degrees phase shift. Hence to total phase shift around

the loop is 360=0degrees, it is essential for sustained oscillations. At the oscillation frequency each of the

resistor capacitor filter produces a phase shift of 60° so the whole filter circuit produces a phase shift of 180°.


51/94



0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5-1

-0.5

0

0.5

1

time

a m p l i t u d e

sine wave

WEIN BEIDGE OSCILLATOR:

MODEL GRAPH:


52/94



The energy storage capacity of capacitor in this circuit produces a noise voltage which is similar to a

small sine wave, it is then amplified using op amp inverting amplifier.

By taking feedback, the output sine wave also attenuates 1/29 times while passing through the RC

network, so the gain of inverting amplifier should be 29 in order to keep loop gain as unity. The unity loop gain

and 360 degree phase shift are essential for the sustained oscillation. RC Oscillators are stable and provide a

well-shaped sine wave output with the frequency being proportional to 1/RC and therefore, a wider frequency

range is possible when using a variable capacitor. However, RC Oscillators are restricted to frequency

applications because at high frequency the reactance offered by the capacitor is very low so it acts as a short

circuit.

Number of RC stages help improve the frequency stability. The total phase shift introduced by the

feedback network is 180 degrees, if we are using N RC stages each RC section provide 180/N degree phase

shift. When 2 RC sections are cascaded, the frequency stability is low. For 3 sections cascaded the phase change

rate is high so there is improved frequency stability. However for 4 RC sections there is an good phase change

rate resulting in the most stable oscillator configuration. But 4 RC sections increases cost and makes circuit

complexity. Hence phase shift oscillators make use of 3 RC sections in which each section provides a phase

shift of 60 degree. The latter is generally used in high precision applications where cost is not much regarded

and only accuracy plays a major role.

WIEN BRIDGE OSCILLATOR:

Wien bridge oscillator is an audio frequency sine wave oscillator of high stability and simplicity. Before

that let us see what is oscillator? An oscillator is a circuit that produces periodic electric signals such as sine

wave or square wave. The application of oscillator includes sine wave generator, local oscillator for

synchronous receivers etc. Here we are discussing wein bridge oscillator using 741 op amp IC. It is a low

frequency oscillator. The op-amp used in this oscillator circuit is working as non-inverting amplifier mode

Here the feedback network need not provide any phase shift. The circuit can be viewed as a wien bridge with a

series RC network in one arm and parallel RC network in the adjoining arm. Resistors Ri and Rf are connected

in the remaining two arms.

The feedback signal in this oscillator circuit is connected to the non-inverting input terminal so that the

op-amp works as a non-inverting amplifier. The condition of zero phase shift around the circuit is achieved by balancing the bridge, zero phase shift is essential for sustained oscillations.

The frequency of oscillation is the resonant frequency of the balanced bridge and is given by the

expression fo = 1/2πRC. At resonant frequency ( ƒo), the inverting and non-inverting input voltages will be

equal and “in- phase” so that the negative feedback signal will be cancelled out by the positive feedback causing

the circuit to oscillate. From the analysis of the circuit, it can be seen that the feedback factor β= 1/3 at the

frequency of oscillation. Therefore for sustained oscillation, the amplifier must have a gain of 3 so that the loop


53/94



TABULATION:


S.No Measurements Practical Theoretical

1.Amplitude


2.Time period



WEIN BRIDGE OSCILLATOR:

S.No Measurements Practical Theoretical

1.Amplitude


2.Time period



MODEL CALCULATION:


54/94



gain becomes unity. For an inverting amplifier the gain is set by the feedback resistor network Rf and Ri and is

given as the ratio -Rf/Ri.

DESIGN:


Frequency of oscillation (F):

Gain of the Op Amp inverting amplifier (G) :

Attenuation offered by the feedback RC network is 1/29, so the gain of inverting amplifier should be 29

Use R i=1.2 KΩ

So, R f =35KΩ Use 50KΩ potentiometer and adjust its value to obtain output on CRO

WEIN BRIDGE OSCILLATOR:

The required frequency of oscillation fo=1 kHz

We have,

Take C=0.01µF, then R=1.6kΩ (Use 1.5kΩ standard)

Gain of the amplifier section is given by,

Take Ri=1kΩ, then Rf=2.2kΩ (Use 4.7kΩ Potentio meter for fine corrections)


55/94



VIVA-QUESTIONS:

1. Define Oscillator.

2. Mention the types of Oscillator.

3. State Barkhausen Criterion.

4. Infer the function of tank circuit.

5. How the Barkhausen criteria is satisfied with RC Phase shift Oscillator.

6. How the Barkhausen criteria is satisfied with Wien Bridge Oscillator.

7. Mention the requirements for producing sustained Oscillations.

8. List any two audio frequency oscillator.

9. Define Conversion time.

10. Define settling time.

11. Define stability.

12. How will you determine the stability of an Oscillator?

13. Mention the factors affecting sustained oscillations.

14. What are the problems associated with switch type phase detector.

15. Why do we need compensation in the feedback circuit.


56/94



RESULT:

Marks Allocation


Awarded

Preparation 20

Conducting 20


Results 5


Viva-Voice 15

Record 10

Total 100



57/94



CIRCUIT DIAGRAM:

4-BIT R/2R LADDER DAC:

DESIGN:

Output voltage,42

432

322

212

1 bbbb

R

f R

RV oV

Binary value=1000(given)

Output voltage=6v (given)

Reference resistor =10K (given)

Reference Voltage, VR =10V (given)

R f =12k

Resolution,

f R

R

RV

nV

2

1

k k

V V 12

10

10

42

1

75.0V


58/94



AIM:

To design R-2R ladder type and weighted resistor type DAC using op-amp.

To design and test a 4- bit Flash type A/D converter using op-amp.

APPARATUS REQUIRED:


1. Dual RPS 0 - 30 V 3

2. Op-Amp IC 741 1

3. Bread Board - 1

4. Resistors10K ,470 4

20K , 1K 4

5. DPDT(switch) - 1

6. Single RPS 0-30 V 1

7. LED - 4

THEORY:

In R-2R ladder type D to A converter, only two values of resistor is used (i.e. R and 2R). Hence it is

suitable for integrated circuit fabrication. The typical values of R are from 2.5K to 10K . In this output

voltage is a weighted sum of digital inputs. Since the resistive ladder is a linear network, the principle of super

position can be used to find the total analog output voltage for a particular digital input by adding the output

voltages caused by the individual digital inputs.

Digital systems are used in ever more applications, because of their increasingly

efficient, reliable, and economical operation with the development of the microprocessor, data

processing has become an integral part of various systems Data processing involves transfer

of data to and from the microcomputer via input/output devices. Since digital systems such a

microcomputers use a binary system of ones and zeros, the data to be put into the microcomputer must be

converted from analog to digital form. On the other hand, a digital-to-analog

converter is used when a binary output from a digital system must be converted to some

equivalent analog voltage or current. The function of DAC is exactly opposite to that of an

ADC.

Ex. No:DESIGN OF D-A AND A-D CONVERETER USING OP-AMP

DATE:


59/94



CIRCUIT DIAGRAM:

BINARY WEIGHTED RESISTOR DAC:

DESIGN:

I = I +I +.......+In10 2

V V VR R RI = d + d +...........+ dnn10 222R 2 R2 R

V -1 -2 -nRI = (d 2 +d 2 +........+d 2 )n10 2R

The output voltage,

R -1 -2 -nf V = I R = V (d 2 +d 2 +........+d 2 )nR 10 0 2f R

TABULATION:

WEIGHTED RESISTOR:

S.No D C B A Theoretical voltage (mv) Practical Voltage (mv)

R-2R LADDER:

S.No D C B A Theoretical voltage (mv) Practical Voltage (mv)


60/94



A DAC in its simplest form uses an op-amp and either binary weighted resistors or R-

2R ladder resistors. In binary-weighted resistor op-amp is connected in the inverting mode, it can also be

connected in the non-inverting mode. Since the number of inputs used is four, the converter is called a 4-bi

binary digital converter.

A-D CONVERTER:

The analog to digital converter is normally required at the input of a digital system for the measurement

or control of analog quantities. In A/D converters, the input is an analog voltage and the output is a digital code

A/D converters are more complex and time consuming than D/A converters.

A/D converters can be designed with or without the use of D/A converters as part of their circuitry. The

commonly used types of A/D converters incorporating D/A converters are (a) Successive- approximation

converter and (b) Counting or digital ramp converter.

PROCEDURE:

D-A CONVERTER:


3. The power supply is switched on.

4. Reference voltage is set as 10V.

5. Binary values are applied according to the binary input values.

6. The output voltage is noted down.

7. The output voltage obtained is compared with the given output voltage.

A-D CONVERTER:

1. Make the connections as per the circuit diagram

2. Switch on the power supply

3. The variable terminal of the potentiometer is given to the analog input channel 2.

4. To select the analog input channel 2, the channel select switch position is as follows

SW1 SW2 SW3

0 1 0

5. The Start of Conversion (SOC) button is pressed once to start the conversion.


61/94



CIRCUIT DIAGRAM:

A-D CONVERTER:

TABULATION:

S.No Analog Input in (Volts)Digital Output

B3 B2 B1 B0


62/94



6. The digital output for the corresponding analog input is displayed on LEDs D0 throughD7.

7. The address latch enable (ALE) button is also pressed once, so as to enable the digital data to be sent

to the output

8. The End of Conversion (EOC) is indicated by the LED 10

9. The above procedure is repeated for different values of analog voltages.


63/94



MODEL GRAPH:

VIVA QUESTIONS:

1. Mention any two specifications of a DAC.

2. Name any two types of ADC.

3. In a binary ladder network of a DAC, the value of the smaller resistance is 10 k .What is the resistance

value of the other set?

4. What output voltage would be produced by a DAC whose output range is 0 to 10V and whose input binary

number is 10 (for a 2 – bit DAC)?

5. What is the range value for resistor (R) in DAC?

6.

What is meant by the word resolution in reference to an ADC or a DAC? Why is resolution important to us,and how may it be calculated for any particular circuit knowing the number of binary bits?

7. The practical use of binary-weighted digital-to-analog converters is limited to:

8. The difference between analog voltage represented by two adjacent digital codes, or the analog step size is

__________

9. The primary disadvantage of the flash analog-to digital converter (ADC) is __________

10. A binary-weighted digital-to-analog converter has a feedback resistor, R f , of 12 k . If 50 A of current is

through the resistor, the voltage out of the circuit is:

11. What is the major advantage of the R/2R ladder digital-to-analog (DAC), as compared to a binary-weighted

digital-to-analog DAC converter?

12. The resolution of a 0 – 5 V 6-bit digital-to-analog converter (DAC) is:

13. In a flash analog-to-digital converter, the output of each comparator is connected to an input of a:

14. Which is not an analog-to-digital (ADC) conversion error?

15. Sample-and-hold circuits in analog-to digital converters (ADCs) are designed for________


64/94



RESULT:

Marks Allocation


Awarded

Preparation 20

Conducting 20


Results 5


Viva-Voice 15

Record 10

Total 100



65/94



PIN DIAGRAM OF IC555:

CIRCUIT DIAGRAM:

MODEL GRAPH:

VCC

Discharge

Threshold

Control Voltage

Trigger

Output

Reset

Ground

5555

VOD

RA

6.8k

Vcc

+5 V

0.01 F

0. 1 F

RB

3.3k

7

2

6

1 5

8 4

3

5555

Vc

t(ms)

VUT

VUT

t high

tlow

t(ms)

VO


66/94



Ex. No:DESIGN OF

MONOSTABLE AND ASTABLE MULTIVIBRATORS USING IC555

DATE:

AIM:

To design and test an Astable and Monostable Multivibrators using 555 timer with duty cycle ratio.

APPARATUS REQUIRED:


1. 555 TIMER -- 1

2. Resistors 3.3K, 6.8k 1

3. Capacitors 0.1 µF,0.01 µF 2

4. Diode IN4001 1

5. CRO -- 1

6. Power supply ±15 V 1

7. Probe -- 2

8. Bread Board -- 1

THEORY:

ASTABLE MULTIVIBRATORS USING 555:

The 555 timer connected as an Astable Multivibrators. Initially, when the output is high. Capacitor C

starts charging towards Vcc through R A and R B. As soon as capacitor voltage equals 2/3 Vcc upper comparator

(UC) triggers the flip flop and the output switches low. Now capacitor C starts discharging through R B and

transistor Q1.

When the voltage across C equals 1/3 Vcc lower comparator (LC), output triggers the flip-flop and the

output goes high. Then the cycle repeats.

The capacitor is periodically charged and discharged between 2/3 Vcc and 1/3 Vcc respectively. The time

during which the capacitor charges form 1/3 Vcc to 2/3 Vcc is equal to the time the output is high and is given by

T c = 0.69(R A+R B) C (1)

Where R A and R B are in Ohms and C is in farads. Similarly the time during which the capacitor

discharges from 2/3 Vcc to 1/3 Vcc is equal to the time the output is low and is given by

T d = 0.69 R B C (2)


67/94



CIRCUIT DIAGRAM:

MODEL DIAGRAM:

VO

RA10k

Vcc

+5 V

0.01 F

0. 1 F

7

6

1 5

8 4

3

555

2Trigger i/p

0.01 F


68/94



The total period of the output waveform is

T = T c + T d = 0.69 (R A + 2R B) C (3)

The frequency of oscillation

f o = 1 / T =1.45 / (R A+2R B)C (4)

Eqn (4) shows that fo is independent of supply voltage Vcc

The duty cycle is the ratio of the time td during which the output is low to the total time period T. This

definition is applicable to 555 A stable Multivibrators only: conventionally the duty cycle ratio is defined as the

ratio as the time during which the output is high to the total time period.

Duty cycle = td T

R B + R A+ 2R B

Obtain 50% duty cycle a diode should be connected across R B and R A must be a combination of a fixed

resistor and a potentiometer. So that the potentiometer can be adjusted for the exact square waves

MONOSTABLE MULTIVIBRATORS USING 555

Monostable Multivibrators has one stable state and other is a quasi-stable state. The circuit is useful for

generating single output pulse at adjustable time duration in response to a triggering signal. The width of the

output pulse depends only on external components, resistor and a capacitor.

The stable state is the output low and quasi stable state is the output high. In the stable state transistor

Q1 is „on‟ and capacitor C is shorted out to ground. However upon application of a negative trigger pulse to pin2, Q1 is turned „off‟ which releases the short circuit across the external capacitor C and drives the outpu

high. The capacitor C now starts charging up towards V cc through R A. However when the voltage across C

equal 2/3 Vcc the upper comparator output switches form low to high which in turn drives the output to its low

state via the output of the flip flop. At the same time the output of the flip flop turns Q1 „on‟ and hence C

rapidly discharges through the transistor. The output remains low until a trigger is again applied. Then the cycle

repeats. The pulse width of the trigger input must be smaller than the expected pulse width of the output. The

trigger pulse must be of negative going signal with amplitude larger than 1/3 Vcc. The width of the output pulse

is given by,

T = 1.1 R AC

DESIGN:

Design an Astable Multivibrators for a frequency of ______KHz with a duty cycle ratio of

D = 50%


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TABULATION:

MONOSTABLE MULTIVIBRATOR:


1.

Amplitude


2.

Time period



ASTABLE MULTIVIBRATOR:


1.

Amplitude


2.

Time period




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fo = 1/T = 1.45 / (R A+2R B)C

Choosing C = 1 µF

R A = 560k Ω

D = R B / R A +2R B= 0.5 [50%]

R B = ______

DESIGN:

Given a pulse width of duration of 100 µs

Let C = 0.01 mfd

F = _________KHz

Here,

T= 1.1 R AC

So, R A =

PROCEDURE:

1. Rig-up the circuit of 555 Astable Multivibrators as shown in fig with the designed value of components.

2. Switch on the power supply to CRO and the circuit.

3. Connect the CRO probes to pin 3 and 2 to display the output signal and the voltage across the timing

capacitor. Set suitable voltage sensitively and time-base on the CRO.

4. Observe the waveforms on the CRO and draw to scale on a graph sheet. Measure the voltage levels at

which the capacitor starts charging and discharging, output high and low timings and frequency.

5. Switch off the power supply. Connect a diode across R B as shown in dashed lines in fig to make the

Astable with 50 % duty cycle ratio. Switch on the power supply. Observe the output waveform. Draw to

scale on a graph sheet.


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VIVA-QUESTIONS:

1. What are the features of 555 timers?

2. What are the applications of 555 timers?

3. Define duty cycle ratio.

4. What are the applications of Monostable Multivibrators?

5. What is meant by quasi stable state?

6. What should be the amplitude of trigger pulse?

7. What is other name for A stable Multivibrators?

8. How an Op-amp is used to generate square wave?

9. What are the changes to be done in a symmetric square wave generator to generate asymmetric square

wave?

10. What are the basic elements of 555 Timer?

11. What is the function of pin2 in IC555?

12. List down the applications of a stable Multivibrator in IC555.

13. Write down the design equations of duty cycle and frequency of oscillations for a stable circuit.


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RESULT:

Marks Allocation


Awarded

Preparation 20

Conducting 20


Results 5


Viva-Voice 15

Record 10

Total 100



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PIN DIAGRAM: (IC 565 & IC7490)

FREQUENCY MULTIPLIER:


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Ex. No: DESIGN OF FREQUENCY MULTIPLIER AND DIVIDER CIRCUIT USING

PHASE LOCKED LOOP(PLL)DATE:

AIM:

To construct and verify the output of the frequency multiplier and divider application circuits using PLL (IC565).APPARATUS REQUIRED:

S.NO APPARATUS NAME RANGE QUANTITY

1. RPS (0-30) Volts 2

2. Signal generator 1MHz 1

3. CRO 20MHz 1

4. Resistors 20K ,2K ,4.7K ,10K Each Two

5. PLL and Counter IC565,IC7490 1

6. Capacitors 0.01µF, 0.001µF, 10µF 1

7. Transistor 2N2222 1

THEORY:

In the frequency multiplier using PLL565, a divided by N network is inserted between the VCO output and the

phase comparator input. Since the output of the comparator is locked to the input frequency fin, the VCO is running at a

multiple of the input frequency. Therefore in the locked state the VCO output frequency fo is given by,

fo= N*fin

FREQUENCY MULTIPLIER:

The block diagram of a frequency multiplier (or synthesizer) is shown in figure. In this circuit, a

frequency divider is inserted between the output of the VCO and the phase comparator (PC) so that the loop

signal to the PC is at frequency f OUT while the output of VCO is N f OUT. This output is a multiple of the input

frequency as long as the loop is in lock. The desired amount of multiplication can be obtained by selecting a

proper divide- by N network where N is an integer. Figure shows this function performed by a 7490 configured

as a divide-by-4 circuit.In this case the input V in at frequency /in is compared with the output frequency f OUT at pin 5. An outpu

at N f OUT (4 f OUT in this case) is connected through an inverter circuit to give an input at pin 14 of the 7490,

which varies between 0 and + 5 V. Using the output at pin 9, which is one-fourth of that at the input to the 7490

the signal at pin 4 of the PLL is four times the input frequency as long as the loop remains in lock. Since the

VCO can be adjusted over a limited range from its centre frequency, it may become necessary to change the CO

frequency whenever the divider value is changed. For verification of the circuit operation,


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TABULATION:

Vin=

S.No. fin (Hz) fo (Hz)Multiple Factor

Designed Obtained

MODELGAPH:


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one must determine the input frequency range and then adjust the free running f OUT of the VCO by

means of R 1 and C 1 so that the output frequency of the 7490 divider is midway within the predetermined input

frequency range. The output of VCO should now be equal to 4 f in.

PROCEDURE:

1. The connections are given as per the circuit diagram.

2. The circuit uses a 4- bit binary counter 7490 used as a divide-by-5 circuit.

3. Measure the free running frequency of VCO at pin 4, with the input signal Vi set equal to zero. Compare

it with the calculated value = 0.25 / (RT CT).

4. Now apply the input signal of 1 VPP square wave at 500 Hz to pin 2.

5. Vary the VCO frequency by adjusting the 20kΩ potentiometer till the PLL is locked. Measure the output

frequency. It should be 5 times the input frequency.

6. Repeat steps 4,5 for input frequency of 1 kHz and 1.5 kHz.


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VIVA QUESTIONS:

1. List the basic building blocks of a PLL.

2. Define Capture range.

3. Define lock range.

4. Define pull in time.

5. Which is greater Capture range or pull in time?

6. What is the major difference between digital and analog PLLs?

7. List the application of PLL.

8. What is the range of modulating input voltage applied to a VCC?

9. What is meant by VCO? What is the need of it in PLL?

10. Why the low pass filter circuit is need in the PLL?

11. Define accuracy of converter.

12. Define resolution.

13. What are the factors which might determine the choice of either a synchronous or asynchronous FSK

demodulator ?

14. Mention the merits and demerits of PLL.

15. Mention the applications of PLL in communication areas.


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RESULT:

Marks Allocation


Awarded

Preparation 20

Conducting 20


Results 5


Viva-Voice 15

Record 10

Total 100



79/94



CIRCUIT DIAGRAM OF HALF WAVE RECTIFIER:

MODEL GRAPH:

TABULATION:

S.No.

Input Output

Amplitude

( No. of div x

Volts per div )

Time period

(No. of div x Time

per div )

Amplitude

( No. of div x Volts

per div )

Time period

(No. of div x Time

per div )

1.

2.


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AIM:

To construct and study the working of half wave and full wave precision rectifiers using op-amp IC.

APPARATUS REQUIRED:


1. CRO 30 MHz 1

2. Dual RPS 0 – 30 V 1

3. Op-Amp IC741 3 Nos

4. Bread Board - 1


8. Resistors 10K,4.7K Each 6

9. Diode IN4007 2 Nos

THEORY:

DEISGN:

All the resistances are chosen as 10 Ohms and this condition make output voltage is equal to the input

voltage.

Matched diodes are used to obtain equal response in both positive and negative side signal transition. If

matched are not used for full wave rectifier the positive halves of the rectified wave will not be equal. Precision

rectifier rectifies voltages of the order of millivolts much lower than the cut in voltage of diodes. All the

resistances are chosen in kilo ohm range so that the AFO is not loaded and much greater than the output

resistance of AFO (50 ohm).

Resistances used in the design are 1Kohm and 10Kohms .The maximum voltages across the resistance will

be supply voltage. Hence wattage of resistance is V2 / R. V2 /R= 225 / 10K which is so much lower than 1/8W or

1/4W.So resistances with 5% tolerance, carbon film resistor with 1/8W or 1/4W is used.

HALF WAVE RECTIFIER:

There are several different types of precision rectifier In its simplest form, a half wave precision rectifier

is implemented using an opamp, and includes the diode in the feedback loop. This effectively cancels the

forward voltage drop of the diode, so very low level signals (well below the diode's forward voltage) can still be

rectified with minimal error.

Ex. No:DESIGN OF HALF WAVE AND FULL WAVE RECTIFIERS USING OP-AMP

DATE:


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CIRCUIT DIAGARM OF FULL WAVE RECTIFIER:

MODEL GRAPH:

TABULATION:

S.No.

Input Output

Amplitude

( No. of div x

Volts per div )

Documents

40 Ei 4p2-Lic Lab Manual