4 Z-80 Microprocessor - Universitas Brawijayamikroprosesor.lecture.ub.ac.id/files/2010/08/4-Z... · Address Bit Map A15 to A0 (HEX) AA AA 11 11 54 32 AAAA 1198 10 AAAA 7654 AAAA 3210

Z‐80Microprocessor

Addressing Modes • Immediate • Immediate Extended • Modified Page Zero Addressing (rst p) • Relative Addressing

– Jump Relative (2 byte) • One Byte Op Code • 8-Bit Two’s Complement Displacement (A+2)

• Extended Addressing – Absolutejump

• Onebyteopcode• 2byteaddress

• Indexed Addressing – (Index Register + Displacement) (IX+d) – 2byteopcode– 1bytedisplacement

Addressing Modes(cont.) • Register Addressing

– LD C,B • Implied Addressing

– Op Code implies other operand(s) – ADD E

• Register Indirect Addressing – 16-bit CPU register pair as pointer (such as

HL) – ADD (HL)

• Bit Addressing – set, reset, and test instructions. – SET 3,A – RES 7,B

Minimal Configuration of a Z80 Microcomputer

Z80Memoryconnec<on

• CPU16bitaddressbus64kmemory(max)• CPU8bitdatabus8bitdatawidth

• Generallyshouldbeconnected– Datatodata– Addresstoaddress– Wrtowr

– Rdtord– Mreqtocs

Memory connection (cont.)

RAM64kb

Z80CPU

D7~D0D7~D0

A15~A0A15~A0

If only one RAM chip Full size (64 kb capacity)


RAM32kb

Z80CPU

D7~D0D7~D0

A14~A0A14~A0

A15

If RAM capacity was 32 kb A15 composed with MREQ RAM area is from 0000h to 7FFFh


• Thereistwo32kbRAM• Problem:BusConflict.Thetwomemorychipswillprovidedataatthesame<mewhenmicroprocessorperformsamemoryread.

• Solu<on:UseaddresslineA15asan“arbiter”.IfA15outputsalogic“1”theuppermemoryisenabled(andthelowermemoryisdisabled)andvice‐versa.


RAM32kb

Z80CPU

D7~D0D7~D0

A14~A0A14~A0

RAM32kb

D7~D0

A14~A0

A15

There is two 32 kb RAM A15 applied to select one RAM chip TwoRAM area is from 0000h to 7FFFh (RAM1) and 8000h to FFFFh(RAM1)


ROM32kb

Z80CPU

D7~D0D7~D0

A14~A0A14~A0

RAM32kb

D7~D0

A14~A0

A15

32 kb ROM and 32 kb RAM ROM doesn’t have wr signal


Z80CPU

ROM16kb

D7~D0D7~D0

A13~A0A13~A0

RAM16kb

D7~D0

A13~A0

A15

RAM16kb

D7~D0

A13~A0

RAM16kb

D7~D0

A13~A0

A14 En

S0S1

There is 4 memory chip A14 and A15 applied to chip selection

Address Bit Map

A15 to A0 (HEX)

AA AA 11 11 54 32

AAAA 1198

10

AAAA 7654

AAAA 3210

Memory Chip

0000h

3FFFh

00 00

00 11

0000

1111

0000

1111

0000

1111 ROM

4000h

7FFFh

01 00

01 11

0000

1111

0000

1111

0000

1111 RAM1

8000h

BFFFh

10 00

10 11

0000

1111

0000

1111

0000

1111 RAM2

C000h

FFFFh

11 00

11 11

0000

1111

0000

1111

0000

1111 RAM3

Selects location within chips Selects chip

Memory Map • Representsthememorytype

• Addressareaofeachmemorychip

• Emptyarea

0000h

3FFFh

ROM 16k

4000h

7FFFh

RAM1 16k

8000h

BFFFh

RAM2 16k

C000h

FFFFh

RAM3 16k

ROM16kb

D7~D0D7~D0

A13~A0A13~A0

RAM16kb

D7~D0

A13~A0

A15

RAM16kb

D7~D0

A13~A0

RAM16kb

D7~D0

A13~A0

A14

En

S0

S1

Memory Map • EmptyAreacann’twriteandread

• Readop.returnsFFhvalue(usualy)

• Writeop.cann’tstoreanyvalueonit

0000h

3FFFh ROM

4000h

7FFFh

Empty

8000h

BFFFh RAM2

C000h

FFFFh RAM3

ROM16kb

D7~D0D7~D0

A13~A0A13~A0

A15

RAM16kb

D7~D0

A13~A0

RAM16kb

D7~D0

A13~A0

A14

En

S0

S1

Memory Map • EmptyAreacann’twriteandread

• Readop.returnsFFhvalue(usualy)

• Writeop.cann’tstoreanyvalueonit

0000h

3FFFh ROM

4000h

7FFFh

Empty

8000h

BFFFh RAM

C000h

FFFFh Empty

ROM16kb

D7~D0D7~D0

A13~A0A13~A0

A15

RAM16kb

D7~D0

A13~A0

A14

En

S0

S1

Full and Partial Decoding

• Full(exhaust)Decoding– Alloftheaddresslinesareconnectedtoanymemory/deviceto

performselec<on

– Absoluteaddress:anymemoryloca<onhasoneaddress

• Par<alDecoding– Whensomeoftheaddresslinesareconnectedthememory/deviceto

performselec<on

– Usingthistypeofdecodingresultsintoroll‐overaddresses(foldbackorshading).

– roll‐overaddress:anymemoryloca<onhasmorethanoneaddress

Partial Decoding • A15~A12hasnoconnec<on• Thendoesn’tplayanyroleinaddressing• WhatistheMemoryandAddressBitmap?

RAM4kb

Z80CPU

D7~D0D7~D0

A11~A0A11~A0

X A15~A12

Partial Decoding

A15 to A0 (HEX)

AAAA 1111 5432

AAAA 1198 10

AAAA 7654

AAAA 3210

Memory Chip

X000h

XFFFh

xxxx

xxxx

0000

1111

0000

1111

0000

1111 RAM

RAM4kb

Z80CPU

D7~D0D7~D0

A11~A0A11~A0

XA15~A12

0000h

0FFFh RAM

1000h 1FFFh RAM’

2000h 2FFFh

RAM’

3000h 3FFFh

RAM’

F000h

FFFFh RAM’

Every memory location has more than one address For example first RAM location has addresses:

0000h 1000h 2000h 3000h ……………. …………….

F000h

Roll-over Address

Partial Decoding • A12onlyconnectedtoRAM• A13hasnoconnec<on• Whatisthememorymap?

ROM4kb

Z80CPU

D7~D0D7~D0

A11~A0A12~A0

RAM8kb

D7~D0

A12~A0

A14

A15

X A13

Partial Decoding • 8roll‐overaddressforROM

• 4roll‐overaddressforRAM

AAAA 1111 5432

AAAA 1198 10

AAAA 7654

AAAA 3210

Memory Chip

0xxx

0xxx

0000

1111

0000

1111

0000

1111 ROM

X0x0

X0x1

0000

1111

0000

1111

0000

1111 RAM

ROM4kb

Z80CPU

D7~D0D7~D0

A11~A0A12~A0

RAM8kb

D7~D0

A12~A0

A14

A15

X A13

Partial Decoding

AAAA 1111 5432

AAAA 1198 10

AAAA 7654

AAAA 3210

Memory Chip

0xxx

0xxx

0000

1111

0000

1111

0000

1111

4k

ROM

X0x0

X0x1

0000

1111

0000

1111

0000

1111

8k

RAM

0000h

1FFFh

RAM’ 0000h 0FFFh

ROM 1000h 1FFFh ROM’

2000h

3FFFh RAM’

2000h 2FFFh ROM’ 3000h 3FFFh ROM’

4000h

5FFFh


6000h

7FFFh


8000h

9FFFh RAM

F000h

FFFFh

A000h

BFFFh RAM’

C000h

DFFFh E000h

FFFFh

ROM4kb

Z80CPU

D7~D0D7~D0

A11~A0A12~A0

RAM8kb

D7~D0

A12~A0

A14

A15

X A13

Conflict

Partial Decoding

AAAA 1111 5432

AAAA 1198 10

AAAA 7654

AAAA 3210

Memory Chip

0xxx

0xxx

0000

1111

0000

1111

0000

1111

4k

ROM

X1x0

X1x1

0000

1111

0000

1111

0000

1111

8k

RAM

0000h

1FFFh

0000h 0FFFh

ROM 1000h 1FFFh ROM’

2000h

3FFFh


4000h

5FFFh

RAM’ 4000h 4FFFh ROM’ 5000h 5FFFh ROM’

6000h

7FFFh RAM’


8000h

9FFFh

F000h

FFFFh

A000h

BFFFh C000h

DFFFh RAM

E000h

FFFFh RAM’

ROM4kb

Z80CPU

D7~D0D7~D0

A11~A0A12~A0

RAM8kb

D7~D0

A12~A0

A14

A15

X A13

Conflict

Full (exhaustive) decoding

74138

Y0

Y1

Y2

Y3

Y6

Y4

Y7

Y5

C

B

A

G2A

G2B

G1

2764EPROM8k×8

D7~D0A12~A0

6116RWM2k×8

D7~D0A10~A0

D7~D0

A12~A0

A10~A0

A13

A12

A11

A15

A14

7421

0000h-07FFh

0800h-0FFFh

1000h-17FFh

1800h-1FFFh

2000h-27FFh

AAAA 1111 5432

AAAA 1198

10

AAAA 7654

AAAA 3210

Memory Chip

0000

0001

0000

1111

0000

1111

0000

1111 ROM

0010

0010

0000

0111

0000

1111

0000

1111 RAM

Partial decoding

74138

Y0

Y1

Y2

Y3

Y6

Y4

Y7

Y5

C

B

A

G2A

G2B

G1

2764EPROM8k×8

D7~D0A12~A0

6116RWM2k×8

D7~D0A10~A0

D7~D0

A12~A0

A10~A0

A15

A14

A13

0000h-1FFFh

2000h-3FFFh

AAAA 1111 5432

AAAA 1198

10

AAAA 7654

AAAA 3210

Memory Chip

0000

0001

0000

1111

0000

1111

0000

1111 ROM

001x

001x

x000

x111

0000

1111

0000

1111 RAM

GND

VCC

1 Bit Memory With Separated I/O

2147RWM4k×1

DoutA11~A0

Din

2147RWM4k×1

DoutA11~A0

Din

2147RWM4k×1

DoutA11~A0

Din

D0 D1 D7

D7-D0

A11-A0 A11-A0 A11-A0

What is the memory(addr. bit) map

D0

2147RWM4k×1

DoutA11~A0

Din

2147RWM4k×1

DoutA11~A0

Din

2147RWM4k×1

DoutA11~A0

Din

D1 D7 D7-D0

A11-A0 A11-A0 A11-A0

2764EPROM8k×8

D7~D0A12~A0

74138

Y0

Y1

Y2

Y3

Y6

Y4

Y7

Y5

C

B

A

G2A

G2B

G1

0000h-1FFFh

2000h-3FFFh

A15

A14

A13

GND

VCC

Adding RAM & ROM

Minimum Z80 Computer System

Z80‐µP‐Family(TypicalEnvironment)

Z80 Input Output Z80 at most could have 256 input port and 256 output 8 bit port address is placed on A7–A0 pin to select the I/O device OUT (n), A

n is 8 bit port address Content of A is data

OUT (C), r Content of C is a port address r is a data register

IN A, (n) n is 8 bit port address Data is transfered to A

IN r (C) Content of Reg C is a port address Input data is transfered to r (data reg)

Remember IO read/write cycle

Z80 and simple output port

Z80 CPU

A14A0:D7D6

WRIORQ

A15

D5D4D3D2D1D0

A7A6A5A4A3A2A1A0IOWR

74LS373

Q0Q1Q2Q3Q4Q5Q6Q7

D0D1D2D3D4D5D6D7

OELE

OUT(03),A

Z80 and simple input port

Z80 CPU

A14A0:D7D6

RDIORQ

A15

D5D4D3D2D1D0

A7A6A5A4A3A2A1A0IORD

74LS244

A0A1A2A3A4A5A6A7

Y0Y1Y2Y3Y4Y5Y6Y7

G1G2

5VINA,(02)

8088 and simple output port

A15

8088Minimum

Mode

A18A0:D7D6

IORIOW

A19

D5D4D3D2D1D0

A14A13A12A11A10A9A8A7A6A5A4A3A2A1A0IOW

74LS373

Q0Q1Q2Q3Q4Q5Q6Q7

D0D1D2D3D4D5D6D7

OELE

8088 and simple input port

A15

8088Minimum

Mode

A18A0:D7D6

IORIOW

A19

D5D4D3D2D1D0

A14A13A12A11A10A9A8A7A6A5A4A3A2A1A0IOW

Whatisthis?

74LS244

A0A1A2A3A4A5A6A7

Y0Y1Y2Y3Y4Y5Y6Y7

G1G2

5V

Simplified Drawing of 8088 Minimum Mode

D7 - D0 Q7 - Q0OELE 74LS373

D7 - D0 Q7 - Q0OELE 74LS3738088

AD7 - AD0

A15 - A8

A19/S6 - A16/S3

DENDT / R

IO / MRD

WR

ALE

D7 - D4 Q7 - Q4

OELE 74LS373D3 - D0 Q3 - Q0

GND

GND

GND

A7 - A0 B7 - B0EDIR 74LS245

MEMR MEMW

IOR IOW

A7-A0

A15-A8

A19-A16

D7-D0

Minimum Mode 220 bytes or 1MB memory

1 MB Memory

D7 - D0

A19 - A0

RDWR

SimplifiedDrawing of

8088 MinimumMode

D7 - D0

A19 - A0

MEMRMEMW

CS

Whatarethememoryloca<onsofa1MB(220bytes)Memory?

A19 to A0

(HEX)

AAAA 1111 9876

AAAA 1111 5432

AAAA 1198

10

AAAA 7654

AAAA 3210

00000 0000 0000 0000 0000 0000

FFFFF 1111 1111 1111 1111 1111

Example: 34FD0

0011 0100 11111 1101 0000

Minimum Mode 512 kB memory

512 kB Memory

D7 - D0

A18 - A0

RDWR


8088 MinimumMode

D7 - D0

A18 - A0

MEMRMEMW

CS

A19 What do we do with A19?

1) Don’t connect it 2) Connect to cs

What is the difference?

512 kB Memory Map

• Don’tconnectit– A19isnotconnectedtothe

memorysoevenifthe8088microprocessoroutputsalogic“1”,thememorycannot“see”it.

– A19=0isthesameasA19=1forMemory

• Connecttocs– IfA19=0Memorychipact

normalfanc<on

00000h

7FFFFh

512k Mem

80000h

FFFFFh

512k Mem’

00000h

7FFFFh

512k Mem

80000h

FFFFFh Empty

2 × 512 kB memory

512 kB RAM1

D7 - D0

A18 - A0RDWR


8088 MinimumMode

D7 - D0

A18 - A0MEMR

MEMW

CS

A19

MEMRMEMW

512 kB RAM2

D7 - D0

A18 - A0RDWR

MEMRMEMW

CS

2 × 512 kB memory

AAAA 1111 9876

AAAA 1111 5432

AAAA 1198

10

AAAA 7654

AAAA 3210

Memory Chip

0000

0111

0000

1111

0000

1111

0000

1111

0000

1111 ROM

1000

1111

0000

1111

0000

1111

0000

1111

0000

1111 RAM

00000h

7FFFFh

512k RAM1

80000h

FFFFFh

512k RAM2

What are the memory locations of two consecutive 512KB (219 bytes) Memory?

Interfacingfour256KMemoryChipstothe8088Microprocessor

8088Minimum

Mode

A17A0:

D7D0:

MEMRMEMW

A18

256KB#3

A17A0:D7D0:RDWRCS

A19

256KB#2

A17A0:D7D0:RDWRCS

256KB#1

A17A0:D7D0:RDWRCS

256KB#4

A17A0:D7D0:RDWRCS

Interfacingfour256KMemoryChipstothe8088Microprocessor

8088Minimum

Mode

A17A0:

D7D0:

MEMRMEMW

A18

256KB#3

A17A0:D7D0:RDWRCS

A19

256KB#2

A17A0:D7D0:RDWRCS

256KB#1

A17A0:D7D0:RDWRCS

256KB#4

A17A0:D7D0:RDWRCS

Memory chip#__ is mapped to:

AAAA 1111 9876

AAAA 1111 5432

AAAA 1198

10

AAAA 7654

AAAA 3210 Memory

Chip

RAM#1

RAM#2

RAM#3

RAM#4

Interfacing several 8K Memory Chips to the 8088 µP

8088Minimum

Mode

A12A0:

D7D0:

MEMRMEMW

A13A14

8KB#2

A12A0:D7D0:RDWRCS

8KB#1

A12A0:D7D0:RDWRCS

8KB#?

A12A0:D7D0:RDWRCS

A15A16A17A18A19

::

Interfacing 128 8K Memory Chips to the 8088 µP

8088Minimum

Mode

A12A0:

D7D0:

MEMRMEMW

A13A14

8KB#2

A12A0:D7D0:RDWRCS

8KB#1

A12A0:D7D0:RDWRCS

8KB#128

A12A0:D7D0:RDWRCS

A15A16A17A18A19

::

Interfacing 128 8K Memory Chips to the 8088 µP 8088

MinimumMode

A12A0:

D7D0:

MEMRMEMW

A13A14

8KB#2

A12A0:D7D0:RDWRCS

8KB#1

A12A0:D7D0:RDWRCS

8KB#128

A12A0:D7D0:RDWRCS

A15A16A17A18A19

::

Memory chip#__ is mapped to:

AAAA 1111 9876

AAAA 1111 5432

AAAA 1198

10

AAAA 7654

AAAA 3210 Memory

Chip

RAM#1

RAM#2

RAM#126

RAM#127

RAM#128

What is the Memory and Address Bit map?

74138

Y0

Y1

Y2

Y3

Y6

Y4

Y7

Y5

C

B

A

G2A

G2B

G1

2764EPROM8k×8

D7~D0A12~A0

6116RWM2k×8

D7~D0A10~A0

D7~D0

A12~A0

A10~A0

A14

A13

A12

A15

7408

VCC

74244 input

Documents

4 Z-80 Microprocessor - Universitas Brawijayamikroprosesor.lecture.ub.ac.id/files/2010/08/4-Z... · Address Bit Map A15 to A0 (HEX) AA AA 11 11 54 32 AAAA 1198 10 AAAA 7654 AAAA 3210