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4 Service Mianual Nakamichi
Nakamichi OMS-5
CONTENTS
10. 11.
General é 6-e scent diene ee ew ks g: thy me Beacham io tara eR cae to eet. tae es ee Gees Seria eee irterie sto fede 2 Pickup Replacement Procedures ... 2... cee ee eee ee eee eens Pe ee eee are ee ee sais 2
2. 2s Notice in Handling Pickup (6 5 6<¢. 36 4008-3 se Hdd 4-6 OR ee ke hla Sek ah WA OR es 2
2. 2: Pickup Replacement Procedures ..........000ee0005% Sir i sit cal Ue eri tey ocean fo Wid. el Mista ee ash. esas “ee 62
2, 3. Adjustment After Replacement of Pickup ........ 0... ce ee ee ttt ww we ew eee eet ee 3
Measurement Instruments and Test Discs ....... 0.2 ce ee tere tee eee ee tee te ee et et et wee te eee 4
Parts Location for AGiUSUMENE: 6062-4. 6 he a BO ee SR Aw Oe RS BO 4
4, 1. Parts On-P CB. ASS Yo tsesg es 8 GS 4cd Seer ate eS SCS E sd shodoes ae taeuas taler wal aries Ath Giek th Belicia wed acy es 4 4, 2. Parts on Pickup ....... ope: OR at) GRD MR ahs tints SSS Grease US Baler ia Me ae eee we, cea nig Nepean 4
Adjustments ...... Be he ay a ate ca Saree ae ee Real ade etiklee a hs ts tes steal Chiat eo lente airs a, Caneel we at estas eek See A gk 5 5. 1. INQUCS oe aia w Sica ase Ra ee a ee aca a Ck ae iy der pe a fos dae Be cesag en Sas cea ee gas Sauteed Sanee Saxe ed 5 5. 2. AGIVSUMENE INSEIUCHIONS <6. gorse shied a has 0s ee ee a Ee ew PS ee Cathe Ss 5
Mechanism Ass’y and Parts List ........ 0c ee eee eee ere eevee ode Hels, Gr Slat aah shee eter det Bie A orate eee Seca nears 10
6. 1. SV FUOSIS fee Gehan a a A FR BE, Bh 8a aw Aa oan =O 6. 2. Prone PanetAssy (AOL). ceshin Ss beau eee aia a SU eae Rls Wea ee eee BG ® HR ae Vt 6. 8. Chassis ASs ¥ (A002 F oss: 8 s.0555. ss he oe a OWS Bw RU SO OS ee es Beh GS ha eee ke 12 6. 4. Dise Mechanism Assy (B01) v.15 9-70. so yin: fe os Was ae Viste Wap eI ee: Dee a tes wee el ee 13 6. 5. Rear Panel Ass’y (B02) ..........- Soha 2 et an oe tas We, oe a ea, ete tg ete eee cetrtes we eae he, tenes ag 15 6. 6. Dise Mechanism Sub-Ass ¥ (COL) © cp cn hh dS id eee eh ee kr eS) A Se eae aoe eS 15 6. 7. Analog Processor Unit (DOL). a 55:6 ioe hws FG Rw Ole Ga Ew or Re ee ES 16
Mounting Diagrams and Parts Dist. coh 3 se sss 6 ree oy ee oo Sel eae LE Roe ee Mw BEATE eee eas 17 qe. As PHOCO Pransister 0. B.ASs Yo s.< 26/5, Shite aha Ose eS eek eee bao es Oe a ee Saree 17 ee. cas Photo Diode CoB. Ags’ Ye i. oe w6 0: ea a ees ao ae bs SS i Rew AS ae eG: aw ee eee ae 17 7. 38. Open End Switch 2.C.B. Asay. exh iso 6-6 iS 6 eee we Sw Sd oo F- e e e 17 7. 4, Close End Switch P.C.B. Ass’y ........20800. bas Se oes conte Sagaide aataaitg he aE aes eae ae od Aa ae Gan 17 7. #5, Bject/ Load Switen 2.0 BuASs y.s.6- 3 hie eee Bee OR SES See ho ee RIOR. We el Bak ek Se 17 7. 6, Power Switch 2:C. Fo Ass yo ith. od ero ko oie eee Oe ws: Sly ob Se ea aes CSN bees 17 1. OF Remote Control PC BiAsey” siecs.2'660s Kee and BAe eee ee ee Oe ES Fe es 17
7. 8. Pin: dack P.C.B.Ass’¥ 64 3. 6S eee SO Gicist Neo Gar teh eh as Toe icine SG sah ay ich wan late ph’ ge case nag a) Mal tg Oae ab Dates Se 18
1. 9, PL Indicator (©: BASS 9 oxc6. ae es Sek S Ss eke ee a ae EE OS SK ee he Se 18 7. 10. Auto Power Control? CB Aegs Yi. g kee ee hk a Bak hs ee eR ee SE SS 19
he weeks RY Pre-Amo..F:C BASS yk. ok etree Sse hse Bae A ae te A wD owe Se EE 20
te dee Power Supply ?.C.B:. Ass Ya. 4-3-4536. ho hs Ph we whe Ae 8 ods sigh ie. ttahea wietee ase ant. S48 ete anor 21 7. 13. Control Switch P.C.B. Ass’y .... 2... ee ee ee ew eee Codi Be naan iap dav anon ok co eid ak vat aestah etal aes Ge Segal celts 92
7. 14, Analog Processor P.C.B. Ass’y ......+. Nestle: Sen'g Te ea) Were Sine die Sah es Ge Gt RE ae cae ea ical te, Ja, We 22
Lie VS: D/A Converter P.C, B. BSS YS eee Gece eB Ado adi “in, cor Ady tec ak tees os aes x ak Aen artay Ge Bete Sin Ir Sa ak AED a eho ede a 23
7. 16. Main PCBs Aas out ono as Re we BS ee RS Bie ES eS Be ER ESOS 26
Schematic Diagram ...... pea BIG. ds igh pee ph set seo Bis laren RS IE SOU vo Gt Sao an cid ag’ oes ale Wh gies Res ae gah oe ee noes 27 8. 2. IC Block Diagrams and Descriptions ssp arte tates MEETS ere os Pend sa Saal ected sce Sk eh GE Ph cea ee NE, Sees 27
8, 2. Wavetorms: ab MajOrr OInts: oie e6 y.4 Ss Was ao Bw Bk oe ae eS US RE ee ee eo ee 37 8. 3. Schematic Diagram . i... ccc cee eee ee ee eee eh eRe ECHR eee ee he ee we meee ons 38
Witing Diagram: | s.6).c24-0 4 hee es bw ea Se ESE E SS 0 OS ee eS OA Kee SOR Re Ry 9 eS 39 Block Diagram ..... 0. e eee en eene Teer eee eee eee eee ee ee eee eee ee 40 SUCCIIGHUIONS: 36. oii fs teess do ee aetes eG eR Se erase B/W We a a oe SO SE vee BS Ew eae ONS 41
SEAT AY ST
1. GENERAL
1.1. Voltage Selector
Voltage selector is installed on the rear panel for Other version of the Nakamichi OMS-5.
This voltage sele ctor can select either 120 V or 220-240 V at customer’s disposal,
1.2. Packing Materials and Owner’s Manual
Part No.
0C81048A O0C81083A 0C81084A 0C81049A 0C81087A OC81088A 0C81051A 0C81050A 0C81052A ODO04491A 0D04493A
0D04492A
WARNING: To protect eyes from laser beam during servicing, DO NOT LOOK AT THE LASER BEAM.
Note: Laser Diode Properties
2.
2.1. Notice in Handling Pickup
In case of repair or replacement of the Pickup, pay attention to
the following handling instructions since the laser diode in the
Pickup is not resistant to static electricity.
(1) Repair or replace on a work stand on which the conducting
rubber is spread.
(2) Use ceramic soldering iron with GND.
(3) Since Pickup is supplied as a spare part in a conductive bag,
take it out of the bag only when you need it. .
(4) Remove the shorting pin and conductive sponge that short the
connector pins of the Pickup after entire work is completed.
(5) Do not turn the adjustment screws (Focus Screw, RF Signal
Phase Screw and Tracking Screw) of the Pickup. If they are
turned widely, it may take much time to readjust them.
© ct %< Description
Outer Carton OMS-5 Outer Carton OMS-5E
Outer Carton OMS-50 (Japan) Inner Carton OMS-5 Inner Carton OMS-5E Inner Carton OMS-50 (Japan Side Packing L
Side Packing R Mirror Mat Bag
Owner’s Manual OMS-7 & OMS-5 (English)
Qwner’s Manual OMS-7/7E & OMS-5/5E (English/German/French)
Owner’s Manual OMS-70/50 (Japanese)
ee
ps
GaAlAs Material: Wavelength: 790 nm — 820 nm
Emission Duration: continuous
Laser Output: 0.7 mW max.
Classification: Class TI b
PICKUP REPLACEMENT PROCEDURES
2.2. Pickup Replacement Procedures
(1) Place the Compact Disc Player upside down on the work
stand and remove the Bottom Cover by unfastening 10
screws. .
(2) Rotate the pulley of the Disc Mechanism Ass’y to move the Fig. 2.2
Pickup in the direction of the arrow, See Fig. 2.1.
(3) Remove FO1, FO2 and FO3, and pull out FO4, See Fig. 2.2.
(4) Remove FO5, FO6 and FO7, and pull out FO8. See Fig. 2.3. FOS
Fig. 2.1 Fig. 2.3
AS OGM SSPE AAP RRR NOSIS SPCIRE ON BU SMT Re a AER TE ie EA * TEPER TERRE ER ERP ET Mut- arene Lt en —
are i RE a gE eA Be a EE TAY
(5) Remove two connectors, unsolder the two-core shield cable, and unsolder F09 to separate FO9 from the Pickup. See Fig. 2.4,
(6) Loosen F10 and remove Fil (Pickup). See Fig. 2.5. (7 Mount a new Pickup and temporarily fasten it with F10.
See Fig. 2.5.
(8) Remove the conductive sponge of the new Pickup. (3) Mount FO9 on the new Pickup by soldering. Plug in the two
connectors and solder the two-core shield cable to the original place, Soldering of the shield cable must be made in the order of GND wire with black tube and then signal wires,
(10) Mount the new Pickup by reversing the disassembly procedures.
(11) Pull F12 (shorting pin) out of the Pickup. See Fig. 2.6.
Fig. 2.4
FIO
Fig. 2.5
Fig. 2.6
2.3, Adjustment After Replacement of Pickup Upon completion of replacement of the Pickup, perform rough adjustments following the flow chart shown in Fig, 2.7. Then proceed to the final stage adjustment, i.e., “Adjustment Instructions’’ in item 5.2 except step 1 ‘‘Laser Power Adjustment” (step 1 is already done in the rough adjustment).
Laser Power Adjustment as per Step 1
Offset Adjustment of Focus Servo (TP7, RV105) © as per Steps 2-1 & 2-2
Tracking Servo Adjustment
(TP6, RV102, RV103) as per Steps 3-1 to 3-5
Focus Screw Adjustment (TP7, Focus Screw) as per Steps 4-4 & 4-5
RF Signal Phase Alignment (TP1, RF Signal Phase Screw) as per Steps 5-4 & 5-5
Tracking Screw Adjustment (TP1, Tracking Screw) - as per Steps 6-3 & 6-4
DL Signal Adjustment (Emitter of Q103, RV101) as per Steps 3-6 &3-7
EFM Signal Adjustment (TP1, RV104) as per Step 3-8
Are
EFM signal at TP1 & playback
sound clear 9
Yes
Adjustment for Scratch and Dot on Dise
as per Step 10
END
Fig, 2.7
-
3. MEASUREMENT INSTRUMENTS AND TEST DISCS
(1) Synchroscope (15 MHz or more) (2) VTVM (3) DC Voltmeter (4) Optical Power Meter (5) Philips Test Sample Dise 5A (6) Sony Test C.D. YEDS-7
4. PARTS LOCATION FOR ADJUSTMENT
4.1, Parts on P.C.B. Ass’y
g [ooooos00] }
CN201
RMOS 180M ——t- 0139 ove
Laser Power
RVMO! RVtOS §=RVIO4
jAuto Power Control PC. B. RAVIO7 e 6
(7) LPF (Low Pass Filter): Pass Band — 4 Hz to 20 kHz, Attenuation — 60 dB or more for 24,1 kHz or higher frequency Recommended LPF: Philips Type 7122 780 29020
(8) Distortion Meter .
Main P.C.B.
D/A Converter PC.B.
RV50} Audio Signai Balance
@c RVIO9
Pickup Movement
Fig. 4.1
4.2. Parts on Pickup
Focus Screw
Tracking Adjustment Screw
Lock Screws
for Tracking Adjustment
RF Signal Phase Adjustment Screw
Lock Screws for Focus & RF Signa! Phase
Adjustment
Fig. 4.2
ABNF MIT me ESTE Fee fT Le RRA NN TE LED LE TINS COTTER TEST OOM EG EERSTE EEC POR ira Io 24h TSA Lh eC i hae ead ey io. be Me RENTERS RSET ENT SATAY gee ADS eta FP eon PUBL ERLO i cite cz PEER ay +
5. ADJUSTMENTS
5.1. Note
Pay attention to the following before adjustment.
(1) Keep the Compact Dise Player horizontal during adjustment.
(2) Before starting adjustment, allow three minutes after the
power is turned ON. Offset voltate will be stabilized in this
period of time.
(3) When a Philips 5A test disc is used, perform the adjustment
while listening to the playback sound,
(4) Connect a low pass filter (pass band: 4 Hz to 20 kHz) in
series to the distortion meter to be used,
(5) When the Main P.C.B. Ass’y is replaced with new one, set
each of the potentiometers as follows:
RV106,RV107: 1 o’clock direction (marked on the P.C.B.)
RV108: 10 o’clock direction (marked on the P.C.B.)
Others: Mechanical center positions
5.2. Adjustment Instructions
baci rae
waverive
Optical Auto Power Power Meter | Control
to Pickup P.C.B. Lens RVMO1
or
DC Voltmeter
across RM09
on Auto
Power
Control
P2C.3%
Laser Power] None
Adjustment
(6) Potentiometers that are not stated in the adjustment instructions must be set to the preset positions stated in (5).
(7) When the Auto Power Control P.C.B. Ass’y or Pickup is replaced with new one, turn the potentiometer RVMO1 full counterclockwise to prevent damage to the Pickup.
(8) Keep the Pickup Lens clean, Carefully clean it with lens cleaner or similar tools,
Danger: Invisible laser radiation when opened and interlock failed
or defeated, Avoid direct exposure to beam.
REMARKS
1. Using Optical Power Meter a, Unsolder one of the leads of diode D135 on the
Main P.C.B. Ass'y. b. See Fig. 5.1. Remove the Feed Motor Belt and,
with rotating the Pulley, position the Pickup so that an optical power meter can be put onto the lens of the Pickup. Position the optical power meter at such a position and angle that provide maximum power
meter reading. ce. Check that RVMO1 is at full counterclockwise
position, and then turn ON the power, d. Rotate RVMO1 slowly clockwise until the power
meter reads 0.27 mW. Caution: Use care not to exceed 0.3 mW at any
moment, otherwise Pickup will be damaged,
e, Turn OFF the power and then solder the lead of © D135 and put the belt on the feed motor.
2. Without using Optical Power Meter a, Unsolder one of the leads of diode D135 on the
Main P.C.B. Ass'y. b., Connect a DC voltmeter across RMO9 (180-ohm
1 W) on the Auto Power Control P.C.B. Ass'y. c. Check that RVMOl is at full counterclockwise
position, and then turn ON the power. d. Rotate RVMO1 slowly clockwise until the reading
on the DC voltmeter reaches 90% of the operating current Iop. Iop is marked on the Pickup (however, it is actually marked as Io). Example: If Iop is 37 mA, the voltmeter reading
which corresponds to 90% of Iop is
0.037 (A) x 0.9 x 180 (ohms) = 5.99 (V). Caution: Use care not to exceed Iop at any
moment, otherwise the Pickup will be damaged. In this example (lop = 37 mA), the limit is 6.66 V.
e, Turn OFF the power and then solder the lead of
D135.
+h we
et
:
ITEM SIGNAL OUTPUT ADJUST- REMARKS } SOURCE CONNECTION MENT
2 |Focus Servo] Test Disc] Synchroscope| Main P.C.B. - Set a synchroscope to DC input and 50 mV/div., Adjustment to TP1,TP7 RV104 ,RV1LO5 and connect it to TP7.
on Main 2. Adjust RV105 to obtain 0+50 mV on the
|P.C.B. synchroscope.
3. Connect the synchroscope to TP] and play back the test disc. |
4. While listening to the playback sound, adjust RV104 so that the horizontal waving of the EFM (Eight-to~Fourteen Modulation) signal at TP1 is minimized and the EFM signal waveform becomes clear. See Fig. 5.2.
3 |Tracking Test Disc]Synchroscope| Main P.C.B. 1. Set a synchroscope to DC input and 50 mV/div., Servo Philips {to TP1,TP6, {| RV101,RV102 and connect it to TP6. Adjustment 5A emitter of RV103,RV104 | 2. Adjust RV103 to obtain Q-100 mV on the synchro-
7 Q103 on scope. Main P.C.B. 3. Short between pins 4 (A+C signal) and 5 (GND)
of CN201 and between pins 6 (GND) and 7 (B+D signal) of CN201 on the Main P.C.B. Ass'y. Short between the emitter and the base of Q113 on the Main P.C.B. Ass'y.
4, Adjust VR102 to obtain 0-50 mV on the synchro- | scope. |
5. Remove the short of CN201 and Qil3. 6. Connect the synchroscope to the emitter of Qi03
and play back the test disc. 7. Adjust RV1OL to obtain minimum DL signal (RF
error signal) on the synchroscope. 8. Connect the synchroscope to TP] and, while
listening to the playback sound, adjust RV104 so that EFM signal is maximized and becomes clear.
Focus Screw|Test Disc |Synchroscope|Main P.C.B. . Loosen the two Lock Screws used for focus Adjustment | Philips RV105 adjustment by referring to Fig. 4.2.
5A .C.B. . Set a synchroscope to DC input and 50 mV/div., | Focus Screw -and connect it to TP7. |
. Adjust RV105 to obtain 0+50 mV on the syncro- scope.
. Play back the 7th or 8th music on the test disc.
. While listening to the playback sound, adjust the Focus Screw of the Pickup to obtain exactly or approximately 0 V on the synchroscope.
. After completion of adjustment, securely tighten the Lock Screws alternately.
Worse: Wren
| XXXXXKXXKK AX NE VAVAYAVAVAVAYAYAYAYS'. OT 7 NS Na Sa Set eS
Optical Power Meter
g
Fig. 5.2 EFM Signal at TP1
-
; cs é ao * . a se one es we Meee pet Z t. onset . « a AMIN TE A TE ei a ROR Be tt UGE REI PE Ea NEN aT ETRE | YLT: TR THN BERS SA EN EMO EN BSE MIE SGD TN TIE, REA LTE SPENSER EY TERT : “2 Sa lo a a RE 2 ES Me TERE EY SO HO sr “ : . SARS HELTER
soins grata REMARKS bomanies ci
5 |RF Signal Test Disc Synchroscope Main P.C.B. Loosen the two Lock Screws used for RF signal Phase Philips RV104 phase alignment by referring to Fig. 4.2. Adjustment 5A 2. Connect a synchroscope to TP] and play back the
test disc,
3. While listening to the playback sound, adjust RV104 so that the horizontal waving of the EFM signal at TPl is minimized and the EFM signal becomes clear.
4, Play back the 7th or 8th music on the test disc. 5. Adjust the RF Signal Phase Screw of the Pickup
so that the EFM signal waveform at TP] becomes clear and maximized and that its horizontal waving is minimized.
- Repeat 2. to 5, above two or three times,
Securely tighen the Lock Screws alternately.
RF Signal
Phase Screw
1. Loosen the two Lock Screws used for tracking adjustment by referring to Fig. 4.2.
2. Conduct step 3 "Tracking Servo Adjustment", 3. Connect a synchroscope to TP1l and play back the
7th or 8th music on the test disc, 4, While listening to the playback sound, adjust
the Tracking Screw of the Pickup so that the EFM signal at TPl becomes clear and maximized.
3. Connect the synchroscope to the emitter of Q103 and adjust RV101 to obtain minimum DL signal on the synchroscope.
6. While listening to the playback sound, adjust RV104 so that the EFM signal at TPi is maximized and becomes clear, :
. Securely tighten the Lock Screws alternately.
Tracking Test Disc| Synchroscope| Tracking Screw Philips to TP1,TP6, Adjustment | 5A emitter of
Q103 on Main}|Main P.C.B. P.C.B. RV1O1,RV102
RV103 ,RV104
- Connect a synchroscope to the test point CTl and play back the 18th music, Finger Print,-on the test disc,
2. While listening to the playback sound and observing the VCO signal level on the synchro- scope, turn the core of L501 counterclockwise and clockwise to find out the upper and the lower limits of VCO voltage, i.e., the limits at which the playback sound is about to cut off.
3. Adjust the core of L501 so that the VCO level is the midpoint between the upper and lower limit voltages. (This VCO level will be approx, a little under 5.0 Vv).
Test Disc|Synchroscope/D/A Converter to test
point CT1 on] L501 D/A Converter
P.C.B.
7 }VCO Adjustment
. Connect a synchroscope to the anode of the diode D138.
2. Play back the test disc and then press the F., Fwd button to set the Compact Dise Player in
Test Disc]|Synchroscope|Main P.C.B. to anode of } RV109,RV1I10
D138 (or pin 3 of U115),
Pickup Movement
Adjustment
anode of Cue mode,
D139 (or pin 3. Adjust RV109 to obtain a 180 usec pulse width. 11 of U115) See Fig. 5.3.1. on Main 4, Press the F. Fwd button further several times, P.C.B. and check whether the time indication on the
Time Indicator regularly increases, If not, repeat 3,
5. Connect the synchroscope to the anode of diode D139.
6. Play back the test disc and then press the Rev button to set the Compact Disc Player in Cue mode,
(to be continued) ot Se
Ate,
Dh Nira ee
ITEM SIGNAL OUTPUT ADJUST—
SOURCE CONNECTION MENT
Adjust RVI110 to obtain a 160 psec pulse width.
See Fig. 5.3.2.
8. Press the Rev button further several times,
and check whether the Time Indicator regularly
changes its time indication. If not, repeat /.
Test Disc|VIVM to
Sony Output Pin Jacks
Audio Signal Balance
Adjustment
Play back the first music on the test disc to
play back 1 kHz 0 dB level signals.
2. Measure both L and R channel output, levels and
adjust RV501 so that the difference between
them is less than Q.1 V.
10 |Adjustment | Test Disc|Synchroscope Main P.C.B. 1. Seratch 900 »~m
for Scratch] Philips |to TPi on RV104 Play back the 9th music with a 900 pm scratch on
and Dot on} 5A Main P.C.B. the test disc and listen to the playback sound.
Disc If playback is not made properly, conduct step 6
| "Tracking Screw Adjustment", Turn the Tracking
Screw counterclockwise when tracking stops, but
turn it clockwise when track is skipped.
If still proper playback is not made yet, conduct
step 7 "VCO Adjustment",
2. Black Dot 800 zm Play back the 17th music with a 800 pm black dot
on the test disc, If playback is not made properly, that is, if tracking stops, make the following adjustment:
1. Set a synchroscope to 1 msec/div. and connect
it to TPl. 2. Adjust RV104 so that the waveform at TPl is as
shown in Fig. 5.4.2 when passing through a | | | | | | black dot. |
180 p Sec
FL. Fwd.
Fig. 5.3.1
yi / ‘
160 Sec | ‘ ]
~ Ps
Rev.
Fig. 5.3.2
Fig. 5.4.2 After Adjustment
Se A RM Maga ONY ae TPES NO DT As AMER NE PI TES INSEE EP TERETE TG IAI ERNIE ETE TT EE A IS WM he tha nt om Fr aa ve Fie RSAC RM AYA MUR SIS
‘ : _—s ial Ree A NTAREES 3 ARES ON ran ae PERNT eRe NEEL one tant teeta eT Ing ST aie te oe
z a
mace gage
spmecrioe
Tracking
Adjustment with
Eccentric
Disc
ae ee eee we
Approx.
Q.]mm
Positive
side of C173; RV108,RV109
Eccentrici|on Main
Disc P.C.B.
Main P.C.B.
RV110
REMARKS
Perform this adjustment only if a disc with eccentricity is not played back properly.
Precisely re-adjust Step 3 "Tracking Servo Disc Adjustment" and Step 6 "Tracking Screw Adjustment" and check whether playback is made properly. If not, perform the following adjustment to insure
correct tracking for a 0.1 mm eccentric disc. 1. Preparation for 0.1 mm Eccentric Disc
Find a disc with approx. 0.1 mm eccentricity in the following manner; a. Set a synchroscope to DC input and connect
it to the positive side of C173 on the Main P.C.B. Ass'y.
b. Play back the first music on eccentric discs and press the Pause button to set the Com
pact Disc Player in Pause mode. Then observe the peak-to-peak level (Vpp) on the synchroscope. The amount of eccentricity, X (mm), is given in the following formula:
X = 1/2 x (1.3 x (Vpp/(5.8 + 4.7))
where, 1.3 mm/A: sensitivity of Tracking Servo
5.8 ohms: DC resistance value of
Traking Coil
4.7 ohms: value of resistor R197
If amount of eccentricity (X) is assumed to be 0.1 m,
Vpp = 2 x (5.8 + 4.7)/1.3 x 0.1 = 1.6 (V)
That is, the disc which shows approx. 1.6 V on the synchroscope should be selected.
2. Load the disc found in ] above and play back the first music of the disc. Check whether it takes much time to enter Standby mode or whether the time indication of the Time
Indicator begins with 00:00. If not, re-adjust Step 3 "Tracking Servo Adjustment" and then turn RV108 approx. 10 degrees in the counterclockwise direction.
3. During playback, press the F. Fwd button several times and check that the time indication of the Time Indicator regularly increases, If not, turn RV109 to correct it.
4, Next, during playback, press the Rev button several times to see whether the time indication of the Time Indicator regularly decreases.
If not, turn RVL10 to correct it.
Fie < aats
6. MECHANISM ASS’Y AND PARTS LIST
6.1. Synthesis
0C81206A CA80295A CA80296A CA80297A OC80715A OC80716A OC80717A O0C80718A CA80237A
OC80719A OMO04377A 0C80720A 0C81062A
0C81063A
Synthesis
Indicator Lens Front Panel Ass’y OMS-5 Front Panel Ass’y OMS-5E Front Panel Ass’y OMS-50 Eject Button Lid Lid Frame Eject Button Base Eject/Load Switch P.C.B. Ass’y Chassis Ass’y Top Cover — Caution Label A Vibration Isolating Sheet A Vibration Isolating Sheet B
(except U.S.A.) Vibration Isolating Sheet C
(U.S.A.)
Fig. 6.1
Fk ek bk ND ek at at at pk fk ek eed ed ek pt
10
OC80721A 0C80722A 0M04621B QEOO9Z1A
OEO00855A 0C81064A
OEO097TOA OEO0888A OC81267A O0C81095A
Bottom Cover Leg Caution Label B BT 8x8 @ Binding
(Black Chromate) BT 2.6x6 ®@ Binding M4x8 @Pan Washer-faced
(Black Chromate) M3x4 & Binding BT 3x12 © Binding Shipping Washer Shipping Screw
NAPE AAA NIT EER ASS CNG UME, PETER gt RP SRST EN TN ONT EP NEI SATEEN ENT SUS Pie sets LETTS SPE: FER SOP STEMEE NM AYY Tia a ah a a
BPeEhO BN OHH
6.2. Front Panel Ass’y (A01)
Fig, 6.2
Aol CA80295A | Front Panel Assy OMS-5 | CA80296A | Front Panel Ass’y OMS-5E _ CA80297A | Front Panel Ass’y OMS-50
OC81351A 0C81352A 0C81353A CA80355A
Front Panel OMS-5 Front Panel OMS-5E Front Panel OMS-50 Power Button Ass’y
er a Ae inte ae
OC80723A OC80724A OC80725A OC81377A OC80726A OC 81367A 0C81366A 0C81369A 0C81368A 0C81365A 0C81364A 0C81363A 0C81370A OC80706A OC81375A OC 80707A OC81376A 0C80708A CA80244A OC81371A OE00792A
Spring Side Frame L Sponge Button Guide Push Button R. Skip Button F. Skip Button Rev Button F. Fwd Button Pause Button Stop Button Play Button Side Frame R FL Filter Sponge B LED Holder Sponge C LED Holder B Control Switch P,C.B. Ass’y Insulator BT 2.6x6 © Binding
11
CO fash ak pak peek prok fed fed fork Pak fat pak feud feck fad bak ND fea et ek at at et pe fad et
are rn te Ey Fone, ne ee Lee
ee >
Ms rae S, oy
6.3. Chassis Ass*y (A02)
01
LO!
12
Fig. 6,3
| Schematic
; A02 —
22 23
24 25 26
L01 L02 L03 L04 LO5 LO6 LO7
L08
LO9
0C80689A CA80243A /OC80691A 0C80693A 0C80694A OC80695A OC80696A OC80697A CA80240A OC80698A OC80699A OC81066A CA80256A 0C81065A 0C80700A CA80303A CA80233A OC80701A 0C80702A CA80232A OC80760A 0C80761A
0C80762A
OC80763A
OC80764A
OC80TO3A CA80298A CA80299A
CA80300A CA803802A OBO8515A OB08037U 0C81208A 0C81209A
0C81210A OC81211A OB08347U
OBO8457A
0C81033A OEO0522A OEO8583A O0C80704A OCOQO507A OEOO0S58A QOEO00921A
0C81032A
0OE00818A
Chassis Ass’y
FL Filter A FL Indicator P.C.B. Ass’y Front Chassis Joint Bar Power Switch Bracket . Power Switch Insulator Power Switch Sponge A Power Swtich Sponge B Power Switch P,C.B. Ass’y P.C.B. Bracket L Side Chassis L Damper Spring Dise Mechanism Ass’y Hinge
Center Chassis Main P.C.B. Ass’y D/A Converter P.C.B. Ass’y Side Chassis R P.C.B. Bracket R Power Supply P.C.B. Ass’y Power Transformer 100V (Japan) Power Transformer 120V
(U.S.A. & Canada) Power Transformer 220V
(220V Class 2) Power Transformer 240V
(Australia) Power Transformer
110V/220-240V (Others) Power Transfomer Bracket Rear Panel Ass’y OMS-50 (Japan) Rear Panel Ass’y OMS-5
(U.S.A., Canada & Australia) Rear Panel Ass’y OMS-5E Rear Panel Ass’y OMS-5 (Others) Insu-Lock Cord Bushing Power Cord (Japan) Power Cord (U.S,A., Canada &
Others) Power Cord (220V Class 2) Power Cord (Australia) Fuse TIA 250V
(220V Class 2) Fuse T500mA 250V
(220V Class 2) BT 3x8 ® Round M3x4 ®Pan Plastic Rivet Wire Clamp Nut Hex. M3 M4x6 ®Pan BT 3x8 ® Binding
. (Black Chromate) BT 3x8 ®Nailtap Screw
(Black Chromate) M3x8 © Binding
(Black Chromate)
a
1 1 1 1 1 1 1 1 i 1 1 1 1 2 1 1 1 1 2 1 1 1
1
1
2
1 1 1
a 1 1 1 1 1
1 1 2
2
4 2 2 1 2 4 8
4
2
t. ie
oF aati
ym,
f%
“ sg
iaae
LE
YR
eee
Bem
: fe
@&@
© G
G «
w G)
&
2 ©
13.
‘Fig. 6.4
oO J
6.4, Disc Mechanism Ass*’y (B01)
20 Ber iag -
Disc Mechanism Ass'y CA80256A
OC81156A OC80998A OC80997A OC80996A O0C81005A4 OC80995A OC 80984A 0C80972A CA80283A OC81001A OC81006A O0C81360A OC80982A OC81058A OC80971A O0C81145A OC81007A OC80999A 0C80994A OC80981A OC80985A OCB1149A CA80354A CA80279A OC80976A O0C81009A OC81143A 0C81010A 0C81008A 0C80983A. CA80239A CA80234A4 0C81350A CA80280A 0C80973A4 OC80975A
| OC81003A OC81000A OC80941A 00809404 0C80949A OC80948A 0C80942A 0C80946A OC80945A 0C80943A CA80277A O0C80944A CA80276A 0C80947A CA80236A OC81158A 0C80969A4 0C81004A OC80974A CA80353A 0C81002A O0C80992A OC81016A 0C81022A O0C80773A 0C81020A OC81018A CA80282A OC81017A CA80281A OC80774A 0C80993A O0C80963A
OE00042A QOE00222A OC80959A OEO0029A OEOO985A
OF03175A 0C80954A OC80965A
OEO0678A
OEOO967A 0C80990A OC80955A
Gear Cover Gear A Gear B
Gear C Damper A Bushing Spacer Spring Gear Bracket Ass’y Gear M Sheet Loading Motor Box Rail L Flexible P.C.B. Switch Plate Lock Arm Spring Lock Arm Cushion Disc Drawer Box Rail R Guide Screw A Cord Cover Rack Arm Ags’y -2P Connector Cord Ass’ y Rack Arm Plate Rack B Table Roller Disc Tray Rack A Guide Screw B Open End Switch P.C.B. Ass’y Photo Diode P.C.B. Ass’y Sponge Box Guide Ass’y Stopper Guide Rail L Roller Guide Roller Chuck Spring Chuck B Chuck Arm Chuck A Arm Shaft Collar B Collar A Chuck Arm Spring Arm Bracket Ass’y Timing Arm Spring Timing Arm Ass’y Collar C Close End Switch P.C.B. Ass’y Switch Holder Rear Bracket Sheet Guide Rail R Disc Mechanism Sub Ass’y Guide Sheet Rear Bracket L Collar Damper B Mechanism Bracket L Mechanism Spring Damper Washer Front Bracket L Ass’y Shipping Screw Rear Bracket R Ass’y Mechanism Brackt R Front Bracket R M2xi.8 ®@ Binding
(Black Chromate) E-Ring 1.5mm E-Ring 2mm M2x4 ®Pan Washer 2x6x0.2 M38x6 ® Binding
(Biack Chromate) M2.6x6 ®Pan (Black Chromate) Plastic Rivet BT 2.6x6 ®Nailtap Screw
(Black Chromate) M2.6x6 ® Countersunk
(Black Chromate) CS Stopper Ring 3mm Wire Clamp M2x8 © Binding
(Black Chromate) Re RD REDD et gS Bah fe te et tt BS ft 00 Bt tt Bd Bd Bt be Bt Bt et 0 0
14
Wire Clamp BT 2.6x4 @Nailtap Screw
(Black Chromate) M2x6 ®Pan M2x16 ®Pan E-Ring 2.5mm M3x6 ® Binding (Nickel) M3x8 ® Binding (Black Chromate) M3x15 © Pan M2.6x6 © Pan (Black Chromate) Plastic Rivet
fu
ESP h hee Nw it
TE REL AFR ITA Neth TEL BEER MM, SO Me TENE aT LET UES PALL TE STON ST ESE ERT I
rsa [meee [eee Toe
OC80991A 0C80939A
0C80964A 0C80956A OEO0698A 0EO3030A 0OE00818A OEO0514A OROSLTSA 0C80953A
pate ne
Mo nu, ete lee Be get tome = beeen eet wee eee ne eee
ee ae le rete eee ei i ee a nm ee me
. Sea MS x
6.5, Rear Panel Ass’y (B02)
ers
Sy,
I)
(% }
i) ry
} | i)
’
ie
.j Fig. 6.5 6.6. Disc Mechanism Sub Ass’y (C01)
ry Mp
01
LO}
02
LO2
6.7. Analog Processor Unit (DO1)
CA80299A
CA80302A CA80300A CA80298A
01 0C81351A
0C81373A 0C81358A 0C81359A
02 OC80709A 03 BAO5515A 04 0C81372A 05 CA80245A 06 0C80710A 07 OM03948A 08 0B07092U
LO1 0C81032A LO2 OEO092Z1A
LO3 0E00818A
OE00818A
CA80353A
CA80261A 0C80820A OC80770A OC80792A O0C80782A OC80797A OC80790A 0C80785A OC80789A O0C80788A OC 80793A OC80794A OC80769A CA80242A OC 80926A OC80819A CA80241A OC80771A OC80767A OC80795A OC80775A 0C80780A OC80784A OC80776A OC80791A 0C80779A OC80781A CA80260A 0C80783A 0C81338A OC80768A OC80778A OC80772A OC80786A
“BY a TON TAG UN EE TE AE NO
Rear Panel Ass’y OMS-5 (U.S.A., Canada & Australia)
Rear Panel Ass’y OMS-5 (Others) Rear Panel Ass*’y OMS-5E Rear Panel Ass’y OMS-50 (Japan)
Rear Panel OMS-5 (U.S.A., Canada & Australia)
‘Rear Panel OMS-5 (Others) Rear Panel OMS-5E Rear Panel OMS-50 Angle Analog Processor Unit Insulator Remote Control P.C.B. Ass’y DIN Jack Plate Voltage Lock Plate OMS-7 (Others) Voltage Selector OMS-7 (Others) BT 3x8 @Nailtap Screw BT 3x8 © Binding
(Black Chromate) M3x8 © Binding (Black Chromate)
(except OMS-7 (Others)) M3x8 © Binding (Black Chromate)
OMS-7 (Others)
Disc Mechanism Sub Ass’y
Gear Base Ass’y Feed Motor Motor Bracket Belt Guide Rack Spring Rack Gear GearA Spring A Gear C Gear B Belt Sheet Chassis Photo Transistor P.C.B. Ass’y Microswitch Dise Motor Auto Power Control P.C.B. Ass’y Limiter Lever Bearing Damper Holder Plate Shaft A Spring B Plate Spring Slider Shaft B Shaft Holder Ground Wire Ass’y Spring C
Bushing A Pickup Bracket Bushing B Adjuster Bracket Spring D
Fig. 6.7
BSNS NS BIS ett at bk INS Bet ek a Bak ed ad fd ed ed fed et ek ee pe ppd
NY OC NRE BEBE Be pe
16
LO1 L02 L03 L04 L0O5 LO6 LO7 L08 LO9 L10 L11 L12 L13 L14 L15 L1i6 L17 L18 L19 L20
L23
CA80235A CA80255A OE03030A
OEOO866A 0E00804A OE00973A OC80777A O0C81126A 0OE00222A 0C81127A 0E00042A 0C81340A 0C81341A OE03031A 0C80704A OE03046A 0C81342A 0C81343A 0C81344A 0C81346A 0C81345A OE00249A 0C81347A OE03138A
BAO5515A
0H04510A OHO4511A BA05494A BAO05498A
RF Pre-Amp. P.C.B. Ass’y Laser Pickup Ass’y M38x6 © Binding (Nickel) Washer (Belongs to Feed Motor) M2.6x4 ® Binding M2x4 © Binding (Black Chromate) M2x6 © Binding Pulley Support Mylar Washer 2.5mm E-Ring 2mm Mylar Washer 2mm E-Ring 1.5mm M2.6x6 ® Binding (Nickel) M2.6x10 © Pan (Nickel) M 3x8 © Binding (Nickel): Wire Clamp M2.6x6 ®Pan (2A) M2.6x10 @ Pan Bolt M3x12 (Hex. Socket Head) Bolt M3x10 (Hex. Socket Head) Washer 3mm (3x8x0.5) Bolt M3x16 (Hex. Socket Head) Washer 2.6mm (Nickel) M2.6x8 © Binding (Nickel) M3x10 © Binding (Nickel)
Analog Processor Unit
Unit Case Side Cover
Analog Processor P, C. B,. Ass’y 'Pin Jack P.C.B. Ass’y
ce RT Oe ERENT DERRY RIE LINN YAM nes
a
NEE HON REE HOD NR EHH HEE HOME
Sea wy ee
7. MOUNTING DIAGRAMS AND PARTS LIST
Notes: 1. Mounting diagram shows a dip side view of the printed circuit board.
2. Diode is MA150, 18853, 181555, or 1SS176 unless otherwise specified. 3. Abbreviation for part name:
TR — Transistor, SiD — Silicon Diode, Varicap — Variable Capacitance Diode RK — Carbon Resistor, RM — Metal Film Resistor, RF — Fail Safe Type Resistor
CE — Electrolytic Capacitor, CM — Mylar Capacitor, CC — Cement Capacitor, CT — Tantalum Capacitor, C — Mica Capacitor
7.1. Photo Transistor P.C.B. Ass’y.
to Auto Power Control P.C.8.
QTo! TPS605-~
Fig. 7.1
7.2. Photo Diode P.C.B. Ass’y
UDO! TENIO4
Control
P.C.B.
Fig. 7,2
7.3. Open End Switch P.C.B. Ass’y
ee er a 43
/O SOPEN END <0. ee
to Auto Power Control P.C.8.
Fig. 7.3
1.4. Close End Switch P.C.B. Ass’y
a CLOSE | END. 1. .°] lo a Le ro CLOSE END re |
oe a Eee
to Auto Power Control P.C.8.
Fig. 7.4
7.5. Eject/Load Switch P.C.B. Ass’y
Fig. 7.5
17
7.6. Power Switch P.C.B. Ass’y
ue re rr. rey
Fig. 7.6
7.7, Remote Control P.C.B. Ass’y
R50 {OOK
" ORSI4, 47K.
R S07, 100K
Fig. 7.7
ap ek re oe ers
nee _
ae So
‘es Zp <e
— —— ~~ ”. 4 id ; % R32
7.8. Pin Jack P.C.B. Ass’y
Coed
ke
x 2
° N N
red
7.9, FL Indicator P.C.B. Ass’y
Q302
2S8C445L
Fig. 7.8
FLO-ES
_G7G6 65 65 G4G3 i 62 61 ;
eT
CA80242A
0C81201A
QTO1 OC80758A
CA80234A
0C81200A LDO1 OC80759A
CA80239A
0C81199A
OC80911A CA80291A
CA80236A
0C81180A
0C80912A
CA80237A
OC81195A
0C80913A
ee EN AT ae OTT ROEM GE TA MITT THOS KAM ERS BE TY ST aw
Photo Transistor
P.C.B. Ass’y
Photo Transistor P.C.B. Photo TR TPS605
Photo Diode P.C.B.
Ass’y
Photo Diode P.C.B. Photo Diode
TLN104
Open End Switch P.C.B. Ass’y
Open End Switch P.C.B. Microswitch (1) 2P Connector Cord Ass’y > (1)
Close End Switch P.C.B. Ass’y
Close End Switch P.C.B. Microswitch (1)
Eject/Load Switch P.C.B. Ass’y
Eject/Load Switch P.C.B. Key Switch
B3F-1000
Cl SWl
Q302 D304 R119,121 219,221
R120,220
CA80240A
0C81202A OC81175A OC80914A
CA80245A
0C81203A
0C80739A
OBO01889A
OB01888A OB05641A OC80917A
BA05498A
0B60124B 0B10025A OB06398A OB22602A
OB22594A OBO9677A OB90038A 0B82341B
0B81282A
18
Power Switch P.C.B. Ass’y
Power Switch P.C.B. CC 1000P 500V Push Switch
SDL1P-B
Remote Control
P.C.B. Ass’y
Remote Control P.C.B. TR 2S8C1685
RK 100K 1/4W J
RK 10K 1/4WJd RK 47K 1/4W J 8P DIN Socket
Pin Jack P.C.B. Ass’y
Pin Jack P.C.B. TR SiD RM
18S176 220 1/4WF
RM 10K 1/4WF RK 1K 1/6W J DS Relay 12V XH Connector 3P
700mm (1) Pin Jack 2P (1)
CA80243A
OC81197A FL1 0C80813A
CA80263A
CA80293A
CA80265A
2SC945L (P,K)
PEABO ERIN TENA ATENEO AGE Ss Sage st
Ass’y
Ass’y
Ass’y
Ass’y
Hyer Apne ntgaNns mea Rapt
FL Indicator P.C.B.
FL Indicator P.C.B. FL Display 8P Connector Cord
7P Connector Cord
( 4P Connector Cord
7.10. Auto Power Control P.C.B. Ass’y ; :
Schematic goss
Part No. Description
Feed Motor Ref. No.
p
19
CA80241A | Auto Power Control P.C.B. Ass’y
Sor | 0C81174A | Auto Power Control
QSAIOIS GT. P.C.B.
ce eee UMOL] O0C80923A | IC BA4558
dl Nas QMO01 0C80743A | TR 2SA1015
>) QM02 OC80756A | TR 2SA7T94
8 DMO1 0C80932A | ZD 8.2V MA1082
ae DM02,03_ | 0C80877A | SiD MA150
,2 04,05
i = LMO1 0C80922A | RF Coil 10unH
eae, RVMO1 OC80887A | Potentiometer 10K
— RMO1 OB05641A | RK 47K 1/4WJd
RMO2 OB05625A | RK 220K 1/4W J
Be na OBO1888A | RK 10K 1/4WJ
07,08 RMO05,06 OBO5S09A | RK 838K 1/4WJ
RMO9 0C80924A | RM 180 i1WJd
ee CMOl 0B40112A | CE ly 50V
Motor CM02 O0C80930A | CC 1000P 50V M
CM03 OBO5797A | CC 0.047y 50V Z
CNMO0O6 O0C80928A | 3P Connector Terminal
CNM0O7 0C80929A | 8P Connector Terminal
CNM08 OC80927A | 2P Connector Terminal
CA80272A | 1P Connector Cord Ass’y (1)
CA80273A | 2P Connector Cord
Ass’y (1) CA80274A | 4P Connector Cord
Ass’y (1)
CA80275A | 8P Connector Cord Ass’y (1)
OC80919A | Ribbon Wire (1) |
7.11. RF Pre-Amp. P.C.B. Ass’y
U301 Q301A 301B 301C 301D
D301 R301A 301B 301C 301D
R302A 302B 302C 302D 306A 306B 306C 306D
R303A 303B 303C 303D
R304A 304B 304C 304D
R305A 305B
R307 R309,310 311,312 313
R314,315 316,317
LS Pe LON EERO ep Sgr on sameeren Ne et
CA80235A
0C81204A O0C80923A OC81067A
0C80871A OB23065A
0B23025A
0B23103A
OB23087A
OB23057A
OBO9660A 0B23073A
0B23125A
R301ID 470,
R301B 470
“R303A dK : mone
cron @
aw,
ose «ae
RF Pre-Amp. P.C.B. | C301A Ass’y 301B
301C RF Pre-Amp. P.C.B. IC BA4558 TR 2SC2813
301D,304 C302A 302B
63020 O.1Sp , <O-4br-o |
- R306D 10
; A OSX gs010 Sie Sts 28C2813 A : : ‘
& : | ta R304B 3.9K
R306B 10 Oo-—Wh-—O
Sos €3028 0.15 p
0B40128A | CE 22u 6.3V
CC 0.154 50V K (Chip)
OC81176A
302C 302D
C303,305 ZD 5.1V RD5.1EB1 RK 470 1/8WJ (Chip)
(Chip)
RK 10 (Chip)
1/8W J
RK 18K (Chip)
1/8W J
RK 3.9K 1/8WJ (Chip)
RK 220 (Chip) RK 200 RK 1K (Chip)
RK 150K (Chip)
1/8W J
1/4W J 1/8W J
1/8W J
20
OB40075A
O0C80875A
CA80294A
CE 22u 16V
8P Connector Terminal Lug Ass’y
wi Da Stee ISLET PRE ROT SO CNN OE
7.12. Power Supply P.C.B. Ass’y
uso3 7912 uso2 7812 UsOl Bi a PPS $Q802 “= QBO!
ees OUT{O_,9 Oy ouT je _< "o )_OgIN , OUTS ° x ON 8 sos 4 oo —<— <1 Se ay = e eo rss par Sen ae C825 : “3
‘ R604 560. wetted ott? Ss Ha 3 “cag, 4 paSeen e819 e-4-eeeae “801 S2vB
So > , 060222 9 emg, ae aie
S$ Re03) 560... °, 82! COIS) |, OtORee Veet ale eo R80, "sag OHt-o. REO2 340 2 hie : 0.022y) c820._—ti Sto , fete oes
o-{t-o . ofro | 8 T§ 4 804, 7-5V. 470 16V : "oF o—14-—0
, 470 pI6V Lag Soe fe a
Onset so r 3 “ €806 al etre’ ol 23’ 2200nlev & ; (Sema
CN~ 807
| pe as 7
fo ol pre Se
}+ Po tye
i} NM. N Nn
oO g ©. | : o fo}
OG padi ‘ov ov 2 OD oO.
Sgt.
Except for 220V Class 2 220V Class2
TIA 250V Shorted
1500mA 250V| Shorted
at TANS
Fig. 7,12 t
CA80232A | Power Supply P.C.B A80304A | Control Switch R1ii6,216 | 0B22589A | 100K 1/2W F |
Ass’y P.C.B. Ass’y ati a38 OB22591A 1K 1/4WF i 18 i
0C81414A | Power Supply P.C.B. 0C81181A | Control Switch P.C.B, R301,306 OB09677A | RK 1K 1/6W J
U801 OB11010A ; IC pwPCT805H LDK02,03 | 0C80755A | LED 1301 R302,303 | 0B09725A | RK 100K 1/6W J
UB02 OB11011A | IC pwPC7812H 04 R304,305 | 0B09741A | RK 470K 1/6W J :
U8 03 OB11057A |; 1C wPC7912H RK09,10 OB01706A | RK 47 1/4W J C101,201 0B41195A ; CM 4700P 100V G ‘
ater 803 | 0C80738A | TR 2SB632 11 C102,202 0B41194A | CM 0.0ip 100V K
804 CA80270A | 9P Connector Cord C103,203 OB09247A | C 220P 50V J
Q802 OC80737A | TR 2SD313 Ass’y (1) | C104,204 OB09903A | CE 2.2u 50V (KS) '
D801 0C80849A | Diode Bridge S2VB CA80268A | 2P Connector Cord 301 .
D8 02 OC80850A | Diode Bridge SW02 Ass’y (1) | C105,205 0B41196A | CM 470P 160V J
D803,804 | 0C80863A | ZD 7.5V MA1075 OC80908A | Key Switch C106,206 0B41198A | CM 1800P 160V J °
D805 0C81068A | ZD 18V MA1180 B3F-1022 (1) C107,207 0B41197A | CM 1200P 160V J iy
D806 OC80864A | ZD 24V MA1240 OC80907A | Key Switch C108 ,208 0B41199A | CM 0.0472 100V K
D807 OC80862A | ZD 5.1V MA1051 B3F-1020 (8) | C109,209 0B41192A | CM 1p 100V K
R801,802 OBO5691A | RK 390 1/4WJ OC80909A | LEDHolderS (1) | €110,111 OB41193A | CM 0.22u 100V K Ad
R803,804 | OB05575A | RK 560 1/4WJ OC80910A | LEDHolderW (1) ] 210,211 es
805 O0C81207A | Shield Case (1) | C112,113 0B41200A | C 47P 500V J
C801,802 OB09291A | CC 0.022u 50V Z 212, 213
803,804 BA05494A | Analog Processor RL301 0OB90038A | DS Relay 12V a
809,810 P.C.B. Ass’y 0B82338B | XH Connector 3P Ng
811,818 480mm (1)
819,824 OB60122A | Analog Processor 0B82339B | EH Connector 4P
C805 0B40233A | CE 10000u 16V P.C.B. 450mm (1) oe
C806 OB40083A | CE 2200u 16V 1C101,201 |0B11155A {IC LF3853N 0B82340A | XH Connector 3P ‘a
C807,808 OBO5899A | CE 220u 10V 301 570mm (1)
C812 OB40067A | CE 470u 10V Q101,201 | 0B06299A 2SC2878 0B82116B | Ribbon Cable 2P on
C813,814 | OB40109A | CE 2200 35V Q102,202 |0B06142A 2SC2240 (BL) : 160mm (2) if
C815,817 OB40036A | CE 47h 25V Q103,203 |O0B10050A 2SA970 (BL) 0B82345A | Ribbon Cable 2P @
C816 OB40088A | CE 22u 25V Q301 0B10025A 2SC945L (P,K) 120mm (2)
C820,821 OB40081A | CE 470yu 16V ZD101,102 |0B12128A | ZD 10V RD10JSB2 °
C822,825 OB09288A | CC 1000P 50V K 201,202 fi,
C823 0B40103A | CE 47 35V D301,302 |0B06398A | SiD 1SS176 =
CN801 OC80859A | 9P Connector
Terminal 0B22585A 887 IWF mr)
CN802 OC80858A | 4P Connector 0B22588A 23.7K 1/2W F yy
Terminal
CN803 CA80292A | 6P Connector Cord 0B22592A 2.21K 1/4WF
Ass’y 0B22593A 8.25K 1/4W F i
CN804 OC80856A | 2P Connector 0B22590A 1M 1/2WG ig
Terminal
CN805,806 | OC80857A | 3P Connector OB22587A 8.25K 1/2W F
Terminal 0B22595A 51.1K 1/4W F Py)
CN807 | CA80267A | 9P Connector Cord eg
Ass’y
0C80847A | Heat Sink A (1) : 0B22596A 100K 1/4WF
0C80848A | Heat Sink B (1) OB22597A 300K 1/4WG Fi
0C80854A | Insulator (1) ie
0B08347U | Fuse T1A 250V (2) | 214,215 (220V Class 2)
OB08457A | Fuse T500mA 250V (220V Class 2) (2)
21
Analog Processor P.C.B. Ass’y 7.14. Control Switch P.C.B. Ass’y 7.13.
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OBO5776A
OBO5627A OBO1889A
OBO5675A OBO1679A OBOL857A OBO5629A 0B05631A OBO5795A OBO09924A 0B01680A OBO5645A 0C 80830A OB80831A OB04060A OB41098A OBO9247A OB05652A OC 80805A
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0B41176A
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D/A Converter
P.C.B. Ass’y
D/A Converter P.C.B. IC SAA7011 IC 74LS74 IC 74LS00 IC SAA7020 IC TMM2016P-2 IC SAA7000 IC SAA7030 IC TDA1540D Varicap SVC321SP SiD SR1K4 ZD 5.1V ZD 2.4V Crystal 4.2336 MHz VCO Coil Potentiometer
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RK 1M 1/4W J
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(10) CM 0.22u 63V J
CE 22u 10V CE 100u 10V CE 33u 25V CE 22u 25V CC 820P 50V K 6P Connector Terminal 8P Connector Terminal 4P Connector Terminal Test Pin
24
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U104 U105,106 107,108 110
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Q108,110 128,303
Q111,112 Q115,118 120
Q116 Q117 Q119,123 126,129 130
Q124 Q125 Q127 D101-114 116-129 134 136-146 305,306
D115,133 135
D131,132 D147 CX101 T101,102 RV101,106
107,108 RV102,105 RV103 RV104 RV109,110 R101 R102,104 145,147 148,185 218,226
R103,132 133,136 137
R105,106 R107,108 R109,110 240,250 308
R1i11,112 123,125
R113,114 115,116
R117 ' R118,119
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| | |
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OC 80742A
0C80743A
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OC80746A OC80738A OC80748A OC80877A
0C80902A
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OC 80888A OC80886A OC80889A OC80890A OBOS5936A OB05622A
OBO5576A
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OBO5795A
OBO5645A
OBO09272A OB0O1857A
OBO1681A
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OBOL706A
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2801449 2SB632 28C1384 MA150 (42)
ZD 4.7V MA1047
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R151,153 241,245
R161 R162,164 230.231
R163 R167 R169,178 R173 R174
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R187,188 R189 R190 R192,193 233,234
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1/4W J
1/4W J 1/4W J 1/4W J 1/4W J 1/4W J
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1/4W J 1/4W J 1/4W J 1/4W J 1/4W J 1/4W J 1/4W J V
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C116,117 C120 C121 C125,129 177,217
C126,131 C127,128 133,134
C137,138 C139,140 C141,142 C145,202 203
C146 C147 C149 C150 C161,190 212
C162 | C163 C166,167 C170 C173 C174,210 C175 C179,199 C192 C193 C194,195 C200 C201 C205 C208 C211 C216 C218 CN201,210
211 CN202,216
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0B40112A
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0C81190A 0C81185A OB40165A 0B41094A
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3. SCHEMATIC DIAGRAM
8.1. IC Block Diagrams and Descriptions
Vee R2 D2 CK2 P2 Q2 a2
~ << (TOP VIEW
Fig. 8.1.1 Inverter C-MOS IC TC4049BP
Ri soot cKI P} Ql Qi GNO
Output A +V
inverting Input A Output B
Ar o6Yi)) A223) GND
(TOP VIEW) inverting Input B
Non- Inverting input B
Non-Inverting
Fig. 8.1.2 Inverter TTL IC 74LS04 Input A
, —V
Von AS Ba Ys Y3 AZ B3 (TOP VIEW)
Fig. 8.1.7 Operational Amp. IC BA4558, LF353N
(24) 13] 15} 16) Power Amp, Pre- Amp,
A1 81 Y4 Y2 A2 B2 GNO
(TOP VIEW)
Fig. 8.1.3 NAND Gate C-MOS IC pPD4011BC
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(TOP VIEW) Fig. 8.1.18 D/A ConverterIC TDA1540D
Fig. 8.1.4 NAND Gate TTL IC 74LS00
Voo A4 84 Y4 Y3 AZ 83
Al Be Ys Y2 A2 82 GNO
(TOP VIEW)
2} £3 5} LS ¢ c ran) oO am ~ 2 .s) a <x © >
Fig. 8.1.5 OR Gate C-MOS IC yPD4071BC
Fig. 8.1.9 Motor Driver BA6208
VOD 16
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O12 OX A lIQ fs
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5 OZ ¢ 990 ‘3
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7 ana = ©
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INH 6Q ps d> 94 Z COM
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VSS VEE
Fig. 8.1.10 Analog Switch HD4053BP
Tl Peak Hold Vcc 4 7 9
[SS () RSWAn CEE Eee O 2 Ga: Sune commen vOncmene cme mommy
Limiter meet Peak Waveform
In 8Q Level Ol Out Detector Shapping
Shift , ' Circuit
D Bias Filter T2 CF
Fig. 8.1.11 Pre-Amp. IC uPC1474HA
27
R80-83 <__|
DI! © ! O DIO
012 O 2 0 09
DIS O 3 008
014 © 4 0 07 DIS Oo 5 O 06
ROO O 6 005
RO! © 7 O D4
RO2 O 8 O D3
RO3 O 9 O 02
R10 O O Dl Rit © O pO
RI2 O O GND
Ri3 O O 0SC 2
R20 O 0 0SsC!
R2! 0 O TEST
R22 0 O RESET R23 0 O R93
RAO O O R92 RAI/ Vdisp © O RQ!
R30 © O R90
P R31 0 O R83 Fig. 8.1.12 RFIF Amp. TA7302P R32/ INTO O > RBZ R33/INTI © O RB}
OSC1, OSC2: Crystal Input for Internal Oscillator Soiues 0 REO Test: Test isis ORTS Reset: Reset R52 0 O R72 INTO, INT1: Interrupt ROS 0 O R7I SCK, SI, SO: Serial Interface R60 O O R70
DO-15: Bidirectional Ports R610 O R43
ROO-03, 60-63, 70-73, 80-83: R62 0 O R42/S0
Output Ports R63 O O RGI/ SI
R1i0-13, 20-23, 30-33, 40-43, 50-53: vec O O R40/ SCK Bidirectional Ports
R90-93, RAV, RAI: Input Ports (Top View)
R40/ R41/ R42/ R33/—R32/ tot SCK SI SO INT! INTO RESET TEST OSCI OSC2 VCC GNO
a eciaez Lf veter. | TIMER | TIMER EXTERNAL
A B INTERRUPT
mon Oe . ; 4096x10bit
: INSTRUCTION RAM 256x4bit SP WECOUER SEED
R60—63 ee
R50-53 <_ > 2
ye Ye ce A) AC | R40—43 R30—33 R20—23 RI0—13 ROO— 03 D0-15 (R40/ SCK) (R32/ INTO) (R417 S1) (R33/INTI) (R42/50)
Fig. 8.1.13 Micro Processor HMCS404C/402C
28
OM TNE TE a i Sh nae ne ae Sin ees ae Pht Sy Avge tt SEEN Se My ROU NERR DCO EN Teg WEE SET Se ONE ot AM Ang te PCE Re pS, er 7 ge LEN OT RR IE LE ETL ee EL I a AS a AN tt Ne” ee ote marge petra thie Aie. te ‘i : : opt et os piacere cattee See ee oe TN ee re mente series a ene Sent en gehen enon sede
Description of Demodulator IC U501 (SAA7011)
(See Figs. 8.1.14 — 8.1.16.)
Pin Description of Demodulator IC:
Pin
No. 1 2
10
11
12
20
21
22
23
Signal Name
VBB SDATA
SBCL
SWCL
DEFM
PD2
PD1 VSSD VDD2 OA1
OA2 OA3
VSSA
vcol
VCO2
CEFM
FD
In/ Out
In
Out
Out
Out
Out
In
In
Oirt
Out
Out
Out
Out
In
In
Out
In
Out
Out
Out
Description
—2.5 V. Back bias supply.
Push-pull output for subcoding data. An 8
bit burst of data (including a 1 bit subcoding frame sync) is output serially
once per frame coincident with SBCL. Push-pull output for subcoding bit clock,
An 8 bit burst clock at nominally 2.1609
MHz which is used to synchronize the subcoding data.
Push-pull output for subcoding word clock. A square wave signal at data frame rate
(7.35 kHz) used to _ synchronize the
subcoding words and the pause (P) bit. Push-pull output for the subcoding pause
bit. This signal is derived from the encoded subcoding word and is used to indicate a
music pause. A debounce circuit is
incorporated to eliminate erroneous data.
Input from external high frequency detector. When this signal is high the
frequency detector output (FD) and phase detector are enabled. (This input is kept High.) Non-inverting input to the level detector. A
differential signal of between 0.5 V and 2.5 V peak-peak is required between pins 7 and
8 to drive the level detector correctly,
Inverting input to the level detector,
Inverted feedback output from the level
detector. These outputs (FB and FB) have a nominal impedance of 10 kf and will default to 1/2 VDD1 when a dropout is
sensed. . | Non-inverted feedback output from the
level detector (see FB). Push-pull output for EFM (Eight-to- Fourteen Modulation) data after it has passed through the level detector.
(This pin is not used.) Phase detector output signal.
These outputs (PD1 and PD2) have a
nominal impedance of 10 k&2 and the differential DC content of the signals is a
measure of the phase difference between the
data and the internal 4.3218 MHz clock,
Phase detector reference signal. (see PD2.)
Digital ground. Main ground terminal.
+12 V supply.
Non-inverting input to the operational
amplifier.
Inverting input to the operational amplifier,
Source follower output of the operational amplifier.
Analog ground. Ground terminal for
operational amplifier only. Connected internally to VSSD via a nominal 25 2
resistor,
Input to voltage controlled oscillator
amplifier. The amplifier is a simple inverter
designed for up to 10 MHz operation.
The frequency control is achieved via an
external ‘“‘Varicap”’ tuned circuit.
Output from voltage controlled oscillator
amplifier. The load for the inverting
transistor may be turned off for test
purposes by reducing VDD2 to OV.
A push-pull output from the internal 4.3218 MHz clock generator, (This pin is not used.) Three state push-pull output from the
frequency detector. This output has a
nominal 1 k{f2 impedance when active but assumes a high impedance state once the
sy stem is in lock,
Pin Signal In/ No. Name Out
24 FSDE Out Push-pull output for frame sync signal to
the Error Corrector IC U504. A positive
going pulse occurring at the end of each
data frame (nominal frequency 7.35 kHz). 25 SSDE Out Push-pull output for symbol sync signal to
the Error Corrector IC U504. A negative
going pulse occurring during the last bit of
each data symbol (nominal frequency 254 kHz).
26 CLDE Out Push-pull output for data bit clock to the
Error Corrector IC U504. An 8 bit burst
clock at nominally 2.1609 MHz which is
used to synchronize the data to U504., 27 DADE Out Push-pull output for data to the Error
Corrector IC U504. Serial data consisting of
382 x 8 bit symbols per frame which is synchronized to CLDE.
+5 V supply.
Description
28 VDD1 In
General Description of Demodulator IC:
| The SAA7011 Demodulator IC forms the front-end of the compact disc digital audio decoding system, supplying
demodulated data and timing signals to the Error Corrector
SAA7020 and the subcoding microprocessor,
The detected signal from the disc is amplified and filtered
externally and then converted to a digital signal via the level
detector. This is an adaptive data slicer which relies on the nature
of the modulation system to determine the optimum slicing level.
A frequency detector and a phase detector provide the coarse and
fine control signals for the phase locked loop (PLL) system. The gain is supplied by an internal operational amplifier which drives a
voltage controlled oscillator (VCO) running at twice the input data
rate which is nominally 4.3218 MHz. The oscillator output is
divided by 2 within the main clock generator which then clocks the input shift register and the timing chain. This clock signal
completes the PLL loop when it is compared with the incoming data in the phase detector.
After the phase detector the data is clocked into the 23 bit input
shift register to enable the frame sync pattern to be detected.
Also, a minimum and maximum data length detector provides frequency limit signals (Tmin and Tmax) for the frequency detector,
The frame sync signal is used to reset the +588 slave-counter
which, together with a+17 symbol rate counter, supplies timing
signals for clocking the Eight-to-Fourteen Modulation (EFM) decoder and the subcoding outputs. The data is read from the
input shift register in symbols of 14 bits which are latched and
then decoded into 8 bit data words. The subcoding part consists of
only one word per frame (see Fig. 8.1.15), therefore the output (SDATA) is a burst of 8 bits of data accompanied by a 2.1609
MHz burst clock signal (SBCL) (see Fig. 8.1.16). One bit of this subcoding output data is replaced by a subcoding frame sync bit
(SF) which is decoded from either of two special EFM codes. The displaced bit is known as the Pause or P bit and is latched to its own output via a debounce circuit to remove erroneous changes.
The +588 slave counter also provides a sync coincidence pulse
which occurs when two detected sync pulses are Precisely one
‘frame length apart (588 clock cycles). This is used by the lock
indication counter as an “‘in-lock’’ signal to reset the counter and
disable the frequency detector output (FD). If the system goes out
of lock for any reason and the sync pulses cease then the lock
indication counter will count frame periods and after 63 frames will enable the frequency detector output.
29
EMP ete ENE TERA TOL CLO PERL MOLE RE NDEI EN ee Ty ee yD FM POO en ery eee RI weNgeEts A5e t STP RSE A IETS PIMA TRE EARS ET ASA COTTE SS TE ABRLOL ROD IEICE AE QA
The sync coincidence pulse is also used via a delay line to reset the
protected +588 master counter. The counter is prevented from
accidental reset by erroneous sync patterns by accepting only
coincident sync pulses or sync pulses which occur during a
predetermined ‘‘window”’ at the beginning of each frame. This
window is wide enough to allow for PLL bit slips, but narrow enough to avoid false sync signals generated by corrupt data.
The +588 master counter, together with a second +17 symbol] rate counter, is used to time the data and clock signals to the Error
Corrector SAA7020 (see Fig. 8.1.16). In this way, even if the data
has been corrupted, the timing signals are correct and only re- synchronized after a complete frame has been sent to the Error Corrector.
eR ee en er ee Se a Oe eS ea Te
Level
Detector
PO | ee Phase &
Freq.
Input Shift Register
Sync Detector
The data to the Error Corrector (DADE) consists of 32 x 8-bit symbols per frame with half bit gaps between each symbol and a
much longer gap during the frame sync period. It is this longer gap
that will change in length when corrupt data upsets the timing system.
Debounce
Shift PD2 129 Latch : O2 SDATA Ep 230 Detector Register
O3 SBCL
O4 SWCL
OAL 16 | ' | : Loop EFM __ Shift A
Amp, Decoder | Register 27 DADE OA2 |7
OA3 18 O26 CLDE
VCO2 219 seal . |
VCO Fi Timing 8 Control ae ARE SSDE
vco | 209 O24 FSOE
eee nee ee cee ey eee ee 14 . 19 28 5
VSS VSS VOD!i VOO2 VBB Digitol Analog
Fig. 8.1.14 DemodulatorIC SAA7011
|-—$————_——_———_——_—— ————— | Frame=588 Channel Bits —————$_________________+|
Sub-
Format of Sync Pattern — 27 Channel Bits Format of Subcoding or Data Symbol~-17 Channel Bits
L Bit , eee channel git fefefs|sfe|7fe/sfioffefmfis) | | ——<—__——__—- May be inver ted, ol M—o [+ 14 bit EFM Word ——+}— 4 —>]
M= Merging and Low Frequency Suppression Bits
Fig. 8.1.15 Input Waveform to HF Pin (SAA7011)
30
OEE IE TE LIEEEIMLE ETON GT eo se. a eat te
(To Error Corrector)
CLDE nn nu nn nan es (U501-26) Se
Symbol 31|————>}+—- Symbol 32, ———>} l-——— Symbot | ————>| i
(U501-27) © MSB8 LSB MSB LSB
SSDE (U501i-25) l | | | ;
FSDE (U50 I-24)
(Subcoding)
ea ee eee ee re ene ener meer fH 07000 ip!) | eee eee SBCL (U50I-— 3)
SDATA (U50I-2)
(WHY KYUKXTASHKR AG) Sync (Note I)
SWCL (U50I-4) eae i a ead inter ents aes
Pp (U501~5)}
Note !: The sync bit Is low whena subcoding sync word is detected.
Fig. 8.1.16 Output Waveforms (SAA7011)
Description of Error Corrector IC U504 (SAA7020)
(See Figs. 8.1.17 and 8.1.18.)
Dota In/Out Address Qut
DOER-DO7ER AOER-AAER WEER OEER CEER 28-35 9-19 24 25 26
i cS commen of ) e : C) STI Ee CEE CE CD CEES | VBB
| | 20 vss
| + VOD |
Data Bus 21 vdo2
22 TEST
3 Cl FLAG Out put Input Cl C2
Register : Decoder Decoder Array -
DADE 59 Shift O37 DAEC
| Register |
CLOE 69 © 36 UNEC
SSDE 70
FSDE 8 A O27 CLEC
CLOX 230-—> O2 FSEC
4 39 38
MCES SMSE GAP
Fig. 8.1.17 Error Corrector IC SAA7020
31
es to ONE IE tN RAE LOR RARE ROE OILS LM DINO BENE, MES IRE MEY Re eat REA NHR RE ee Se Ee Son ier CS Ce Oy tar ar ne EMEA SIMS RUIN MES Think At al oe Sa eka Ba ta Ba ae ices :
Pin Descripiton of Error Corrector IC:
Pin Signal No. Name
1 VBB
2 FSEC
38 Cl Flag
4 MCES
5 DADE
6 CLDE
7 SSDE
8 FSDE
9-19 AOER-
AAER
20 VSS
21 VDD2
22 TEST
23 CLOX
24 WEER
25 OEER
26 CEER
27 CLEC
28- DOER-
85 D7ER
36 UNEC
37 DAEC
In/ Out
In
Out
Out
Out
In
In
In
In
Out
In
In
In
Out
Out
Out
Out
In/
Out
Out
Out
Description
This pin will be connected externally to a
—2.5 V supply for back bias.
Output data clock, data is valid on the
falling edge. See Fig. 8.1.18.
This pin is not connected for normal
operation, it is for testing purposes, Indicating Flags in the Cl Flag store and
hence showing the positions of multiple
errors. This is an open drain output providing a pulse-width modulated signal to control the
rate of data entry. If the data rate has been
correct for a period, MCES will have a 50% duty cycle. If MCES is mostly high data is
entering too slowly and if MCES is mostly
low data is entering too quickly. This pin taken in the data for processing from SAA7011 (Demodulator IC). Data is
clocked in by CLDE in 8 bit symbols, MSB first. See Fig. 8.1.18.
This is the clock for the data input. Data is
accepted into DADE on the negative edge of
CLDE.
This signal is the output from SAA7011. This signal indicates the last bit of each 8 bit
symbol. If it is low during the negative
transition of CLDE a symbol is counted and
clocked in, therefore SSDE must remain low
for only one negative transition in eight for
correct operation.
This signal is the output from SAA7011. A high on this pin during the negative
transition of CLDE indicates the end of a
frame of data. The minimum duration of
FSDE is critical at high rates of data input,
to ensure no FSDE pulses are missed causing
erroneous speed indications of MCES.
Eleven address outputs to 2KB RAM. Provided data is being received by DADE,
CLDE etc., then address AOER to AAER
are completely exercised every four frames
enabling refresh to be automatic for pseudo-
static RAMs. - Ground supply for SAA7020.
Nominal 12 V supply. This pin should be connected directly to
VDD1 or VDD2 for normal operation.
This is the basic clock input for the
SAA7020. A nominal frequency of 4.2336 MHz is fed in from the SAA7000. Write enable bar for control of the memory,
when low S§SAA7020 is writing to the RAM. Output enable bar for control of the
memory output buffers, when low the
memory outputs must be tri-stated.
Chip enable bar for use with pseudo-static
memories, (This pin is open.)
Output data clock, data is valid on the
falling edge, See Fig. 8.1.18.
An 8 bit parallel data bus between SAA7020 and the RAM. The outputs are
high impedance state when OEER is low.
Unreliable data flag, when high indicates
that output data is unreliable. During active
data output (i.e., when CLEC is operating)
UNEC applies to each symbol of 8 bits of
data output at that time. Before each data
word of two symbols is output, UNEC
applies to the whole data word that will
follow in five frames time.
Data output to SAA7000. Data is output in 16 bit words separated by gaps. Each word
is in two’s complement format with MSB
first and is made up of 2x8 bit symbols, Between the data words the state of the GAP pin is output. Data is valid on the
falling edge of CLEC, See Fig. 8.1.18.
32
No, Name Pin Signal In/
Out
38 GAP In
Description
The state of this pin is reflected in the state
of the data output between words on
DAEC. It is used to pass information with
the data words. A high on GAP making the
GAP level on DAEC high and vice versa. See
Fig. 8.1.18, If SMSE is held low the UNEC output will
be held high. This input is used to cause
SAA7000 to mute the data,
Nominal 5 V supply.
39 SMSE In
40 VDD1 In
General Description of Error Corrector IC:
The SAA7020 Error Corrector IC is for the detection and correction of erroneous data samples in the compact disc digital
autio decoding system. Receiving demodulated data and timing
signals from the SAA7011 Demodulator IC SAA7020 sends data samples, corrected if necessary and possible,and timing signals to
the SAA7000 Concealment of Errors by Interpolation and Muting
IC. If it is not possible for SAA7020 to correct the erroneous data
then the unchanged data and an Error Flag is sent to the SAA7000.
SAA7020 Error Corrector IC also supplies the motor speed
contro] signal.
SAA7020 receives serial data from the SAA7011 (Demodulator) at the demodulator clock rate through the input DADE into the
‘“Pre-Fifo’? where it is converted to an 8 bit parallel format and
then clocked out through the Fifo-to-RAM section at the system
crystal clock rate to a 2K x 8 bit RAM via I/O ports DOER to
D7ER.
The ‘‘Pre-Fifo” is also an effective ‘‘de-jitter’’ circuit eliminating
effects such as ‘“‘wow’’ and ‘‘flutter’’? and can cope with deviations from the nominal data rate of plus and minus 2-1/4 frames of
data, From the difference between the nominal data rate and the
actual data rate the motorspeed control signal MCES is derived.
This forms a feed back loop with the motor to control the disc
speed and hence the rate data is read into the ‘‘Pre-Fifo’’, The RAM is used as a temporary data store from which the data,
stored in the form of a “Reed Solomon” code, is de-interleaved and read back into SAA7020 via the I/O ports into the syndrome
generation and locator section. The syndromes formed are
multiplied around to check for erroneous symbols, If one error is
detected the error is corrected and the data symbols are written
back to the RAM with some parity symbols being discarded. If
more than one error is detected the data is read back to the RAM
unchanged but an internal Cl flag is set to mark these symbols as
unreliable.
The data in the RAM is then de-interleaved and read back into
SAA7020 for a second time. The symbols are then checked for errors as previously. If one error is detected it is corrected and the
symbols read back to the RAM as previously. If two errors are detected the information from the syndrome_ generator
multiplication plus the positional data in the Flag store obtained
in the Cl attempt at correction is used to correct both symbols.
This is done by selecting stored data in the ROM and multiplying
it with the data in the C2 stack. The corrected data is then read
back to the RAM. If more than two symbols are in error the data is
read back to the RAM unchanged but a flag is set to mark these
symbols as unreliable. At this stage the remaining parity bits are discarded,
The data is then held in the RAM to give a five frame delay so that
the advanced error flag can be sent to the SAA7000 to warn it to
mute the relevant data, this flag is sent via the UNEC Output Pin.
The UNEC Output Pin also warns of data to be interpolated and
to mute if the SMSE Input Pin is active, i.e., as between tracks,
The data is then read back into SAA7020 in parallel and serially
shifted out through the DAEC Output Pin to the SAA7000.
(From Demodulator)
CLOE (U504—-6)
LSB MSB LSB MSB LSB MSB LSB MSB
DADE (U504-5)
j-————- So +s
SSDE (U504-7) ;
(U504-8)
(To SAA7000 (Concealment of Errors) )
CLEC (U504~- 27)
LSB MSB LSB MSB LSB MSB LSB MSB
ODAEC (U504-37) Gap Level
Advanced by Non- advanced s') UNEC sd. Si" Advanced by Non-advanced city Non advanced og! Non-advanced 4
(U504-36) ' 5 frames. M.S. Symbol L.S. Symbol 5 frames. M.S. Symbol L.S. Symbot
FSEC _ eee a ene eee (U804-2)
Fig. 8.1.18 Typical Input/Output Waveforms (SAA7020)
Description of Concealment of Error IC U506 (SAA7000)
(See Figs. 8.1.19 and 8.1.20.)
Pin Description of Concealment of Error IC:
Pin Signal In/ Pin Signal In/
No, Name Out Description No, Name Out Description
1 VBB In This pin is used for the supply of an 6 CLOX Out CLOX is a buffered form of the clock on
ex ternal VBB of —2.5 V. XTALI.,
2 FSEC In FSEC is an active high pulse which indicates 7 XTAL2 Out XTAL2 is the output drive to a crystal to
the start of a ‘‘Frame’’, It is used to provide the main clock.
synchronize the descramblers to the data 8 XTALI1 In XTALI1 is the input pin for crystal circuit.
frames (12 samples) and also SAA7000 9 VSS —_ Ground supply pin.
clocks to the CLEC input clock, aligning the 10 VDD2 In Nominal 12 V supply pin.
gap in the internal clock to the FSEC pulse. 11 STR2 Out STR2 is an active high strobe pulse of 2
Two consecutive FSEC pulses must occur, CLOX cycles duration occurring every 24
each having a pulse width of approximately CLOX cycles,
6 CLOX cycles. The trailing edge of the (This pin is not used.)
second pulse must occur one frame later 12 STRI1 Out STR1 is an active high strobe pulse of 2
than the trailing edge of the first pulse, for a CLOX cycles duration, occurring every 96
re-synchronization to occur, _ CLOX cycles, after each pair of data words
38 CLEC In CLEC is the input clock, having a clocking . have been output, It is used to strobe data
period of 2 x CLOX period, used for loading to SAA7030 (Digital Filter IC). Both STR1
data from SAA7020. On the negative edge, and STR2 are re-synchronized to XTALI
data at DAEC is shifted in to the input shift to obtain minimum jitter.
register. CLEC clocks a data sample in, then 13 DLCF Out DLCF outputs data for the left channel in
stays low for a gap of 16 CLOX cycles (see either 2’s complement or offset binary
Fig. 8.1.20). format, selected by DAEC.
4 DAEC In DAEC is the data input in 2’s complement 14 CLCF Out CLCF is either a 14 bit or 16 bit output
form with MSB leading. During the gap in clock, selected by pin 16 (14/16). It is used
CLEC the DAEC input is used to select the to clock data from DLCF/DRCF to
output format, a high selects 2’s SAA7030 on its negative edge. (i.e.,
complement, a low offset binary (see Fig. DLCF/DRCF stable during falling edge, see
8,1.20). Fig.-8.1.20.)
Note: the data is descrambled internally so 15 DRCF Out DRCF outputs data for the right channel in
either 2’s complement or offset binary
format, selected by DAEC. the input sample format is complex.
5 UNEC In UNEC is the error flag input. During the
period when CLEC clocks in the DAEC 16 14/16 In 14/16 selects the bit length of the output
input, UNEC is low only if the present clock CLCF.
symbol (8 bits see Fig. 8.1.20) is valid. 17 TEST In This pin selects between normal and test
During the CLEC gap before a word UNEC modes, For normal operation it should be
is low only if the whole of the data word held at OV,
due to arrive 5 frames later is valid. 18 VDD1 In Nominal 5 V supply pin.
33
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General Description of Concealment of Error IC:
The SAA7000 (Concealment of Errors by Interpolation and Muting IC) is used in the compact disc system to reduce audible
annoyance caused by uncorrected erroneous data samples from
the SAA7020 (Error Corrector IC).
Data samples (at DAEC clocked in with CLEC) are first descrambled and then separated into left and right samples. A
similar descramble and separation is performed on the Error Flag
(UNEC). Where no error flags occur the data value is unaffected
through SAA7000.
If for either left or right a single ‘‘error’’ is flagged between two
“go0d” samples then linear interpolation is used to replace the
erroneous value. If two or more adjacent samples are flagged then
the samples in error will be muted. Beginning thirty samples
before the first of the consecutive errors, the value of the samples
will be attenuated smoothly to zero level, using a (O — 7m) cosine
-—---_—
CLEC 39 Input
DAEC 49 Shift
| Register
De- | cn
UNEC 59-4 >
C)
Inter- polation
Sample
Shift Register
w
FSEC
6
XTAL! XTAL 2 CLOX
shape curve. After the error burst the next thirty samples are
attenuated smoothly to full level, using a (7 — 27) cosine shaped curve, This muting/attenuation occurs to data of left and right
channels simultaneously regardless of the source of the mute.
The data (good or processed) is then formatted into 2’s complement or offset binary to match the D/A Converters used. This selection is made with a special function of the data input
(DAEC). Data is then fed to the left and right outputs (DLCF and
DRCF) and is clocked out by the Output Clock (CLCF). Strobes
(STR1 and STR2) are generated for the SAA7030 (Digital Filter IC), Fourteen or sixteen bit D/A Converters can be accomodated
by use of the Select Input (14/16).
A 2x bit rate clock (CLOX) is fed to the system (SAA7020 (Error Corrector IC) and SAA7030 (Digital Filter IC)), SAA7000 automatically .synchronizes to the SAA7020 output using the
frame sync (FSEC) pulse for internal timing reset.
— — I!
Timing @ Control
Output Output
Format Shift O13 OLCF
Select Register |
Output |
Shif? O15 DRCF
Register
O14 CLCF
Ol2 STR!
Oll STR2
Lt tii 14/16 VOD2 VOD! VSS VBB
Fig. 8.1.19 Concealment of Error IC SAA7000
(From Error Corrector)
CLEC (U506-3) eee
nnn mn 48 CL OX LSB MSB
DAEC (U506-4)
UNEC (US06-5)
FSEC (U506-2)
(To Digital Filter)
(Gap)
ce a a a ee
CLCF PUL] (i6 Bit Mode) ALLA]
(U506-14)
CLCF [] (14 Bit Mode) ORRURDARRRORORORAUGRODEDOD
(US06-14)
OLCF/ORCF (U506-B/15)
(Gap) MSB LSB
7, a | | |Legal ne perpef eee ern ne este ee eee ce JUUUUL - (U506-6) ~~
STR) (U506~-12)
STR 2 [| | : rT] [|
(U506=11) Jo————— 24 CLOX Cycles ————_——»}
Fig. 8.1.20 Input/Output Waveforms (SAA7000)
RETR OTIC Tm ee nt mete Se a
34
Aye sere paren gs!
Description of Digital Filter IC U507 (SAA7030)
(See Figs. 8.1.21 and 8.1.22.)
Pin Description of Digital Filter IC:
Pin Signal No, Name
1 VBB
2 OS
3 DLFD
6 CLFD
7 LAT
10 DRFD
11 OB
12 VSS
13 VDD2
15 TINR
16 TINL
eee eR la ee te
In/ Pin Signal In/ Out Description No. Name Out Description
In —2.5 V +0.5 V supply. 17 DRCF In Right channel data input. Data should be 16
In Offset select input. When connected to bit serial, MSB first, offset binary coded. It VDD1 the data output has a fixed DC
offset of 3%. When connected to VSS the
should be valid on the falling edge of the
data clock CLCF.
output has no offset, (This pin is connected 18 CLCF In Input data clock. The falling edge of this
to VDD1.) signal defines input data valid. Out Left channel data output. The data is 14 bit 19 CLOX In Master input clock. Runs continuously at a
serial, MSB first and is valid on the falling nominal frequency of 4.2336 MHz. edge of output clock CLFD. 20 DLCF In Left channel data input. See DRCF.
Out Output data clock, nominal frequency 21 STRI1 In Input 44.1 kHz strobe. The circuit’s internal
4.2336 MHz (= CLOX). The falling edge of
this signal defines output data valid.
Out Output 176.4 kHz strobe. The rising edge of
timing chain is synchronized by the rising edge of STR1 which must run synchro-
nously with CLOX in accordance with the
this pulse says that the output of a 14 bit timings specified in the electrical data word has been completed. characteristics.
Out Right channel data output. See DLFD. The rising edge should follow’ the
In Offset binary not input. When connected to . completion of the input data stream.
VDD1 the output data is coded as 2’s 22 RT In complement. When connected to VSS the
output data is coded as offset binary. (This pin is connected to VSS.)
ane Ground, = In 12 V +10% supply. 23 TE In In Test input (R). Right channel test chain
input. In normal operation this pin should
be connected to either VSS or VDD1.
In Test input (L). Left channel test chain 24 VDD1 = iIn input. See TINR.
Reset test not input. When low resets the
part of the accumulator not reset in normal
operation to initialize the accumulator for
testing. In normal operation should be
connected to VDD1. Test enable not input. When low switches the intemal circuitry into the sequential
scan test mode, In normal operation should
be connected to VDD1.
5 V +10% supply.
TIN R ane <' VBB
igh eae wey = ae ROM
“TE 23 7 13 voo2
| Input Recire Accu- Output
Multiplier Shift ; Mulator Register
OLCF 494- Shift Shift
ie is RAE Coleus
3 OLFD
(ORCF) 17) Register Register 19) (ORFD)
CLCF a
STRI 219 iy Timing & Control
CLOX 190 z O7 LAT
2 I OS 0B
Fig. 8.1.21 Digital Filter IC SAA7030
35
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(Output)
OLFD/ORFO
Osc. e Capacitor 9 O-
(Input)
Ps 2 ss cha a SA eS a aa a a NE ec ot Nl ns yea
TE mm ||| RR ete NC te ogy dea ee ER EON EA Y Ork ern WM
CLCF
(U507-18) UUW TTL
OLCF/ORCF TTT {TT [TTTITTIL LI iLitti tl (U507- 20/17)
STR I (U507-21)
LAT {U507-7)
CLFO {U507-6)
(03807-3710)
Fig. 8.1.22 Input/Output Waveform (SAA7030)
-—_——_— > >
Data IN IQ eens, Shift Register = op hea
Latch
! ! O22 Analog Output
ia aa [ieee ae A a b 24
Latch Enable 20
VI@® 4 be ee _ hos viO 7 a ae es ae ee ee ee ee © | v2© Il ie ea ce ee eevee
ae a Sa eo Sd np cok Vref, ia se =a ese aT Sources
as ae? Sars 2 ae cea oh Raa
Vref. 10
15 Current Oscillator &
Reference 16 4-Bit Source Shift Register
“J
Fig. 8.1.22 D/A Converter IC TDA1540D
36
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P,C.B.
Open/Close End
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Note: Diode isMA150, 18S176, 18853, or 181555 unless otherwise specified.
3~e0s0f
8.2. Waveforms at Major Points
3,"
XXX
BN lait
in NV FES
XX
Fig. 8.2.1 EFM Signal at TP1 on Main P,C.B. Ass’y Fig. 8.2.5 Waveforms at TP4/TP5 on Main P.C.B. Ass’y (when RV107 is set to zero) .
:
4
|
| { !
f t
|
Fig. 8.2.2 Waveforms at emitter of Q104 (above) and TP2 Fig. 8.2.6 Focus Servo Signal at TP7 on Main P.C.B. Ass’y (below) on Main P.C.B. Ass’y
NE OR HT: =
oe
Fig. 8.2.3 Waveforms at emitter of Q104 (above) and TP3
(below) on Main P.C.B. Ass’y Fig. 8.2.7 MCES Signal at TP9 on Main P.C.B. Ass’y iy eteameny
ao wineries heer re
Warning hee Parts marked with the symbol [\n2e critical character
Paul istics. Use ONLY replacement parts recommended by the manu-
Bape ee a ie facturer. It is recommended that the unit be operated from a
Seen 6 pribinoes on suitable DC supply or batteries during initial check-out proce- ad. os ; dure.
Caution: Before returning the unit to the customer, make sure you
make either (1) a leakage current check or (2) a line to
chassis resistance check. If the leakage current exceeds 0.5
milliamp, or if the resistance from chassis to either side of
the power cord is less than 240 k ohms, the unit is de fective,
WARNING — DO NOT return the unit to the customer until
the problem is located and corrected.
Fig. 8.2.4 Waveforms at TP4/TP5 on Main P.C.B. Ass’y
ena ett hanes et ig euber tear tinon inte eee AIIM SACO eS ee ea EIR ARO te 8 Bee Net perth Radar»
37
hearareommeinmeRnaonnes _ wee rnaEe EM RapRMNORE ATTA es * BM NASR RE MATE YY EME ERE OE 8, AONE SOE .
9. WIRING DIAGRAM
AC Input
> mu
Power
Transformer
Power Switch P.C. B. Assy |
U.S.A. & CANADA (120V) (JAPAN 1OOV)
AUSTRALIA(240V) , 220V CLASS 2 (220V) | geet wee ee ee were wee eee cee ee te ce me ee eee ae om een ee mee oe oe oe om
Le ee ee ree we eee ee me ee ne ee ee ee ee ee ee ee en ee ee ee ee me d
a ee YEL “4 ORN ORN
WHT nout -s pT AC Inpu a
BLK 5 4 BLK
BLK 5 0 RED
| Voltage SI Selector
Power
Transformer
Oe eee Carrer Se SIE EES SO
Power Supply
P.C.B. Assy
aaaadaaad:
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9 0 9}; CNBOT se
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i ao =
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BLK
P.C.B. Assy (Dip Side)
Chassis
BRN -
freo} |, BRN] |
Freo} |. me :
att att Saul T
CNMOS
MW~FS-1
Flexible Cable
poco ed Sct +
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iloo09000000f9
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Close End Switch PC. B. Assy
Disc Motor
Photo Transistor
RED
UeRN | VIO gry
~ BLK
ee ee cs Open End Switch
Open/Close Switch P.C.8. Assy
PC.B. : ene Photo Dode
PC.B. Assy
Remote Control
PC.B. Assy
PC.B. Assy Feed Limit (Dip Side) Switch
Loading Motor Feed Motor
eG Os
(Dip Side) ow
Mechanism -
BLK (o> OG
BLK > Chassis
Fig. 9
WHY
CN215] ! [00 | t i
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SERVERS efi afl —selaetelz ee ee
20°}, 3(°°% 6 8 19 cyzog «| CN203_—«CN204 N20!
Main P. C.B. Assy
BRN mp iu
900000},
CN205
ae | on), CN208 yfooo]3
8 WHT
«i WHT
S 5 ) CN213. CN212 cn2i1 ENO 2 1 51 71 a, cnato EN2g9
CODQdFO0CN000} 00000000 }eo000000|00|
BLK (BLK)
ae
0
BLK (BLK)
8LK (BLK)
Pin Jacky aK P.C.B. Assy <>} ¢b>
BRR
REO
Chassis
‘ pa |
85 a Bs O9 “«{ OU Y éc BRN Z
56 Re J 2 RED 415 z
1368LK
EE Saar, BLU O14
Analog Processor
PC.B. Assy
“BLK
— oe oe oe ee oe oe
—- ae coe ee om oe we oe ewe owe ow
On--~ 1
D/A Converter P C.B. Assy
ana Pt
20 01 CREEL CNK4 1CNKIS 1
Control Switch P.C.B. Assy
BLK (BLK)
Pin Jack P.C.B. Assy
O= Chassis
c 90000000
19 GHeog «1 CN203.—-CN204 CN205
BLK (BLK) BLK av
OG
Chassis
BLK
Chassis
eee See
Main P. C.B. Assy
y BRN GRY (BLK)
eae ees ee eee ee
- p
? ofo
51S Sto a
2 c
ee re eee om ae ee ee om ae CNS02
00000000 6
me o wo te Bee = ? i L.
HT BRN ORN: YEL BRN REO ORN
2
=a & 4
REA Pa
[222509] CN5O1
{[000]3 2100};
i a a v WHT
¢ joo}?
WHT
N217 ae §
1
90000000000
ene
co O CN2!10 CN209
812 00000/0000000100000000 aaaeenaclee
i 7 at
ue worms CN2i1
CN214
D/A Converter P-C.B. Assy
BLK (BLK)
000006 0
CNK2 6 1CNKIS 1
FL Indicator PC.B. Assy
iF rrr Control Switch P.C.B. olslelelelele] (elolelelelolele
Notes: 1 Table of wire aolors
BRN — Brown BLU — Blue RED — Red VIO — Violet
ORN — Orange GRY — Gray YEL — Yellow WHT — White GRN — Green BLK — Black
2. Component side view of the P.C.B. is illustrated unless otherwise specified.
3. Wire tube color is shown in (_ ).
39
10. BLOCK DIAGRAM
Compact Disc a
FL Dispt Control
| SP.oy Switch yO
Laser Pickup Dise Motor
Tracking Wired Micro—Processor Remote
Micro-Processor {U1I6) (UII7) Control
Direct— Coupled Linear Phase Analog Signal Processor
(O) = O/A Converter
D/A Converter
Line Output
Digital Filter
Digital Control
vy Dc + lav DC+IIV pc -I7V DC —24V Power
Switch
Power Supply
40
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