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3D-IC technology for future detectors, FNAL, 02/17/2009

3D-IC technology for future

Grzegorz Deptuch

on behalf of the FERMILAB ASIC desi n rou

Raymond Yarema

Grzegorz Deptuch, Jim Hoff, Farah Khalid, Marcel Trimpl, Alpana Shenai,

OUTLINE:

1) History and introduction

2) Why 3D-IC?

3) Key components for 3D-IC technology

1

- 5) Roadmaps and summary

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2

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allowing performing nonlinearfunnctions were vacuum tubes

tubes was complex,

their cost was high, butabove all they were

candidates forminiaturization)D

They are still loved by

3

au p es or g esfidelity in sound But 3D-IC belongs tosolid state transistors

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First integrated circuitexas nstruments

First transistor Ver soon we have two

(Bell Labs 1947)

and more transistors2D integration technologyrulesin electronics ofour days

4

microprocessor

1.9x109 transistorsMore and more components, more andmore functions, growing complexity

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2”, 4”, 6”, 8” planar wafers

X-section of NMOS transistor seen

5Example of a planar process flow

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View of the same simple SRAM cell in 90nm, 65nm and 45nm process node

6

Interconnectivity is THE ISSUE!!!Backplane of PDP-8I machine wire-wrapped

recentprocesses allowup to 10 interconnection metal layers

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--

rendering of 3D IC

AFTER: 3D IC

Only memory directly compatible with logic process

(virtually no choice!)

14× increase in memor densit

Single Die~ 430 mm2 2D IC “All or Nothing”

4× Logic Cost Reduction29× → 100× memory cost reduction

(choice!)

,

Low yield ~ 15%, ~ 10 parts per wafer 128MB not 9MB

memory costs ~ $44/MB memory costs ~ $1.50/MB → $0.44/MB

32-bit ALU operation 5 pJ

32-bit register read 10 pJ

Read 32 bits from 8K RAM 50 J

Calculations using a 130nm

process operating at a core

volta e of 1.2V

7

Move 32 bits across 10mm chip 100 pJ

Move 32 bits off chip 1300 to 1900 pJ

(Source: Bill Dally, Stanford)

From Bob Patti Tezzaron

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--

improvements to achieve using 3Dimprovements to achieve using 3D--IC :IC :

, , , ,, , , ,

reduced interconnect capacitance ( I/O pads ), lower power dissipation,reduced interconnect capacitance ( I/O pads ), lower power dissipation,

higher integration density, may go heterogeneoushigher integration density, may go heterogeneous

high bahigh banndwidthdwidth μ--processorsprocessors

merging different process technologies, mixed materials, system integration,merging different process technologies, mixed materials, system integration,

8

Optimal repartition of functions

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--

3D3DReal estate analogy

How much time, effort and energy

(gas) is needed to communicate with

your neigbors in 2D assembly?

2D2D

9

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--

A chip inA chip in threethree--dimensional integrated circuit (3Ddimensional integrated circuit (3D--IC)IC) technologytechnology isis3D3D--IC definitionIC definition

composedcomposed of of two or more layers of active electronic components,two or more layers of active electronic components,

integrated both vertically and horizontallyintegrated both vertically and horizontally

--

Agressive wafer thinning, through wafer/chip connectivity, backAgressive wafer thinning, through wafer/chip connectivity, back--sideside

metalization and atternin oxide or metal bondin Wmetalization and atternin oxide or metal bondin W--W CW C--W CW C--CC

Fermilab position in 3DFermilab position in 3D--ICIC

Fermilab began exploring the technologies for Fermilab began exploring the technologies for 3D3D circuits in 2006.circuits in 2006.

Fermilab is leading an Int’l Consortium (15 members) on 3DFermilab is leading an Int’l Consortium (15 members) on 3D--IC for IC for

scientific applications, mainly HEPscientific applications, mainly HEP

Importance of 3DImportance of 3D--IC in detectorsIC in detectors

http: 3dic.fnal.gov

10

o on y more rans s orso on y more rans s ors μmm , u, u -- me o s eame o s ea oo rep acemen orep acemen otypictypical bumpal bump bondsbonds and open new frontiers for detectors architecturesand open new frontiers for detectors architectures

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--

11proxy picture

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--

Via LastVia LastFeatures:Features:

-- processprocess v as a e tov as a e to

wafers after bonding and thinning wafers after bonding and thinning )) – –

excludes large area for localexcludes large area for local

interconnect in TSV locationsinterconnect in TSV locations

Readily based on SiliconReadily based on Silicon--onon--

nsu a or process w ere presence onsu a or process w ere presence o

natural oxides acts as etch stoppersnatural oxides acts as etch stoppers

and bonding surfacesand bonding surfaces

potential use of heteregenouspotential use of heteregenous

waferswafers

Two generations of Two generations of Vertically IntegratedVertically Integrated

PixelPixel (VIP) readout chips with features(VIP) readout chips with features

12

for ILC detector vertex (run 3DM2 andfor ILC detector vertex (run 3DM2 and3DM3, 2006 and 2008 respectively)3DM3, 2006 and 2008 respectively)

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--

edge view top view

~700 μm

Metal fill cut

while dicing ~7 μm~7 μm~7 μm

VIP1 chipVIP1 chip

MITMIT--LL 0.18LL 0.18μm processm process

13

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--

VIAVIA--FIRSTFIRST process (viasprocess (vias are part of theare part of the

Features:Features: Via FirstVia First

wafer processing inserted before or wafer processing inserted before or

right after forming transistorsright after forming transistors)) – –

over over TSV locationsTSV locations (TSVs 1.3(TSVs 1.3 μm diameter,m diameter,

3.83.8 μm rec. spacing and 6m rec. spacing and 6 μm depth),m depth),

8” wafers, large ~268” wafers, large ~26××31 mm31 mm22 reticule,reticule,WW 66thth metal used as a bond interface for metal used as a bond interface for

-- -- --

bondingbonding

Submissions:Submissions:3 fully functional prototypes from3 fully functional prototypes from

Fermilab together with 9 otherFermilab together with 9 other

subreticules from participatingsubreticules from participating

14

institutions submitted on a Fermiinstitutions submitted on a Fermi

MPW run in 2009;MPW run in 2009; currently ‘in fab’currently ‘in fab’

0.130.13 μm bulk CMOS by Chartered withm bulk CMOS by Chartered withTezzaronTezzaron 3D via3D via--first technologyfirst technology

11

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--

• Access to the first commercially available 3D-IC process through Tezzaronexcited creation of a consortium centered on Fermilab in late 2008. Theconsortium rou s international laboratories and universities with interest in

Consortium presently comprised of 15 members from 5 countries

High Energy Physics for the development of 3D integrated circuits.

– University atBergamo

– University at Pavia– University of Bonn– AGH University of

– University at Perugia– INFN Bologna– INFN at Pisa

c ence ec no ogy,Poland

– Fermilab, Batavia

– INFN at Rome

– CPPM, Marseilles–

• Others contributing to first

MPW ,

– IRFU Saclay– LAL, Orsay

– ,

– LBNL, Berkeley

15

– ,– CMP, Grenoble http://3dic.fnal.gov

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--

• 3D chip has two tiers• One set of masks used for both

mask cost.– Identical wafers bonded face to

face by Tezzaron. –Tezzaron.

• Frame divided into 12subreticules among consortiummem ers

• More than 25 two-tier designs(circuits and test devices)–

TX1 TX2TY1 TY2

A1 B1 B2 A2

C1 D1 D2 C2

TXL TXRTYL TYR

AL BL BR AR

– ILC pixels– B factory pixels

– X-ray imaging

E1 F1 F2 F2

G1 H1 H2 G2

J1 K1 K2 J2

TX1 TX2T Y1 T Y 2

A1 B1 B 2 A2

C1 D1 D2 C2

E1 F1 F 2 F 2

G 1 H 1 H 2 G2

J1 K 1 K 2 J 2

CL

EL FL FR ER

– es c rcu s• Radiation• Cryogenic operation• Via and bonding reliability

Frame layout

Max frame layout area including

internal saw streets: x=25.760 mm

y= 30.260 mm.

JL JRIL IR

16

• SEU tolerance Wafer Map

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--

Test chips:TX, TY

2.0 x 6.3 mm

– frame organization:

• Top and bottom tiersfabricated on the sameframe; vertical symmetry

frame for flipping onewafer over another andobtaining matching of

circuits in 3D assembly,• All designs initially

submitted by mid-May2009

–Subreticules:

A, B, C, D, E,F, G, H, I, J

5.5 x 6.3 mm

• H = VICTR; short pixelreadout chips realizing ptcut for implementation of L1 trigger embedded in

Full frame

rac er or

• I = VIP2b; time stampingpixel readout chip for

vertex detector @ ILC•

0.13 μm

Charteredrate with sparsificationpixel readout chip for X-rayPhoton CorrelationSpectroscopy @ light

H H*

17Top tiers Bottom Tiers

JI J* I*

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--

Vertically Integrated CMS TrackerVertically Integrated CMS Tracker – How it works:

• Design employing the FEI4ATLAS pixel front-end

• Top tier looks for hits fromlong φ strips and bottom

tier looks for coincidence

shorter z strips connectedto bottom tier.

• Designed for 80 μm pitchsensors

• Serial readout of all top

and bottom strips alongwith coincidenceinformation

•

• Fast OR outputs

• Circuit to be thinned to 24

microns and connectionsmade to both the to andbottom of the chip

18

Processes signals from 2 closely spaced parallelProcesses signals from 2 closely spaced parallel

silicon strip sensor planes (silicon strip sensor planes (φ and Z planes).and Z planes).

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-- – How it works:

• Adapted from earlier MITLL designs inFDSOI technology

• 192 × 192 array of 24 μm2 pixels

Vertically Integrated PixelVertically Integrated PixelVIP Functionalblock diagram

• 8 bit digital time stamp (Δt=3.9 μs)

• Readout between ILC bunch trains of sparsified data

• Sparsification based on token passing

• Single stage signal integrating front-endwith 2 S/H circuits for analog signal outputwith CDS

•resolution

• Separate test input for every pixel cell

• Serial output bus

• Polarit switch for collection of e- or h+

signalssignals are accumulatedare accumulated

and time stamped usingand time stamped using

19

g o a rey co e coun erg o a rey co e coun er

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--

cur_sel<3..0>

FNAL/BNL andFNAL/BNL andUSTUST--AGH PolandAGH Poland

Vertically Integrated Photon Imaging ChipVertically Integrated Photon Imaging Chip

012345191192

outp<15> a l i

z e r

– How it works:

• X-ray Photon

CorrelationGroup<15>

outn<15>

s e r i pec roscopy

is a technique that isused at X-ray lightsources to generatespeckle patterns for

Group<1>

the study of the

dynamics in variousequilibrium and non-equilibrium processes

•

outp<0>64 z

e r

0

65

1

66

2

67

3

68

4

69

5

126

62

127

63

16 group of 256 pixelsread out in parallel butthrough separateLVDS serial ports

192

outn<0>128

s e r i a l i

191

129

190

130

189

131

188

132

187

133

254

190

255

191

LVDS

Group<0>

• a a spars ca on sperformed in eachgroup

20Top view - bump bonding pads on the back of the digital tier l_ C l k

s t a r t

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--

Full separation of analog and digital achieved by dividingFull separation of analog and digital achieved by dividingfunctionalities between tiersfunctionalities between tiers

1400 transistors / pixel 280 transistors / pixel

μ m

8 0

Digital part of pixelDigital part of pixel Analog part of pixelAnalog part of pixel

80μm

21

ower supp es rans erre e ween ers; connec onsower supp es rans erre e ween ers; connec ons

between tiers for signals in each pixelbetween tiers for signals in each pixel

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--

22

• detector/ROIC bonding; with Ziptronix low mass DBI bonding

• Conventional bumps or CuSn are expensive and not low mass fine pitch

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--

Less aggressive mounting optionLess aggressive mounting option

fanout/routing on the detector;fanout/routing on the detector; pads created on the detector, wire bonding topads created on the detector, wire bonding to

the pads on the detector to mount in the systemthe pads on the detector to mount in the system

23

DBI bonding with Ziptronix (a form of oxide bonding)DBI bonding with Ziptronix (a form of oxide bonding)

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--

ROIC to Sensor

uses Direct

Sensor with wire bond fanout

ROIC (400 um)bond

interconnect

(300 um)

Circuit boardrcu oarX-rays

Option 1 - Less Aggressive Mounting

24

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--

Ultimate goal is:Ultimate goal is:aggressive mounting optionaggressive mounting option – – essence of 3Dessence of 3D--ICIC

rsrs --s e u a e e ec or sys ems e u a e e ec or sys em

low density array of I/O pads available on the side of the readout chiplow density array of I/O pads available on the side of the readout chip --

opposite to the detector;opposite to the detector; one side of the readout chip connected to the detector one side of the readout chip connected to the detector

25

,,

on the support PCB with bump or stud bonding techniqueon the support PCB with bump or stud bonding technique

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--

-rays

Sensor (300 um)Sensor to PCB

uses bump bonds

ROIC is 25 um thick

after thinning

Circuit board

Option 2 - More Aggressive Mountingfor four side buttable sensor arrays

26

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--

27

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--‐

at wafger foundries, the role of

packaging houses will be

minimized

We are here now

Transistor

scaling

era

is

dimension is the

future, first 3D

packaging, then 3D

28Source: Knickerbocker,IBM Journal of Research and Development. Vol. 52 No. 6 2008integrated circuits

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3D-IC offers new approaches to old problems in detector development.New high density circuit bonding techniques, wafer thinning, and

Fermilab has been working with two different vendors for 3D chip

fabrication. MIT LL is a via last SOI process using oxide wafer bonding. Tezzaron

-μ .

is a via first CMOS process using Cu-Cu wafer bonding.

Recently a new (third) 3D-IC technique has been explored with a new pixel chip

submission to the OKI-SOI run within the SOIPIX collaboration that is based in

KEK, Japan. The new bonding is based on ZyCube.Chips are still in fab, except the first device, VIP1, that was fabricated in 2007; The

The 3D-IC seems to be the avenue for future development inμelectronics industry we hope to be able to maintain our R&D program

Packa in industr is under revolution because of the transistor

29

scaling era is ending and 3D-IC era with TSVs is beginning.

h l f f d / /

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3D bonding technology to replace bump3D bonding technology to replace bumpbonds in hybrid pixel assemblies.bonds in hybrid pixel assemblies.

FUSION BONDING

7 um dia CuSnpillar on 20micron pitch

Bonding options being explored byBonding options being explored by

FermilabFermilab::

CuSn

--

-- Direct bond interconnect (DBI) using “magicDirect bond interconnect (DBI) using “magic

metal” with Ziptronix. 3um pitch possiblemetal” with Ziptronix. 3um pitch possible

crosssection

-- CuCu fusion with TezzaronCuCu fusion with Tezzaron

Excellent strength and yield obtained withExcellent strength and yield obtained with

Sensors

..

However 10 um of CuSn covering 75% of However 10 um of CuSn covering 75% of

bond area would represents Xo=0.075. Toobond area would represents Xo=0.075. Too

sensorsbondedto BTEV

to 100 umafterchip to

high for some HEP applications.high for some HEP applications.

CuCu fusion and DBI offer the lowestCuCu fusion and DBI offer the lowest

30

wafer bondingmass bond required by many HEPmass bond required by many HEPexperiments.experiments.

3D IC t h l f f t d t t FNAL 02/17/2009

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1 Bondin between Die/Wafers

Fermilabexperience

Electrical and mechanical bondsElectrical and mechanical bonds

a) Adhesive bond Polymer

(BCB)

SiO

c) CuSn Eutectic

bond

Cu3Sn

(MIT LL)

d) Cu thermocompression

eutectic on

CuCu

bond(Tezzaron)

e) DBI (Direct Bond Interconnect)Metal

Oxide

bond

Metal bond

(Ziptronix)

,

formed after bonding. For (c), (d), and (e), the electrical

and mechanical bonds are formed at the same time.

31

3D IC technology for future detectors FNAL 02/17/2009

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VIP1 desi ned in 3 tier MITVIP1 desi ned in 3 tier MIT--LL 0.18LL 0.18 m SOI rocessm SOI rocess

no sensor no sensor

VIP1 / VIP2aVIP1 / VIP2a

Pixel block diagram

VIP1 found to be functional.Architecture proven but:VIP1 Yield was low.VIP2a designed to improve yield

VIP1Test

through: increased sizes of FD SoItransistors, improved power distribution,wider traces and redundant vias amongother things at expense of larger, 30

esu t

32

,

VIP2a is in fabricationFocus has shifted from working in FDSOI to bulk CMOS processes

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