Accelerating the next technology revolution

Copyright ©2009SEMATECH, Inc. SEMATECH, and the SEMATECH logo are registered servicemarks of SEMATECH, Inc. International SEMATECH Manufacturing Initiative, ISMI, Advanced Materials Research Center and AMRC are servicemarks of SEMATECH, Inc. All other servicemarks and trademarks are the property of their respective owners.

3D TSV Interconnects “Stacking the Chips”

Sitaram Arkalgud PhDDirector, Interconnect

SEMATECH/ISMI Symposium

11 September 2009 2

Outline

• SEMATECH overview

• 3D program– Technical update– Cost modeling and consensus building

• Summary

11 September 2009 3

State-of-the-art infrastructure Flexible, adaptable, and cost effective

NanoFab 300S32K ft2 Cleanroom

NanoFab 300N35K Cleanroom

NanoFab 300E

NanoFab 300C15K ft2 Cleanroom

NanoFab 2004K Cleanroom

750K ft2 cutting-edge facilities (80,000 ft2 300mm Wafer Cleanrooms)

11 September 2009 4

3D options

• Die to die stacking

• Die to wafer

• Wafer to wafer

• Device level

Through Silicon ViasSEMATECH R&D

Through Silicon ViasSEMATECH R&D

K Saraswat Stanford U.

Courtesy: Samsung. Courtesy: Tezzaron

11 September 2009 5

SEMATECH 3D R&D Center

300mm CNSE FacilityState of the art

300mm 3D tools

Materials CharacterizationUnit Process DevelopmentTool Development/Hardening Integration (WtW & DtW)YieldEarly ReliabilityFab/Assembly Overlap Region

Product InterlockImpact on CMOS Performance Layout RulesTest Methodology

RoadmapsStandardsCost Models

SEMATECH 3D R&D/Prototyping Center

11 September 2009 6

3D equipment capability

• TSV RIE TEL Telius SP UD• Wafer Align/Bond EVG 540• Spin/bake (materials characterization) Brewer Cee Module• Scanning Acoustic Microscope Sonix• Multicell Cu Plater NEXX Stratus• Thickness Monitor (capacitance) MTII• IR Microscope Olympus• All Surface Inspection Rudolph AXi935• Die Align/bond (manual) SET Kadett• Tools on order

– Die align/bond (automated) 4Q09 (SET FC300)– Wafer backgrind 4Q09– Next generation wafer bonder 1Q10 (EVG Gemini)– Wet hood for cleans and chemical thinning 1Q10

• Access to state of the art BEOL tooling for standard CMOS processing and metrology at CNSE

11 September 2009 7

Key process elements of 3D ICs

Depending on the integration, the order of processing can change and specific process steps may be optional

Considerable number of permutations and combinations

Bottom of via post L-B-S

TEOS

TaN Cu-seed

Bottom WaferTop Wafer

• TSV Reactive Ion Etch– Conventional SF6/O2 or Bosch process– 1 micron vias, 20:1 aspect ratio, non-Bosch

process• Dielectric Liner, Barrier, and Seed

– PVD or CVD/ALD depending on aspect ratio– TEOS/TaN/PVD Cu seed

• Void-free TSV Fill– Cu, W, solder or polysilicon (driven by aspect ratio)– Void free Cu filled TSV

• Bonding of Wafers or Dies– Dielectric, metallic or hybrid– Cu-Cu thermocompression bond, 300 mm wafer-

wafer• Thinning and Handling of Wafers or Dies

– Drives temporary bonding and wafer/die handling materials and processes

– Edge trimmed, 300mm Cu-Cu bonded wafer pair thinned down to 50 microns

11 September 2009 8

Integration flows

• TSV via chains: no bonding required (except to handle wafer)– Demonstrate TSV module

robustness and early reliability; decoupled from bonding development

• Cu bonding development without TSVs– Die to Wafer bonding with all test

structures routed to exposed test pads

– Wafer to Wafer bonding with thinned bonded wafer down to M2

• Die to Wafer bonding with TSVs

M1

V1

MM2

Top wafer

Bottom wafer

Top down SEM, IR microscope image and SEM cross section of a 300mm Cu-Cu bonded wafer

pair with 0.5 micron overlay accuracy

0.5um overlay accuracy

11 September 2009 9

3D Metrology – critical for HVM Requirements & techniques

SEM

TEM

Confocal

Microscopy

IR M

icroscopy

Scanning A

coustic M

icroscopy

Optical &

Electrical Verniers

Capacitance

Micro R

aman

x-ray M

icroscopy/ Tom

ography

TSV Depth

TSV Defectivity

Filled Via Voids

Bond Interface Defectivity

Wafer Alignment Accuracy

??

Wafer Thickness

Residual Stress

11 September 2009 10

TSV supply chain logistics

• Most popular via integration choice – via mid (post CMOS, Cu- or W-filled TSVs) fabricated in the wafer fab– Benefits of footprint, functionality, power and performance

• “Fab or SAT” region will depend on: – Technical capabilities of fab compared to SAT– Ability of each to make capital expenditures

Wafer Fab Fab or SAT SAT

CMOS +

TSV Formation

Final Test +

Assembly

Frontside Bump +

Probe Test+

Wafer Support+

Backgrind+

RDL+

Backside Bump+

Debond From Support

Base

d on

IMA

PS 2

009

Glo

bal C

ounc

il –

Lanz

one

and

Gre

goric

h

11 September 2009 11

Wafer handling logistics Fab front end vs. assembly back end• SEMI M1.15 defines 100’s of parameters…• Wafer diameter, thickness, notch, bevel edge• Bonded, thinned, and edge-trimmed wafers violate this

standard

• Other SEMI standards affected– SEMI E47.1 (FOUP)/ SEMI M31 (FOSB) Carriers– SEMI E15.1 – Load ports– SEMI M1 – Notch– SEMI T7 - Wafer identification

Parameter Single Wafer Bonded/thinned Pair

Diameter 300mm +/- 0.2 mm(usually much tighter)

300mm +/- 0.2 mm (bottom wafer), 294 – 300 mm (edge trim amount)

Thickness 775 micron +/- 20 micron, +/- 10 micron TTV (GBIR)

1550 micron (bonded) 785 – 875 micron (thinned)

Notch dimensions per Figure 7 Overlay alignment, thinning, edge trim dependencies

Edge Bevel T/3,T/4 wafer edge profile Thinning (chipping), edge trim can modify/eliminate bevel

Wafer Top side

Edge Trimmed side Wafer Bevel side

11 September 2009 12

SEMATECH’s cost modeling• Purpose

– Narrow down technology options based on product requirements• For example: die-to-wafer vs. wafer-to-wafer integration, face-to-face vs.

back-to-face– Identify and address expensive steps or modules

• Throughput, uptime, consumables, etc.

• Two primary components of the model– Wafer cost model (WCM)

• Factory level simulator cost/process step or module– Technology tradeoff analyzer

• Cost of 2D vs. 3D (WCMs limitation)– Yield modeling

• Key input to WCM and tradeoff analyzer

• Wafer cost model is a released Excel-based tool

• Technology tradeoff analyzer is being prepared for release

• SEMATECH provides its members with documentation and training

11 September 2009 13

WCM example: TSV fabricationTSV depth needed is smaller of

1. TSV fill capability 2. Final wafer thickness Metallization and integration Thinning

Metrics Standard RIE Bosch Etch Laser DrillVia diameter limits None None > 10 µm

Via count Unlimited Unlimited Throughput Limited

Via depth Limited by PR/HM Selectivity Unlimited Unlimited

Sidewall angle control Difficult Easy Moderate

Sidewall roughness Smooth Scalloped Smooth

Lithography needed? Yes Yes No

Consumables cost High High Low

11 September 2009 14

WCM example: TSV fabrication

TSV Cost per Wafer vs # Vias/die

10

100

1000

10000

10 100 1000 10000# Vias / die

Laser-ALaser-BLaser-CLaser-DDRIE-ADRIE-BDRIE-CDRIE-D

Laser is cost effectiveEtch is cost effective

Etch

Laser

11 September 2009 15

Impact of TSV dimensions on module cost

No tools fullydepreciated All tools fully

depreciatedexcept Si etchand Cu plate

All tools fullydepreciated

3x35

6x60

100%

76%

61%

83%

61%

51%

0%10%20%30%40%50%60%70%80%90%

100%

Combined Effects of TSV Dimensions and Use of Depreciated Tools

TSV etch53%

HM dep/etch/strip37%

TSV Cu ECD10%

• Reducing the TSV dimensions from 6x60 μm to 3x30 μm reduces cost by 17%

• A depreciated toolset contributes greater reductions

11 September 2009 16

Consensus building workshops

• Equipment Challenges for 3D Interconnect SEMICON West - July 16, 2008

• Manufacturing and Reliability Challenges for 3D ICs using TSVs Advanced Metallization Conference - September 25/26, 2008

• Design and Test Challenges for 3D ICs ICCAD - November 13, 2008

• 3D Interconnect Metrology SEMICON West - July 15, 2009

11 September 2009 17

Summary

• 3D can be the new engine to keep the industry on the productivity curve– High performance and high functionality– Lower power consumption and footprint

• Technical feasibility alone does not enable high volume manufacturing– Proven material, process and equipment capability is essential

• Roadmaps to drive consensus and coalesce critical resources– Supply chain readiness is essential

• Industry-wide standards required on equipment and products

• 3D is not a single technology element– Productivity benefits can be realized at several levels– Cost impact needs to be assessed from a system perspective– Industry-wide coordination necessary across front end, assembly, design,

and test

• SEMATECH is accelerating progress in the development of cost-effective and manufacturable 3D TSV solutions

11 September 2009 18

Accelerating the next technology revolution

Research Development Manufacturing