3 PHASE BRUSHLESS DC MOTOR CONTROLL IC · NJW4305A Ver.2014-03-06 - 1 - 3 PHASE BRUSHLESS DC MOTOR CONTROLL IC GENERAL DESCRIPTION PACKAGE OU TLINE The NJW4305A is a 3 phase brush

NJW4305A

- 1 - Ver.2014-03-06

3 PHASE BRUSHLESS DC MOTOR CONTROLL IC ■ GENERAL DESCRIPTION ■ PACKAGE OUTLINE

The NJW4305A is a 3 phase brush less DC motor controller IC. It uses hall element signal inputs and generates motor driving

waveform. Output pre-driver is optimized to work with external Power MOS

transistor for better power handling. Using the NJW4305A, 3-phase DC motor application with NJW4305AVC3

speed control feature can be easily achieved (SSOP20-C3)

■ FEATURES ● Maximum Supply Voltage : 40V ● Operating Voltage Range : 7.3V to 36V ● Operating Ambient Temperature : - 40ºC to + 105ºC ● Quiescent Current : 3.2mA ( typ. ) at VCC=24V ● FG Output ● Lock Protection Function (Auto Release) ● Forward / Reverse Function ● Over Current Detection Function ● Thermal Shutdown Function ● UVLO Protection Circuit ● Direct PWM Control : up to 150kHz ● Bi-CDMOS Technology ● Package Outline : SSOP20-C3

NJW4305A

- 2 - Ver.2014-03-06

H1+

H2+

H3+

OSC

VERR

GND

ILIMIT

WL

VL

UL

WH

VH

UH

FR

FG

H1-

H2-

H3-

VCC

+-

VREF UVLO

SawOscillator

+-

PWM Logic

LockDetect

TSD

+-

+-

+-

DeadTime

RotorPositionDecode

Cｔ

LocalOscillator

ILIMIT

FR

18kHz Fix.

■ BLOCK DIAGRAM

NJW4305A

- 3 - Ver.2014-03-06

NJW

4305A

1. H1+

2. H1-

3. H2+

4. H2-

5. H3+

6. H3-

7. FR

8. VERR

9. OSC

10. Ct

20. VCC

19. UH

18. VH

17. WH

16. UL

15. VL

14. WL

13. ILIMIT

12. FG

11. GND

■ PIN CONFIGURATION ■ PIN DESCRIPTION PIN SYMBOL DESCRIPTION NOTE

1 H1 + Hall Element Input Pin H1 + U Phase Hall Signal Input + 2 H1 - Hall Element Input Pin H1 - U Phase Hall Signal Input - 3 H2 + Hall Element Input Pin H2 + V Phase Hall Signal Input + 4 H2 - Hall Element Input Pin H2 - V Phase Hall Signal Input - 5 H3 + Hall Element Input Pin H3 + W Phase Hall Signal Input + 6 H3 - Hall Element Input Pin H3 - W Phase Hall Signal Input -

7 FR Forward Reverse Select Signal Input Low or Open = Forward Direction, H = Reverse Direction

8 VERR Error Amp Voltage Input Set of PWM Duty. Not use = Pull up

9 OSC Connect Capacitor of PWM Control Set of PWM Frequency 10 Ct Connect Capacitor of Lock Protect Set of ON Time for Lock Protection 11 GND Ground Connecting with Ground

12 FG FG Output Rotation speed output Pin Use = Pull up

13 ILIMIT Over Current Detect L = Operating, H = Stop Nonuse = Pull down

14 WL WL Output Pin W Phase Output for Low Arm 15 VL VL Output Pin V Phase Output for Low Arm 16 UL UL Output Pin U Phase Output for Low Arm 17 WH WH Output Pin W Phase Output for Upper Arm 18 VH VH Output Pin V Phase Output for Upper Arm 19 UH UH Output Pin U Phase Output for Upper Arm 20 VCC Power Supply Input DC Power

* All Ground Pins must be connected at the outside. * Electrical potential of all unused output pins must be fixed at the outside.

NJW4305A

- 4 - Ver.2014-03-06

■ ABSOLUTE MAXIMUM RATINGS (Ta=25C)

PARAMETER SYMBOL RATINGS UNIT NOTES

Supply Voltage VCC 40 V VCC Pin Hi Side Output Pin Voltage VOH 40 V UH, VH, WH Pin FG Pin Voltage VFG 7 V FG Pin

Hall Input Pin Voltage VIH 7 V H1+, H1-, H2+, H2-, H3+, H3- Pin

Logic Input Pin Voltage VIN 7 V FR Pin ILIMIT Pin Voltage VLIM 3.5 V ILIMIT Pin VERR Pin Voltage VVERR 7 V VERR Pin Hi Side Output Current IOH 150 mA UH, VH, WH Pin Low Side Output Current IOL +100 / -150 mA UL, VL, WL Pin FG Output Current IFG 15 mA FG Pin

Power Dissipation PD 1000 mW Mounted on designated board based on EIA/JEDEC. 76.2*114.3*1.6mm 2Layer, FR-4

Operating Ambient Temperature Topr - 40 to + 105 °C Storage Temperature Tstg - 50 to + 150 °C

■ RECOMMENDED OPERATIONAL CONDITIONS

(Ta=25C) PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT

Supply Voltage VCC 7.3 24.0 36.0 V ■ PIN OPERATING CONDITION

(Ta=25C) PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT

► Hall Input Pin ( H1+, H1-, H2+, H2-, H3+, H3- ) Hall Input Sensitivity ΔVMIH Peak to peak 0.08 - - V Hall Input Voltage Range VICMIH 0 - 3.5 V ► Logic Input Pin ( FR ) H Level Input Voltage VHIN 2 - 5.5 V L Level Input Voltage VLIN 0 - 0.8 V ► VERR Pin Input Voltage Range VICMVERR 0 - 5.5 V PWM Input Frequency fIPWMVERR - - 150 kHz

NJW4305A

- 5 - Ver.2014-03-06

■ ELECTRICAL CHARACTERISTICS ( Ta = 25°C, VCC=24V, H1+=H3+=3V, H2+=1V, H1-=H2-=H3-=2V, FR=0V, VERR=5V, OSC=1V, Ct=ILIMIT= 0V ) PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT

► GENERAL Quiescent Current 1 ICC1 VCC = 12V 2.4 2.9 3.8 mA Quiescent Current 2 ICC2 VCC = 24V 2.7 3.2 4.1 mA ► THERMAL SHUTDOWN BLOCK (TSD) TSD Operating Temperature TTSD1 - 180 - °C TSD Recovery Temperature TTSD2 - 130 - °C TSD Hysteresis Temperature ΔTTSD - 50 - °C ► UNDER VOLTAGE LOCK OUT BLOCK UVLO Detect Voltage VDUVLO VCC Decreasing 6.0 6.45 7.19 V UVLO Recovery Voltage VRUVLO VCC Increasing 6.01 6.6 7.2 V UVLO Hysteresis Voltage Range ΔVUVLO - 0.15 - V ► LOCK DETECT BLOCK ( Ct Pin ) Lock Protection ON time tON Ct = 0.47µF 0.18 0.25 0.34 s High Level Voltage VHCt 3.2 3.4 3.6 V Low Level Voltage VLCt 0.8 1.0 1.2 V Lock Charge Current ICHGCt Ct = 0V → 2.5V 5.0 6.5 8.5 µA Lock Discharge Current IDCHGCt1 0.3 0.65 0.9 µA Lock Charge Discharge Current Ratio ICHGCt / IDCHGCt - 10 - -

► HALL AMP BLOCK ( H1+, H1-, H2+, H2-, H3+, H3- Pin ) Hysteresis Voltage Range ΔVHYSH 10 30 50 mV Input Bias Current IBIH at 1 input - - 2 µA ► HIGH SIDE BLOCK ( UH, VH, WH Pin ) High Side Output Voltage VOLH ISINK = 50mA - 0.5 1.2 V High Side Leak Current IOLEAKH VOH = 36V - - 1 µA ► LOW SIDE BLOCK ( UL, VL, WL Pin ) Low Side Output Voltage1 VOHL1 VCC = 12V, ISOURCE = 50mA 8.0 10.0 - V Low Side Output Voltage2 VOHL2 VCC = 24V, ISOURCE = 50mA 8.0 10.0 - V Low Side Output L Voltage VOLL ISINK = 50mA - 0.5 1.2 V Low Side Clamp Voltage VOCLL VCC = 36V, ISOURCE = 0.1mA - - 16.0 V ► FG OUTPUT BLOCK ( FG Pin ) Output Voltage VOFG IFG = 10mA - 0.2 0.6 V Leak Current ILEAKFG VFG = 5V - - 1 µA ► OVER CURRENT DETECT BLOCK ( ILIMIT Pin ) Detect Voltage VDETLIM 0.25 0.28 0.31 V Input Bias Current IBLIM - 1.0 2.0 µA ► ERROR AMP BLOCK ( VERR Pin ) PWM0% Detect Voltage VPWM1VERR Output ON Duty = 0% - - 0.6 V PWM100% Detect Voltage VPWM2VERR Output ON Duty = 100% 3.5 - - V Input Bias Current IBVERR - 1.0 2.0 µA ► OSCILLATOR BLOCK ( OSC Pin ) Saw Wave Peak Voltage VPOSC 2.7 3.0 3.3 V Saw Wave Bottom Voltage VBOSC 0.8 1.0 1.2 V OSC Charge Current ICHGOSC OSC = 0V → 2.5V 50 80 120 µA OSC Discharge Current IDCHGOSC OSC = 5V → 2.5V 0.6 1.3 2.0 mA Oscillation Frequency fOSC COSC = 1000pF - 35 50 kHz ► CONTROL INPUT BLOCK H Level Input Current IHIN VIN = 5V 30 50 100 µA L Level Input Current ILIN VIN = 0V - - 1 µA Pull Down Resistance RIN - 100 - kΩ

NJW4305A

- 6 - Ver.2014-03-06

■ OPERATIONAL DEFINITION ( TERMINAL and CIRCUIT ) ► Hole input Pin Common mode input voltage range ► Hall input hysteresis voltage width

► Input Pin ► Oscillation frequency

fosc = 1 / ( tCHGOSC + tDCHGOSC )

VICMH

3.5V

0V

VICMH

3.5V

0V

LogicInversion

LogicInversion

ΔVHYSIH

Low LevelVoltage

High LevelVoltage

Undefined

VIN

5.5V

2.0V

0.8V

0VtDCHGOSC

tCHGOSC

VOSC

Time : t

VPOSC

VBOSC

NJW4305A

- 7 - Ver.2014-03-06

► PWM 0% / PWM 100% detect voltage

► Over current detect voltage

► Thermal shutdown (TSD) operational temperature

HysteresisTemperature

TSD ResetTemperature

( NormalOperating )

TSD OperatingTemperature

( Output Stop )

-40ºC 150ºC(Tjmax)

TTSD1TTSD2105ºC Tj

VVERR

VPOSCVariable Speed Control

VBOSC

Full Speed ( = Output ON Duty 100% )

Stop ( = Output ON Duty 0% )

VVERRVOSC

VPWM1VERR

VPWM2VERR

VOL

(VUL, VVL, VWL) L

Motor Operation

VILIMIT

Time : t

Time : t

Time : t

VDETLIM

STOP

Active

Rotate

Active

Rotate

LOCAL_OSC(fOSCLO)=18kHz typ. Fix.

NJW4305A

- 8 - Ver.2014-03-06

► Under voltage protection operating voltage

► Lock detect

VCC

VRUVLOHysteresis Voltage

VDUVLO

UVLO Reset Volage( Nomral Operation )

UVLO Operating Voltage( Output Stop )

36V

0V

7.3V Recommended Operational Voltage (min.)

Recommended Operational Voltage (max.)

FG

VCt

VHCt

VLCt

Time : t

tON

Hole Signal Input Timing

tOFF

Motor Rotate Motor Hold

NJW4305A

- 9 - Ver.2014-03-06

■ TRUTH TABLE Input vs. Output Truth table 1 ( H1+ > H1 -, H2+ > H2 -, H3+ > H3 - = “ H ”, Don’t Care = “ X ” )

Input vs. Output Truth table 2 ( H1+ > H1 -, H2+ > H2 -, H3+ > H3 - = “ H ”, Don’t Care = “ X ” )

H1 H2 H3 TSD UVLO ILIMIT VERR OSC Ct FR UH VH WH UL VL WL FG COMMENTH L L Hi-Z Hi-Z L H L L Hi-ZH H L Hi-Z Hi-Z L L H L LL H L L Hi-Z Hi-Z L H L Hi-ZL H H L Hi-Z Hi-Z L L H LL L H Hi-Z L Hi-Z L L H Hi-ZH L H Hi-Z L Hi-Z H L L LH L L L Hi-Z Hi-Z L L H Hi-ZH H L Hi-Z L Hi-Z L L H LL H L Hi-Z L Hi-Z H L L Hi-ZL H H Hi-Z Hi-Z L H L L LL L H Hi-Z Hi-Z L L H L Hi-ZH L H L Hi-Z Hi-Z L H L LH L L Hi-Z Hi-Z L Hi-ZH H L Hi-Z Hi-Z L LL H L L Hi-Z Hi-Z Hi-ZL H H L Hi-Z Hi-Z LL L H Hi-Z L Hi-Z Hi-ZH L H Hi-Z L Hi-Z LH L L Hi-Z Hi-Z L Hi-ZH H L Hi-Z Hi-Z L LL H L L Hi-Z Hi-Z Hi-ZL H H L Hi-Z Hi-Z LL L H Hi-Z L Hi-Z Hi-ZH L H Hi-Z L Hi-Z LH L L L Hi-Z Hi-Z Hi-ZH H L Hi-Z L Hi-Z LL H L Hi-Z L Hi-Z Hi-ZL H H Hi-Z Hi-Z L LL L H Hi-Z Hi-Z L Hi-ZH L H L Hi-Z Hi-Z LH L L L Hi-Z Hi-Z Hi-ZH H L Hi-Z L Hi-Z LL H L Hi-Z L Hi-Z Hi-ZL H H Hi-Z Hi-Z L LL L H Hi-Z Hi-Z L Hi-ZH L H L Hi-Z Hi-Z LH L L Hi-Z Hi-Z L Hi-ZH H L Hi-Z Hi-Z L LL H L L Hi-Z Hi-Z Hi-ZL H H L Hi-Z Hi-Z LL L H Hi-Z L Hi-Z Hi-ZH L H Hi-Z L Hi-Z LH L L L Hi-Z Hi-Z Hi-ZH H L Hi-Z L Hi-Z LL H L Hi-Z L Hi-Z Hi-ZL H H Hi-Z Hi-Z L LL L H Hi-Z Hi-Z L Hi-ZH L H L Hi-Z Hi-Z LH L L Hi-ZH H L LL H L Hi-ZL H H LL L H Hi-ZH L H LH L L Hi-ZH H L LL H L Hi-ZL H H LL L H Hi-ZH L H L

L L

L L L

L

L L L PWM( Reverse )

OFF OFF L HLX H

L L L Lock Detect( Reverse )OFF OFF X HHX

X ON X

X

L

ON Hi-Z L

X

X

X

X

Hi-Z

Hi-Z

Forward

X

Under voltagelock detect

OFF

Thermal shutdown

X L L

X

Reverse

PWM( Forward )

OFF

OFF

OFF Lock Detect( Forward )L LL

L

H

L L L

L

Hi-Z

L

Hi-Z

H

X

X

H

X L L

HOFF

Hi-Z

X

L

X

L

L

H

L

L

L

X

H

OFF

X

X

OFF OFF ON

OFF

OFFOFF

OFF

Over current protection

X L H

L L

Over current protection

OFF OFF ON H

H1 H2 H3 TSD UVLO ILIMIT VERR OSC Ct FR UH VH WH UL VL WL FG COMMENTH H HL L L

Error pattern Hole signal inputL L L Hi-ZHi-Z Hi-Z Hi-ZXXX X X XX

NJW4305A

- 10 - Ver.2014-03-06

■ TIMING CHART 1. Forward Rotation

0 60 120 180 240 300 360 420 480 540 600 660 720 780 840 900

24V

L

5V

0V

0V

Rotor Electrical Position (deg)

Forward Rotation

VCC

H1

H2

H3

FR

VERR

OSC

Ct

ILimit

FG

UH

VH

WH

UL

VL

WL

Condition

NJW4305A

- 11 - Ver.2014-03-06

2. Forward Rotation at PWM

0 60 120 180 240 300 360 420 480 540 600 660 720 780 840 900

24V

0V

0V


L

Forward Rotation Forward Rotation DUTY50% Forward Rotation DUTY0%

VCC

H1

H2

H3

FR

VERR

OSC

Ct

ILimit

FG

UH

VH

WH

UL

VL

WL

Condition

NJW4305A

- 12 - Ver.2014-03-06

3. Change for Forward Rotate to Reverse Rotate

0 60 120 180 240 300 360 420 480 540 600 660 720 780 840 900

24V

5V

0V

0V


Forward RotationSTOP(Brake)

Reverse Rotation

Brake Dead Time

100 110 010 011 001 001 001001 100 110 010 011 001 101101 100 110

VCC

H1

H2

H3

FR

VERR

OSC

Ct

ILimit

FG

UH

VH

WH

UL

VL

WL

Condition

Local OSC

NJW4305A

- 13 - Ver.2014-03-06

4. Forward Rotation → Lock Detect

0 60 120 180 240 300 360 420 480 540 600 660 720 780 840 900

24V

5V

0V

0V


100 110 010 011 001 001 001 001 001 001 001 001 001 101 100 110

Lock Detect

Lock Rereace

VCC

H1

H2

H3

FR

VERR

OSC

Ct

ILimit

FG

UH

VH

WH

UL

VL

WL

ConditionForward Rotation

Detect Abnormal Stop End Abnormal Stop

Abnormal Stop

Forward Rotation

Abnormal Stop Abnormal Stop

Lock Detect

NJW4305A

- 14 - Ver.2014-03-06

5. Forward Rotation → UVLO

0 60 120 180 240 300 360 420 480 540 600 660 720 780 840 900

24V

L

5V

0V

0V


UVLO

VCC

H1

H2

H3

FR

VERR

OSC

Ct

ILimit

FG

UH

VH

WH

UL

VL

WL

Condition Forward Rotation Forward Rotation

NJW4305A

- 15 - Ver.2014-03-06

6. Forward → THD

0 60 120 180 240 300 360 420 480 540 600 660 720 780 840 900

24V

L

5V

0V

0V


TSD

VCC

H1

H2

H3

FR

VERR

OSC

Ct

ILimit

FG

UH

VH

WH

UL

VL

WL

Forward Rotation Forward Rotation

NJW4305A

- 16 - Ver.2014-03-06

Technical Information ■ TYPICAL APPLICATION < MOS FET Drive Circuit, PWM Control, Operating Voltage VCC=24V, Motor Voltage VMM=24V >

VERR

N

N

SSH

H

H

+-

VREF UVLO

SawOscillator

+-

PWM Logic

LockDetect

TSD

+-

+-

+-

RotorPositionDecode

DeadTime

LocalOscillator

18kHz Fix.

+

VDD

RFG

FG

H1+

H1-

H2+

H2-

H3+

H3-

FR

OSC

COSC

FR

ILIMIT

GND

Ct

Cct

Lowpass Filter

ILIMIT

RUH1 RVH1

RUH2

RVH2

RWH2

RUL

RVL

RWLWL

VL

UL

WH

VH

UH

+

GND

VMM

3 Phase Motor

FG Out

VCC

CVERR

RWH1

C1 C2 C3 C4

NJW4305A

- 17 - Ver.2014-03-06

The hall signal peak value must not exceed VICMIH.

Technical Information

■ FUNCTION DESCRIPTIONS 1. Hall Signal Input (H1+, H1-, H2+, H2-, H3+, H3- Pin) 1-1: Using Hall Device These pins are hall device input pin. These are connected to input differential amplifier (hall amplifier) with hall device input pin. When the Hall input level becomes "H" or "L" at the same time of three-phase, the outputs (WL, VL, UL, WH, VH, UH) become OFF. The Rotor Position decode circuit judges like following that the voltage level is “H” at H + > H – and “L” at H + < H -. The hall amplifier has the input hysteresis voltage of 50mV (max). You should input the amplitude greater than 100mVp-p with considering the margin. At this time, the hall signal peak value must not exceed the input common-mode input voltage range VICMIH. It should be used the hall bias resistance of same value at VCC and GND side. Some noise might overlap to the hall signal based on the GND level fluctuations by phase current change or the unbalance of an output signal course, etc. When the malfunction of the output chattering etc. occurs, it should connect between the positive pin and the negative pin with filter capacitor in range of from 1nF to 100nF. 1-2: Using Hall IC This products is a usage hall device, but can use a hall ICs. But please add the voltage conversion circuit such as the figure because it is necessary to adapt the output amplitude of hall IC to the input voltage range of the IC. H1 is High, please set R3, R4 at the time of high so that the voltage ov VH1+ is as follows 3.5V. < Hall IC – Hall Device Exchange Circuit >

VICMH

3.5V

0V

R24.7kΩ

12V

NJW4305A

Hall IC H1

R130kΩ

R312kΩ

R44.7kΩ

3.4V

1.6V (H1-)

About 0V

Signal Amplitude

H1+

Time : t

NJW4305A

- 18 - Ver.2014-03-06


2. Output Block (WL, VL, UL / WH, VH, UH Pin) 2-1: Output for Lower Arm (120º Excitation Output + ON/OFF Output ) It is an output pin that can drive directly Nch FET gate for three-phase motor lower arm. The phase switching signal is output that generated by the hall signal. The output interrupter switch is built in. The PWM function by VERR/OSC, Protection function by Ct pin and OCP by ILIMIT are operating to the lower arm. Moreover, the voltage clamp circuit that prevents the excess voltage input to an external Nch FET gate is built in. The output series resistance is suppressing the transient current and/or vibration at the time of switching. In case of using 3A to 5A class MOS FET, you should consider the resistance value in the range of 100Ω to 1,000Ω. 2-2: Output Upper Arm (120º Excitation Output ) It is an output pin that can drive directly Pch FET gate for three-phase motor upper arm. The phase switching signal is output that generated by the hall signal. Because these are open-drain configuration, pull-up resistor is required. The upper arm output is different from the lower arm output, and the output interrupter switch is not built in. You should consider gate output series resistor value in the range from 100Ω to 1,000Ω as with the lower arm.

And you should set pull-up resistor that ensures sufficient VGS.

3. Forward / Reverse Function Switching (FR Pin) It is the pin that a motor forward / reverse function switching. It can switch the phase excitation sequence by the FR input logic. As a result, the direction where the motor is rotated can be switched. The sequence at the time of a motor rotation switching is shown below and the internal oscillator controls it. In addition, an internal oscillator is fixed with 18kHz, and becomes operation of normal rotation reversal at the 4th clock.

4. FG Output (FG Pin) It is the pin that outputs the pulse at the cycle proportional to the rotation of a motor. This pin is open-drain output of 7V absolute maximum rating. This pin should be pull-up with resistor to power supply that is 5V or more. This pin should be pull-up with resistor to power supply that is 5V or more. Do not connect this pin to power supply (VCC) or power supply for motor (VMM).

DeadTime

DeadTime

Brake

L

L LL

Based on a turn value Based on a turn value L

DeadTime

DeadTime

Brake

L LL

FR

CLK

Upper Arm

Lower Arm

NJW4305A

- 19 - Ver.2014-03-06

tDCHGOSC

tCHGOSC

VOSC

Time : t

VPOSC

VBOSC


5. Oscillation Block (VERR, OSC Pin) The PWM function is successively compared the DC voltage (VVERR) that is input to the VERR and the triangular wave (sawtooth wave) voltage (VOSC) generated from COSC connected with OSC. As a result, the lower arm output is turned on at VVERR>VOSC. The PWM frequency (fOSC) is determined by the following elements that are charging/discharging to COSC. : The triangular wave peak voltage (VPOSC), the bottom voltage (VBOSC), the charge current (ICHGOSC), and the discharge current (IDCHGOS). It is possible to approximate from the relation of ICHGOSC≪IDCHGOSC by the following formula. The COSC recommended value is from 330pF to 2200pF.

ITEM SYMBOL FORMULA Oscillation Frequency fOSC fOSC 35 106 / COSC

It is possible to use the direct PWM input that inputs duty controlled logic signal to VERR, and chopping driving the lower arm output. In this case, it should be biased to the OSC pin voltage with approx 2V (between 1V and 3V). In case of the ON duty is light at the time of the PWM signal is input to the VERR pin, the switching (power) device saturation and/or the ON resistance reduction might become insufficient. As the result, the switching device might cause unexpected heat. You should confirm that external power device ASO having sufficient margin to your application. Ex.: In cases of VERR=2.2V Fixed setting When the pull-up voltage is 5V, it should be pulled-up to approx 1.8kΩ. When the pull-up voltage is 12V, it should be pulled-up to approx 6.2kΩ. The output ON is when VERR is 2.2V or more.

fOSC=1/(tCHGOSC+tDCHGOSC)

VERR1.44kΩ

OSC

NJW4305A1.8kΩ(6.2kΩ)

5.0V(12V)

5.0V

OSC Voltage : About 2.2V

About 0V

Signal Amplitude

VERR Input Signal

Output Signal(UL, VL, WL)

Time : t

Time : t

NJW4305A

- 20 - Ver.2014-03-06

Rotate 1 Rotate Stop

Motor LockFG

VCt

VHCt

VLCt

tDCt1 tDCt2tRCt

Auto Release

Time : t

Time : t

Rotate 2 ( Low Speed than Rotate 1 ) Rotate Stop

Motor LockFG

VCt

VHCt

VLCt

tDCt1 tDCt2tRCt

Auto Release

Time : t

Time : t


6. Lock Protection Circuit / Lock Protection Locked Time, Lock Protection Release Time (Ct Pin) This pin is the setting pin for Lock Protection Time. It connects to capacitor (CCt). Under normal conditions the Ct pin feeds charge current (ICHGCt) through CCt. However, while the motor rotation the Ct is fast discharging CCt according to the edge timing of the FG signal. Therefore, the minute shape saw-tooth waveform appears as shown in the following figure at Ct pin. This Ct pin voltage VCt is approx 0V. When the hall signal is stopped after the motor locked, the fast discharge is lost and VCt rises gradually. When the VCt reaches lock protection H level voltage (VHCt), the low-side output (WL, VL, UL) becomes turned off (lock protection). The lock protection locked time (tDCt1) is defined the following: the time from the ICHGCt charge start time to the output OFF. When the VCt reaches the VHCt once, the Ct pin is discharged by discharge current (IDCHGCt), and the VCt pin voltage gradually comes down. The lock protection is released when VCt falls below lock protection L level voltage (VLCt), and returns to normal output (auto release). The lock protection release time (tRCt) is defined the following: the time from the CCt discharge start time to the output OFF is released. Even if output OFF is released, CCt begins the charging again when the hall signal is not input with the motor locked. As a result, when VCt exceeds VHCt, it becomes output OFF. The lock protection re-locked time (tDCt2) is defined the following: the time of until lock protection is re-operating. It is attention that the definition is different from the lock protection locked time (tDCt1). After that, the lock protection and an auto release are repeated for every tRCt and tDCt2 until FG signal is generated. The tDCt1/tDCt2/tRCt can be calculated by the following formulas. You should consider the CCt in the range of 0.1μF to 10μF.

ITEM SYMBOL FORMULA Lock Protection Locked Time

tDCt1 tDCt VHCt CCt / ICHGCt = 0.523 106 CCt

Lock Protection Re-locked Time

tDCt2 tDCt1 (VHCt-VLCt) CCt / ICHGCt = 0.369 106 CCt

Lock Protection Release Time

tRCt tRCt (VHCt-VLCt) CCt / IDCHGCt = 3.69 106 CCt

NJW4305A

- 21 - Ver.2014-03-06


At the during rotation 1 in the left figure, VCt waveform becomes a sawtooth waveform of approx 0V as described above. The during rotation 2 figure shows a case of slower status than at the during rotation 1 condition. And it shows the saw tooth waveform peak rises. When it is made extremely low-speed on the velocity changeable application etc., the FG signal edge timing might become long. As a result, VCt might rise and the lock protection circuit malfunctions. To avoid the lock protection malfunction, you should consider Ct discharge circuit adding or value adjustment of Ct. Moreover, when the Ct pin is connected to GND, this lock protection function is canceled. < Low-speed Lock Protection Operation Avoidance Circuit > It is Ct discharge circuit with the FG signal output. For example in the speed control application, the hall signals input timing becomes long at low speed time. Therefore, Ct voltage peak level rises and the lock protection circuit operates early. The Vct rise is suppressed by extending the rapid discharge time of Cct with the differentiation circuit by C1 and R1 and the comparator.

7. Over Current Detect Circuit (ILIMIT Pin) When the voltage that exceeds the detection voltage VDETLIM=0.28V typ. input to ILIMIT, all the lower arm output (UL, VL, WL) level is in “L” all. By flowing the resistor to match the source current of the lower arm of the external FET input to ILIMIT terminal voltages developed , and such a configuration can detect an overcurrent occurs in either r phase . ILIMIT will return as a trigger by local oscillator (typical frequency 18kHz) . This behavior is independent of the Hall signal, internal signal as rock protection and PWM signal from the VERR/OSC pins. If the speed of the motor is controlled by the duty signal input by external circuit to VERR, note that it can not output returns with the trigger by local oscillator , to stop the motor, therefore ILIMIT can be operated once. Since not only the winding current of the motor ,spike current of the number 100ns about caused by the charging and discharging of the parasitic capacitance of the external FET flows , short surge pulses are frequently entered the ILIMIT to RILIMIT. When the behavior of the ILIMIT comparator reacts to short pulses of them, there is the PWM pulse missing, causing a reduction of torque and/or rotation speed of the motor. By adding an RC low-pass filter to ILIMIT, it is possible to avoid the effects of such surge pulses. The product of C and R, I set the output voltage V of the RC circuit does not exceed VDETLIM. RC condition give the following:

NJW4305A

FG

CT

FG-IN

VREF(5V)

FG-OUTC1

RFG

R1

D1R2

R3

CCt

NJW4305A

- 22 - Ver.2014-03-06

Vi is the pulse voltage generated in the RILIMIT, t is the duration. ln means the natural logarithm. In order to obtain the RC value, it is assigned to vi the amplitude of the surge pulse, t the duration and VDETLIM the target value with standard minimum and some margin in this equation. Adjust R and C as appropriate while cheking the actual equipment. Example: VDETLIM = 0.22 [V] minimum standard and 0.03[V] margin, vi = 1 [V], for t = 1 [μs] Ans.: RC>4.02E-6 It is available in a combination such as R=4.3kohm, C=1nF. * Constant setting of other <Filter capacitor of the power supply> In order to reduce the influence to the Hall bias current, be installed capacitors C1 and C2 suppress variations i In VDD near the Hall bias resistors. C3 and C4 capacitors to suppress the fluctuation of the VMM by the motor winding current are also in consideration of the current loop, the wiring length to GND and the VMM do not be long carelessly.

i

DETLIM

vV

tCR1ln

NJW4305A

- 23 - Ver.2014-03-06

■ ELECTRICAL CHARACTERISTICS EXAMPLES < GENERAL >

Quiescent Current1 vs. Ambient TemperatureVCC=12V, H1+=H3+=3V, H2+=1V, H1-=H2-=H3-=2V,

FR=CT=ILIMIT=0V, VERR=5V, OSC=1V

2.0

2.5

3.0

3.5

4.0

4.5

5.0

-50 -25 0 25 50 75 100 125 150Ambient Temperature : Ta [ºC]

Qui

esce

nt C

urre

nt1

: IC

C1

[mA

]

< GENERAL >Quiescent Current1 vs. Ambient Temperature

VCC=24V, H1+=H3+=3V, H2+=1V, H1-=H2-=H3-=2V,FR=CT=ILIMIT=0V, VERR=5V, OSC=1V

2.0

2.5

3.0

3.5

4.0

4.5

5.0


Qui

esce

nt C

urre

nt2

: IC

C2

[mA

]

< GENERAL >Quiescent Current vs. Supply VoltageTa=25ºC, H1+=H3+=3V, H2+=1V, H1-=H2-=H3-=2V,


0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

0 5 10 15 20 25 30 35 40Supply Voltage : VCC [V]

Qui

esce

nt C

urre

nt :

I CC [m

A]

< UNDER VOLTAGE LOCK OUT BLOCK >UVLO Detect Voltage vs. Ambient Temperature

VCC Decreasing, H1+=H3+=3V, H2+=1V, H1-=H2-=H3-=2V,FR=CT=ILIMIT=0V, VERR=5V, OSC=1V

6

6.2

6.4

6.6

6.8

7

7.2


UV

LO D

etec

t Vol

tage

: V

DU

VLO

[V]

< UNDER VOLTAGE LOCK OUT BLOCK >UVLO Recovery Voltage vs. Ambient Temperature

VCC Increasing, H1+=H3+=3V, H2+=1V, H1-=H2-=H3-=2V,FR=CT=ILIMIT=0V, VERR=5V, OSC=1V

6

6.2

6.4

6.6

6.8

7

7.2


UV

LO R

ecov

ery

Vol

tage

: V

RU

VLO

[V]

0

0.05

0.1

0.15

0.2

0.25

0.3


UV

LO H

yste

resi

s V

olta

ge R

ange

: Δ

V UV

LO [V

]

< UNDER VOLTAGE LOCK OUT BLOCK >UVLO Hysteresis Voltage Range vs. Ambient Temperature

VCC =24V, H1+=H3+=3V, H2+=1V, H1-=H2-=H3-=2V,FR=CT=ILIMIT=0V, VERR=5V, OSC=1V

NJW4305A

- 24 - Ver.2014-03-06

■ ELECTRICAL CHARACTERISTICS EXAMPLES < LOCK DETECT BLOCK >

H Level Voltage vs. Ambient TemperatureVCC=24V, H1+=H3+=3V, H2+=1V, H1-=H2-=H3-=2V,

FR=ILIMIT=0V, VERR=5V, OSC=1V

3.20

3.25

3.30

3.35

3.40

3.45

3.50

3.55

3.60


H L

evel

Vol

tage

: V H

Ct [

V]

< LOCK DETECT BLOCK >L Level Voltage vs. Ambient Temperature

VCC=24V, H1+=H3+=3V, H2+=1V, H1-=H2-=H3-=2V,FR=ILIMIT=0V, VERR=5V, OSC=1V

0.80

0.85

0.90

0.95

1.00

1.05

1.10

1.15

1.20


L Le

vel V

olta

ge :

V LC

t [V

]

< LOCK DETECT BLOCK >Lock Charge Current vs. Ambient Temperature

VCt=0V2.5V, VCC=24V, H1+=H3+=3V, H2+=1V, H1-=H2-=H3-=2V,FR=ILIMIT=0V, VERR=5V, OSC=1V

4

5

6

7

8

9

10


Lock

Cha

rge

Cur

rent

: I C

HG

Ct

[μA

]

< LOCK DETECT BLOCK >Lock Discharge Current vs. Ambient TemperatureVCt=3.8V2.5V,VCC=24V, H1+=H3+=3V, H2+=1V, H1-=H2-=H3-=2V,

FR=ILIMIT=0V, VERR=5V, OSC=1V

0.3

0.4

0.5

0.6

0.7

0.8

0.9


Lock

Dis

char

ge C

urre

nt :

I DC

HG

Ct [μA

]

7

8

9

10

11

12

13


Lock

Cha

rge

Dis

char

ge C

urre

nt R

atio

:I C

HG

Ct/I

DC

HG

t

< LOCK DETECT BLOCK >Lock Charge Discharge Current Ratio vs. Ambient Temperature

VCC=24V, H1+=H3+=3V, H2+=1V, H1-=H2-=H3-=2V,FR=ILIMIT=0V, VERR=5V, OSC=1V

NJW4305A

- 25 - Ver.2014-03-06

■ ELECTRICAL CHARACTERISTICS EXAMPLES < HALL AMP BLOCK >

Hysteresis Voltage Range vs. Ambient TemperatureMEAS:VH1+, VCC=24V, H3+=3V, H2+=1V, H1-=H2-=H3-=2V,


10

15

20

25

30

35

40

45

50


Hys

tere

sis

Vol

tage

Ran

ge :

ΔV H

YS

H [m

V]

< HALL AMP BLOCK >Input Bias Current vs. Ambient TemperatureH1+=1V, H1-=3V, MEAS:IH1+, VCC=24V, H3+=3V, H2+=1V,

H2-=H3-=2V, FR=CT=ILIMIT=0V, VERR=5V, OSC=1V

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8


Inpu

t Bia

s C

urre

nt :

I BIH

[μA

]

< HIGH SIDE OUTPUT BLOCK >High Side Output Voltage vs. Ambient Temperature

H1+=H3+=1V, H2+=3V, UH=50mA, MEAS:VUH, VCC=24V,H1-=H2-=H3-=2V, FR=CT=ILIMIT=0V, VERR=5V, OSC=1V

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2


Hig

h S

ide

Out

put V

olta

ge :

V OLH

[V]

< HIGH SIDE OUTPUT BLOCK >High Side Leak Current vs. Ambient TemperatureUH=36V, MEAS:IUH, VCC=24V, H1+=H2+=H3+=3V, H1-=H2-=H3-=2V,


0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0


Hig

h S

ide

Leak

Cur

rent

: I O

LEA

KH [μ

A]

5

6

7

8

9

10

11

12

13


Low

Sid

e O

utpu

t Vol

tage

1 : V

OH

L1 [V

]

< LOW SIDE OUTPUT BLOCK >Low Side Output Voltage1 vs. Ambient Temperature

VCC=12V, UL=-50mA, MEAS: VUL, H1+=H3+=3V, H2+=1V,H1-=H2-=H3-=2V, FR=0V, VERR=3.5V, OSC=1V, CT=ILIMIT=0V

< LOW SIDE OUTPUT BLOCK >Low Side Output Voltage vs. Ambient Temperature

VCC=24V, UL=-50mA, MEAS: VUL, H1+=H3+=3V, H2+=1V,H1-=H2-=H3-=2V, FR=0V, VERR=3.5V, OSC=1V, CT=ILIMIT=0V

5

6

7

8

9

10

11

12

13


Low

Sid

e O

utpu

t Vol

tage

: V

OH

L2 [V

]

NJW4305A

- 26 - Ver.2014-03-06

■ ELECTRICAL CHARACTERISTICS EXAMPLES

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6


Low

Sid

e O

utpu

t L V

olta

ge :

V OLL

[V]

< LOW SIDE OUTPUT BLOCK >Low Side Output L Voltage vs. Ambient Temperature

VCC=24V, H1+=1V, H2+=H3+=3V, UL=150mA, MEAS:VUL,H1-=H2-=H3-=2V, FR=0V, VERR=5V, OSC=1V, CT=ILIMIT=0V

< LOW SIDE OUTPUT BLOCK >Low Side Clamp Voltage vs. Ambient Temperature

VCC=36V, UL=-0.1mA, MEAS:VUL, IH1+=H3+=3V, H2+=1V,H1-=H2-=H3-=2V, FR=0V, VERR=3.5V, OSC=1V, CT=ILIMIT=0V

5

6

7

8

9

10

11

12

13


Low

Sid

e C

lam

p V

olta

ge :

V OC

LL [V

]

< FG OUTPUT BLOCK >Output Voltage vs. Ambient Temperature

FG=10mA, VCC=24V, H1+=H2+=H3+=3V, H1-=H2-=H3-=2V,FR=CT=ILIMIT=0V, VERR=5V, OSC=1V

0.00

0.10

0.20

0.30

0.40

0.50

0.60


Out

put V

olta

ge :

VO

FG [V

]

< FG OUTPUT BLOCK >Leak Current vs. Ambient TemperatureH1+=1V, FG=5V, VCC=24V, H2+=H3+=3V, UL=150mA,

H1-=H2-=H3-=2V, FR=CT=ILIMIT=0V, VERR=5V, OSC=1V

0.0

0.1

0.2

0.3

0.4

0.5

0.6


Leak

Cur

rent

: I O

LEA

KFG

[μA

]

< OVER CURRENT DETECT BLOCK >

Detect Voltage vs. Ambient TemperatureVCC=24V, H1+=H2+=H3+=3V, H1-=H2-=H3-=2V,

FR=CT=0V, VERR=5V, OSC=1V

0.25

0.26

0.27

0.28

0.29

0.30

0.31


Det

ect V

olta

ge :

V DE

TLIM

[V]

< OVER CURRENT DETECT BLOCK >Input Bias Current vs. Ambient Temperature

VCC=24V, H1+=H2+=H3+=3V, H1-=H2-=H3-=2V, FR=CT=ILIMIT=0V,VERR=5V, OSC=1V

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0


Inpu

t Bia

s C

urre

nt :

I BLI

M [μ

A]

NJW4305A

- 27 - Ver.2014-03-06

■ ELECTRICAL CHARACTERISTICS EXAMPLES < ERROR AMP BLOCK >

Input Bias Current vs. Ambient TemperatureVERR=0V, VCC=24V, H1+=H3+=3V, H2+=1V, H1-=H2-=H3-=2V,

FR=CT=ILIMIT=0V, OSC=1V

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0


Inpu

t Bia

s C

urre

nt :

I BV

ER

R [μ

A]

< OSCILLATOR BLOCK >Saw Wave Peak Voltage vs. Ambient Temperature

VCC =24V, H1+=H3+=3V, H2+=1V, H1-=H2-=H3-=2V,FR=CT=ILIMIT=0V, VERR=5V

2.702.752.802.852.902.953.003.053.103.153.203.253.30


Saw

Wav

e P

eak

Vol

tage

: V

PO

SC [

V]

0.80

0.85

0.90

0.95

1.00

1.05

1.10

1.15

1.20


Saw

Wav

e B

otto

m V

olta

ge :

V BO

SC [V

]

< OSCILLATOR BLOCK >Saw Wave Bottom Voltage vs. Ambient Temperature

VCC =24V, H1+=H3+=3V, H2+=1V, H1-=H2-=H3-=2V,FR=CT=ILIMIT=0V, VERR=5V

< OSCILLATOR BLOCK >OSC Charge Current vs. Ambient Temperature

VCC =24V, H1+=H3+=3V, H2+=1V, H1-=H2-=H3-=2V,FR=CT=ILIMIT=0V, VERR=5V, OSC=0V->2.5V

50

60

70

80

90

100

110

120


OS

C C

harg

e C

urre

nt :

I CH

GO

SC [μ

A]

< OSCILLATOR BLOCK >OSC Discharge Current vs. Ambient Temperature

VCC =24V, H1+=H3+=3V, H2+=1V, H1-=H2-=H3-=2V,FR=CT=ILIMIT=0V, VERR=5V, OSC=5V->2.5V

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0


OS

C D

isch

arge

Cur

rent

:I D

CH

GO

SC [m

A]

< OSCILLATOR BLOCK >Oscillation Frequency vs. Ambient TemperatureCosc=1000pF, VCC =24V, H1+=H3+=3V, H2+=1V, H1-=H2-=H3-=2V,

FR=CT=ILIMIT=0V, VERR=5V

10

15

20

25

30

35

40

45

50


Osc

illat

ion

Freq

uenc

y : f

OS

C [k

Hz]

NJW4305A

- 28 - Ver.2014-03-06

■ ELECTRICAL CHARACTERISTICS EXAMPLES

< CONTROL INPUT BLOCK >H Level Input Current vs. Ambient Temperature

FR=5V, VCC=24V, H1+=H3+=3V, H2+=1V, H1-=H2-=H3-=2V,CT=ILIMIT=0V, VERR=5V, OSC=1V

30

40

50

60

70

80

90

100


H L

evel

Inpu

t Cur

rent

: I H

IN [μ

A]

< CONTROL INPUT BLOCK >L Level Input Current vs. Ambient Temperature


-0.2

-0.1

0.0

0.1

0.2

0.3

0.4

0.5

0.6


L Le

vel I

nput

Cur

rent

: I LI

N [μ

A]

50

60

70

80

90

100

110

120

130

140

150


Pul

l Dow

n R

esis

tanc

e : R

IN [kΩ

]

< CONTROL INPUT BLOCK >Pull Down Resistance vs. Ambient Temperature


NJW4305A

- 29 - Ver.2014-03-06

[CAUTION] The specifications on this databook are only

given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights.

Documents

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