2T1D Memory Cell with Voltage Gain

Wing K. Luk, Robert H. Dennard

Presented by:

Madhulika PannuriDepartment of Electrical Engineering

VLSI SYSTEMS I

1. Size: 100 k bits.

2. Power Supply: VDD = 1.2V and bit-line voltage = 0.6V.

3. Cell size: 100kb

4. Die size (using standard design rules) = 76F^2 ~ 2/3 SRAM cell. 120nm technology.

5. Word line material and routing width:

6. Cell capacitance: 2fF

7. Bit-line swing: 1.2V – 0.6V

8. Bit-line bias: 0.6V

9. Maximum refresh time: 70us @ room temperature.

10.Maximum cell / row: 256 cells / bitline.

11. Interfacing & clocking

12.External IO voltage

13. Burst Cycles supported:

14. Error Correcting

15. Number of banks

16.

a) The 2T1D dynamic memory cell uses two transistor and a gate diode (D).

b) The gate diode is a MOS device consisting of a gate and a source.

c) When the gate to source voltage is above a threshold voltage, substantial amount of charge is stored in the inversion region.

d) When the gate to source voltage is below threshold, the charge stored is less.

e) The DRAM cells the stored voltage to turn on a transistor in the read-out path. Thus a non-destructive read.

f) Low wordline voltage to drive the write devices, resulting in small word line drivers compared to conventional DRAM.

g) The voltage-sensitive capacitance characteristic of the gate diode and voltage boosting together provide 2T1D cell

- Voltage amplification of the internal stored voltage.

- Fast access

- Short cycle.

- Higher S/N ration

- low voltage operation.