28/40/44-Pin Enhanced Flash Microcontrollers with ECAN … · 2018. 10. 3. · PIC18F2585/2680/4585/4680 family introduces design enhancements that make these microcontrollers a logical

PIC18F2585/2680/4585/468028/40/44-Pin Enhanced Flash Microcontrollers with

ECAN™ Technology, 10-Bit A/D

Power Managed Modes:• Run: CPU on, peripherals on• Idle: CPU off, peripherals on• Sleep: CPU off, peripherals off• Idle mode currents down to 5.8 A typical• Sleep mode currents down to 0.1 A typical• Timer1 Oscillator: 1.1 A, 32 kHz, 2V• Watchdog Timer: 2.1 A• Two-Speed Oscillator Start-up

Flexible Oscillator Structure:• Four Crystal modes, up to 40 MHz• 4x Phase Lock Loop (PLL) – available for crystal

and internal oscillators• Two External RC modes, up to 4 MHz• Two External Clock modes, up to 40 MHz• Internal oscillator block:

- 8 user selectable frequencies, from 31 kHz to 8 MHz- Provides a complete range of clock speeds,

from 31 kHz to 32 MHz when used with PLL- User tunable to compensate for frequency drift

• Secondary oscillator using Timer1 @ 32 kHz• Fail-Safe Clock Monitor

- Allows for safe shutdown if peripheral clock stops

Special Microcontroller Features:• C compiler optimized architecture with optional

extended instruction set• 100,000 erase/write cycle Enhanced Flash

program memory typical• 1,000,000 erase/write cycle Data EEPROM

memory typical• Flash/Data EEPROM Retention: > 40 years• Self-programmable under software control• Priority levels for interrupts• 8 x 8 Single Cycle Hardware Multiplier• Extended Watchdog Timer (WDT):

- Programmable period from 41 ms to 131s• Single-Supply 5V In-Circuit Serial

Programming™ (ICSP™) via two pins• In-Circuit Debug (ICD) via two pins• Wide operating voltage range: 2.0V to 5.5V

Peripheral Highlights:• High current sink/source 25 mA/25 mA• Three external interrupts• One Capture/Compare/PWM (CCP1) module• Enhanced Capture/Compare/PWM (ECCP1) module

(40/44-pin devices only):

- One, two or four PWM outputs- Selectable polarity- Programmable dead time- Auto-Shutdown and Auto-Restart

• Master Synchronous Serial Port (MSSP) module supporting 3-wire SPI (all 4 modes) and I2C™ Master and Slave modes

• Enhanced Addressable USART module:- Supports RS-485, RS-232 and LIN 1.3- RS-232 operation using internal oscillator

block (no external crystal required)- Auto-Wake-up on Start bit- Auto-Baud Detect

• 10-bit, up to 11-channel Analog-to-Digital Converter module (A/D), up to 100 Ksps- Auto-acquisition capability- Conversion available during Sleep

• Dual analog comparators with input multiplexing

ECAN Module Features:• Message bit rates up to 1 Mbps• Conforms to CAN 2.0B ACTIVE Specification• Fully backward compatible with PIC18XXX8 CAN

modules• Three modes of operation:

- Legacy, Enhanced Legacy, FIFO• Three dedicated transmit buffers with prioritization• Two dedicated receive buffers• Six programmable receive/transmit buffers• Three full 29-bit acceptance masks• 16 full 29-bit acceptance filters w/ dynamic association• DeviceNet™ data byte filter support• Automatic remote frame handling• Advanced error management features

2007-2018 Microchip Technology Inc. DS30009625D-page 1

PIC18F2585/2680/4585/4680

Pin Diagrams

DeviceProgram Memory Data Memory

I/O 10-BitA/D (ch)CCP1/ECCP1(PWM)

MSSP

EUSA

RT

Comp. Timers8/16-bitFlash(bytes)

# Single-WordInstructions

SRAM(bytes)

EEPROM(bytes) SPI

MasterI2C™

PIC18F2585 48K 24576 3328 1024 28 8 1/0 Y Y 1 0 1/3PIC18F2680 64K 32768 3328 1024 28 8 1/0 Y Y 1 0 1/3PIC18F4585 48K 24576 3328 1024 44 11 1/1 Y Y 1 2 1/3PIC18F4680 64K 32768 3328 1024 40/44 11 1/1 Y Y 1 2 1/3

RB7/KBI3/PGDRB6/KBI2/PGCRB5/KBI1/PGMRB4/KBI0/AN9RB3/CANRXRB2/INT2/CANTXRB1/INT1/AN8RB0/INT0/FLT0/AN10VDDVSSRD7/PSP7/P1DRD6/PSP6/P1CRD5/PSP5/P1BRD4/PSP4/ECCP1/P1ARC7/RX/DTRC6/TX/CKRC5/SDORC4/SDI/SDARD3/PSP3/C2IN-RD2/PSP2/C2IN+

MCLR/VPP/RE3RA0/AN0/CVREF

RA1/AN1RA2/AN2/VREF-RA3/AN3/VREF+

RA4/T0CKIRA5/AN4/SS/HLVDIN

RE0/RD/AN5RE1/WR/AN6/C1OUTRE2/CS/AN7/C2OUT

VDDVSS

OSC1/CLKI/RA7OSC2/CLKO/RA6

RC0/T1OSO/T13CKIRC1/T1OSIRC2/CCP1

RC3/SCK/SCLRD0/PSP0/C1IN+RD1/PSP1/C1IN-

1234567891011121314151617181920

4039383736353433323130292827262524232221

PIC

18F4

585

40-Pin PDIP

PIC

18F4

680

PIC

18F2

585

1011

23456

1

87

9

121314 15

1617181920

232425262728

2221

MCLR/VPP/RE3RA0/AN0RA1/AN1

RA2/AN2/VREF-RA3/AN3/VREF+


VSSOSC1/CLKI/RA7

OSC2/CLKO/RA6RC0/T1OSO/T13CKI

RC1/T1OSIRC2/CCP1

RC3/SCK/SCL

RB7/KBI3/PGDRB6/KBI2/PGCRB5/KBI1/PGMRB4/KBI0/AN9RB3/CANRXRB2/INT2/CANTXRB1/INT1/AN8RB0/INT0/AN10VDDVSSRC7/RX/DTRC6/TX/CKRC5/SDORC4/SDI/SDA

28-Pin PDIP, SOIC

PIC

18F2

680


PIC18F2585/2680/4585/4680

Pin Diagrams (Continued)

1011

23

6

1

18 19 20 21 2212 13 14 15

38

87

44 43 42 41 40 3916 17

2930313233

232425262728

36 3435

9

PIC18F4585

37

RA

3/A

N3/

VRE

F+R

A2/A

N2/

V RE

F-R

A1/

AN

1R

A0/

AN

0/C

VRE

FM

CLR

/VP

P/R

E3

NC

RB7

/KB

I3/P

GD

RB6

/KB

I2/P

GC

RB5

/KB

I1/P

GM

RB4

/KB

I0/A

N9

NC

RC

6/TX

/CK

RC

5/S

DO

RC

4/S

DI/S

DA

RD

3/P

SP3/

C2I

N-

RD

2/P

SP2/

C2I

N+

RD

1/P

SP1/

C1I

N-

RD

0/P

SP0/

C1I

N+

RC

3/S

CK/

SCL

RC

2/C

CP

1R

C1/

T1O

SI

NC

NCRC0/T1OSO/T13CKIOSC2/CLKO/RA6OSC1/CLKI/RA7VSSVDDRE2/CS/AN7/C2OUTRE1/WR/AN6/C1OUTRE0/RD/AN5RA5/AN4/SS/HLVDINRA4/T0CKI

RC7/RX/DTRD4/PSP4/ECCP1/P1A

RD5/PSP5/P1BRD6/PSP6/P1C

VSSVDD

RB0/INT0/FLT0/AN10RB1/INT1/AN8

RB2/INT2/CANTXRB3/CANRX

44-Pin TQFP

RD7/PSP7/P1D 54

44-Pin QFN

1011

23

6

1

18 19 20 21 2212 13 14 15

38

87

44 43 42 41 40 3916 17

2930313233

232425262728

36 3435

9

PIC18F4585

37

RA

3/A

N3/

VRE

F+R

A2/

AN

2/VR

EF-

RA

1/A

N1

RA

0/A

N0/

CVR

EF

MC

LR/V

PP/R

E3

RB7

/KB

I3/P

GD

RB6

/KB

I2/P

GC

RB5

/KB

I1/P

GM

RB

4/K

BI0

/AN

9N

CR

C6/

TX/C

KR

C5/

SD

OR

C4/

SD

I/SD

AR

D3/

PS

P3/C

2IN

-R

D2/

PS

P2/C

2IN

+R

D1/

PS

P1/C

1IN

-R

D0/

PS

P0/C

1IN

+R

C3/

SC

K/S

CL

RC

2/C

CP1

RC

1/T1

OS

IR

C0/

T1O

SO

/T13

CK

I

OSC2/CLKO/RA6OSC1/CLKI/RA7VSS

AVDDRE2/CS/AN7/C2OUTRE1/WR/AN6/C1OUTRE0/RD/AN5RA5/AN4/SS/HLVDINRA4/T0CKI

RC7/RX/DT

RD5/PSP5/P1BRD6/PSP6/P1C

VSS

VDDRB0/INT0/FLT0/AN10

RB1/INT1/AN8RB2/INT2/CANTX

RB

3/C

AN

RX

RD7/PSP7/P1D 54 AVSS

VDD

AVDD

PIC18F4680

PIC18F4680

RD4/PSP4/ECCP1/P1A


PIC18F2585/2680/4585/4680

Table of Contents1.0 Device Overview .......................................................................................................................................................................... 72.0 Oscillator Configurations ............................................................................................................................................................ 233.0 Power Managed Modes ............................................................................................................................................................. 334.0 Reset .......................................................................................................................................................................................... 415.0 Memory Organization ................................................................................................................................................................. 616.0 Flash Program Memory.............................................................................................................................................................. 957.0 Data EEPROM Memory ........................................................................................................................................................... 1058.0 8 x 8 Hardware Multiplier.......................................................................................................................................................... 1119.0 Interrupts .................................................................................................................................................................................. 11310.0 I/O Ports ................................................................................................................................................................................... 12911.0 Timer0 Module ......................................................................................................................................................................... 14712.0 Timer1 Module ......................................................................................................................................................................... 15113.0 Timer2 Module ......................................................................................................................................................................... 15714.0 Timer3 Module ......................................................................................................................................................................... 15915.0 Capture/Compare/PWM (CCP1) Modules ............................................................................................................................... 16316.0 Enhanced Capture/Compare/PWM (ECCP1) Module.............................................................................................................. 17317.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 18718.0 Enhanced Universal Synchronous Receiver Transmitter (EUSART)....................................................................................... 22719.0 10-Bit Analog-to-Digital Converter (A/D) Module ..................................................................................................................... 24720.0 Comparator Module.................................................................................................................................................................. 25721.0 Comparator Voltage Reference Module................................................................................................................................... 26322.0 High/Low-Voltage Detect (HLVD)............................................................................................................................................. 26723.0 ECAN™ Technology ................................................................................................................................................................ 27324.0 Special Features of the CPU.................................................................................................................................................... 34325.0 Instruction Set Summary .......................................................................................................................................................... 36126.0 Development Support............................................................................................................................................................... 41127.0 Electrical Characteristics .......................................................................................................................................................... 41528.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 45129.0 Packaging Information.............................................................................................................................................................. 453Appendix A: Revision History............................................................................................................................................................. 461Appendix B: Device Differences ........................................................................................................................................................ 461Appendix C: Conversion Considerations ........................................................................................................................................... 462Appendix D: Migration From Baseline to Enhanced Devices ............................................................................................................ 462Appendix E: Migration from Mid-Range to Enhanced Devices .......................................................................................................... 463Appendix F: Migration from High-End to Enhanced Devices............................................................................................................. 463The Microchip Web Site..................................................................................................................................................................... 477Customer Change Notification Service .............................................................................................................................................. 477Customer Support .............................................................................................................................................................................. 477Reader Response .............................................................................................................................................................................. 478PIC18F2585/2680/4585/4680 Product Identification System ............................................................................................................ 479


PIC18F2585/2680/4585/4680

TO OUR VALUED CUSTOMERSIt is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchipproducts. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined andenhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department viaE-mail at [email protected]. We welcome your feedback.

Most Current Data SheetTo obtain the most up-to-date version of this data sheet, please register at our Worldwide Website at:

http://www.microchip.comYou can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).

ErrataAn errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for currentdevices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revisionof silicon and revision of document to which it applies.To determine if an errata sheet exists for a particular device, please check with one of the following:• Microchip’s Worldwide Website; http://www.microchip.com• Your local Microchip sales office (see last page)When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you areusing.

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mailto:[email protected]://www.microchip.comhttp://www.microchip.com

PIC18F2585/2680/4585/4680

1.0 DEVICE OVERVIEWThis document contains device specific information forthe following devices:

• PIC18F2585• PIC18F2680• PIC18F4585• PIC18F4680

This family of devices offers the advantages of all PIC18microcontrollers – namely, high computationalperformance at an economical price – with the additionof high-endurance, Enhanced Flash program memory.In addition to these features, thePIC18F2585/2680/4585/4680 family introduces designenhancements that make these microcontrollers alogical choice for many high-performance, powersensitive applications.

1.1 New Core Features

1.1.1 TECHNOLOGYAll of the devices in the PIC18F2585/2680/4585/4680family incorporate a range of features that can signifi-cantly reduce power consumption during operation.Key items include:

• Alternate Run Modes: By clocking the controller from the Timer1 source or the internal oscillator block, power consumption during code execution can be reduced by as much as 90%.

• Multiple Idle Modes: The controller can also run with its CPU core disabled but the peripherals still active. In these states, power consumption can be reduced even further, to as little as 4% of normal operation requirements.

• On-the-fly Mode Switching: The power managed modes are invoked by user code during operation, allowing the user to incorporate power-saving ideas into their application’s software design.

• Lower Consumption in Key Modules: The power requirements for both Timer1 and the Watchdog Timer have been reduced by up to 80%, with typical values of 1.1 and 2.1 A, respectively.

• Extended Instruction Set: In addition to the standard 75 instructions of the PIC18 instruction set, PIC18F2585/2680/4585/4680 devices also provide an optional extension to the core CPU functionality. The added features include eight additional instructions that augment indirect and indexed addressing operations and the implementation of Indexed Literal Offset Addressing mode for many of the standard PIC18 instructions.

1.1.2 MULTIPLE OSCILLATOR OPTIONS AND FEATURES

All of the devices in the PIC18F2585/2680/4585/4680family offer ten different oscillator options, allowingusers a wide range of choices in developing applicationhardware. These include:

• Four Crystal modes, using crystals or ceramic resonators

• Two External Clock modes, offering the option of using two pins (oscillator input and a divide-by-4 clock output) or one pin (oscillator input, with the second pin reassigned as general I/O)

• Two External RC Oscillator modes with the same pin options as the External Clock modes

• An internal oscillator block which provides an 8 MHz clock (±2% accuracy) and an INTRC source (approximately 31 kHz, stable over temperature and VDD), as well as a range of 6 user selectable clock frequencies, between 125 kHz to 4 MHz, for a total of 8 clock frequencies. This option frees the two oscillator pins for use as additional general purpose I/O.

• A Phase Lock Loop (PLL) frequency multiplier, available to both the high-speed crystal and internal oscillator modes, which allows clock speeds of up to 40 MHz. Used with the internal oscillator, the PLL gives users a complete selection of clock speeds, from 31 kHz to 32 MHz – all without using an external crystal or clock circuit.

Besides its availability as a clock source, the internaloscillator block provides a stable reference source thatgives the family additional features for robustoperation:

• Fail-Safe Clock Monitor: This option constantly monitors the main clock source against a refer-ence signal provided by the internal oscillator. If a clock failure occurs, the controller is switched to the internal oscillator block, allowing for continued low-speed operation or a safe application shutdown.

• Two-Speed Start-up: This option allows the internal oscillator to serve as the clock source from Power-on Reset, or wake-up from Sleep mode, until the primary clock source is available.


PIC18F2585/2680/4585/4680

1.2 Other Special Features• Memory Endurance: The Enhanced Flash cells

for both program memory and data EEPROM are rated to last for many thousands of erase/write cycles – up to 100,000 for program memory and 1,000,000 for EEPROM. Data retention without refresh is conservatively estimated to be greater than 40 years.

• Self-programmability: These devices can write to their own program memory spaces under inter-nal software control. By using a bootloader routine located in the protected Boot Block at the top of program memory, it becomes possible to create an application that can update itself in the field.

• Extended Instruction Set: The PIC18F2585/2680/4585/4680 family introduces an optional extension to the PIC18 instruction set, which adds 8 new instructions and an Indexed Addressing mode. This extension, enabled as a device configuration option, has been specifically designed to optimize re-entrant application code originally developed in high-level languages, such as C.

• Enhanced CCP1 module: In PWM mode, this module provides 1, 2 or 4 modulated outputs for controlling half-bridge and full-bridge drivers. Other features include Auto-Shutdown, for disabling PWM outputs on interrupt or other select conditions and Auto-Restart, to reactivate outputs once the condition has cleared.

• Enhanced Addressable USART: This serial communication module is capable of standard RS-232 operation and provides support for the LIN bus protocol. Other enhancements include automatic baud rate detection and a 16-bit Baud Rate Generator for improved resolution. When the microcontroller is using the internal oscillator block, the EUSART provides stable operation for applications that talk to the outside world without using an external crystal (or its accompanying power requirement).

• 10-bit A/D Converter: This module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period and thus, reduce code overhead.

• Extended Watchdog Timer (WDT): This enhanced version incorporates a 16-bit prescaler, allowing a time-out range from 4 ms to over 131 seconds, that is stable across operating voltage and temperature.

1.3 Details on Individual Family Members

Devices in the PIC18F2585/2680/4585/4680 family areavailable in 28-pin (PIC18F2X8X) and 40/44-pin(PIC18F4X8X) packages. Block diagrams for the twogroups are shown in Figure 1-1 and Figure 1-2.

The devices are differentiated from each other in sixways:

1. Flash program memory (48 Kbytes forPIC18FX585 devices, 64 Kbytes forPIC18FX680).

2. A/D channels (8 for PIC18F2X8X devices, 11 forPIC18F4X8X devices).

3. I/O ports (3 bidirectional ports and 1 input onlyport on PIC18F2X8X devices, 5 bidirectionalports on PIC18F4X8X devices).

4. CCP1 and Enhanced CCP1 implementation(PIC18F2X8X devices have 1 standard CCP1module, PIC18F4X8X devices have onestandard CCP1 module and one ECCP1module).

5. Parallel Slave Port (present only onPIC18F4X8X devices).

6. PIC18F4X8X devices provide two comparators.

All other features for devices in this family are identical.These are summarized in Table 1-1.

The pinouts for all devices are listed in Table 1-2 andTable 1-3.

Like all Microchip PIC18 devices, members of thePIC18F2585/2680/4585/4680 family are available asboth standard and low-voltage devices. Standarddevices with Enhanced Flash memory, designated withan “F” in the part number (such as PIC18F2585),accommodate an operating VDD range of 4.2V to 5.5V.Low-voltage parts, designated by “LF” (such asPIC18LF2585), function over an extended VDD rangeof 2.0V to 5.5V.


PIC18F2585/2680/4585/4680

TABLE 1-1: DEVICE FEATURES

Features PIC18F2585 PIC18F2680 PIC18F4585 PIC18F4680

Operating Frequency DC – 40 MHz DC – 40 MHz DC – 40 MHz DC – 40 MHzProgram Memory (Bytes) 49152 65536 49152 65536Program Memory (Instructions) 24576 32768 24576 32768Data Memory (Bytes) 3328 3328 3328 3328Data EEPROM Memory (Bytes) 1024 1024 1024 1024Interrupt Sources 19 19 20 20I/O Ports Ports A, B, C, (E) Ports A, B, C, (E) Ports A, B, C, D, E Ports A, B, C, D, ETimers 4 4 4 4Capture/Compare/PWM Modules 1 1 1 1Enhanced Capture/Compare/PWM Modules

0 0 1 1

ECAN Module 1 1 1 1Serial Communications MSSP,

Enhanced USARTMSSP,

Enhanced USARTMSSP,

Enhanced USARTMSSP,

Enhanced USARTParallel Communications (PSP) No No Yes Yes10-bit Analog-to-Digital Module 8 Input Channels 8 Input Channels 11 Input Channels 11 Input ChannelsComparators 0 0 2 2Resets (and Delays) POR, BOR,

RESET Instruction, Stack Full,

Stack Underflow (PWRT, OST),

MCLR (optional),WDT

POR, BOR, RESET Instruction,

Stack Full, Stack Underflow (PWRT, OST),

MCLR (optional),WDT



MCLR (optional),WDT



MCLR (optional),WDT

Programmable High/Low-Voltage Detect

Yes Yes Yes Yes

Programmable Brown-out Reset Yes Yes Yes YesInstruction Set 75 Instructions;

83 with Extended Instruction Set

enabled

75 Instructions; 83 with Extended

Instruction Set enabled





Packages 28-pin PDIP28-pin SOIC

28-pin PDIP28-pin SOIC

40-pin PDIP44-pin QFN

44-pin TQFP

40-pin PDIP44-pin QFN

44-pin TQFP


PIC18F2585/2680/4585/4680

FIGURE 1-1: PIC18F2585/2680 (28-PIN) BLOCK DIAGRAM

InstructionDecode &

Control

PORTA

PORTB

PORTC


RB0/INT0/AN10

RC0/T1OSO/T13CKIRC1/T1OSIRC2/CCP1RC3/SCK/SCLRC4/SDI/SDARC5/SDORC6/TX/CKRC7/RX/DT

RA3/AN3/VREF+RA2/AN2/VREF-RA1/AN1RA0/AN0

RB1/INT1/AN8

Data Latch

Data Memory(3.9 Kbytes)

Address Latch

Data Address12

AccessBSR4 4

PCH PCL

PCLATH

8

31 Level Stack

Program Counter

PRODLPRODH

8 x 8 Multiply

8

88

ALU

Address Latch

Program Memory(48/64 Kbytes)

Data Latch

20

8

8

Table Pointer

inc/dec logic

21

8

Data Bus

Table Latch8

IR

12

3

ROM Latch

RB2/INT2/CANTXRB3/CANRX

PCLATU

PCU

PORTE

MCLR/VPP/RE3(1)

OSC2/CLKO/RA6

Note 1: RE3 is multiplexed with MCLR and is only available when the MCLR Resets are disabled.2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O.

Refer to Section 2.0 “Oscillator Configurations” for additional information.

RB4/KBI0/AN9RB5/KBI1/PGMRB6/KBI2/PGCRB7/KBI3/PGD

EUSARTComparator MSSP 10-bit ADC

Timer2Timer1 Timer3Timer0

ECCP1

HLVD

CCP1

BOR DataEEPROM

W

Instruction Bus

STKPTR Bank

8

State MachineControl Signals

8

8Power-up

TimerOscillator

Start-up TimerPower-on

ResetWatchdog

Timer

OSC1(2)

OSC2(2)

VDD,

Brown-outReset

InternalOscillator

Fail-SafeClock Monitor

ReferenceBand Gap

VSS

MCLR(1)

Block

INTRCOscillator

8 MHzOscillator

Single-SupplyProgramming

In-CircuitDebugger

T1OSI

T1OSO

OSC1/CLKI/RA7

ECAN

BITOP

FSR0FSR1FSR2

inc/dec

Address

12

Decode

logic


PIC18F2585/2680/4585/4680

FIGURE 1-2: PIC18F4585/4680 (40/44-PIN) BLOCK DIAGRAM

InstructionDecode &

Control

Data Latch

Data Memory(3.9 Kbytes)

Address Latch

Data Address12

AccessBSR4 4

PCH PCL

PCLATH

8

31 Level Stack

Program Counter

PRODLPRODH

8 x 8 Multiply

8

BITOP88

ALU

Address Latch

Program Memory(48/64 Kbytes)

Data Latch

20

8

8

Table Pointer

inc/dec logic

21

8

Data Bus

Table Latch8

IR

12

3

ROM Latch

PORTDRD0/PSP0

PCLATU

PCU

PORTE

MCLR/VPP/RE3(1)RE2/CS/AN7/C2OUT

RE0/RD/AN5RE1/WR/AN6/C1OUT

Note 1: RE3 is multiplexed with MCLR and is only available when the MCLR Resets are disabled.2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O.

Refer to Section 2.0 “Oscillator Configurations” for additional information.

/C1IN+

EUSARTComparator MSSP 10-bit ADC

Timer2Timer1 Timer3Timer0

CCP1

HLVD

ECCP1

BOR DataEEPROM

W

Instruction Bus

STKPTR Bank

8

State MachineControl Signals

8

8Power-up

TimerOscillator

Start-up TimerPower-on

ResetWatchdog

Timer

OSC1(2)

OSC2(2)

VDD,

Brown-outReset

InternalOscillator

Fail-SafeClock Monitor

ReferenceBand Gap

VSS

MCLR(1)

Block

INTRCOscillator

8 MHzOscillator

Single-SupplyProgramming

In-CircuitDebugger

T1OSI

T1OSO

RD1/PSP1/C1IN-RD2/PSP2/C2IN+RD3/PSP3/C2IN-

PORTA

PORTB

PORTC


RB0/INT0/FLT0/AN10

RC0/T1OSO/T13CKIRC1/T1OSIRC2/CCP1RC3/SCK/SCLRC4/SDI/SDARC5/SDORC6/TX/CKRC7/RX/DT

RA3/AN3/VREF+RA2/AN2/VREF-RA1/AN1RA0/AN0/CVREF

RB1/INT1/AN8RB2/INT2/CANTXRB3/CANRX

OSC2/CLKO/RA6

RB4/KBI0/AN9RB5/KBI1/PGMRB6/KBI2/PGCRB7/KBI3/PGD

OSC1/CLKI/RA7

ECAN

FSR0FSR1FSR2

inc/dec

Address

12

Decode

logic

RD4/PSP4/ECCP1/P1ARD5/PSP5/P1BRD6/PSP6/P1CRD7/PSP7/P1D


PIC18F2585/2680/4585/4680

TABLE 1-2: PIC18F2585/2680 PINOUT I/O DESCRIPTIONS

Pin Name

Pin Number Pin

TypeBufferType DescriptionPDIP,

SOIC

MCLR/VPP/RE3MCLR

VPPRE3

1I

PI

ST

ST

Master Clear (input) or programming voltage (input).Master Clear (Reset) input. This pin is an active-low Reset to the device.Programming voltage input.Digital input.

OSC1/CLKI/RA7OSC1

CLKI

RA7

9I

I

I/O

ST

CMOS

TTL

Oscillator crystal or external clock input.Oscillator crystal input or external clock source input. ST buffer when configured in RC mode; CMOS otherwise.External clock source input. Always associated with pin function OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.)General purpose I/O pin.

OSC2/CLKO/RA6OSC2

CLKO

RA6

10O

O

I/O

—

—

TTL

Oscillator crystal or clock output.Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode.In RC mode, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. General purpose I/O pin.

Legend: TTL = TTL compatible input CMOS= CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I= Input O = Output P = Power


PIC18F2585/2680/4585/4680

PORTA is a bidirectional I/O port.RA0/AN0

RA0AN0

2I/OI

TTLAnalog

Digital I/O.Analog input 0.

RA1/AN1RA1AN1

3I/OI

TTLAnalog


RA2/AN2/VREF-RA2AN2VREF-

4I/OII

TTLAnalogAnalog

Digital I/O.Analog input 2.A/D reference voltage (low) input.

RA3/AN3/VREF+RA3AN3VREF+

5I/OII

TTLAnalogAnalog

Digital I/O.Analog input 3.A/D reference voltage (high) input.

RA4/T0CKIRA4T0CKI

6I/OI

TTLST

Digital I/O.Timer0 external clock input.

RA5/AN4/SS/HLVDINRA5AN4SSHLVDIN

7I/OIII

TTLAnalog

TTLAnalog

Digital I/O.Analog input 4. SPI slave select input.High/Low-Voltage Detect input.

RA6 See the OSC2/CLKO/RA6 pin.RA7 See the OSC1/CLKI/RA7 pin.

TABLE 1-2: PIC18F2585/2680 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number Pin


SOIC



PIC18F2585/2680/4585/4680

PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.

RB0/INT0/AN10RB0INT0AN10

21I/OII

TTLST

Analog

Digital I/O.External interrupt 0.Analog input 10.


22I/OII

TTLST

Analog


RB2/INT2/CANTXRB2INT2CANTX

23I/OIO

TTLSTTTL

Digital I/O.External interrupt 2.CAN bus TX.

RB3/CANRXRB3CANRX

24I/OI

TTLTTL

Digital I/O.CAN bus RX.

RB4/KBI0/AN9RB4KBI0AN9

25I/OII

TTLTTL

Analog

Digital I/O.Interrupt-on-change pin.Analog input 9.

RB5/KBI1/PGMRB5KBI1PGM

26I/OI

I/O

TTLTTLST

Digital I/O.Interrupt-on-change pin.Low-Voltage ICSP™ Programming enable pin.

RB6/KBI2/PGCRB6KBI2PGC

27I/OI

I/O

TTLTTLST

Digital I/O.Interrupt-on-change pin. In-Circuit Debugger and ICSP programming clock pin.

RB7/KBI3/PGDRB7KBI3PGD

28I/OI

I/O

TTLTTLST

Digital I/O.Interrupt-on-change pin. In-Circuit Debugger and ICSP programming data pin.


Pin Name

Pin Number Pin


SOIC



PIC18F2585/2680/4585/4680

PORTC is a bidirectional I/O port.RC0/T1OSO/T13CKI

RC0T1OSOT13CKI

11I/OOI

ST—ST

Digital I/O.Timer1 oscillator output. Timer1/Timer3 external clock input.

RC1/T1OSIRC1T1OSI

12I/OI

STCMOS

Digital I/O.Timer1 oscillator input.

RC2/CCP1RC2CCP1

13I/OI/O

STST

Digital I/O.Capture1 input/Compare1 output/PWM1 output.

RC3/SCK/SCLRC3SCKSCL

14I/OI/OI/O

STSTST

Digital I/O.Synchronous serial clock input/output for SPI mode.Synchronous serial clock input/output for I2C™ mode.

RC4/SDI/SDARC4SDISDA

15I/OI

I/O

STSTST

Digital I/O.SPI data in.I2C data I/O.

RC5/SDORC5SDO

16I/OO

ST—

Digital I/O.SPI data out.

RC6/TX/CKRC6TXCK

17I/OO

I/O

ST—ST

Digital I/O.EUSART asynchronous transmit. EUSART synchronous clock (see related RX/DT).

RC7/RX/DTRC7RXDT

18I/OI

I/O

STSTST

Digital I/O.EUSART asynchronous receive.EUSART synchronous data (see related TX/CK).

RE3 — — — See MCLR/VPP/RE3 pin.VSS 8, 19 P — Ground reference for logic and I/O pins.VDD 20 P — Positive supply for logic and I/O pins.


Pin Name

Pin Number Pin


SOIC



PIC18F2585/2680/4585/4680

TABLE 1-3: PIC18F4585/4680 PINOUT I/O DESCRIPTIONS

Pin NamePin Number Pin

TypeBufferType DescriptionPDIP QFN TQFP

MCLR/VPP/RE3MCLR

VPPRE3

1 18 18I

PI

ST

ST

Master Clear (input) or programming voltage (input).Master Clear (Reset) input. This pin is an active-low Reset to the device.Programming voltage input.Digital input.

OSC1/CLKI/RA7OSC1

CLKI

RA7

13 32 30I

I

I/O

ST

CMOS

TTL

Oscillator crystal or external clock input.Oscillator crystal input or external clock source input. ST buffer when configured in RC mode; CMOS otherwise.External clock source input. Always associated with pin function OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.)General purpose I/O pin.

OSC2/CLKO/RA6OSC2

CLKO

RA6

14 33 31O

O

I/O

—

—

TTL

Oscillator crystal or clock output.Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode.In RC mode, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. General purpose I/O pin.



PIC18F2585/2680/4585/4680

PORTA is a bidirectional I/O port.RA0/AN0/CVREF

RA0AN0CVREF

2 19 19I/OIO

TTLAnalogAnalog

Digital I/O.Analog input 0.Analog comparator reference output.

RA1/AN1RA1AN1

3 20 20I/OI

TTLAnalog


RA2/AN2/VREF-RA2AN2VREF-

4 21 21I/OII

TTLAnalogAnalog

Digital I/O.Analog input 2.A/D reference voltage (low) input.

RA3/AN3/VREF+RA3AN3VREF+

5 22 22I/OII

TTLAnalogAnalog

Digital I/O.Analog input 3.A/D reference voltage (high) input.

RA4/T0CKIRA4T0CKI

6 23 23I/OI

TTLST

Digital I/O.Timer0 external clock input.

RA5/AN4/SS/HLVDINRA5AN4SSHLVDIN

7 24 24I/OIII

TTLAnalog

TTLAnalog

Digital I/O.Analog input 4.SPI slave select input.High/Low-Voltage Detect input.

RA6 See the OSC2/CLKO/RA6 pin.RA7 See the OSC1/CLKI/RA7 pin.






PIC18F2585/2680/4585/4680

PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.

RB0/INT0/FLT0/AN10RB0INT0FLT0AN10

33 9 8I/OIII

TTLSTST

Analog

Digital I/O.External interrupt 0.Enhanced PWM Fault input (ECCP1 module).Analog input 10.


34 10 9I/OII

TTLST

Analog


RB2/INT2/CANTXRB2INT2CANTX

35 11 10I/OIO

TTLSTTTL

Digital I/O.External interrupt 2.CAN bus TX.

RB3/CANRXRB3CANRX

36 12 11I/OI

TTLTTL

Digital I/O.CAN bus RX.

RB4/KBI0/AN9RB4KBI0AN9

37 14 14I/OII

TTLTTL

Analog

Digital I/O.Interrupt-on-change pin.Analog input 9.

RB5/KBI1/PGMRB5KBI1PGM

38 15 15I/OI

I/O

TTLTTLST

Digital I/O.Interrupt-on-change pin.Low-Voltage ICSP™ Programming enable pin.

RB6/KBI2/PGCRB6KBI2PGC

39 16 16I/OI

I/O

TTLTTLST

Digital I/O.Interrupt-on-change pin. In-Circuit Debugger and ICSP programmingclock pin.

RB7/KBI3/PGDRB7KBI3PGD

40 17 17I/OI

I/O

TTLTTLST

Digital I/O.Interrupt-on-change pin. In-Circuit Debugger and ICSP programmingdata pin.






PIC18F2585/2680/4585/4680

PORTC is a bidirectional I/O port.RC0/T1OSO/T13CKI

RC0T1OSOT13CKI

15 34 32I/OOI

ST—ST

Digital I/O.Timer1 oscillator output. Timer1/Timer3 external clock input.

RC1/T1OSIRC1T1OSI

16 35 35I/OI

STCMOS

Digital I/O.Timer1 oscillator input.

RC2/CCP1RC2CCP1

17 36 36I/OI/O

STST

Digital I/O.Capture1 input/Compare1 output/PWM1 output.

RC3/SCK/SCLRC3SCK

SCL

18 37 37I/OI/O

I/O

STST

ST

Digital I/O.Synchronous serial clock input/output for SPI mode.Synchronous serial clock input/output for I2C™ mode.

RC4/SDI/SDARC4SDISDA

23 42 42I/OI

I/O

STSTST

Digital I/O.SPI data in.I2C data I/O.

RC5/SDORC5SDO

24 43 43I/OO

ST—

Digital I/O.SPI data out.

RC6/TX/CKRC6TXCK

25 44 44I/OOI/O

ST—ST

Digital I/O.EUSART asynchronous transmit.EUSART synchronous clock (see related RX/DT).

RC7/RX/DTRC7RXDT

26 1 1I/OI

I/O

STSTST

Digital I/O.EUSART asynchronous receive.EUSART synchronous data (see related TX/CK).






PIC18F2585/2680/4585/4680

PORTD is a bidirectional I/O port or a Parallel Slave Port (PSP) for interfacing to a microprocessor port. These pins have TTL input buffers when PSP module is enabled.

RD0/PSP0/C1IN+RD0PSP0C1IN+

19 38 38I/OI/OI

STTTL

Analog

Digital I/O.Parallel Slave Port data.Comparator 1 input (+).

RD1/PSP1/C1IN-RD1PSP1C1IN-

20 39 39I/OI/OI

STTTL

Analog

Digital I/O.Parallel Slave Port data.Comparator 1 input (-)

RD2/PSP2/C2IN+RD2PSP2C2IN+

21 40 40I/OI/OI

STTTL

Analog

Digital I/O.Parallel Slave Port data.Comparator 2 input (+).

RD3/PSP3/C2IN-RD3PSP3C2IN-

22 41 41I/OI/OI

STTTL

Analog

Digital I/O.Parallel Slave Port data.Comparator 2 input (-).

RD4/PSP4/ECCP1/P1A

RD4PSP4ECCP1P1A

27 2 2

I/OI/OI/OO

STTTLSTTTL

Digital I/O.Parallel Slave Port data.Capture2 input/Compare2 output/PWM2 output.ECCP1 PWM output A.

RD5/PSP5/P1BRD5PSP5P1B

28 3 3I/OI/OO

STTTLTTL

Digital I/O.Parallel Slave Port data.ECCP1 PWM output B.

RD6/PSP6/P1CRD6PSP6P1C

29 4 4I/OI/OO

STTTLTTL

Digital I/O.Parallel Slave Port data.ECCP1 PWM output C.

RD7/PSP7/P1DRD7PSP7P1D

30 5 5I/OI/OO

STTTLTTL

Digital I/O.Parallel Slave Port data.ECCP1 PWM output D.






PIC18F2585/2680/4585/4680

PORTE is a bidirectional I/O port.

RE0/RD/AN5RE0RD

AN5

8 25 25I/OI

I

STTTL

Analog

Digital I/O.Read control for Parallel Slave Port (see also WR and CS pins).Analog input 5.

RE1/WR/AN6/C1OUTRE1WR

AN6C1OUT

9 26 26I/OI

IO

STTTL

AnalogTTL

Digital I/O.Write control for Parallel Slave Port (see CS and RD pins).Analog input 6.Comparator 1 output.

RE2/CS/AN7/C2OUTRE2CS

AN7C2OUT

10 27 27I/OI

IO

STTTL

AnalogTTL

Digital I/O.Chip select control for Parallel Slave Port (see related RD and WR).Analog input 7.Comparator 2 output.

RE3 — — — — — See MCLR/VPP/RE3 pin.VSS 12,

316, 30,

316, 29 P — Ground reference for logic and I/O pins.

VDD 11, 32 7, 8, 28, 29

7, 28 P — Positive supply for logic and I/O pins.

NC — 13 12, 13, 33, 34

— — No connect.






PIC18F2585/2680/4585/4680

2.0 OSCILLATOR CONFIGURATIONS

2.1 Oscillator TypesPIC18F2585/2680/4585/4680 devices can be operatedin ten different oscillator modes. The user can programthe Configuration bits, FOSC3:FOSC0, in ConfigurationRegister 1H to select one of these ten modes:

1. LP Low-Power Crystal2. XT Crystal/Resonator3. HS High-Speed Crystal/Resonator4. HSPLL High-Speed Crystal/Resonator

with PLL enabled5. RC External Resistor/Capacitor with

FOSC/4 output on RA66. RCIO External Resistor/Capacitor with I/O

on RA67. INTIO1 Internal Oscillator with FOSC/4 output

on RA6 and I/O on RA78. INTIO2 Internal Oscillator with I/O on RA6

and RA79. EC External Clock with FOSC/4 output10. ECIO External Clock with I/O on RA6

2.2 Crystal Oscillator/Ceramic Resonators

In XT, LP, HS or HSPLL Oscillator modes, a crystal orceramic resonator is connected to the OSC1 andOSC2 pins to establish oscillation. Figure 2-1 showsthe pin connections.

The oscillator design requires the use of a parallel cutcrystal.

FIGURE 2-1: CRYSTAL/CERAMIC RESONATOR OPERATION (XT, LP, HS OR HSPLL CONFIGURATION)

TABLE 2-1: CAPACITOR SELECTION FOR CERAMIC RESONATORS

Note: Use of a series cut crystal may give afrequency out of the crystalmanufacturer’s specifications.

Typical Capacitor Values Used:

Mode Freq OSC1 OSC2

XT 455 kHz2.0 MHz4.0 MHz

56 pF47 pF33 pF

56 pF47 pF33 pF

HS 8.0 MHz16.0 MHz

27 pF22 pF

27 pF22 pF

Capacitor values are for design guidance only. These capacitors were tested with the resonatorslisted below for basic start-up and operation. Thesevalues are not optimized.Different capacitor values may be required to produceacceptable oscillator operation. The user should testthe performance of the oscillator over the expectedVDD and temperature range for the application.

See the notes on page 22 for additional information.

Resonators Used:

455 kHz 4.0 MHz2.0 MHz 8.0 MHz

16.0 MHz

Note: When using resonators with frequenciesabove 3.5 MHz, the use of HS mode,rather than XT mode, is recommended.HS mode may be used at any VDD forwhich the controller is rated. If HS isselected, it is possible that the gain of theoscillator will overdrive the resonator.Therefore, a series resistor should beplaced between the OSC2 pin and theresonator. As a good starting point, therecommended value of RS is 330.

Note 1:See Table 2-1 and Table 2-2 for initial values of C1 and C2.

2: A series resistor (RS) may be required for AT strip cut crystals.

3: RF varies with the oscillator mode chosen.

C1(1)

C2(1)

XTAL

OSC2

OSC1

RF(3)

Sleep

To

Logic

PIC18FXXXXRS(2)

Internal


PIC18F2585/2680/4585/4680

TABLE 2-2: CAPACITOR SELECTION FOR

CRYSTAL OSCILLATOR

An external clock source may also be connected to theOSC1 pin in the HS mode, as shown in Figure 2-2.

FIGURE 2-2: EXTERNAL CLOCK INPUT OPERATION (HS OSCILLATOR CONFIGURATION)

2.3 External Clock InputThe EC and ECIO Oscillator modes require an externalclock source to be connected to the OSC1 pin. There isno oscillator start-up time required after a Power-onReset or after an exit from Sleep mode.

In the EC Oscillator mode, the oscillator frequencydivided by 4 is available on the OSC2 pin. This signalmay be used for test purposes or to synchronize otherlogic. Figure 2-3 shows the pin connections for the ECOscillator mode.

FIGURE 2-3: EXTERNAL CLOCK INPUT OPERATION (EC CONFIGURATION)

The ECIO Oscillator mode functions like the EC mode,except that the OSC2 pin becomes an additionalgeneral purpose I/O pin. The I/O pin becomes bit 6 ofPORTA (RA6). Figure 2-4 shows the pin connectionsfor the ECIO Oscillator mode.

FIGURE 2-4: EXTERNAL CLOCK INPUT OPERATION (ECIO CONFIGURATION)

Osc Type Crystal Freq

Typical Capacitor Values Tested:

C1 C2

LP 32 kHz 33 pF 33 pF200 kHz 15 pF 15 pF

XT 1 MHz 33 pF 33 pF4 MHz 27 pF 27 pF

HS 4 MHz 27 pF 27 pF8 MHz 22 pF 22 pF

20 MHz 15 pF 15 pFCapacitor values are for design guidance only. These capacitors were tested with the crystals listedbelow for basic start-up and operation. These valuesare not optimized.Different capacitor values may be required to produceacceptable oscillator operation. The user should testthe performance of the oscillator over the expectedVDD and temperature range for the application.

See the notes following this table for additionalinformation.

Crystals Used:32 kHz 4 MHz

200 kHz 8 MHz1 MHz 20 MHz

Note 1: Higher capacitance increases the stabil-ity of the oscillator but also increases thestart-up time.

2: When operating below 3V VDD, or whenusing certain ceramic resonators at anyvoltage, it may be necessary to use theHS mode or switch to a crystal oscillator.

3: Since each resonator/crystal has its owncharacteristics, the user should consultthe resonator/crystal manufacturer forappropriate values of externalcomponents.

4: Rs may be required to avoid overdrivingcrystals with low drive level specification.

5: Always verify oscillator performance overthe VDD and temperature range that isexpected for the application.

OSC1

OSC2Open

Clock fromExt. System PIC18FXXXX

(HS Mode)

OSC1/CLKI

OSC2/CLKOFOSC/4


OSC1/CLKI

I/O (OSC2)RA6



PIC18F2585/2680/4585/4680

2.4 RC OscillatorFor timing insensitive applications, the “RC” and“RCIO” device options offer additional cost savings.The actual oscillator frequency is a function of severalfactors:

• supply voltage• values of the external resistor (REXT) and

capacitor (CEXT)• operating temperature

Given the same device, operating voltage and tempera-ture and component values, there will also be unit-to-unitfrequency variations. These are due to factors such as:

• normal manufacturing variation• difference in lead frame capacitance between

package types (especially for low CEXT values) • variations within the tolerance of limits of REXT

and CEXT

In the RC Oscillator mode, the oscillator frequencydivided by 4 is available on the OSC2 pin. This signalmay be used for test purposes or to synchronize otherlogic. Figure 2-5 shows how the R/C combination isconnected.

FIGURE 2-5: RC OSCILLATOR MODE

The RCIO Oscillator mode (Figure 2-6) functions likethe RC mode, except that the OSC2 pin becomes anadditional general purpose I/O pin. The I/O pinbecomes bit 6 of PORTA (RA6).

FIGURE 2-6: RCIO OSCILLATOR MODE

2.5 PLL Frequency MultiplierA Phase Locked Loop (PLL) circuit is provided as anoption for users who wish to use a lower frequencyoscillator circuit or to clock the device up to its highestrated frequency from a crystal oscillator. This may beuseful for customers who are concerned with EMI dueto high-frequency crystals or users who require higherclock speeds from an internal oscillator.

2.5.1 HSPLL OSCILLATOR MODEThe HSPLL mode makes use of the HS mode oscillatorfor frequencies up to 10 MHz. A PLL then multiplies theoscillator output frequency by 4 to produce an internalclock frequency up to 40 MHz.

The PLL is only available to the crystal oscillator whenthe FOSC3:FOSC0 Configuration bits are programmedfor HSPLL mode (= 0110).

FIGURE 2-7: PLL BLOCK DIAGRAM (HS MODE)

2.5.2 PLL AND INTOSCThe PLL is also available to the internal oscillator blockin selected oscillator modes. In this configuration, thePLL is enabled in software and generates a clockoutput of up to 32 MHz. The operation of INTOSC withthe PLL is described in Section 2.6.4 “PLL in INTOSCModes”.

OSC2/CLKO

CEXT

REXT

PIC18FXXXX

OSC1

FOSC/4

InternalClock

VDD

VSS

Recommended values: 3 k REXT 100 kCEXT > 20 pF

CEXT

REXT

PIC18FXXXX

OSC1 InternalClock

VDD

VSS

Recommended values: 3 k REXT 100 kCEXT > 20 pF

I/O (OSC2)RA6

MU

X

VCO

LoopFilter

CrystalOsc

OSC2

OSC1

PLL Enable

FINFOUT

SYSCLK

PhaseComparator

HS Osc Enable

4

(from Configuration Register 1H)

HS Mode


PIC18F2585/2680/4585/4680

2.6 Internal Oscillator BlockThe PIC18F2585/2680/4585/4680 devices include aninternal oscillator block which generates two differentclock signals; either can be used as the microcontroller’sclock source. This may eliminate the need for externaloscillator circuits on the OSC1 and/or OSC2 pins.

The main output (INTOSC) is an 8 MHz clock source,which can be used to directly drive the device clock. Italso drives a postscaler, which can provide a range ofclock frequencies from 31 kHz to 4 MHz. The INTOSCoutput is enabled when a clock frequency from 125 kHzto 8 MHz is selected.

The other clock source is the internal RC oscillator(INTRC), which provides a nominal 31 kHz output.INTRC is enabled if it is selected as the device clocksource; it is also enabled automatically when any of thefollowing are enabled:

• Power-up Timer• Fail-Safe Clock Monitor• Watchdog Timer• Two-Speed Start-up

These features are discussed in greater detail inSection 24.0 “Special Features of the CPU”.The clock source frequency (INTOSC direct, INTRCdirect or INTOSC postscaler) is selected by configuringthe IRCF bits of the OSCCON register (Register 2-2).

2.6.1 INTIO MODESUsing the internal oscillator as the clock sourceeliminates the need for up to two external oscillatorpins, which can then be used for digital I/O. Two distinctconfigurations are available:

• In INTIO1 mode, the OSC2 pin outputs FOSC/4, while OSC1 functions as RA7 for digital input and output.

• In INTIO2 mode, OSC1 functions as RA7 and OSC2 functions as RA6, both for digital input and output.

2.6.2 INTOSC OUTPUT FREQUENCYThe internal oscillator block is calibrated at the factoryto produce an INTOSC output frequency of 8.0 MHz.

The INTRC oscillator operates independently of theINTOSC source. Any changes in INTOSC acrossvoltage and temperature are not necessarily reflectedby changes in INTRC and vice versa.

2.6.3 OSCTUNE REGISTERThe internal oscillator’s output has been calibrated atthe factory but can be adjusted in the user’s applica-tion. This is done by writing to the OSCTUNE register(Register 2-1). The tuning sensitivity is constantthroughout the tuning range.

When the OSCTUNE register is modified, the INTOSCand INTRC frequencies will begin shifting to the newfrequency. The INTRC clock will reach the newfrequency within 8 clock cycles (approximately8 * 32 s = 256 s). The INTOSC clock will stabilizewithin 1 ms. Code execution continues during this shift.There is no indication that the shift has occurred.

The OSCTUNE register also implements the INTSRCand PLLEN bits, which control certain features of theinternal oscillator block. The INTSRC bit allows usersto select which internal oscillator provides the clocksource when the 31 kHz frequency option is selected.This is covered in greater detail in Section 2.7.1“Oscillator Control Register”. The PLLEN bit controls the operation of the frequencymultiplier, PLL, in internal oscillator modes.

2.6.4 PLL IN INTOSC MODESThe 4x frequency multiplier can be used with the inter-nal oscillator block to produce faster device clockspeeds than are normally possible with an internaloscillator. When enabled, the PLL produces a clockspeed of up to 32 MHz.

Unlike HSPLL mode, the PLL is controlled through soft-ware. The control bit, PLLEN (OSCTUNE), is usedto enable or disable its operation.

The PLL is available when the device is configured touse the internal oscillator block as its primary clocksource (FOSC3:FOSC0 = 1001 or 1000). Additionally,the PLL will only function when the selected output fre-quency is either 4 MHz or 8 MHz (OSCCON = 111or 110). If both of these conditions are not met, the PLLis disabled.

The PLLEN control bit is only functional in those internaloscillator modes where the PLL is available. In all othermodes, it is forced to ‘0’ and is effectively unavailable.

2.6.5 INTOSC FREQUENCY DRIFTThe factory calibrates the internal oscillator blockoutput (INTOSC) for 8 MHz. However, this frequencymay drift as VDD or temperature changes, which canaffect the controller operation in a variety of ways. It ispossible to adjust the INTOSC frequency by modifyingthe value in the OSCTUNE register. This has no effecton the INTRC clock source frequency.

Tuning the INTOSC source requires knowing when tomake the adjustment, in which direction it should bemade and in some cases, how large a change isneeded. Three compensation techniques arediscussed in Section 2.6.5.1 “Compensating withthe EUSART”, Section 2.6.5.2 “Compensating withthe Timers” and Section 2.6.5.3 “Compensatingwith the CCP1 Module in Capture Mode”, but othertechniques may be used.


PIC18F2585/2680/4585/4680

REGISTER 2-1: OSCTUNE: OSCILLATOR TUNING REGISTER

2.6.5.1 Compensating with the EUSART An adjustment may be required when the EUSARTbegins to generate framing errors or receives data witherrors while in Asynchronous mode. Framing errorsindicate that the device clock frequency is too high. Toadjust for this, decrement the value in OSCTUNE toreduce the clock frequency. On the other hand, errorsin data may suggest that the clock speed is too low. Tocompensate, increment OSCTUNE to increase theclock frequency.

2.6.5.2 Compensating with the TimersThis technique compares device clock speed to somereference clock. Two timers may be used; one timer isclocked by the peripheral clock, while the other isclocked by a fixed reference source, such as the Tim-er1 oscillator.

Both timers are cleared, but the timer clocked by thereference generates interrupts. When an interruptoccurs, the internally clocked timer is read and bothtimers are cleared. If the internally clocked timer valueis greater than expected, then the internal oscillatorblock is running too fast. To adjust for this, decrementthe OSCTUNE register.

2.6.5.3 Compensating with the CCP1 Module in Capture Mode

The CCP1 module can use free running Timer1 (orTimer3), clocked by the internal oscillator block and anexternal event with a known period (i.e., AC powerfrequency). The time of the first event is captured in theCCPRxH:CCPRxL registers and is recorded for uselater. When the second event causes a capture, thetime of the first event is subtracted from the time of thesecond event. Since the period of the external event isknown, the time difference between events can becalculated.

If the measured time is much greater than thecalculated time, the internal oscillator block is runningtoo fast. To compensate, decrement the OSCTUNEregister. If the measured time is much less than thecalculated time, the internal oscillator block is runningtoo slow. To compensate, increment the OSCTUNEregister.

R/W-0 R/W-0(1) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INTSRC PLLEN(1) — TUN4 TUN3 TUN2 TUN1 TUN0

bit 7 bit 0

bit 7 INTSRC: Internal Oscillator Low-Frequency Source Select bit1 = 31.25 kHz device clock derived from 8 MHz INTOSC source (divide-by-256 enabled)0 = 31 kHz device clock derived directly from INTRC internal oscillator

bit 6 PLLEN: Frequency Multiplier PLL for INTOSC Enable bit(1)

1 = PLL enabled for INTOSC (4 MHz and 8 MHz only)0 = PLL disabled

Note 1: Available only in certain oscillator configurations; otherwise, this bit is unavailableand reads as ‘0’. See text for details.

bit 5 Unimplemented: Read as ‘0’bit 4-0 TUN4:TUN0: Frequency Tuning bits

01111 = Maximum frequency• •• •00001 00000 = Center frequency. Oscillator module is running at the calibrated frequency.11111 • •• •10000 = Minimum frequency

Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown


PIC18F2585/2680/4585/4680

2.7 Clock Sources and Oscillator

SwitchingLike previous PIC18 devices, the PIC2585/2680/4585/4680 family includes a feature that allows thedevice clock source to be switched from the mainoscillator to an alternate low-frequency clock source.PIC18F2585/2680/4585/4680 devices offer two alter-nate clock sources. When an alternate clock source isenabled, the various power managed operating modesare available.

Essentially, there are three clock sources for thesedevices:

• Primary oscillators• Secondary oscillators• Internal oscillator block

The primary oscillators include the External Crystaland Resonator modes, the External RC modes, theExternal Clock modes and the internal oscillator block.The particular mode is defined by the FOSC3:FOSC0Configuration bits. The details of these modes arecovered earlier in this chapter.

The secondary oscillators are those external sourcesnot connected to the OSC1 or OSC2 pins. Thesesources may continue to operate even after thecontroller is placed in a power managed mode.

PIC18F2585/2680/4585/4680 devices offer the Timer1oscillator as a secondary oscillator. This oscillator, in allpower managed modes, is often the time base forfunctions such as a real-time clock.

Most often, a 32.768 kHz watch crystal is connectedbetween the RC0/T1OSO/T13CKI and RC1/T1OSIpins. Like the LP mode oscillator circuit, loadingcapacitors are also connected from each pin to ground.

The Timer1 oscillator is discussed in greater detail inSection 12.3 “Timer1 Oscillator”.In addition to being a primary clock source, the internaloscillator block is available as a power managedmode clock source. The INTRC source is also used asthe clock source for several special features, such asthe WDT and Fail-Safe Clock Monitor.

The clock sources for the PIC18F2585/2680/4585/4680devices are shown in Figure 2-8. See Section 24.0“Special Features of the CPU” for Configurationregister details.

FIGURE 2-8: PIC18F2585/2680/4585/4680 CLOCK DIAGRAM

PIC18FX585/X680

4 x PLL

FOSC3:FOSC0

Secondary Oscillator

T1OSCENEnableOscillator

T1OSO

T1OSI

Clock Source Option for other Modules

OSC1

OSC2

Sleep

Primary Oscillator

HSPLL, INTOSC/PLL

LP, XT, HS, RC, EC

T1OSC

CPU

Peripherals

IDLEN

Pos

tsca

ler

MU

X

MU

X

8 MHz

4 MHz

2 MHz

1 MHz

500 kHz

125 kHz

250 kHz

OSCCON

11111010110001101000100031 kHz

INTRCSource

InternalOscillator

Block

WDT, PWRT, FSCM

8 MHz

Internal Oscillator

(INTOSC)

OSCCON

ClockControl

OSCCON

Source8 MHz

31 kHz (INTRC)

OSCTUNE

01

OSCTUNE

and Two-Speed Startup


PIC18F2585/2680/4585/4680

2.7.1 OSCILLATOR CONTROL REGISTERThe OSCCON register (Register 2-2) controls severalaspects of the device clock’s operation, both in fullpower operation and in power managed modes.

The System Clock Select bits, SCS1:SCS0, select theclock source. The available clock sources are theprimary clock (defined by the FOSC3:FOSC0 Configu-ration bits), the secondary clock (Timer1 oscillator) andthe internal oscillator block. The clock source changesimmediately after one or more of the bits is written to,following a brief clock transition interval. The SCS bitsare cleared on all forms of Reset.

The Internal Oscillator Frequency Select bits,IRCF2:IRCF0, select the frequency output of theinternal oscillator block to drive the device clock. Thechoices are the INTRC source, the INTOSC source(8 MHz) or one of the frequencies derived from theINTOSC postscaler (31 kHz to 4 MHz). If the internaloscillator block is supplying the device clock, changingthe states of these bits will have an immediate changeon the internal oscillator’s output. On device Resets,the default output frequency of the internal oscillatorblock is set at 1 MHz.

When an output frequency of 31 kHz is selected(IRCF2:IRCF0 = 000), users may choose whichinternal oscillator acts as the source. This is done withthe INTSRC bit in the OSCTUNE register(OSCTUNE). Setting this bit selects INTOSC as a31.25 kHz clock source by enabling the divide-by-256output of the INTOSC postscaler. Clearing INTSRCselects INTRC (nominally 31 kHz) as the clock source.

This option allows users to select the tunable and moreprecise INTOSC as a clock source, while maintainingpower savings with a very low clock speed. Regardlessof the setting of INTSRC, INTRC always remains theclock source for features such as the Watchdog Timerand the Fail-Safe Clock Monitor.

The OSTS, IOFS and T1RUN bits indicate which clocksource is currently providing the device clock. TheOSTS bit indicates that the Oscillator Start-up Timerhas timed out and the primary clock is providing thedevice clock in primary clock modes. The IOFS bitindicates when the internal oscillator block hasstabilized and is providing the device clock in RC Clockmodes. The T1RUN bit (T1CON) indicates whenthe Timer1 oscillator is providing the device clock insecondary clock modes. In power managed modes,only one of these three bits will be set at any time. Ifnone of these bits are set, the INTRC is providing theclock or the internal oscillator block has just started andis not yet stable.

The IDLEN bit determines if the device goes into Sleepmode or one of the Idle modes when the SLEEPinstruction is executed.

The use of the flag and control bits in the OSCCONregister is discussed in more detail in Section 3.0“Power Managed Modes”.

2.7.2 OSCILLATOR TRANSITIONSPIC18F2585/2680/4585/4680 devices contain circuitryto prevent clock “glitches” when switching betweenclock sources. A short pause in the device clock occursduring the clock switch. The length of this pause is thesum of two cycles of the old clock source and three tofour cycles of the new clock source. This formulaassumes that the new clock source is stable.

Clock transitions are discussed in greater detail inSection 3.1.2 “Entering Power Managed Modes”.

Note 1: The Timer1 oscillator must be enabled toselect the secondary clock source. TheTimer1 oscillator is enabled by setting theT1OSCEN bit in the Timer1 Control regis-ter (T1CON). If the Timer1 oscillator isnot enabled, then any attempt to select asecondary clock source when executing aSLEEP instruction will be ignored.

2: It is recommended that the Timer1oscillator be operating and stable beforeexecuting the SLEEP instruction, or avery long delay may occur while the Tim-er1 oscillator starts.


PIC18F2585/2680/4585/4680

REGISTER 2-2: OSCCON: OSCILLATOR CONTROL REGISTER

R/W-0 R/W-1 R/W-0 R/W-0 R(1) R-0 R/W-0 R/W-0IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0

bit 7 bit 0

bit 7 IDLEN: Idle Enable bit1 = Device enters Idle mode on SLEEP instruction0 = Device enters Sleep mode on SLEEP instruction

bit 6-4 IRCF2:IRCF0: Internal Oscillator Frequency Select bits111 = 8 MHz (INTOSC drives clock directly)110 = 4 MHz 101 = 2 MHz 100 = 1 MHz(3) 011 = 500 kHz 010 = 250 kHz001 = 125 kHz000 = 31 kHz (from either INTOSC/256 or INTRC directly)(2)

bit 3 OSTS: Oscillator Start-up Time-out Status bit(1)

1 = Oscillator start-up time-out timer has expired; primary oscillator is running0 = Oscillator start-up time-out timer is running; primary oscillator is not ready

bit 2 IOFS: INTOSC Frequency Stable bit 1 = INTOSC frequency is stable and the frequency is provided by one of the RC modes0 = INTOSC frequency is not stable

bit 1-0 SCS1:SCS0: System Clock Select bits1x = Internal oscillator block01 = Timer1 oscillator00 = Primary oscillator

Note 1: Depends on state of the IESO Configuration bit.2: Source selected by the INTSRC bit (OSCTUNE), see text.3: Default output frequency of INTOSC on Reset.

Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown


PIC18F2585/2680/4585/4680

2.8 Effects of Power Managed Modes

on the Various Clock SourcesWhen PRI_IDLE mode is selected, the designatedprimary oscillator continues to run without interruption.For all other power managed modes, the oscillatorusing the OSC1 pin is disabled. The OSC1 pin (andOSC2 pin, if used by the oscillator) will stop oscillating.

In secondary clock modes (SEC_RUN and SEC_I-DLE), the Timer1 oscillator is operating and providingthe device clock. The Timer1 oscillator may also run inall power managed modes if required to clock Timer1 orTimer3.

In internal oscillator modes (RC_RUN and RC_IDLE),the internal oscillator block provides the device clocksource. The 31 kHz INTRC output can be used directlyto provide the clock and may be enabled to supportvarious special features, regardless of the powermanaged mode (see Section 24.2 “Watchdog Timer(WDT)”, Section 24.3 “Two-Speed Start-up” andSection 24.4 “Fail-Safe Clock Monitor” for moreinformation on WDT, Two-Speed Start-up and Fail-SafeClock Monitor). The INTOSC output at 8 MHz may beused directly to clock the device or may be divideddown by the postscaler. The INTOSC output is disabledif the clock is provided directly from the INTRC output.

If the Sleep mode is selected, all clock sources arestopped. Since all the transistor switching currentshave been stopped, Sleep mode achieves the lowestcurrent consumption of the device (only leakagecurrents).

Enabling any on-chip feature that will operate duringSleep will increase the current consumed during Sleep.The INTRC is required to support WDT operation. TheTimer1 oscillator may be operating to support a

real-time clock. Other features may be operating thatdo not require a device clock source (i.e., SSP slave,PSP, INTn pins and others). Peripherals that may addsignificant current consumption are listed inSection 27.2 “DC Characteristics: Power Downand Supply Current”.

2.9 Power-up DelaysPower-up delays are controlled by two timers, so thatno external Reset circuitry is required for most applica-tions. The delays ensure that the device is kept inReset until the device power supply is stable under nor-mal circumstances and the primary clock is operatingand stable. For additional information on power-updelays, see Section 4.5 “Device Reset Timers”.The first timer is the Power-up Timer (PWRT), whichprovides a fixed delay on power-up (parameter 33,Table 27-10). It is enabled by clearing (= 0) thePWRTEN Configuration bit.

The second timer is the Oscillator Start-up Timer(OST), intended to keep the chip in Reset until thecrystal oscillator is stable (LP, XT and HS modes). TheOST does this by counting 1024 oscillator cyclesbefore allowing the oscillator to clock the device.

When the HSPLL Oscillator mode is selected, thedevice is kept in Reset for an additional 2 ms, followingthe HS mode OST delay, so the PLL can lock to theincoming clock frequency.

There is a delay of interval TCSD (parameter 38,Table 27-10), following POR, while the controllerbecomes ready to execute instructions. This delay runsconcurrently with any other delays. This may be theonly delay that occurs when any of the EC, RC or INTIOmodes are used as the primary clock source.

TABLE 2-3: OSC1 AND OSC2 PIN STATES IN SLEEP MODE OSC Mode OSC1 Pin OSC2 Pin

RC, INTIO1 Floating, external resistor should pull high At logic low (clock/4 output)RCIO, INTIO2 Floating, external resistor should pull high Configured as PORTA, bit 6ECIO Floating, pulled by external clock Configured as PORTA, bit 6EC Floating, pulled by external clock At logic low (clock/4 output)LP, XT and HS Feedback inverter disabled at quiescent

voltage levelFeedback inverter disabled at quiescent voltage level

Note: See Table 4-2 in Section 4.0 “Reset” for time-outs due to Sleep and MCLR Reset.


PIC18F2585/2680/4585/4680

3.0 POWER MANAGED MODESPIC18F2585/2680/4585/4680 devices offer a total ofseven operating modes for more efficient powermanagement. These modes provide a variety ofoptions for selective power conservation in applicationswhere resources may be limited (i.e., battery-powereddevices).

There are three categories of power managed modes:

• Run modes• Idle modes • Sleep mode

These categories define which portions of the deviceare clocked and sometimes, what speed. The Run andIdle modes may use any of the three available clocksources (primary, secondary or internal oscillatorblock); the Sleep mode does not use a clock source.

The power managed modes include several powersaving features offered on previous PIC® devices. Oneis the clock switching feature, offered in other PIC18devices, allowing the controller to use the Timer1oscillator in place of the primary oscillator. Alsoincluded is the Sleep mode, offered by all PIC devices,where all device clocks are stopped.

3.1 Selecting Power Managed ModesSelecting a power managed mode requires twodecisions: if the CPU is to be clocked or not and theselection of a clock source. The IDLEN bit(OSCCON) controls CPU clocking, while theSCS1:SCS0 bits (OSCCON) select the clocksource. The individual modes, bit settings, clock sourcesand affected modules are summarized in Table 3-1.

3.1.1 CLOCK SOURCESThe SCS1:SCS0 bits allow the selection of one of threeclock sources for power managed modes. They are:

• the primary clock, as defined by the FOSC3:FOSC0 Configuration bits

• the secondary clock (the Timer1 oscillator)• the internal oscillator block (for RC modes)

3.1.2 ENTERING POWER MANAGED MODES

Switching from one power managed mode to anotherbegins by loading the OSCCON register. TheSCS1:SCS0 bits select the clock source and determinewhich Run or Idle mode is to be used. Changing thesebits causes an immediate switch to the new clocksource, assuming that it is running. The switch mayalso be subject to clock transition delays. These arediscussed in Section 3.1.3 “Clock Transitions AndStatus Indicators” and subsequent sections.Entry to the Power Managed Idle or Sleep modes istriggered by the execution of a SLEEP instruction. Theactual mode that results depends on the status of theIDLEN bit.

Depending on the current mode and the mode beingswitched to, a change to a power managed mode doesnot always require setting all of these bits. Manytransitions may be done by changing the oscillatorselect bits, or changing the IDLEN bit, prior to issuing aSLEEP instruction. If the IDLEN bit is alreadyconfigured correctly, it may only be necessary toperform a SLEEP instruction to switch to the desiredmode.

TABLE 3-1: POWER MANAGED MODES

ModeOSCCON Bits Module Clocking

Available Clock and Oscillator SourceIDLEN(1) SCS1:SCS0 CPU Peripherals

Sleep 0 N/A Off Off None – All clocks are disabledPRI_RUN N/A 00 Clocked Clocked Primary – LP, XT, HS, HSPLL, RC, EC, INTRC(2):

This is the normal full power execution mode.SEC_RUN N/A 01 Clocked Clocked Secondary – Timer1 OscillatorRC_RUN N/A 1x Clocked Clocked Internal Oscillator Block(2)PRI_IDLE 1 00 Off Clocked Primary – LP, XT, HS, HSPLL, RC, ECSEC_IDLE 1 01 Off Clocked Secondary – Timer1 OscillatorRC_IDLE 1 1x Off Clocked Internal Oscillator Block(2)Note 1: IDLEN reflects its value when the SLEEP instruction is executed.

2: Includes INTOSC and INTOSC postscaler, as well as the INTRC source.


PIC18F2585/2680/4585/4680

3.1.3 CLOCK TRANSITIONS AND STATUS

INDICATORSThe length of the transition between clock sources isthe sum of two cycles of the old clock source and threeto four cycles of the new clock source. This formulaassumes that the new clock source is stable.

Three bits indicate the current clock source and itsstatus. They are:

• OSTS (OSCCON) • IOFS (OSCCON) • T1RUN (T1CON)

In general, only one of these bits will be set while in agiven power managed mode. When the OSTS bit isset, the primary clock is providing the device clock.When the IOFS bit is set, the INTOSC output is provid-ing a stable 8 MHz clock source to a divider thatactually drives the device clock. When the T1RUN bit isset, the Timer1 oscillator is providing the clock. If noneof these bits are set, then either the INTRC clocksource is clocking the device, or the INTOSC source isnot yet stable.

If the internal oscillator block is configured as theprimary clock source by the FOSC3:FOSC0 Configura-tion bits, then both the OSTS and IOFS bits may be setwhen in PRI_RUN or PRI_IDLE modes. This indicatesthat the primary clock (INTOSC output) is generating astable 8 MHz output. Entering another RC powermanaged mode at the same frequency would clear theOSTS bit.

3.1.4 MULTIPLE SLEEP COMMANDSThe power managed mode that is invoked with theSLEEP instruction is determined by the setting of theIDLEN bit at the time the instruction is executed. Ifanother SLEEP instruction is executed, the device willenter the power managed mode specified by IDLEN atthat time. If IDLEN has changed, the device will enterthe new power managed mode specified by the newsetting.

3.2 Run ModesIn the Run modes, clocks to both the core andperipherals are active. The difference between thesemodes is the clock source.

3.2.1 PRI_RUN MODEThe PRI_RUN mode is the normal, full power executionmode of the microcontroller. This is also the defaultmode upon a device Reset, unless Two-Speed Start-upis enabled (see Section 24.3 “Two-Speed Start-up”for details). In this mode, the OSTS bit is set. The IOFSbit may be set if the internal oscillator block is theprimary clock source (see Section 2.7.1 “OscillatorControl Register”).

3.2.2 SEC_RUN MODEThe SEC_RUN mode is the compatible mode to the“clock switching” feature offered in other PIC18devices. In this mode, the CPU and peripherals areclocked from the Timer1 oscillator. This gives users theoption of lower power consumption while still using ahigh accuracy clock source.

SEC_RUN mode is entered by setting the SCS1:SCS0bits to ‘01’. The device clock source is switched to theTimer1 oscillator (see Figure 3-1), the primary oscilla-tor is shut down, the T1RUN bit (T1CON) is set andthe OSTS bit is cleared.

On transitions from SEC_RUN mode to PRI_RUN, theperipherals and CPU continue to be clocked from theTimer1 oscillator while the primary clock is started.When the primary clock becomes ready, a clock switchback to the primary clock occurs (see Figure 3-2).When the clock switch is complete, the T1RUN bit iscleared, the OSTS bit is set and the primary clock isproviding the clock. The IDLEN and SCS bits are notaffected by the wake-up; the Timer1 oscillatorcontinues to run.

Note 1: Caution should be used when modifyinga single IRCF bit. If VDD is less than 3V, itis possible to select a higher clock speedthan is supported by the low VDD.Improper device operation may result ifthe VDD/FOSC specifications are violated.

2: Executing a SLEEP instruction does notnecessarily place the device into Sleepmode. It acts as the trigger to place thecontroller into either the Sleep mode orone of the Idle modes, depending on thesetting of the IDLEN bit.

Note: The Timer1 oscillator should already berunning prior to entering SEC_RUNmode. If the T1OSCEN bit is not set whenthe SCS1:SCS0 bits are set to ‘01’, entryto SEC_RUN mode will not occur. If theTimer1 oscillator is enabled but not yetrunning, device clocks will be delayed untilthe oscillator has started. In such situa-tions, initial oscillator operation is far fromstable and unpredictable operation mayresult.


PIC18F2585/2680/4585/4680

FIGURE 3-1: TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE

FIGURE 3-2: TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL)

3.2.3 RC_RUN MODEIn RC_RUN mode, the CPU and peripherals areclocked from the internal oscillator block using theINTOSC multiplexer; the primary clock is shut down.When using the INTRC source, this mode provides thebest power conservation of all the Run modes, whilestill executing code. It works well for user applicationswhich are not highly timing sensitive or do not requirehigh-speed clocks at all times.

If the primary clock source is the internal oscillatorblock (either INTRC or INTOSC), there are no distin-guishable differences between PRI_RUN andRC_RUN modes during execution. However, a clockswitch delay will occur during entry to and exit fromRC_RUN mode. Therefore, if the primary clock sourceis the internal oscillator block, the use of RC_RUNmode is not recommended.

This mode is entered by setting SCS1 to ‘1’. Althoughit is ignored, it is recommended that SCS0 also becleared; this is to maintain software compatibility withfuture devices. When the clock source is switched tothe INTOSC multiplexer (see Figure 3-3), the primaryoscillator is shut down and the OSTS bit is cleared. TheIRCF bits may be modified at any time to immediatelychange the clock speed.

Q4Q3Q2

OSC1

Peripheral

Program

Q1

T1OSI

Q1

Counter

Clock

CPUClock

PC + 2PC

1 2 3 n-1 n

Clock Transition

Q4Q3Q2 Q1 Q3Q2

PC + 4

Q1 Q3 Q4

OSC1

Peripheral

Program PC

T1OSI

PLL Clock

Q1

PC + 4

Q2

Output

Q3 Q4 Q1

CPU Clock

PC + 2

Clock

Counter

Q2 Q2 Q3

Note 1:TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.

SCS1:SCS0 bits changed

TOST(1) TPLL(1)1 2 n-1 n

Clock

OSTS bit set

Transition

Note: Caution should be used when modifying asingle IRCF bit. If VDD is less than 3V, it ispossible to select a higher clock speedthan is supported by the low VDD.Improper device operation may result ifthe VDD/FOSC specifications are violated.


PIC18F2585/2680/4585/4680

If the IRCF bits and the INTSRC bit are all clear, theINTOSC output is not enabled and the IOFS bit willremain clear; there will be no indication of the currentclock source. The INTRC source is providing thedevice clocks.

If the IRCF bits are changed from all clear (thus,enabling the INTOSC output) or if INTSRC is set, theIOFS bit becomes set after the INTOSC outputbecomes stable. Clocks to the device continue whilethe INTOSC source stabilizes after an interval ofTIOBST.

If the IRCF bits were previously at a non-zero value orif INTSRC was set before setting SCS1 and theINTOSC source was already stable, the IOFS bit willremain set.

On transitions from RC_RUN mode to PRI_RUN mode,the device continues to be clocked from the INTOSCmultiplexer while the primary clock is started. When theprimary clock becomes ready, a clock switch to theprimary clock occurs (see Figure 3-4). When the clockswitch is complete, the IOFS bit is cleared, the OSTSbit is set and the primary clock is providing the deviceclock. The IDLEN and SCS bits are not affected by theswitch. The INTRC source will continue to run if eitherthe WDT or the Fail-Safe Clock Monitor is enabled.

FIGURE 3-3: TRANSITION TIMING TO RC_RUN MODE

FIGURE 3-4: TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE

Q4Q3Q2

OSC1

Peripheral

Program

Q1

INTRC

Q1

Counter

Clock

CPUClock

PC + 2PC

1 2 3 n-1 n

Clock Transition

Q4Q3Q2 Q1 Q3Q2

PC + 4

Q1 Q3 Q4

OSC1

Peripheral

Program PC

INTOSC

PLL Clock

Q1

PC + 4

Q2

Output

Q3 Q4 Q1

CPU Clock

PC + 2

Clock

Counter

Q2 Q2 Q3

Note 1:TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.

SCS1:SCS0 bits changed

TPLL(1)1 2 n-1 n

Clock

OSTS bit set

Transition

Multiplexer

TOST(1)


PIC18F2585/2680/4585/4680

3.3 Sleep ModeThe Power Managed Sleep mode in thePIC18F2585/2680/4585/4680 devices is identical tothe legacy Sleep mode offered in all other PIC devices.It is entered by clearing the IDLEN bit (the default stateon device Reset) and executing the SLEEP instruction.This shuts down the selected oscillator (Figure 3-5). Allclock source status bits are cleared.

Entering the Sleep mode from any other mode does notrequire a clock switch. This is because no clocks areneeded once the controller has entered Sleep. If theWDT is selected, the INTRC source will continue tooperate. If the Timer1 oscillator is enabled, it will alsocontinue to run.

When a wake event occurs in Sleep mode (by interrupt,Reset or WDT time-out), the device will not be clockeduntil the clock source selected by the SCS1:SCS0 bitsbecomes ready (see Figure 3-6), or it will be clockedfrom the internal oscillator block if either the Two-SpeedStart-up or the Fail-Safe Clock Monitor are enabled(see Section 24.0 “Special Features of the CPU”). Ineither case, the OSTS bit is set when the primary clockis providing the device clocks. The IDLEN and SCS bitsare not affected by the wake-up.

3.4 Idle ModesThe Idle modes allow the controller’s CPU to beselectively shut down while the peripherals continue tooperate. Selecting a particular Idle mode allows users

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