22’’s Complement Multiplieraccess.ee.ntu.edu.tw/course/advanced_VLSI_91/course...22’’s Complement Multiplier For Advanced VLSI Design Fall 2002 台大電機系吳安宇教授

ACCESS IC LAB

Graduate Institute of Electronics Engineering, NTU

2’s Complement Multiplier2’s Complement Multiplier

For Advanced VLSI DesignFall 2002

台大電機系吳安宇教授

Advanced VLSI Graduate Institute of Electronics Engineering, NTU

pp. 2台灣大學吳安宇教授2002.9.24

Binary representation

2’s complement representation

Ex. W=55=(00101)2 (-5)=(11011)2

[ ]12,222 112

0

110121 −−∈⋅+⋅−=⋅⋅⋅ −−

−

=

−−−− ∑ WW

W

i

ii

WWWW Aaaaaaa=A

[ ]12,021

00121 −∈⋅=⋅⋅⋅= ∑

−

=−−

WiW

iiWW BbbbbbB

Sign-bit Magnitude

W: Wordlength

Representation SystemRepresentation System



Decimal (2’s)Decimal (2’s)

Representation of decimal numberDefine decimal dot

A W-bits 2’s complement number A is represented as:

∑−

=

−−−−−− +−=⋅⋅⋅=

1

1110121 2.

W

i

iiWWWW aaaaaaA

[ ]121,1 +−−−∈ WA



2’s Complement Multiplication2’s Complement MultiplicationParallel Multipliers

Their product

1

1 2 1 0 1 11

1

1 2 1 0 1 11

. 2

. 2

W

W W W W ii

W

W W W W ii

A a a a a a a

B b b bb b b

−−

− − − − −=

−−

− − − − −=

= ⋅⋅⋅ = − +

= ⋅⋅⋅ = − +

∑

∑2 2

2 2 2 21

2W

W Wi

P A B p p−

−− −

=

= × = − +∑ i−

In constant word length multiplication, W-1 lower order bits in the product P is ignored and the Product is denoted as X <= P=AxB, where

∑−

=

−−−− +−=

1

111 2

W

i

iiWW xxX

→→

101.0110.0

TruncateRouding

0.10111

Check bit



Negative 2’s Complement NumberNegative 2’s Complement NumberIn 2’s complement, negative number is equivalent to taking 1’s complement and add 1 to LSB

11

111 22 +−

−

=

−−−− ++−= ∑ W

W

i

iiWw aa

∑∑∑−

=

−−−

=−−−

−

=

−− −−+=−=−

1

1

1

111

1

11 22)1(2

W

i

iiW

iiWW

W

i

iW aaaA

∑−

=−−− +−=

1

11

W

iiWW aaA1

1

111 212)1( +−−

−

=−−− +−−+= ∑ Wi

W

iiWW aa

11

111 22)1()1( +−−

−

=−−− +−+−−= ∑ Wi

W

iiWW aa

−2 ii

Geometric series

(1‘s complement +1)



Parallel Multiplication with Sign Parallel Multiplication with Sign ExtensionExtension

Multiplication of A and B can be written as)2( 11 ∑ −

−−− ⋅+−×= iiWW bbAP

11101321 2]...]2]2[[...[[ −−−

−−− ⋅+⋅++⋅+⋅+⋅−= bAbAbAbAbA WWW12] −

2-1 denotes a scaling operation

Modified term

Normal multiplication



Sign ExtensionSign Extension

3−0

11

12 222 −− +++ aaa

Sign extension Imagine many MSB in front of sign bit5=00101 ; (-5)=11011 11..1111011

3−= aA32−

01

11

2 22 −− +++ aaa33 2 +−= aa32−

01

11

2 22 −− +++ aaa332

3 22 ++−= aaa

Virtual

signextension

Prof.(4 bits)

(5 bits)

(6 bits)

___

________

______________



Example: Array MultiplicationExample: Array Multiplication

NxN multiplier: N(N-2) Full addersN Half addersN2 AND gates

Worst-case delay: (2N+1)Can be drawn as a “Squared Array”

gτ

γτ : worst-case adder delay



Array Multiplication (Tabular form)Array Multiplication (Tabular form)Sign extension is necessary

The addition can’t be carried out directly due to the terms with negative weight

- + + + 2‘s complelent

Modified term



Array Multiplication with Sign Array Multiplication with Sign ExtensionExtension

Sign extension



Parallel Carry-Ripple Array MultiplierParallel Carry-Ripple Array Multiplier

Sign extension

Carry prorogation

Sum (discard)C Carry

S

added term



Parallel Carry-Ripple Array MultiplierParallel Carry-Ripple Array Multiplier



Carry-Save MultiplierCarry-Save Multiplier



Vector Merging AdderVector Merging AdderCarry-save

Carry-ripple

Combined



Bauth-Wooley MultiplicationBauth-Wooley Multiplication

BAX ×=

+++−==+++−==

−−−

−−−

30

211230123

30

211230123

222222

bbbbbbbbBaaaaaaaaA

)222)(222( 30

21

123

30

21

123

−−−−−− +++−+++−= bbbbaaaaP

)]222)(222([ 30

21

12

30

21

1233

−−−−−− +++++= bbbaaaba)222()222( 3

02

11

233

02

11

23−−−−−− ++−++− aaabbbba

+++++= −−−− )2222(][ 3303

213

123 bababaA

)2222( 3303

213

123

−−−− +++ ababab3

30032

13131

3223 2)(2)1(2)(][ −−− +++++++= babaabbababaAReal

integer Compensation term for 2’s complement

[ ]A[ ]B



Baugh-Wooley MultipliersBaugh-Wooley MultipliersHandles the sign bits of multiplicand and multiplier efficiently

1

Compensation term



Baugh-Wooley MultipliersBaugh-Wooley Multipliers

truncation



Interleaved Floor-planInterleaved Floor-plan

Main ideaPerform the computation and accumulation of partial products simultaneously

AdvantageReduction in the routing complexityBetter accuracy in truncation (truncate in final step)



Example of Interleaved Floor-planExample of Interleaved Floor-plan



Carry Save

Vector Merging

Architecture for multiplication chartArchitecture for multiplication chart



Modified multiplication



Bit-plan ArchitectureBit-plan Architecture



ConclusionConclusion2’s complement adder

Carry-Select adderCarry-Save adderCarry Look-ahead adder

2’s complement multiplicationSign extension is necessaryCSA architecture for high speed

CSD representationLess nonzero term



Wallace Tree Multiplier OperationWallace Tree Multiplier Operation



Wallace Tree MultiplierWallace Tree Multiplier

Operation: (unsigned number)



4x4 Wallace Tree Multiplier4x4 Wallace Tree Multiplier

Documents

22’’s Complement Multiplieraccess.ee.ntu.edu.tw/course/advanced_VLSI_91/course...22’’s Complement Multiplier For Advanced VLSI Design Fall 2002 台大電機系吳安宇教授