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+22 dBm PSAT 3V Power Amplifier
for 0.5– 6 GHz Applications
Technical Data
MGA-83563
Features• +22 dBm PSAT at 2.4 GHz,
3.0V
+23 dBm PSAT at 2.4 GHz,
3.6V
• 22 dB Small Signal Gain at
2.4 GHz
• Wide Frequency Range 0.5
to 6 GHz
• Single 3V Supply
• 37% Power Added
Efficiency
• Ultra Miniature Package
Applications
• Amplifier for Driver and
Output Applications
Surface Mount PackageSOT-363 (SC-70)
Pin Connections andPackage Marking
Equivalent Circuit(Simplified)
Note:
Package marking provides orientationand identification; “x” is date code.
Description
Agilent’s MGA-83563 is an easy-to-use GaAs RFIC amplifier thatoffers excellent power output andefficiency. This part is targetedfor 3V applications where con-stant-envelope modulation isused. The output of the amplifieris matched internally to 50 Ω.However, an external match canbe added for maximum efficiencyand power out (PAE = 37%, Po =22 dBm). The input is easilymatched to 50 Ω.
Due to the high power output ofthis device, it is recommended foruse under a specific set ofoperating conditions. The thermalsections of the ApplicationsInformation explain this in detail.
The circuit uses state-of-the-artPHEMT technology with provenreliability. On-chip bias circuitryallows operation from singlesupply voltage.
GND
GND
83x
INPUT
GND
Vd1OUTPUTand Vd2
1 6
2 5
3 4
OUTPUTand Vd2
BIAS
INPUT
Vd1
BIAS
GROUND
2
Thermal Resistance[2]:
θch to c = 175°C/W
Notes:
1. Operation of this device above any oneof these limits may cause permanentdamage.
2. TC = 25°C (TC is defined to be thetemperature at the package pins wherecontact is made to the circuit board).
MGA-83563 Absolute Maximum Ratings
Absolute
Symbol Parameter Units Maximum[1]
V Maximum DC Supply Voltage V 4
Pin CW RF Input Power dBm +13
Tch Channel Temperature °C 165
TSTG Storage Temperature °C -65 to 150
0
200
400
800
600
700
500
300
100
10 30 50 70 90 150110 130
PO
WE
R D
ISS
IPA
TE
D A
S H
EA
T (m
W)
Pd
= (
VO
LT
AG
E)
x (C
UR
RE
NT
) –
(Po
ut)
CASE TEMPERATURE (°C)
1 x 10 6 Hrs MTTF
Temperature/Power Derating Curve.
Figure 1. MGA-83563 Final Production Test Circuit.
Figure 2. MGA-83563 Test Circuit for Characterization.
RFINPUT
1.2 nH
2.2 nH 18 nH20 pF
3.0V
1 pF
50 pFRF
OUTPUT
83
RFINPUT
Circuit A: L1 = 2.2 nH for 0.1 to 3 GHzCircuit B: L1 = 0 nH (capacitor as close as possible) for 3 to 6 GHz
L120 pF
Vd
RFOUTPUT
83
Tuner
Tuner BiasTee
3
MGA-83563 Electrical Specifications, Vd = 3 V, TC = 25°C, using test circuit of Figure 2, unless noted.Std.
Symbol Parameters and Test Conditions Units Min. Typ. Max. Dev.[4]
PSAT Saturated Output Power[3] f = 2.4 GHz dBm 20.5 22.4 0.75
PAE[3] Power Added Efficiency f = 2.4 GHz % 25 37 2.5
Id[5] Device Current mA 152 200 12.4
Gain Small Signal Gain f = 0.9 GHz dB 20f = 1.5 GHz 22f = 2.0 GHz 23f = 2.4 GHz 22f = 4.0 GHz 22f = 5.0 GHz 19f = 6.0 GHz 17
PSAT Saturated Output Power f = 0.9 GHz dBm 20.9f = 1.5 GHz 21.7f = 2.0 GHz 21.8f = 2.4 GHz 22f = 4.0 GHz 21.9f = 5.0 GHz 19.7f = 6.0 GHz 18.2
PAE Power Added Efficiency f = 0.9 GHz % 41f = 1.5 GHz 41f = 2.0 GHz 40f = 2.4 GHz 37f = 4.0 GHz 32f = 5.0 GHz 18f = 6.0 GHz 14
P1 dB[5] Output Power at 1 dB Gain Compression f = 0.9 GHz dBm 19.1
f = 1.5 GHz 19.7f = 2.0 GHz 19.7f = 2.4 GHz 19.2f = 4.0 GHz 18.1f = 5.0 GHz 16f = 6.0 GHz 15
VSWRin Input VSWR into 50 ΩCircuit A f = 0.9 to 1.7 GHz 3.5
f = 1.8 to 3.0 GHz 2.6Circuit B f = 3.0 to 6.0 GHz 2.3
VSWRout Output VSWR into 50 ΩCircuit A f = 0.9 to 2.0 GHz 1.4
f = 2.0 to 3.0 GHz 2.5Circuit B f = 3.0 to 4.0 GHz 3.5
f = 4.0 to 6.0 GHz 4.5
ISOL Isolation f = 0.9 to 3.0 GHz dB -38f = 3.0 to 6.0 GHz -30
IP3 Third Order Intercept Point f = 0.9 GHz to 6.0 GHz dBm 29
Notes:
3. Measured using the final test circuit of Figure 1 with an input power of +4 dBm.4. Standard Deviation number is based on measurement of at least 500 parts from three non-consecutive wafer lots during
the initial characterization of this product, and is intended to be used as an estimate for distribution of the typicalspecification.
5. For linear operation, refer to thermal sections in the Applications section of this data sheet.
4
MGA-83563 Typical Performance, Vd = 3 V, TC = 25°C, using test circuit of Figure 2, unless noted.
10
14
18
26
22
24
20
16
12
0 1 2 3 4 65
3.3V3.0V2.7V
GA
IN (d
B)
FREQUENCY (GHz)
Figure 3. Tuned Gain vs. Frequency
and Voltage.
14
16
18
24
22
20
0 1 2 3 4 65
P1d
B (d
Bm
)
FREQUENCY (GHz)
Figure 4. Output Power at 1 dB
Compression vs. Frequency and Voltage.
2.7V3.0V3.3V3.6V
14
16
18
24
22
20
0 1 2 3 4 65
PS
AT
(dB
m)
FREQUENCY (GHz)
Figure 5. Saturated Output Power
(+4 dBm in) vs. Frequency and Voltage.
2.7V3.0V3.3V3.6V
10
14
18
26
22
24
20
16
12
0 1 2 3 4 65
-40°C+25°C+85°C
GA
IN (d
B)
FREQUENCY (GHz)
Figure 6. Gain vs. Frequency and
Temperature.
14
16
18
24
22
20
0 1 2 3 4 65
OU
TP
UT
PO
WE
R (d
Bm
)
FREQUENCY (GHz)
Figure 7. Saturated Output Power
(+4 dBm in) vs. Frequency and
Temperature.
-40°C+25°C+85°C
2
4
6
12
10
8
0 1 2 3 4 65
NO
ISE
FIG
UR
E (d
B)
FREQUENCY (GHz)
Figure 8. Noise Figure vs. Frequency
and Temperature.
-40°C+25°C+85°C
0
2
4
10
8
6
0 1 2 3 4 65
VS
WR
FREQUENCY (GHz)
Figure 9. Input and Output VSWR
vs. Frequency.
0
40
80
200
160
140
120
180
100
60
20
0 1 2 43
-40°C+25°C+85°C
DE
VIC
E C
UR
RE
NT
, Id
(mA
)
FREQUENCY (GHz)
Figure 10. Supply Current vs. Voltage
and Temperature. Pin = -27 dBm.
70
110
150
170
130
90
0
20
40
50
30
10
-14 -10 -6 -2 2 6
DE
VIC
E C
UR
RE
NT
, Id
(mA
)
PA
E (
%)
INPUT POWER (dBm) @ 2.4 GHz
Figure 11. Device Current and Power
Added Efficiency vs. Input Power.
Note: Figure 1 test circuit.
Id
PAE
INPUT
OUTPUT
5
MGA-83563 Typical Performance, continuedVd = 3 V, TC = 25°C, using test circuit of Figure 2, unless noted.
10
14
18
24
22
20
16
12
-10 -8 -6 -2-4 20 64
2.7V3.0V3.3V3.6V
OU
TP
UT
PO
WE
R (d
Bm
)
INPUT POWER (dBm) @ 2.4 GHz
Figure 12. Output Power vs. Input
Power and Voltage.
Note: Figure 1 test circuit.
25
27
29
33
31
32
30
28
26
-14 -10 -6 -2 62
2.7V3.0V3.3V3.6V
TH
IRD
OR
DE
R IN
TE
RC
EP
T (d
Bm
)
INPUT POWER (dBm) @ 2.4 GHz
Figure 13. Third Order Intercept
vs. Input Power and Voltage.
Note: Figure 1 test circuit.
20
25
30
50
45
40
35
0 1 2 3 4 65
PA
E (
%)
and
IP3
(dB
m)
FREQUENCY (GHz)
Figure 14. Power Added Efficiency
and Third Order Intercept vs.
Frequency (Vd = 3.6 V).
-50
-45
-40
-20
-25
-30
-35
0 1 2 3 4 65
ISO
LA
TIO
N (d
B)
FREQUENCY (GHz)
Figure 15. Isolation vs. Frequency.
6
Table 1.
MGA-83563 Typical Scattering Parameters[1]
TC = 25°C, Vd = 3.0V, Id = 165 mA, CW Operation, Pin = -27 dBm
Freq. RIin S11 |S21|2 S21 Gain S12 RLout S22 Gmax
L GHz dB Mag Ang Gain Mag Ang dB Mag Ang dB Mag Ang K dB
Sim 18.0 nH 0.6 -4.6 0.59 -48 23.9 15.61 43 -46.7 0.005 105 -21.1 0.09 150 4.47 25.8Sim 18.0 nH 0.8 -9.6 0.33 -57 24.6 16.96 6 -39.0 0.011 102 -16.8 0.15 -130 2.37 25.2Sim 18.0 nH 1.0 -16.0 0.16 -27 24.1 16.02 -25 -35.5 0.017 87 -10.1 0.31 -146 1.80 24.6Sim 18.0 nH 1.4 -10.1 0.31 22 21.7 12.22 -68 -32.8 0.023 66 -5.8 0.51 177 1.48 23.5Sim 18.0 nH 1.8 -7.3 0.43 17 19.1 9.03 -97 -31.7 0.026 54 -4.4 0.61 150 1.45 22.0Sim 8.2 nH 0.8 -4.1 0.63 -36 21.2 11.52 48 -47.4 0.004 95 -17.2 0.14 121 6.01 23.5Sim 8.2 nH 1.0 -5.8 0.51 -45 22.7 13.65 22 -41.1 0.009 111 -35.2 0.02 130 3.13 24.0Sim 8.2 nH 1.4 -13.0 0.22 -45 23.7 15.30 -27 -33.7 0.021 94 -10.4 0.30 -139 1.54 24.3Sim 8.2 nH 1.8 -13.0 0.22 13 22.4 13.15 -68 -30.9 0.029 74 -5.5 0.53 -179 1.21 24.1Sim 8.2 nH 2.0 -10.7 0.29 18 21.3 11.65 -84 -30.3 0.031 67 -4.4 0.60 166 1.16 23.7Sim 8.2 nH 2.4 -8.2 0.39 15 19.1 8.98 -111 -29.5 0.034 57 -3.4 0.68 141 1.14 22.5Sim 4.7 nH 1.4 -6.7 0.46 -44 22.1 12.72 4 -37.6 0.013 109 -26.7 0.05 -78 2.44 23.1Sim 4.7 nH 1.8 -12.0 0.25 -43 22.9 13.99 -37 -32.3 0.024 94 -9.9 0.32 -143 1.44 23.7Sim 4.7 nH 2.0 -14.3 0.19 -23 22.6 13.53 -57 -30.8 0.029 85 -7.1 0.44 -164 1.26 23.7Sim 4.7 nH 2.4 -11.9 0.26 10 21.1 11.36 -90 -29.2 0.035 70 -4.3 0.61 163 1.09 23.4Sim 4.7 nH 2.8 -9.4 0.34 12 19.1 9.03 -115 -28.3 0.038 61 -3.2 0.69 138 1.05 22.5Meas 2.2 nH 1.8 -6.3 0.49 -53 21.5 11.92 -23 -37.2 0.014 90 -15.1 0.18 -100 2.40 22.8Meas 2.2 nH 2.0 -7.4 0.43 -51 21.9 12.48 -45 -34.8 0.018 85 -9.7 0.33 -130 1.82 23.3Meas 2.2 nH 2.4 -7.9 0.40 -36 20.9 11.07 -82 -32.4 0.024 68 -6.2 0.49 -175 1.52 22.8Meas 2.2 nH 2.8 -7.1 0.44 -27 19.0 8.93 -113 -31.2 0.027 56 -4.1 0.63 150 1.40 22.1Meas 2.2 nH 3.0 -6.6 0.47 -25 18.0 7.90 -123 -31.0 0.028 52 -4.1 0.62 138 1.48 21.1Sim 1.2 nH 2.4 -7.9 0.40 -41 20.5 10.61 -36 -33.4 0.021 97 -18.0 0.13 -120 1.98 21.3Sim 1.2 nH 2.8 -10.8 0.29 -37 20.7 10.90 -67 -30.4 0.030 88 -9.6 0.33 -168 1.47 21.6Sim 1.2 nH 3.0 -11.9 0.25 -29 20.5 10.56 -82 -29.4 0.034 82 -7.4 0.43 176 1.34 21.6Sim 1.2 nH 3.2 -12.3 0.24 -20 20.0 9.97 -95 -28.6 0.037 76 -5.9 0.51 161 1.24 21.5Sim 1.2 nH 3.6 -11.7 0.26 -7 18.6 8.49 -120 -27.5 0.042 67 -4.1 0.62 137 1.14 21.0Meas 0.0 nH 3.0 -5.6 0.53 -33 17.9 7.87 -13 -39.1 0.011 109 -12.8 0.23 -7 4.07 19.6Meas 0.0 nH 3.4 -4.7 0.58 -31 20.1 10.13 -43 -34.1 0.020 107 -7.9 0.40 -73 1.72 22.7Meas 0.0 nH 3.8 -5.5 0.53 -50 20.0 9.95 -81 -31.7 0.026 94 -6.2 0.49 -132 1.43 22.6Meas 0.0 nH 4.0 -7.4 0.43 -52 19.4 9.28 -94 -30.9 0.028 93 -4.5 0.60 -148 1.38 22.1Meas 0.0 nH 4.2 -8.4 0.38 -48 18.7 8.62 -106 -30.2 0.031 91 -3.5 0.67 -163 1.27 21.9Meas 0.0 nH 4.6 -9.0 0.36 -44 17.0 7.08 -129 -28.8 0.036 84 -3.1 0.70 173 1.25 20.5Meas 0.0 nH 5.0 -9.2 0.35 -39 15.4 5.87 -145 -27.9 0.040 78 -3.0 0.71 155 1.29 19.0Meas 0.0 nH 5.4 -9.7 0.33 -32 13.8 4.88 -159 -27.2 0.044 77 -3.0 0.71 140 1.38 17.3Meas 0.0 nH 5.8 -7.8 0.41 -29 12.4 4.16 -170 -25.9 0.051 73 -3.6 0.66 127 1.47 15.7Meas 0.0 nH 6.0 -6.6 0.47 -46 12.1 4.03 177 -24.9 0.057 64 -3.3 0.68 123 1.33 15.9
Note:
1. Reference plane per Figure 26 in Applications Information section.
MGA-83563 Test CircuitTypical s-parameters are shownbelow for various inductor values(L). Those marked “Sim” aresimulated and those marked“Meas” are measured using anICM (Intercontinental Micro-wave) fixture. Figure 17 showsthe available gain for each Lvalue. The user should first selectthe L value for the application
s-parameter reference plane
L
OUT83
BiasTee
50 pF
IN
Vd
GA
IN (d
B)
FREQUENCY (GHz)
Figure 17. Available Gain (Gmax) vs.
Frequency for the MGA-83563 Amplifier
over Various Inductance Values.
10
14
18
26
22
24
20
16
12
0 1 2 3 4 65
18 nH8.2 nH
4.7 nH
2.2 nH1.2 nH
0 nH
Figure 16. S-parameter Test Circuit.
frequency before designing aninput, output, or power matchingstructure.
7
MGA-83563 Applications
InformationThe MGA-83563 is two-stage,medium power GaAs RFICamplifier designed to be used fordriver and output stages intransmitter applications operatingwithin the 500 MHz to 6 GHzfrequency range.
This device is designed foroperation in the saturated modewhere it delivers a typical outputpower of +22 dBm (158 mW) witha power-added efficiency of 37%.The MGA-83563 has a large signalgain of 18 dB requiring an inputsignal level of only +4 dBm todrive it well into saturation. Thehigh output power and highefficiency of the MGA-83563,combined with +3-volt operationand subminiature packaging,make this device especially usefulfor battery-powered, personalcommunication applications suchas wireless data, cellular phones,and PCS.
The upper end of the frequencyrange of the MGA-83563 extendsto 6 GHz making it a usefulsolution for medium poweramplifiers in wireless communi-cations products such as 5.7 GHzspread spectrum or other ISM/license-free band applications.Internal capacitors on the RFICchip limit the low-end frequencyresponse to applications aboveapproximately 500 MHz.The thermal limitations of thesubminiature SOT-363 (SC-70)package generally restrict the useof the MGA-83563 to applicationsthat use constant envelope typesof modulation. These types ofsystems are able to take fulladvantage of the MGA-83563’shigh efficiency, saturated mode ofoperation. The use of the
MGA-83563 for linear applicationsat reduced power levels isdiscussed in the “Thermal Designfor Reliability” and “Use of theMGA-83563 for Linear Applica-tions” in this applications note.
Application GuidelinesThe use of the MGA-83563 is verystraightforward. The on-chip,partial RF impedance matchingand integrated bias control circuitsimplify the task of using thisdevice.
The design steps consist of (1)selecting an interstage inductorfrom the data provided, (2)adding provision for bringing inthe DC bias, and (3) designingand optimizing an output imped-ance match for the particularfrequency band of interest. Theinput is already well matched to50 ohms for most frequencies andin many cases no additional inputmatching will be necessary.
Each of the three design steps forusing the MGA-83563 will now bediscussed in greater detail.
Step 1—Selecting the
Interstage Inductor
The drain of the first stage FET ofthis two-stage RFIC amplifier isconnected to package Pin 1. Thesupply voltage Vd is connected tothis drain through an inductor,L2, as shown in Figure 18. Thesupply end of the inductor isbypassed to ground.
This interstage inductor servesthe purpose of completing theimpedance match between thefirst and second stages. The valueof inductor L2 depends on theparticular frequency for whichthe MGA-83563 is to be used andis chosen from the look-up graphin Figure 19.
RFInput
RFInput
RFC
Vd
3
L2
1
6
Figure 18. Interstage Inductor L2 and
Bias Current.
The values for inductor L2 aresomewhat dependent on thespecific printed circuit boardmaterial, thickness, and RF layoutthat are used. The inductor valuesshown in Figure 19 have beencreated for the PCB and RFlayout that is used for the circuitexamples presented in thisapplication note. The methodol-ogy that was used to determinethe optimum values for L2 and forcreating Figure 19 is presented inthe Appendix. If the user’s PCBand/or layout differ significantlyfrom the example circuits, referto the Appendix for a descriptionof how to determine the values ofL2 for any arbitrary frequency,PCB material, or RF layout.
Step 2—Bias Connections
The MGA-83563 is a voltage-biased device and operates froma single, positive power supply.The supply voltage, typically+3-volts, must be applied to thedrains of both stages of the RFICamplifier. The connection to thefirst stage drain is made throughthe interstage inductor, L2, asdescribed in the previous step.The supply voltage is applied tothe second stage drain throughPin 6, which is also the RF Outputconnection. Referring toFigure 18, an inductor (RFC) isused to separate the RF outputsignal from the DC supply. The
8
supply side of the RFC is capaci-tively bypassed. A DC blockingcapacitor is used at the output toisolate the supply voltage fromthe succeeding stage.
In order to prevent loss of outputpower, the value of the RFC ischosen such that its reactance isseveral hundred ohms at thefrequency band of operation. Athigher frequencies, it may bepractical to use a length of highimpedance transmission line(preferably λ/4) in place of theRFC.
The value of the DC blocking andRF bypass capacitors are chosento provide a small reactance(typically < 1Ω) at the lowestoperating frequency.
Since both stages of the RFIC arebiased from the same voltagesource, particular care should betaken to ensure that the supplyline between the two is wellbypassed to prevent inadvertent
feedback from the RF output tothe drain of the first stage.Otherwise, the circuit couldbecome unstable.
The RF Input (Pin 3) connectionto the MGA-83563 is at DC groundpotential. The use of a DCblocking capacitor at the input ofthe MGA-83563 is not requiredunless a circuit that has a DCvoltage present at its outputprecedes the RFIC. Although atground potential, the input to theMGA-83563 should not be used asa current sink.
Step 3—
Output Impedance Match
The most interesting aspect ofusing the MGA-83563 is arrivingat an optimum, large signalimpedance match at the output. Asimple but effective approach isto begin with a circuit thatprovides a small signal imped-ance match, then empiricallyadjust the tuning for optimumlarge signal performance.
The starting place is to design acircuit that matches the smallsignal Γml (the reflection coeffi-cient of the load impedancerequired to conjugately match theoutput of the MGA-83563) to50 ohms. The small signalS-parameter data for designingthe output circuit is taken fromTable 1, using the data corre-sponding to be nearest value ofinterstage inductor that waschosen in step one.
A RF CAD program such asAgilent’s Touchstone can be usedto easily calculate Γml. Touch-
stone will interpolate the Table 1S-parameter data for the particu-lar design frequency of interest.
As the MGA-83563 is driven intosaturation, the output impedancewill generally become lower.Choose a circuit topology thatwill match Γml as well as therange of impedances on the lowside of Γml. Beginning with thissmall signal output match, tunethe circuit under large signalconditions for maximumsaturated output power and bestefficiency.
It should be noted that both thesaturated output power (Psat) andpower-added efficiency (PAE) foreach MGA-83563 is 100% RFtested at 2.4 GHz in a productiontest fixture that simulates anactual amplifier application. Thismethod of testing not onlyguarantees minimumperformance standards, but alsoensures repeatable RFperformance in the user’sproduction circuits.
Figure 19. Values for Interstage Inductor L2.
L2
(nH
)
FREQUENCY (GHz)
10.90.80.7
10
20
30
40
987654
3
2
0.5 1.0 1.5 2.0 2.5 3.0
9
Step 4 (Optional)—
Input Impedance Match
As previously noted, the internalinput impedance match to theMGA-83563 is already reasonablygood (return loss is typically8 dB) and may be adequate formany applications as is. Thedesign of the MGA-83563 is suchthat the second stage will enterinto compression before the firststage. The isolation provided bythe first stage therefore results ina minimal impact on the inputmatching as the amplifierbecomes saturated.
If an improved input return loss isneeded, an input circuit is de-signed to match 50 Ω to Γms (thereflection coefficient of thesource impedance for a conjugatematch at the input of theMGA-83563). The value of Γms iscalculated from the S-parametersin Table 1 in the same way as wasdone for Γml. Since the real partof the input impedance to theMMIC is near 50 Ω and thereactive part is capacitive, theaddition of a simple seriesinductor is often all that is neededif a better input match is required.
PCB Layout
Recommendations
When laying out a printed circuitboard for the MGA-83563, severalpoints should be taken intoaccount. The PCB layout will be abalance of electrical, thermal, andassembly considerations.
Package Footprint
A recommended printed circuitboard footprint for the miniatureSOT-363 (SC-70) package that isused by the MGA-83563 is shownin Figure 20.
This package footprint providesample allowance for packageplacement by automated assem-bly equipment without addingparasitics that could impair thehigh frequency performance ofthe MGA-83563. (The padprint inFigure 20 is shown with thefootprint of a SOT-363 packagesuperimposed on the PCB padsfor reference.)
PCB Materials
FR-4 or G-10 printed circuit boardtype of material is a good choicefor most low cost wirelessapplications for frequenciesthrough 3 GHz. Typical single-layer board thickness is 0.020 to0.031 inches. Multi-layer boardsgenerally use a dielectric layerthickness in the 0.005 to0.010 inch range.
For higher frequency applica-tions, e.g., 5.8 GHz, circuit boardsmade with PTFE/glass dielectricmaterials are suggested.
0.026
0.075
0.016
0.035
Figure 20. PCB Pad Layout for
MGA-83563 Package (dimensions in
inches).
RF Considerations
Starting with the packagepadprint of Figure 20, the nucleusof a PCB layout is shown inFigure 21. This layout is a goodgeneral purpose starting point fordesigns using the MGA-83563amplifier.
RFInput
RFOutput
L2
Vd1
BypassCapacitor
83
Figure 21. Basic PCB Layout.
This layout is a microstriplinedesign (solid groundplane on thebackside of the circuit board)with a 50 Ω input and output andprovision for inductor L2 with itsbypass capacitor.
Adequate RF grounding is criticalto obtain maximum performanceand to maintain device stability.All of the ground pins of the RFICshould be connected to the RFgroundplane on the backside ofthe PCB by means of platedthrough holes (vias) that areplaced very near the packageterminals. As a minimum, one viashould be located next to eachground pin to ensure good RFgrounding. It is a good practice touse multiple vias as in Figure 21to further minimize ground pathinductance.
While it might be considered aneffective RF practice, it is recom-mended that the PCB pads for theground pins not be connectedtogether underneath the body ofthe package for two reasons. Thefirst reason is that connecting theground pins of multi-stageamplifiers together can some-times result in undesirablefeedback between stages. Eachground pin should have its ownindependent path to ground. Thesecond reason is that PCB traceshidden under the package cannotbe adequately inspected forsolder quality.
10
Thermal Considerations
The DC power dissipation of theMGA-83563, which can be on theorder of 0.5 watt, is approachingthe thermal limits of subminiaturepackaging such as the SOT-363.As a result, particular care shouldbe taken to adequately heatsinkthe MGA-83563.
The primary heat path from theMMIC chip to the system heatsinkis by means of conductionthrough the package leads andground vias to the groundplaneon the backside of the PCB. Aspreviously mentioned in the“PCB Layout” section, the use ofmultiple vias near all of theground pins is desirable for lowinductance. The use of multiplevias is also an especially impor-tant part of the heatsinkingfunction.
For heatsinking purposes, athinner PCB with more vias,thicker clad metal, and heavierplating in the vias all result inlower thermal resistance andbetter heat conduction. Circuitboards thicker than 0.031 inchesare not recommended for boththermal and electrical reasons.
The importance of good thermaldesign on reliability is discussedin the next section.
Thermal Design for
Reliability
Good thermal design is animportant consideration in thereliable use of medium powerdevices such as the MGA-83563because the Mean Time ToFailure (MTTF) of semiconductordevices is inversely proportionalto the operating temperature.
The following examples show thethermal prerequisites for usingthe MGA-83563 reliably in bothsaturated and linear modes.
Saturated Mode Thermal
Example
Less heat is dissipated in theMGA-83563 when operated in thesaturated mode because asignificant amount of power isremoved from the RFIC as RFsignal power. It is for this reasonthat the saturated mode allowsthe device to be used reliably athigher circuit board temperaturesthan for full power, linearapplications.
As an illustration of a thermal/reliability calculation, considerthe case of an MGA-83563 biasedat 3.0 volts for use in a saturatedmode application with a MTTFreliability goal of 106 hours(114 years). Reliability calcula-tions will first be presented fornominal conditions, followed bythe conservative approach ofusing worst-case conditions.
The first step is to calculate thepower dissipated by theMGA-86353 as heat. Power flowfor the MGA-83563 is representedin Figure 22.
Σ Pn = 0
PDC
Pin Pout
PdissHEAT
Figure 22. Thermal Representation
of MGA-83563.
From Figure 22,
Pin + PDC = Pout + Pdiss
where Pin and Pout are the RFinput and output power, PDC isthe DC input power, and Pdiss isthe power dissipated as heat. Forthe saturated mode, Pout = Psat ,and, Pdiss = Pin + PDC – Psat
From the table of ElectricalSpecifications, the device current(typical) is 152 mA with a powersupply voltage of 3 volts. Refer-ring to Figure 10, it can be seenthat the current will decreaseapproximately 8% at elevatedtemperatures. The device DCpower consumption is then:
PDC = 3.0 volts * 152 mA * 0.92
PDC = 420 mW
For a saturated amplifier, the RFinput power level is +4 dBm(2.51 mW) and the saturatedoutput power is +22 dBm(158 mW).
The power dissipated as heat isthen: Pdiss = 2.51 + 420 – 158 mW
Pdiss = 264 mW
The channel-to-case thermalresistance (θch-c) from the tableof Absolute Maximum Ratings is175°C/watt. Note that the mean-ing of “case” for packages such asthe SOT-363 is defined as theinterface between the packagepins and the mounting surface,i.e., at the PCB pads. The tem-perature rise from the mountingsurface to the MMIC channel isthen calculated as0.264 watt * 175°C/watt, or 46°C.
11
Operating life tests [1] for theMGA-83563 have established thata MTTF of 106 hours will be metfor channel temperatures ≤ 150°C.To achieve the 106 hour MTTFgoal, the circuit to which thedevice is mounted (i.e., the casetemperature) should thereforenot exceed 150° – 46°C, or 104°C.
Repeating the reliability calcula-tion using the worst case maxi-mum device current of 200 mA,the DC power dissipation is552 mW. Summing the RF inputand output powers, Pdiss is397 mW which results in achannel-to-case temperature riseof 69°C. The maximum casetemperature for the MTTF goal of106 hours is then 150°– 69°C, or81°C.
For other MTTF goals, powerdissipation, or operating tempera-tures, Agilent publishes reliabilitydata sheets based on operatinglife tests to enable designers toarrive at a thermal design fortheir particular operating environ-ment. For a reliability data sheetcovering the MGA-83563, requestAgilent publication number 5964-4128E, titled “GaAs MMIC Ampli-fier Reliability Data.” This reliabil-ity data sheet covers the Agilentfamily of PHEMT GaAs RFICs.
Linear Amplifier Thermal
Example
If the MGA-83563 is used in alinear application, the total powerdissipation is significantly higherthan for the saturated mode. Thedissipated power is greater due tohigher device current (not asefficient as the saturated mode)and also because no signal poweris being removed.
The maximum power dissipationfor reliable linear operation iscalculated in the same manner aswas done for the saturatedamplifier example. For linearcircuits, the RF input and outputpower are negligible and assumedto be zero. All of the DC power isthus dissipated as heat. Forpurposes of comparison to thesaturated mode example, thiscalculation will use the sameMTTF goal of 106 hours andsupply voltage of 3 volts.Calculations are again made forboth nominal and worst caseconditions.
From the data of Figure 10, thetypical 3-volt, small signal devicecurrent for the MGA-83563 atelevated temperatures is 156 mA.The total device power dissipa-tion, Pdiss, is then 3.0 volts *156 mA, or 468 mW. The tempera-ture increment from the RFICchannel to case is 0.468 watt *175°C/watt, or 82°C.
Commensurate with the MTTFgoal of 106 hours, the circuit towhich the device is mountedshould therefore not exceed150°– 82°C, or 68°C.
For the worst case calculation, aguard band of 40% is added to thetypical current to arrive at amaximum DC current of 218 mA.The Pdiss is 655 mW and thechannel-to-case temperature riseis 115°C. The maximum casetemperature for worst casecurrent condition is 35°C.
A case temperature of 68°C fornominal operation, or 35°C in theworst case, is unacceptably lowfor most applications. In order touse the MGA-83562 reliably forlinear applications, the Pdiss mustbe lowered by reducing thesupply voltage.
The implication on RF outputpower performance for amplifiersoperating with a reduced Vd iscovered later in this applicationnote in the section subtitled “Useof the MGA-83563 for LinearApplications”.
Design Example for
2.5 GHzThe design of a 2.5 GHz amplifierwill be used to illustrate theapproach for using theMGA-83563. The basic designprocedure outlined earlier will beused, in which the interstageinductor (L2) is chosen first,followed by the design of aninitial small signal, output match.The output match will then beempirically optimized for largesignal conditions after which aninput match will be added.
The printed circuit layout inFigure 21 is used as the startingplace. The circuit is designed forfabrication on 0.031-inch thickFR-4 dielectric material.
Interstage Inductor L2
The first step is to choose a valuefor the interstage inductor, L2.Referring to Figure 19, a value of1.5 nH corresponds to the designfrequency of 2.5 GHz. A chipinductor is chosen for L2 in thisexample. However, for smallinductance values such as this,the interstage inductor could alsobe realized with a length of highimpedance transmission line.
The interstage inductor is by-passed with a 62 pF capacitor,which has a reactance of 1 Ω at2.5 GHz. Connecting the supplyvoltage to the bypassed side ofthe inductor completes theinterstage part of the amplifier.
12
Output Match
The design of the small signaloutput matching circuit beginswith the calculation of the smallsignal match impedance, Γml. Theset of S-parameters in Table 1 foran inductor value of 1.2 nH isused since this is the closestvalue to the 1.5 nH that waschosen for L2 in the first designstep.
Agilent’s Touchstone programwas used to interpolate the s-parameter data and calculate aΓml of 0.14 ∠172° for 2.5 GHz.
This Γml point is plotted on theSmith chart in Figure 23 asPoint C, along with an indicationof the area of lower impedancefrom this point. (The outputimpedance is expected todecrease under large signalconditions.) A two-elementmatching network consisting of ashunt capacitor and seriestransmission line is chosen tomatch the output to 50 ohms.
A
1
C
A (50 Ω)C (Γml) B
2
-2
B
0.5
0.2
-0.2
21
-0.5
-1
MLINRF
Output C
LARGE SIGNAL
Figure 23. Initial Output Match for
Small Signal.
The shunt-C, series-line topologyis chosen based on its ability tocover the expected range ofimpedance to be matched andbecause it will pass DC bias intothe output pin of the MGA-83563.
(For the latter reason, impedancematching circuits using seriescapacitors are avoided.)
In some cases, it may be morepractical to implement the seriestransmission line element with achip inductor. If the series line isexcessively long, the cost of anadditional chip component can betraded off against circuit boardspace. The substitution of anopen-circuit line for the shunt Cmay also be possible, thuseliminating the a capacitor.
Referring to the Smith chart inFigure 23, the initial output matchfor Γml was determined to be a0.4 pF shunt capacitor followedby a 0.32-inch length of 50 Ωmicrostripline.
DC Bias
A 22 nH RFC is added to the 50 Ωside of the output matchingcircuit to apply bias voltage to thedrain of the second stage. TheRFC is bypassed with a 62 pFcapacitor. A series DC blockingcapacitor, also 62 pF, is added tothe RF output to complete thebias circuit.
Optimizing the Output
Match
To reach the final outputmatching circuit for maximumsaturated output power, an inputpower of +4 dBm is applied tosaturate the amplifier circuit. Theoutput matching circuit is thenexperimentally optimized byadjusting the value of the shuntcapacitor and the distance thecapacitor is located along theoutput line from the MGA-83563.
During the tuning process, thesaturated output power of theamplifier is monitored with apower meter connected to the
amplifier’s output. An ammeter isused to observe total device DCcurrent drain (Id) as an indicationof amplifier efficiency. Thedesired output match is thenachieved at the tuning point ofmaximum Psat and minimum Id.
The optimum output match for2.5 GHz was achieved with ashunt capacitor value of 0.9 pFlocated 0.08 inches along the 50 Ωline from the output pin of theMGA-83563. The final outputcircuit is shown in Figure 24.
0.9 pF50 Ω
0.08 in.
RFOutput
RFInput
MGA-83563
Figure 24. Final RF Output Match for
the 2.5 GHz Amplifier Tuned for
Maximum Psat.
When tuned for maximumsaturated output power, the smallsignal output return loss for theamplifier was measured as 5.5 dBat 2.5 GHz.
Input Match
The input return loss without anyexternal matching was measuredas 7.6 dB (2.4:1 VWSR). For manyapplications no further matchingis necessary. If, however, animproved input match is required,a simple series inductor is all thatwill be needed.
Agilent’s Touchstone CAD pro-gram is again used to extrapolatethe 2.5 GHz S-parameters in Table1 and calculate a small signal Γmsof 0.37 ∠47°. The conjugate ofΓms, 0.37 ∠ -47°, is plotted on theSmith chart as Point A inFigure 25.
13
A
1
1C
A (Γms*)B
2
-2
B
0.5
0.5
0.2
-0.2
0.2 2
-0.5
-1
MLINRF
Input
C (50 Ω)
L1
Figure 25. Initial Small Signal Input
Match.
The addition of a 0.15 inch length(actual length on FR-4) of 50 Ωtransmission line rotates Point Aaround to Point B on the R = 1circle of the Smith chart. A series2.5 nH inductor (L1) is then allthat is required to complete thematch to 50 Ω at Point C.While the input impedance of theMGA-83563 is somewhat isolatedfrom the nonlinear effects of thesaturated output stage, someempirical optimization of theinput inductor may increase theinput return loss still further. Theinput is easily fine-tuned underlarge signal conditions by observ-ing the input return loss while aninput power of +4 dBm is appliedto the amplifier. The inputinductor is then “swept” byplacing various values of chipinductors across the gap providedin the 50 Ω line at the input of theMGA-83563. For this exampleamplifier, increasing the inductorfrom the initial small signal valueof 2.5 nH to 2.7 nH was found toprovide the best input match. Thefinal input circuit tuned as forlarge signal conditions is shownin Figure 26.
2.7 nH
50 Ω0.17 in.
RFOutput
RFInput
MGA-83563
Figure 26. Final Large Signal RF Input
Match for the 2.5 GHz Amplifier.
The addition of the 2.7 nH seriesinductor increased the largesignal input return loss from7.6 dB (with no matching) to14.8 dB (1.4:1 VSWR) at 2.5 GHz.
Completed 2.5 GHz
Amplifier
A schematic diagram of the final2.5 GHz circuit is shown inFigure 27. All unmarked capaci-tors are 62 pF.
Vd
RFOutput
RFInput
83
L1 = 2.7 nH L2 = 1.5 nH
RFC =22 nH
50 Ω0.17 in
3
6
1
50 Ω0.08 in C2 = 0.9 pF
Figure 27. Schematic Diagram of
2.5 GHz Amplifier.
The completed 2.5 GHz amplifierassembly with all components isshown in Figure 28.
Input
Output
L2
+3V
L1RFC
CC
CC2
83
Figure 28. Completed 2.5 GHz
Amplifier Assembly.
The small signal gain of thecompleted amplifier was mea-sured as 22.0 dB at 2.5 GHz. Gainover a frequency range of 2.0 to3.0 GHz is shown in Figure 29.
14
18
22
28
26
24
20
16
2 2.2 2.4 2.6 32.8
GA
IN (d
B)
FREQUENCY (GHz)
Figure 29. Small Signal Gain of the
Completed 2.5 GHz Amplifier.
The (small signal) input andoutput return losses for thecompleted amplifier are 14.9 dBand 5.5 dB respectively at2.5 GHz. Input and output returnloss over the 2.0 to 3.0 GHzfrequency range is shown inFigure 30.
-25
-15
0
-5
-10
-20
2 2.2 2.4 2.6 32.8
RE
TU
RN
LO
SS
(dB
)
FREQUENCY (GHz)
Figure 30. Input and Output
Return Loss of the Completed
2.5 GHz Amplifier.
INPUT
OUTPUT
Table 2 summarizes measuredresults for this particular ampli-fier at 2.5 GHz.
Output
Mode Gain Power Id
(dB) (dBm) (mA)
Small Signal 22.0 — 148G-1dB 21.0 19.2 165
Saturated 17.8 21.8 139
Table 2. Performance Summary for
2.5 GHz Amplifier.
14
The power-added efficiency(PAE) in the saturated mode is36% as calculated from:
PAE = Σ PRF
PDC
PAE = (Pout – Pin)
PDC
Note the current increasesslightly from small signal condi-tions to the 1 dB compressionpoint, then falls appreciably asthe amplifier goes into saturation.(The 1-dB compressed outputpower will be higher for amplifi-ers that are tuned for linearperformance.)
Psat
and PAE Sensitivity to
Inductor L2
The output match of the com-pleted 2.5 GHz amplifier was heldfixed while various values of L2were substituted for the purposesof (1) verifying the optimumvalue for L2, and (2) determiningthe sensitivity of Psat and PAE tothe value of L2. These results areplotted in Figure 31.
The data in Figure 31 indicatesthere is some tradeoff betweentuning for maximum outputpower and maximum efficiency.The original choice of 1.5 nH forthe interstage inductor L2 ap-pears well optimized.
The results of this tuning processsupplied the 2.5 GHz data pointreferred to in the Appendix thatwas used to create Plot B ofFigure 47.
Output Match Sensitivity
The sensitivity of Psat and PAE tothe value of the shunt capacitor inthe output matching circuit wasinvestigated by varying the valueof C2 while noting Psat and devicecurrent. The input power wasfixed at +4 dBm for this test.
The length of the series linebetween the output of theMGA-83563 and C2 is also part ofthe matching circuit. This line wasnot considered as a variable in thesensitivity analysis since photo-fabrication of micro-striplines oncircuit boards is highly repeatable.
Psat and PAE for each value of C2are plotted in Figure 32.Inspection of Figure 32 revealsthat a variation in C2 of ±10% isacceptable for most applications.
The most important observationof this data is that the PAEremains high for values of C2 thatare toward the left of the maxi-mum Psat point (lower values ofC2), while the PAE begins to dropoff toward for higher values ofC2. This data points out theimportance of choosing a valuefor C2 that is toward the lowerside of the maximum Psat point(lower C2) in order to maintainhigh efficiency with productiontolerance components.
0
10
25
20
15
5
0 0.5 1 1.5 42 2.5 3 3.5
Psa
t (d
Bm
)
10%
20%
40%
35%
30%
25%
15%
PA
E (%
)
L2 (nH)
PAE
Psat
Figure 31. 2.5 GHz Psat and PAE vs. L2.
18
21.5
23
22.5
22
21
20
20.5
19.5
19
18.5
0 0.5 1 1.5 2
Psa
t (d
Bm
)
10%
30%
50%
45%
40%
35%
25%
20%
15%
PA
E (%
)
C2 (pF)
PAE
Psat
Figure 32. 2.5 GHz Psat and PAE vs. C2.
15
Amplifier Designs for
1.9 GHz and 900 MHz
The same design process used forthe 2.5 GHz amplifier above wasrepeated for the design of amplifi-ers for the 1.9 GHz and 900 MHzfrequency bands. Examplecircuits were built using the samePCB layout as used for the2.5 GHz amplifier. The schematicdiagram, component values, andassembly drawing for the 1.9 GHzand 900 MHz designs are shownin the “Summary of ExampleAmplifiers“ section.
1.9 GHz Amplifier Measured
Results
Performance of this amplifier issummarized in Table 3. The PAEis 41%.
Output
Mode Gain Power Id
(dB) (dBm) (mA)
Small Signal 23.8 — 155G-1dB 22.8 19.6 182
Saturated 17.5 21.5 114
Table 3. Performance Summary for
1.9 GHz Amplifier.
Small signal gain over the 1.5 to2.3 GHz frequency range is shownin Figure 33.
14
18
22
26
24
20
16
1.5 1.7 1.9 2.1 2.3
GA
IN (
dB
)
FREQUENCY (GHz)
Figure 33. Small Signal Gain of the
Completed 1.9 GHz Amplifier.
The small signal input and outputreturn loss over the 1.5 to 2.3 GHzfrequency range is shown inFigure 34.
-20
-12
0
-4
-8
-16
1.5 1.7 1.9 2.1 2.3
RE
TU
RN
LO
SS
(dB
)
FREQUENCY (GHz)
Figure 34. Input and Output
Return Loss of the 1.9 GHz
Amplifier.
INPUT
OUTPUT
900 MHz Amplifier Measured
Results
Measured results for this 900 MHzamplifier is shown in Table 4. ThePAE is 40%.
Output
Mode Gain Power Id
(dB) (dBm) (mA)
Small Signal 24.5 — 168G-1dB 23.5 20.9 177
Saturated 18.5 22.5 144
Table 4. Performance Summary for
900 MHz Amplifier.
Gain over the 500 to 1300 MHzfrequency range is shown inFigure 35.
14
18
22
26
24
20
16
0.5 0.7 0.9 1.1 1.3
GA
IN (d
B)
FREQUENCY (GHz)
Figure 35. Small Signal Gain of the
900 MHz Amplifier.
Input and output return loss(small signal) from 500 to1300 MHz is shown in Figure 36.
-20
-10
0
-5
-15
0.5 0.7 0.9 1.1 1.3
RE
TU
RN
LO
SS
(dB
)
FREQUENCY (GHz)
Figure 36. Input and Output
Return Loss of the 900 MHz
Amplifier.
OUTPUT
INPUT
16
Psat and PAE Sensitivity to
Inductor L2 for the 900 MHz
Amplifier
As was done for the 2.5 GHzamplifier example, values for L2were “swept” for verification andto observe sensitivity of Psat andPAE. The results are plotted inFigure 37. This process verifiedthe correct value of L2 andprovided the 900 MHz data pointused in the Appendix to createPlot B of Figure 47.
Summary of Example
AmplifiersA schematic diagram for the threeexample amplifiers covering2.5 GHz, 1.9 GHz, and 900 MHz isshown in Figure 38.
Component values for the threedesigns are summarized inTable 5.
Frequency(nH, pF)
900 MHz 1.9 GHz 2.5 GHz
L1 5.6 2.2 2.7
L2 12 2.7 1.5
L3 82 33 22
L4 Not used (short circuit)
C2 3.6 1.2 0.9
C1, C3, C4 150 82 62
C5 1000
Table 5. Component Values for
Example Amplifiers.
The completed amplifier with allcomponents and SMA connectorsis shown in Figure 39. The circuitis fabricated on 0.031-inch FR-4material.
The additional 1000 pF bypasscapacitor, C5, was added to thebias line near the Vd connectionto eliminate interstage feedback.This layout has provision for aninductor (L4) at the output of theMGA-83563. This inductor is notused in for these example amplifi-ers and is replaced by a short.
21.0
21.4
23.0
21.8
22.0
21.6
22.2
22.6
22.8
22.4
21.2
0 5 10 15 454020 25 30 35
Psa
t (d
Bm
)
30%
40%
55%
50%
45%
35%
PA
E (%
)
L2 (nH)
PAE
Psat
Figure 37. 900 MHz Psat and PAE vs. L2.
Vd
RFOutput
RFInput 83
L1L2
L4
L3(RFC)
3
4 6
1
C2C3
C5C4
C1
50 Ω0.17 in
50 Ω0.08 in
Figure 38. Schematic Diagram for the Example Amplifiers.
17
Use of the MGA-83563 for
Linear Applications
Due to the thermal limitationscovered in the “Thermal Designfor Reliability” section, the MGA-83563 is best suited for use as asaturated mode amplifier. TheMGA-83563 can however be usedwith reduced output powerperformance by lowering thesupply voltage.
Some saturated amplifier applica-tions may also benefit fromoperation at reduced Vd for thepurpose of reducing current drainand extending battery life.
P1dB and Psat vs. Vd for the2.5 GHz and 900 MHz circuitexamples are shown in Figures 40and 41, respectively. The methodspresented in the “Thermal Designfor Reliability” section may beused to arrive at a maximumsupply voltage that correspondsto the desired MTTF goal.
The P1dB power plotted in Figures40 and 41 is taken from theexample amplifiers tuned formaximum Psat. P1dB will behigher with linear tuning. Whendesigning for linear applications,the value for the interstageinductor L2 is taken from Plot Aof Figure 47 in the Appendix.
The data in Tables 2–4 showsthat some increase in devicecurrent occurs as the outputpower approaches P1dB. Allow-ance should be made in thethermal analysis for the increasedPdiss if the circuit is to be used ator near P1dB.
Operation at Higher
Supply VoltagesWhile the MGA-83563 is designedprimarily for use in +3 voltapplications, the output powercan be increased by using ahigher supply voltage. Referringto Figure 5, the Psat can beincreased by up to 1 dB by using apower supply voltage of+3.6 volts.
Note: If bias voltages greater than3 volts are used, appropriatecaution should be given to boththe thermal limits and the Abso-lute Maximum Ratings.
Hints and
Troubleshooting
Oscillation
Unconditional stability of theMGA-83563 is dependent onhaving good grounding. Inad-equate device grounding or poorPCB layout techniques couldcause the device to be potentiallyunstable. In a multistage RFICsuch as the MGA-83563, feedbackthrough bias lines supplyingvoltage to both stages can lead tooscillation. It is important to wellbypass the connections to biassupply to ensure stable operation.
C5
C3
C4
L3L1
L4
IN
OUT
+Vd
MGA-83-A
C2
L2
83
Figure 39. Completed MGA-83563 Amplifier Assembly.
Figure 40. Output Power vs. Supply Voltage for the 2.5 GHz Amplifier.
5.00
9.00
25.00
13.00
15.00
11.00
17.00
21.00
23.00
19.00
7.00
1.00 1.25 1.50 1.75 3.00 3.30 3.502.00 2.25 2.50 2.70
OU
TP
UT
PO
WE
R (d
Bm
)
SUPPLY VOLTAGE, Vd (V)
P1dB
Psat
18
Statistical Parameters
Several categories of parametersappear within this data sheet.Parameters may be describedwith values that are either“minimum or maximum,” “typi-cal,” or “standard deviations.”
The values for parameters arebased on comprehensive productcharacterization data, in whichautomated measurements aremade on of a minimum of 500parts taken from three non-consecutive process lots ofsemiconductor wafers. The dataderived from product character-ization tends to be normallydistributed, e.g., fits the standardbell curve.
Parameters considered to be themost important to system perfor-mance are bounded by minimum
or maximum values. For theMGA-83563, these parametersare: Saturated Output Power(Psat), Power Added Efficiency(PAE), and Device Current (Id).Each of the guaranteed param-eters is 100% tested as part of themanufacturing process.
Values for most of the parametersin the table of Electrical Specifi-cations that are described bytypical data are the mathematicalmean (µ), of the normal distribu-tion taken from the characteriza-tion data. For parameters wheremeasurements or mathematicalaveraging may not be practical,such as S-parameters or NoiseParameters and the performancecurves, the data represents anominal part taken from thecenter of the characterizationdistribution. Typical values areintended to be used as a basis forelectrical design.
To assist designers in optimizingnot only the immediate amplifiercircuit using the MGA-83563, butto also evaluate and optimizetrade-offs that affect a completewireless system, the standard
deviation (σ) is provided formany of the Electrical Specifica-tions parameters (at 25°C) inaddition to the mean. The stan-dard deviation is a measure of thevariability about the mean. It willbe recalled that a normal distribu-tion is completely described bythe mean and standard deviation.
Standard statistics tables orcalculations provide the probabil-ity of a parameter falling betweenany two values, usually symmetri-cally located about the mean.Referring to Figure 42 for ex-ample, the probability of aparameter being between ±1σ is68.3%; between ±2σ is 95.4%; andbetween ±3σ is 99.7%.
68%
95%
99%
Parameter Value
Mean (µ) (typical)
-3σ -2σ -1σ +1σ +2σ +3σ
Figure 42. Normal Distribution.
Phase Reference PlanesThe positions of the referenceplanes used to specify S-param-eters and Noise Parameters forthe MGA-83563 are shown inFigure 43. As seen in the illustra-tion, the reference planes arelocated at the point where thepackage leads contact the testcircuit.
REFERENCEPLANES
TEST CIRCUIT
Figure 43. Phase Reference Planes.
SMT AssemblyReliable assembly of surfacemount components is a complexprocess that involves manymaterial, process, and equipmentfactors, including: method ofheating (e.g., IR or vapor phase
12.00
14.00
26.00
18.00
20.00
16.00
22.00
24.00
1.5 3.0 3.52.0 2.5
OU
TP
UT
PO
WE
R (
dB
m)
SUPPLY VOLTAGE, Vd (V)
P1dB
Figure 41. Output Power vs. Supply Voltage for the 900 MHz Amplifier.
Psat
19
reflow, wave soldering, etc.)circuit board material, conductorthickness and pattern, type ofsolder alloy, and the thermalconductivity and thermal mass ofcomponents. Components with alow mass, such as the SOT-363package, will reach solder reflowtemperatures faster than thosewith a greater mass.
The MGA-83563 is qualified to thetime-temperature profile shownin Figure 44. This profile isrepresentative of an IR reflowtype of surface mount assemblyprocess.
After ramping up from roomtemperature, the circuit boardwith components attached to it(held in place with solder paste)passes through one or morepreheat zones. The preheat zonesincrease the temperature of theboard and components to preventthermal shock and begin evapo-rating solvents from the solderpaste. The reflow zone brieflyelevates the temperature suffi-ciently to produce a reflow of thesolder.
The rates of change of tempera-ture for the ramp-up and cool-down zones are chosen to be lowenough to not cause deformationof the board or damage tocomponents due to thermalshock. The maximum tempera-ture in the reflow zone (TMAX)should not exceed 235°C.
These parameters are typical fora surface mount assemblyprocess for the MGA-83563. As ageneral guideline, the circuitboard and components should beexposed only to the minimumtemperatures and times neces-sary to achieve a uniform reflowof solder.
Electrostatic SensitivityRFICs are electro-static discharge (ESD)sensitive devices.Although theMGA-83563 is robust in design,permanent damage may occur tothese devices if they are sub-jected to high-energy electrostaticdischarges. Electrostatic chargesas high as several thousand volts
(which readily accumulate on thehuman body and on test equip-ment) can discharge withoutdetection and may result indegradation in performance,reliability, or failure.
Electronic devices may besubjected to ESD damage in anyof the following areas:
• Storage & handling• Inspection & testing• Assembly• In-circuit use
The MGA-83563 is a ESD Class 1device and proper ESD precau-tions are recommended whenhandling, inspecting, testing,assembling, and using thesedevices to avoid damage. Forcases is which the MGA-83563 isused as an output stage withcoupling to an external antenna,the device should be protectedfrom high voltage spike damagedue to human contact with theantenna.
Appendix—
Determination of
Interstage Inductor
Value.
A methodology is presented herefor determining the value of theinterstage inductor, L2 thatproduces optimum large signalperformance at any frequency.This is the method used to createthe plot of Optimum L2 vs.Frequency in Figure 19. Thisprocedure is included as areference for PCB designs thatmay differ considerably from theexample circuit of Figure 40.
While the method described herecovers a wide range of frequen-cies for generic applications, thesame approach can be used for a
TIME (seconds)
TMAX
TE
MP
ER
AT
UR
E (
°C)
00
50
100
150
200
250
60
PreheatZone
Cool DownZone
ReflowZone
120 180 240 300
Figure 44. Surface Mount Assembly Profile.
20
single frequency of interest.Although the printed circuitboard layout of Figure 40 is usedhere for demonstration purposes,the same procedure is equallyapplicable to the any other circuitboard material, thickness, ortopology.
This is a 2-step process in whichthe value for L2 for best smallsignal performance is firstascertained followed by anempirical adjustment of L2 toallow for large signal effects.
The first step in this process is toassemble a test circuit for theMGA-83563 with 50-ohm inputand output lines. This test circuitshould use the same printedcircuit board material, thickness,and ground via arrangement forthe MGA-83563 that will be usedto the final amplifier circuit. Theconnection to Pin 1 should haveprovision for a chip inductor thatis bypassed to ground. Thebypassed side of the inductor isconnected to the supply voltage.The supply voltage is also con-nected to the RF Output/Vd2(Pin 6) by means of an external,wideband bias tee. The testcircuit is shown in Figure 45.
L2
OUT
+VdTest Circuit
IN
MGA-83563
BIASTEE
50 Ω50 Ω
Figure 45. L2 Test Circuit.
Next, the wideband gain responseof the test circuit is observedwhile substituting various valuesof chip inductors for L2. For eachvalue of L2, the gain should beplotted and/or the frequency at
which the maximum gain occursrecorded. Note that the smallsignal input and output matchprovided by the internal matchingof the MGA-83563 is sufficientlyclose to 50 ohms for most combi-nations of L2 and frequencies thatfurther matching would notsignificantly skew the data. Thisis a small signal test and the inputpower level should be less than-15 dBm.
0
10
25
2.7
1533
15
20
5
0.5 1.0 2.0 4.0 5.03.0 6.0
GA
IN (d
B)
FREQUENCY (GHz)
1.5
0 nH
6.84.7
Figure 46. Small Signal Gain vs.
Frequency for Various Values of L2.
Various values of Toko, Inc.©
type LL1608 inductors were usedfor this particular example. Aninductance value of 0.5 nH wasused for the case of a shortcircuit placed across the gapprovided for L2. For use at5.8 GHz, Pin 1 should be bypassedthrough the most direct path(minimum inductance) to ground.Referring to Figure 21, L2 is notused and a bypass capacitor isplaced from Pin 1 directly to theground pad for Pin 2.
The result of this step is themultiple plot shown in Figure 46of gain vs. frequency with L2 as aparameter. This plot is similar tothe plot in Table 1, but differs inthat the data in Figure 46 isspecific to the designer’s particu-lar PCB layout. The Table 1 datais a combination of test data
taken in a relatively parasitic-sterile characterization fixtureand computer simulations. Thetest data in Figure 46 includes theeffects of all circuit parasitics,ground vias, parasitics of theactual chip inductor that will beused, and also takes into accountthe length of line and bypasscapacitor used to make theconnection to L2 that will be usedin the final circuit.
The value of L2 is then plotted vs.the frequency at which the gainpeak occurred for each value ofinductance. This plot is done as alog plot with a straight-line curvefit added to smooth the data. Thisdata, shown as Plot A in Figure47, then gives the optimum valueof L2 for maximum small signal
gain, i.e., linear performance.
The results of the 2.5 GHz and900 MHz example amplifierspresented in this ApplicationNote were used to modify Plot Afor large signal use. The optimum,large signal value for L2 at2.5 GHz was determined to be1.5 nH, and 12 nH for 900 MHz.These two L2-frequency pointsare added to the data plot ofFigure 47. A straight line is drawnthrough these two points tocreate Plot B.
Plot B provides a look-up forvalues of L2 for saturated ampli-fier designs. Plot A is used forlinear amplifiers. Note: Plot B isreplicated as Figure 19 in the“Application Guidelines” sectionof this note.
[1] Operating life test conducted for a casetemperature of 60°C and with a Vd of3.6 volts. After 1000 hours, there were 0failures.
21
Figure 47. Optimum L2 for Small Signal Gain vs. Frequency.
L2
(nH
)
FREQUENCY (GHz)
10.90.80.7
10
20
30
40
987654
3
2
0.5 1.0 1.5 2.0 2.5 3.0
PLOT A
PLOT B
22
MGA-83563 Part Number Ordering Information
Part Number Devices per Container Container
MGA-83563-TR1 3000 7" reel
MGA-83563-BLK 100 Antistatic bag
Package Dimensions
Outline 63 (SOT-363/SC-70)
2.20 (0.087)2.00 (0.079)
1.35 (0.053)1.15 (0.045)
1.30 (0.051)REF.
0.650 BSC (0.025)
2.20 (0.087)1.80 (0.071)
0.10 (0.004)0.00 (0.00)
0.25 (0.010)0.15 (0.006)
1.00 (0.039)0.80 (0.031)
0.20 (0.008)0.10 (0.004)
0.30 (0.012)0.10 (0.004)
0.30 REF.
10°
0.425 (0.017)TYP.
DIMENSIONS ARE IN MILLIMETERS (INCHES)
PACKAGEMARKINGCODE (XX)
X X X
DATE CODE (X)
23
Tape Dimensions and Product Orientation
For Outline 63
Device Orientation
P
P0
P2
FW
C
D1
D
E
A0
8° MAX.
t1 (CARRIER TAPE THICKNESS) Tt (COVER TAPE THICKNESS)
5° MAX.
B0
K0
DESCRIPTION SYMBOL SIZE (mm) SIZE (INCHES)
LENGTHWIDTHDEPTHPITCHBOTTOM HOLE DIAMETER
A0B0K0PD1
2.24 ± 0.102.34 ± 0.101.22 ± 0.104.00 ± 0.101.00 + 0.25
0.088 ± 0.0040.092 ± 0.0040.048 ± 0.0040.157 ± 0.0040.039 + 0.010
CAVITY
DIAMETERPITCHPOSITION
DP0E
1.55 ± 0.054.00 ± 0.101.75 ± 0.10
0.061 ± 0.0020.157 ± 0.0040.069 ± 0.004
PERFORATION
WIDTHTHICKNESS
Wt1
8.00 ± 0.300.255 ± 0.013
0.315 ± 0.0120.010 ± 0.0005
CARRIER TAPE
CAVITY TO PERFORATION(WIDTH DIRECTION)
CAVITY TO PERFORATION(LENGTH DIRECTION)
F
P2
3.50 ± 0.05
2.00 ± 0.05
0.138 ± 0.002
0.079 ± 0.002
DISTANCE
WIDTHTAPE THICKNESS
CTt
5.4 ± 0.100.062 ± 0.001
0.205 ± 0.0040.0025 ± 0.00004
COVER TAPE
USERFEED DIRECTION
COVER TAPE
CARRIERTAPE
REEL END VIEW
8 mm
4 mm
TOP VIEW
83x 83x 83x 83x
www.semiconductor.agilent.com
Data subject to change.Copyright © 1999 Agilent TechnologiesObsoletes 5966-1730E5968-6307E (11/99)
This datasheet has been downloaded from:
www.DatasheetCatalog.com
Datasheets for electronic components.
