2012 49th ACM/EDAC/IEEE Design Automation Conference (DAC …toc.proceedings.com/15388webtoc.pdf · 2012. 8. 10. · San Francisco, California, USA 3-7 June 2012 IEEE Catalog Number:

IEEE Catalog Number: ISBN:

CFP12DAC-PRT 978-1-4503-1199-1

2012 49th ACM/EDAC/IEEE Design Automation Conference (DAC 2012)

San Francisco, California, USA 3-7 June 2012

Pages 1-677

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General Chair's Message

Proceedings of the 49th Automation Conference®

Committees

Executive CommitteeTechnical Program CommitteePanel CommitteesIndustry Liaison CommitteeStrategy CommitteeUser Track CommitteePR/Marketing CommitteeBest Paper Award CommitteeSpecial Session OrganizersTechnical Panel OrganizersPavilion Panel Contributors

Tuesday Keynote Address

Wednesday Keynote Address

Thursday Keynote

Perspective Paper Abstracts

Technical Panel Abstracts

Awards

Marie R. Pistilli Women in EDA Achievement AwardThe P. O. Pistilli Undergraduate Scholarships for Advancement in Computer Science andElectrical EngineeringA. Richard Newton Graduate ScholarshipsACM/IEEE A. Richard Newton Technical Impact Award in Electronic Design Automation2011 Phil Kaufman Award for Distinguished Contributions to EDAIEEE CEDA Outstanding Service ContributionDonald O. Pederson Best Paper Award for the IEEE Transaction on CADSIGDA Outstanding New Faculty AwardACM/SIGDA Outstanding Ph.D. Dissertation AwardIEEE FellowIEEE FellowIEEE Fellow49th DAC Best Paper Candidates

Reviewers

Author Index

Session 2: E-Health: A Killer Application for ElectronicDevices?

Chair: Rajesh Gupta (Univ. of California at San Diego)

Biomedical Electronics Serving as Physical Environmental and Emotional Watchdogs

Table of Contents file:///L:/JOBS/51490 IEEE DAC/51490 CD/HTML/data/toc.htm

1 of 24 5/17/2012 3:28 PM

2.1 1

2.2 6

2.3 12

3.1 18

3.2 26

3.3 36

3.4 42

4.1 48

4.2 56

4.3 62

Rudy Lauwereins (IMEC)

Integrated Biosensors for Personalized Medicine

Giovanni De Micheli, Cristina Boero, Camilla Baj-Rossi, Irene Taurino, SandroCarrara (Ecole Polytechnique Fédérale de Lausanne)

Design Challenges for Secure Implantable Medical Devices

Shane Clark, Ben Ransford (Univ. of Massachusetts, Amherst); WayneBurleson, Kevin Fu (Univ. of Massachusetts, Amherst)

Session 3: Design Automation for Things Wet, Small, Spooky, and Tamable

Chair: Tsung-Yi Ho (National Cheng Kung Univ.)

Design of Pin-Constrained General-Purpose Digital Microfluidic Biochips

Yan Luo, Krishnendu Chakrabarty (Duke Univ.)

Path Scheduling on Digital Microfluidic Biochips

Daniel Grissom, Philip Brisk (Univ. of California, Riverside)

Realizing Reversible Circuits Using a New Class of Quantum Gates

Robert Wille (Univ. of Bremen); D. Michael Miller, Zahra Sasanian (Univ. ofVictoria)

Physical Synthesis onto a Sea-of-Tiles with Double-Gate Silicon NanowireTransistors

Shashikanth Bobba, Michele De Marchi, Yusuf Leblebici, Giovanni De Micheli(Ecole Polytechnique Fédérale de Lausanne)

Session 4: Be Efficient: Low-Power Design TechniquesChair: Hamid Mahmoodi (San Francisco State Univ.)

A Semiempirical Model for Wakeup Time Estimation in Power-Gated LogicClusters

Vivek D. Tovinakere, Olivier Sentieys, Steven Derrien (Univ. de Rennes 1)

Cost-Effective Power Delivery to Support Per-Core Voltage Domains forPower-Constrained Processors

Michael J. Schulte (Advanced Micro Devices, Inc.); Abhishek A. Sinkar, HamidReza Ghasemi, Nam Sung Kim (Univ. of Wisconsin, Madison)

A Hybrid and Adaptive Model for Predicting Register File and SRAM PowerUsing a Reference Design

Eric Donkoh, Alicia Lowery, Emily Shriver (Intel Corp.)


2 of 24 5/17/2012 3:28 PM

4.4 68

5.1 77

5.2 83

5.3 90

5.4 96

6.1 106

6.2 115

6.3 121

Coding-Based Energy Minimization for Phase Change Memory

Azalia Mirhoseini (Rice Univ.); Miodrag Potkonjak (Univ. of California, LosAngeles); Farinaz Koushanfar (Rice Univ.)

Session 5: Design and Data Security: Is It Even Possible?Chair: Mohammad Tehranipoor (Univ. of Connecticut)

A Code Morphing Methodology to Automate Power AnalysisCountermeasures

Giovanni Agosta, Alessandro Barenghi, Gerardo Pelosi (Politecnico di Milano)

Security Analysis of Logic Obfuscation

Youngok Pino (Air Force Research Lab); Ozgur Sinanoglu (New York Univ.);Jeyavijayan Rajendran, Ramesh Karri (Polytechnic Institute of New YorkUniv.)

Hardware Trojan Horse Benchmark via Optimal Creation and Placement ofMalicious Circuitry

Sheng Wei (Univ. of California, Los Angeles); Kai Li, Farinaz Koushanfar (RiceUniv.); Miodrag Potkonjak (Univ. of California, Los Angeles)

On Improving the Uniqueness of Silicon-Based Physically UnclonableFunctions via Optical Proximity Correction

Domenic Forte, Ankur Srivastava (Univ. of Maryland)

Session 6: System Simulation: The Need for Speed!Chair: Gunar Schirner (Northeastern Univ.)

Transformer: A Functional-Driven Cycle-Accurate Multicore Simulator

Qinghao Min, Weihua Zhang, Binyu Zang (Fudan Univ.); Jian Li (IBM Corp.);Haibo Chen (Shanghai Jiao Tong Univ.); Zhenman Fang, Keyong Zhou, Yi Lu,Yibin Hu (Fudan Univ.)

SAGA: SystemC Acceleration on GPU Architectures

Sara Vinco (Univ. of Verona); Debapriya Chatterjee, Valeria Bertacco (Univ.of Michigan); Franco Fummi (Univ. of Verona)

Synchronization for Hybrid MPSoC Full-System Simulation

Juan Eusse, Gerd Ascheid, Rainer Leupers, Jovana Jovic, Luis Gabriel Murillo,Sergey Yakoushkin (RWTH Aachen Univ.)


3 of 24 5/17/2012 3:28 PM

6.4 127

8.1 133

9.1 139

9.2 145

9.3 151

9.4 157

10.1 163

10.2 169

A Non-Intrusive Timing Synchronization Interface for Hardware-AssistedHW/SW Co-Simulation

Yu-Hung Huang, Yi-Shan Lu, Hsin-I Wu, Ren-Song Tsay (National Tsing HuaUniv.)

Session 8: Can EDA Combat the Rise of ElectronicCounterfeiting?

Chair: Miodrag Potkonjak (Univ. of California, Los Angeles)

Can EDA Combat the Rise of Electronic Counterfeiting?

Carl McCants (Defense Advanced Research Projects Agency); William Bryson(Analytical Solutions, Inc.); Matthew Sale (U.S. Naval Surface WarfareCenter); Saverio Fazzari (Booz Allen Hamilton, Inc.); Farinaz Koushanfar(Rice Univ.); Miodrag Potkonjak (Univ. of California, Los Angeles); PeilinSong (IBM Research)

Session 9: Reliability: From Atoms to 3-DChair: Angan Das (Intel Corp.)

Physics Matters: Statistical Aging Prediction under Trapping/Detrapping

Jyothi Bhaskarr Velamala, Ketul Sutaria (Arizona State Univ.); Takashi Sato(Kyoto Univ.); Yu Cao (Arizona State Univ.)

Library-Aware Resonant Clock Synthesis (LARCS)

Xuchu Hu (Cadence Design Systems, Inc., Univ. of California, Santa Cruz);Walter Condley, Matthew Guthaus (Univ. of California, Santa Cruz)

Incremental Power Grid Verification

Farid N. Najm, Abhishek (Univ. of Toronto)

Analysis of DC Current Crowding in Through-Silicon-Vias and its Impact onPower Integrity in 3-D ICs

Sung Kyu Lim, Xin Zhao (Georgia Institute of Technology); MichaelScheuermann (IBM T.J. Watson Research Ctr.)

Session 10: EDA for Emerging Applications at the Kilometer,Meter, Micron, and Nanometer Scales

Chair: Sai-Wang (Rocco) Tam (Marvell Semiconductor, Inc.)

Tracking Appliance Usage Information in Residential Settings UsingOff-the-Shelf Low-Frequency Meters

Deokwoo Jung (Advanced Digital Sciences Center); Andreas Savvides (YaleUniv.); Athanasios Bamis (Univ. of Connecticut)

Implementing an FPGA System for Real-Time Intent Recognition forProsthetic Legs


4 of 24 5/17/2012 3:28 PM

10.3 176

10.4 182

11.1 188

11.2 197

11.3 205

11.4 214

11.5 220

12.1 229

Xiaorong Zhang, He Huang, Qing Yang (Univ. of Rhode Island)

Statistical Design and Optimization for Adaptive Post-silicon Tuning ofMEMS Filters

Fa Wang, Gary Fedder, Larry Pileggi, Tamal Mukherjee, Jonathan Rotner, XinLi, Gokce Keskin, Andrew Phelps (Carnegie Mellon Univ.)

Generic Low-Cost Characterization of VTH and Mobility Variations in LTPSTFTs for Non-Uniformity Calibration of Active-Matrix OLED Displays

Reza Chaji, Javid Jaffari (IGNIS Innovations, Inc.)

Session 11: Facing Dependability: System-Level Solutionsand Cybercar Challenges

Chair: Hans-Joachim Wunderlich (Univ. of Stuttgart)

Towards Fault-Tolerant Embedded Systems with Imperfect Fault Detection

Jia Huang, Kai Huang, Andreas Raabe, Christian Buckl (fortiss GmbH); AloisKnoll (Technische Univ. München)

Steady-State Dynamic Temperature Analysis and Reliability Optimizationfor Embedded Multiprocessor Systems

Ivan Ukhov, Zebo Peng, Min Bao, Petru Eles (Linköping Univ.)

Considering Diagnosis Functionality during Automatic System-LevelDesign of Automotive Networks

Michael Eberl, Michael Glass, Jürgen Teich (Univ. of Erlangen-Nuremberg);Ulrich Abelein (Audi AG)

Meta-Cure: A Reliability Enhancement Strategy for Metadata in NANDFlash Memory Storage Systems

Zili Shao, Yi Wang (The Hong Kong Polytechnic Univ.); Luis Angel Bathen,Nikil Dutt (Univ. of California, Irvine)

EDA for Secure and Dependable Cybercars: Challenges and Opportunities

Hervé Seudié, Ahmad-Reza Sadeghi (Fraunhofer SIT, and Intel-TU DarmstadtSecurity Institute, Germany); Farinaz Koushanfar (Rice University)

Session 12: Volatile or Non-Volatile? That's the QuestionChair: Tei-Wei Kuo (National Taiwan Univ.)

Software Controlled Cell Bit-Density to Improve NAND Flash Lifetime

Xavier Jimenez, David Novo, Paolo Ienne (Ecole Polytechnique Fédérale deLausanne)

Observational Wear Leveling: An Efficient Algorithm for Flash Memory Management


5 of 24 5/17/2012 3:28 PM

12.2 235

12.3 243

12.4 253

14.1 259

14.2 265

14.3 271

14.4 277

15.1 283

Chundong Wang, Weng-Fai Wong (National Univ. of Singapore)

Cache Revive: Architecting Volatile STT-RAM Caches for EnhancedPerformance in CMPs

Yuan Xie, Chita R. Das, Vijaykrishnan Narayanan, Cong Xu (PennsylvaniaState Univ.); Asit K. Mishra (Intel Corp.); Adwait Jog (Pennsylvania StateUniv.); Ravishankar Iyer (Intel Corp.)

Point and Discard: A Hard-Error-Tolerant Architecture for Non-Volatile LastLevel Caches

Jue Wang, Xiangyu Dong, Yuan Xie (Pennsylvania State Univ.)

Session 14: Self-Aware and Adaptive Technologies: TheFuture of Computing Systems?

Chair: Xiaoyun Zhu (VMware, Inc.)

Self-Aware Computing in the Angstrom Processor

Martina Maggio (Lund Univ.); Anantha Chandrakasan, Anant Agarwal, YildizSinangil, Mahmut Sinangil, Srini Devadas, Eric Lau, George Kurian(Massachusetts Institute of Technology); Jim Holt (Massachusetts Institute ofTechnology, Freescale Semiconductor, Inc.); Henry Hoffman, SabrinaNeuman, Jason Miller (Massachusetts Institute of Technology)

The Case for Elastic Operating System Services in fos

Charles Gruenwald (Massachusetts Institute of Technology); David Wentzlaff(Princeton Univ.); Harshad Kasture, Nathan Beckmann (MassachusettsInstitute of Technology); Lamia Youseff (Google, Inc.); Anant Agarwal(Massachusetts Institute of Technology)

A Compiler and Runtime for Heterogeneous Computing

Joshua Auerbach, David Bacon, Ioana Burcea, Perry Cheng, Stephen Fink,Rodric Rabbah, Sunil Shukla (IBM T.J. Watson Research Ctr.)

The Helix Project: Overview and Directions

Gu-Yeon Wei, David Brooks, Glenn Holloway, Simone Campanoni (HarvardUniv.); Timothy Jones (Univ. of Cambridge)

Session 15: Why Model? Because Reality is ComplicatedEnough!

Chair: Ibrahim Elfadel (Masdar Institute of Science and Technology)

Exploring Sub-20nm FinFET Design with Predictive Technology Models

Saurabh Sinha, Greg Yeric, Vikas Chandra, Brian Cline (ARM, Inc.); Yu Cao(Arizona State Univ.)


6 of 24 5/17/2012 3:28 PM

15.2 289

15.3 295

15.4 301

15.5 311

15.6 317

16.1 327

16.2 334

16.3 344

16.4 350

Fast Nonlinear Model Order Reduction via Associated Transforms ofHigh-Order Volterra Transfer Functions

Neric Fong, Ngai Wong, Qing Wang, Haotian Liu, Yang Zhang (The Univ. ofHong Kong)

AMOR: An Efficient Aggregating Based Model Order Reduction Method forMany-Terminal Interconnect Circuits

Fan Yang, Xuan Zeng, Yangfeng Su (Fudan Univ.)

BLAST: Efficient Computation of Nonlinear Delay Sensitivities in Electronicand Biological Networks using Barycentric Lagrange Enabled Transient AdjointAnalysis

Arie Meir, Jaijeet Roychowdhurry (Univ. of California, Berkeley)

DAE2FSM: Automatic Generation of Accurate Discrete-Time LogicalAbstractions for Continuous-Time Circuit Dynamics

Karthik Aadithya, Jaijeet Roychowdhury (Univ. of California, Berkeley)

Chip/Package Co-Analysis of Thermo-Mechanical Stress and Reliability inTSV-based 3-D ICs

Moongon Jung (Georgia Institute of Technology); David Pan (Univ. of Texas,Austin); Sung Kyu Lim (Georgia Institute of Technology)

Session 16: Is Formal Verification Ready for the SystemLevel?

Chair: Erik Seligman (Intel Corp.)

Symbolic Model Checking on SystemC Designs

Chiao Hsieh, Yen-Sheng Ho, Chun-Nan Chou, Chung-Yang (Ric) Huang(National Taiwan Univ.)

System Verification of Concurrent RTL Modules by Compositional PathPredicate Abstraction

Joakim Urdahl, Dominik Stoffel, Markus Wedler, Wolfgang Kunz (Univ. ofKaiserslautern)

Equivalence Checking for Behaviorally Synthesized Pipelines

Kecheng Hao (Portland State Univ.); Sandip Ray (Univ. of Texas, Austin); FeiXie (Portland State Univ.)

Proving Correctness of Regular Expression Accelerators

Christoph Hagleitner, Mitra Purandare, Kubilay Atasu (IBM Research - Zurich)

Sciduction: Combining Induction, Deduction, and Structure for Verification and


7 of 24 5/17/2012 3:28 PM

16.5 356

17.1 366

17.2 376

17.3 382

17.4 392

17.5 398

17.6 406

18.1 412

18.2 421

Synthesis

Sanjit Seshia (Univ. of California, Berkeley)

Session 17: NoCs Next Top Model: From System-Level toPrototype

Chair: Fabien Clermidy (CEA-LETI)

Cost-Efficient Buffer Sizing in Shared-Memory 3-D MPSoCs using Wide I/OInterfaces

Abbas Sheibanyrad (TIMA Laboratory/CNRS); Frédéric Pétrot, Sahar Foroutan(TIMA Laboratory, Grenoble Institute of Technology)

Attackboard: A Novel Dependency-Aware Traffic Generator for ExploringNoC Design Space

Yoshi Shih-Chieh Huang, Yu-Chi Chang, Tsung-Chan Tsai, Yuan-Ying Chang,Chung-Ta King (National Tsing Hua Univ.)

Towards Graceful Aging Degradation in NoCs Through an Adaptive RoutingAlgorithum

Sanghamitra Roy, Kshitij Bhardwaj, Koushik Chakraborty (Utah State Univ.)

Explicit Modeling of Control and Data for Improved NoC Router Estimation

Siddhartha Nath, Bill Lin, Andrew B. Kahng (Univ. of California at San Diego)

Approaching the Theoretical Limits of a Mesh NoC with a 16-Node ChipPrototype in 45nm SOI

Sunghyun Park, Tushar Krishna, Chia-Hsin O. Chen, Bhavya Daya, Li-ShiuanPeh, Anantha P. Chandrakasan (Massachusetts Institute of Technology)

High Radix Self-Arbitrating Switch Fabric with Multiple ArbitrationSchemes and Quality of Service

Trevor Mudge, Dennis Sylvester, Ronald Dreslinski, Reetuparna Das, SudhirSatpathy, David Blaauw (Univ. of Michigan)

Session 18: Timing Analysis and Software-ControlledMemory: Are We Safe?

Chair: Frank Slomka (Univ. of Ulm)

WCET-Centric Partial Instruction Cache Locking

Huping Ding (National Univ. of Singapore); Yun Liang (Advanced DigitalSciences Center); Tulika Mitra (National Univ. of Singapore)

Worst-Case Execution Time Analysis for Parallel Run-Time Monitoring

Daniel Lo, G. Edward Suh (Cornell Univ.)


8 of 24 5/17/2012 3:28 PM

18.3 430

18.4 437

18.5 447

18.6 453

20.1 459

20.2 465

20.3 471

21.1 476

Conforming the Runtime Inputs for Hard Real-Time Embedded Systems

Kai Huang, Gang Chen, Christian Buckl (fortiss GmbH); Alois Knoll(Technische Univ. München)

STM Concurrency Control for Embedded Real-Time Software with TighterTime Bounds

Mohammed El-Shambakey, Binoy Ravindran (Virginia Polytechnic Institute andState Univ.)

HaVOC: A Hybrid-Memory-Aware Virtualization Layer for On-ChipDistributed ScratchPad and Non-Volatile Memories

Nikil Dutt, Luis Angel Bathen (Univ. of California, Irvine)

Age-Based PCM Wear Leveling with Nearly Zero Search Cost

Chi-Hao Chen (National Taiwan Univ.); Pi-Cheng Hsiu (Academia Sinica);Tei-Wei Kuo (National Taiwan Univ., Academia Sinica); Chia-Lin Yang(National Taiwan Univ.); Cheng-Yuan Michael Wang (Macronix InternationalCo., Ltd.)

Session 20: Routing-Driven Design ClosureChair: Shankar Krishnamoorthy (Mentor Graphics Corp.)

Algorithms and Data Structures for Fast and Good VLSI Routing

Christian Schulte, Jens Vygen, Christian Panten, Tim Nieberg, Dirk Mueller,Michael Gester (Univ. of Bonn)

Guiding a Physical Design Closure System to Produce Easier-to-RouteDesigns with More Predictable Timing

Charles Alpert (IBM Corp.); Gi-Joon Nam (IBM Research - Austin); NatarajanViswanathan (IBM Systems and Technology Group); Cliff Sze (IBM Research- Austin); Nancy Zhou (IBM Systems and Technology Group); Zhuo Li (IBMResearch - Austin)

Rule Agnostic Routing by Using Design Fabrics

Gyuszi Suto (Intel Corp.)

Session 21: Storing, Computing, and Storing WhileComputing: The New Face of Non-Volatility in Systems

Chair: Charles Augustine (Intel Corp.)

Making Non-Volatile Nanomagnet Logic Non-Volatile

Michael Niemier, Peng Li, Gary Bernstein, Vijay Karthik Sankar, WolfgangPorod, Xiaobo Sharon Hu, Steve Kurtz, Aaron Dingler, Gyorgy Csaba, JosephNahas (Univ. of Notre Dame)


9 of 24 5/17/2012 3:28 PM

21.2 486

21.3 492

21.4 498

22.1 504

22.2 510

22.3 516

22.4 522

23.1 529

mLogic: Ultra-Low Voltage Non-Volatile Logic Circuits Using STT-MTJDevices

Daniel Morris, David Bromberg, Jian-Gang (Jimmy) Zhu, Larry Pileggi(Carnegie Mellon Univ.)

Future Cache Design using STT MRAMs for Improved Energy Efficiency:Devices, Circuits and Architecture

Sumeet Kumar Gupta, Kaushik Roy, Niladri Narayan Mojumder, Sang PhillPark, Anand Raghunathan (Purdue Univ.)

Hardware Realization of BSB Recall Function with Memristor CrossbarArrays

Miao Hu, Hai Li (Polytechnic Institute of New York Univ.); Qing Wu, GarrettS. Rose (Air Force Research Lab)

Session 22: You Can Count on Me: Why it's OK to beImprecise or Unreliable

Chair: Qinru Qiu (Syracuse Univ.)

A Methodology for Energy-Quality Tradeoff Using Imprecise Hardware

Gabriel Robins, Jiawei Huang, John Lach (Univ. of Virginia)

On the Exploitation of the Inherent Error Resilience of Wireless Systemsunder Unreliable Silicon

Andreas Burg (Ecole Polytechnique Fédérale de Lausanne); ChristianBenkeser, Christoph Roth (Eidgenössische Technische Hochschule Zürich);Georgios Karakonstantis (Ecole Polytechnique Fédérale de Lausanne)

Near-Optimal, Dynamic Module Reconfiguration in a Photovoltaic Systemto Combat Partial Shading Effects

Xue Lin, Yanzhi Wang, Siyu Yue (Univ. of Southern California); DonghwaShin, Naehyuck Chang (Seoul National Univ.); Massoud Pedram (Univ. ofSouthern California, Los Angeles)

Networked Architecture for Hybrid Electrical Energy Storage Systems

Qing Xie, Massoud Pedram, Yanzhi Wang (Univ. of Southern California);Sangyoung Park, Younghyun Kim, Naehyuck Chang (Seoul National Univ.)

Session 23: Optimization to the Rescue of AnalogChair: Trent McConaghy (Solido Design Automation, Inc.)

A New Uncertainty Budgeting Based Method for Robust Analog/Mixed-Signal Design

Jin Sun (Orora Design Technologies, Inc.); Priyank Gupta (Cirrus Logic,Inc.); Janet Roveda (Univ. of Arizona)


10 of 24 5/17/2012 3:28 PM

23.2 536

23.3 542

23.4 549

24.1 555

24.2 561

24.3 567

24.4 573

26.2 579

26.3 585

Variability-Aware, Discrete Optimization for Analog Circuits

Seobin Jung, Yunju Choi, Jaeha Kim (Seoul National Univ.)

Efficient Multi-Objective Synthesis for Microwave Components Based onComputational Intelligence Techniques

Soheil Radiom, Guy A. E. Vandenbosch, Hadi Aliakbarian, Bo Liu, GeorgesGielen (Katholieke Univ. Leuven)

Non-Uniform Multilevel Analog Routing with Matching Constraints

Hung-Chih Ou, Hsing-Chih Chang Chien, Yao-Wen Chang (National TaiwanUniv.)

Session 24: Xterminating BugsChair: Sharad Kumar (Freescale Semiconductor, Inc.)

X-Tracer: A Reconfigurable X-Tolerant Trace Compressor for Silicon Debug

Feng Yuan, Xiao Liu, Qiang Xu (The Chinese Univ. of Hong Kong)

Quick Detection of Difficult Bugs for Effective Post-Silicon Validation

Farzan Fallah (Stanford Univ.); Nagib Hakim (Intel Corp.); Ted Hong, DavidLin, Subhasish Mitra (Stanford Univ.)

Test Data Volume Optimization for Diagnosis

Hongfei Wang, Osei Poku, Xiaochun Yu, Sizhe Liu, Ibrahima Komara, ShawnBlanton (Carnegie Mellon Univ.)

Invariance-Based Concurrent Error Detection for Advanced EncryptionStandard

Xiaofei Guo, Ramesh Karri (Polytechnic Institute of New York Univ.)

Session 26: Brain-Inspired Autonomous Computing andModeling

Chair: Yiran Chen (Univ. of Pittsburgh)

Accelerating Neuromorphic Vision Algorithms for Recognition

Matthew Cotter (Pennsylvania State Univ.); Chaitali Chakrabarti (ArizonaState Univ.); Vijaykrishnan Narayanan, Michael DeBole, Ahmed Al Maashri,Nandhini Chandramoorthy, Yang Xiao (Pennsylvania State Univ.)

Statistical Memristor Modeling and Case Study in Neuromorphic Computing

Robinson Pino (Air Force Research Lab); Hai Li (Polytechnic Institute of NewYork Univ.); Yiran Chen (Univ. of Pittsburgh); Miao Hu (Polytechnic Instituteof New York Univ.); Beiye Liu (Univ. of Pittsburgh)


11 of 24 5/17/2012 3:28 PM

27.1 591

27.2 597

27.3 603

27.4 613

27.5 623

28.1 630

28.2 636

28.3 642

Session 27: Design, the Next Generation: From Routing toCapturing Design Expertise

Chair: Charles Chiang (Synopsys, Inc.)

Triple Patterning Aware Routing and its Comparison with DoublePatterning Aware Routing in 14nm Technology

Martin D. F. Wong, Qiang Ma, Hongbo Zhang (Univ. of Illinois at Urbana-Champaign)

GDRouter: Interleaved Global Routing and Detailed Routing for UltimateRoutability

Yanheng Zhang (Cadence Design Systems, Inc.); Chris Chu (Iowa StateUniv.)

Standard Cell Routing via Boolean Satisfiability

Nikolai Ryzhenko, Steven Burns (Intel Corp.)

An Efficient Algorithm for Multi-Layer Obstacle-Avoiding RectilinearSteiner Tree Construction

Chih-Hung Liu, I-Che Chen (Academia Sinica); Der-Tsai Lee (NationalChung-Hsing Univ.)

Avoiding Game Over: Bringing Design to the Next Level

Sameh Galal, Stephen Richardson, Artem Vassilliev, SabarishSankaranarayanan, Mark Horowitz, Andrew Danowitz, Megan Wachs, OferShacham, John Brunhaver, Wajahat Qadeer (Stanford Univ.)

Session 28: Staying Cool: Modeling Thermal Effects in 3-Dand Multicore

Chair: Dhireesha Kudithipudi (Rochester Institute of Technology)

PowerField: A Transient Temperature-to-Power Technique based onMarkov Random Field Theory

Seungwook Paek (KAIST); Seok-Hwan Moon (Electronics andTelecommunications Research Institute); Wongyu Shin, Jaehyeong Sim,Lee-Sup Kim (KAIST)

EigenMaps: Algorithms for Optimal Thermal Maps Extraction and SensorPlacement on Multicore Processors

Juri Ranieri, Martin Vetterli, David Atienza, Alessandro Vincenzi, AminaChebira (Ecole Polytechnique Fédérale de Lausanne)

An Information-theoretic Framework for Optimal Temperature SensorAllocation and Full-chip Thermal Monitoring

Huapeng Zhou, Xin Li (Carnegie Mellon Univ.); Chen-Yong Cher, Eren Kursun,Haifeng Qian (IBM T.J. Watson Research Ctr.); Shi-Chune Yao (Carnegie


12 of 24 5/17/2012 3:28 PM

28.4 648

29.1 656

29.2 664

29.3 672

29.4 678

30.1 688

30.2 697

30.3 703

Mellon Univ.)

Optimizing Energy Efficiency of 3-D Multicore Systems with Stacked DRAMunder Power and Thermal Constraints

Ayse Coskun, Jie Meng, Katsutoshi Kawakami (Boston Univ.)

Session 29: SOS: Specification, Optimization, and Synthesisin System-Level Design

Chair: Brett Meyer (McGill Univ.)

Static Dataflow with Access Patterns: Semantics and Analysis

Arkadeb Ghosal, Rhishikesh Limaye, Kaushik Ravindran (National InstrumentsCorp.); Stavros Tripakis (Univ. of California, Berkeley); Ankita Prasad,Guoqiang Wang, Trung N. Tran, Hugo A. Andrade (National InstrumentsCorp.)

Executing Synchronous Dataflow Graphs on a SPM-Based MulticoreArchitecture

Hyunok Oh (Hanyang Univ.); Sungchan Kim (Chonbuk National Univ.);Junchul Choi, Soonhoi Ha (Seoul National Univ.)

System-Level Synthesis of Memory Architecture for Stream ProcessingSub-Systems of a MPSoC

Glenn Leary, Weijia Che, Karam S. Chatha (Arizona State Univ.)

Courteous Cache Sharing: Being Nice to Others in Capacity Management

Akbar Sharifi, Shekhar Srikantaiah, Mahmut Kandemir, Mary Jane Irwin(Pennsylvania State Univ.)

Session 30: Future of IC ReliabilityChair: Alesandro Pinto (United Technologies Research Center)

A Hybrid Approach to Cyber-Physical Systems Verification

Samarjit Chakraborty (Technische Univ. München); Anuradha Annaswamy(Massachusetts Institute of Technology); Lothar Thiele (EidgenössischeTechnische Hochschule Zürich); Dip Goswami (Technische Univ. München);Pratyush Kumar, Kai Lampka (Eidgenössische Technische Hochschule Zürich)

Reliable Computing with Ultra-Reduced Instruction Set Co-Processors

Aravindkumar Rajendiran, Sundaram Ananthanarayanan, Hiren Patel, MaheshTripunitara, Siddharth Garg (Univ. of Waterloo)

Identification of Recovered ICs using Fingerprints from a Light-WeightOn-Chip Sensor

Xuehui Zhang, Nicholas Tuzzio, Mohammad Tehranipoor (Univ. of


13 of 24 5/17/2012 3:28 PM

30.4 709

32.1 717

32.2 723

32.3 729

32.4 734

33.1 741

33.2 747

33.3 756

33.4 762

33.5 768

Connecticut)

Confidentiality Preserving Integer Programming for Global Routing

Hamid Shojaei, Azadeh Davoodi, Parameswaran Ramanathan (Univ. ofWisconsin)

Session 32: Breaking out of EDA: How to Apply EDATechniques to Broader Applications

Chair: Jason Cong (Univ. of California, Los Angeles)

Design Tools for Artificial Nervous Systems

Louis K. Scheffer (Howard Hughes Medical Institute)

Dynamic River Network Simulation at Large Scale

Frank Liu (IBM Research - Austin); Ben R. Hodges (Univ. of Texas, Austin)

Humans for EDA and EDA for Humans

Valeria Bertacco (Univ. of Michigan)

Application of Logic Synthesis to the Understanding and Cure of GeneticDiseases

Pey-Chang Kent Lin, Sunil Khatri (Texas A&M Univ.)

Session 33: The Right Placement at the Right TimingChair: Saurabh Adya (Magma Design Automation, Inc.)

Exploiting Die-to-Die Thermal Coupling in 3D IC Placement

Krit Athikulwongse, Mohit Pathak, Sung Kyu Lim (Georgia Institute ofTechnology)

ComPLx: A Competitive Primal-Dual Lagrange Optimization for GlobalPlacement

Myung-Chul Kim, Igor Markov (Univ. of Michigan)

PADE: A High-Performance Placer with Automatic Datapath Extraction andEvaluation through High-Dimensional Data Learning

Samuel Ward, Duo Ding, David Pan (Univ. of Texas, Austin)

Structure-Aware Placement for Datapath Intensive Circuit Designs

Sheng Chou, Meng-Kai Hsu, Yao-Wen Chang (National Taiwan Univ.)

GLARE: Global and Local Wiring Aware Routability Evaluation

Charles J. Alpert (IBM Austin Research Lab); Sachin S. Sapatnekar(University of Minnesota); Douglas Keller, Gustavo E. Tellez, Lakshmi Reddy


14 of 24 5/17/2012 3:28 PM

33.6 774

34.1 783

34.2 790

34.3 796

34.4 802

34.5 808

34.6 814

35.1 820

(IBM Systems and Technology Group); Zhuo Li (IBM Austin Research Lab);Natarajan Viswanathan (IBM Systems and Technology Group); Cliff Sze (IBMAustin Research Lab); Yaoguang Wei (University of Minnesota); Andrew D.Huber (IBM Systems and Technology Group)

The DAC 2012 Routability-Driven Placement Contest and Benchmark Suite

Natarajan Viswanathan, Charles Alpert, Cliff Sze, Zhuo Li, Yaoguang Wei(IBM Corp.)

Session 34: Global Views of Synthesis: Broadening theScope

Chair: Herman Schmit (Altera Corp.)

Removing Overhead from High-Level Interfaces

Megan Wachs, Mark Horowitz, Kyle Kelley, Stephen Richardson, JohnStevenson (Stanford Univ.)

On the Asymptotic Costs of Multiplexer-Based Reconfigurability

Johnathan York, Derek Chiou (Univ. of Texas, Austin)

SALSA: Systematic Logic Synthesis of Approximate Circuits

Swagath Venkataramani, Amit Sabne, Vivek Kozhikkottu, Kaushik Roy, AnandRaghunathan (Purdue Univ.)

Timing ECO Optimization Using Metal-Configurable Gate-Array Spare Cells

Iris Hui-Ru Jiang (National Chiao Tung Univ.); Yao-Wen Chang, Hua-Yu Chang(National Taiwan Univ.)

Early Prediction of NBTI Effects Using RTL Source Code Analysis

Kenneth Butler (Texas Instruments, Inc.); Heesoo Kim, Shobha Vasudevan,Jayanand Asok Kumar (Univ. of Illinois at Urbana-Champaign)

Generalized SAT-Sweeping for Post-Mapping Optimization

Tobias Welp (Univ. of California, Berkeley); Smita Krishnaswamy (ColumbiaUniv.); Andreas Kuehlmann (Coverity, Inc.)

Session 35: Adaptive Computing: When, Where, Why, How?Chair: Philip Brisk (Univ. of California, Riverside)

Accuracy-Configurable Adder for Approximate Arithmetic Designs

Andrew B. Kahng, Seokhyeong Kang (Univ. of California at San Diego)


15 of 24 5/17/2012 3:28 PM

35.2 826

35.3 834

35.4 843

35.5 850

35.6 856

36.1 866

36.2 876

36.3 882

Recovery-Based Design for Variation-Tolerant SoCs

Anand Raghunathan (Purdue Univ.); Sujit Dey (Univ. of California at SanDiego); Vivek Kozhikkottu (Purdue Univ.)

A Hybrid NoC Design for Cache Coherence Optimization for ChipMultiprocessors

Ohyoung Jang, Wei Ding, Yuanrui Zhang, Mahmut Kandemir, Mary Jane Irwin,Hui Zhao (Pennsylvania State Univ.)

Architecture Support for Accelerator-Rich CMPs

Jason Cong, Mohammad Ali Ghodrat, Michael Gill, Beayna Grigorian, GlennReinman (Univ. of California, Los Angeles)

A QoS-Aware Memory Controller for Dynamically Balancing GPU and CPUBandwidth Use in an MPSoC

Min Kyu Jeong (Univ. of Texas, Austin); Nigel Paver (ARM, Inc.); Mattan Erez(Univ. of Texas, Austin); Chander Sudanthi (ARM, Inc.)

Metronome: Operating System Level Performance Management viaSelf-Adaptive Computing

Filippo Sironi, Davide Basilio Bartolini (Politecnico di Milano); SimoneCampanoni (Harvard Univ.); Fabio Cancaré (Politecnico di Milano); HenryHoffmann (Massachusetts Institute of Technology); Donatella Sciuto, MarcoSantambrogio (Politecnico di Milano)

Session 36: Yin and Yang of Memories: The Power-Performance Trade-Off

Chair: Yiran Chen (Univ. of Pittsburgh)

Adaptive Power Management of On-Chip Video Memory for MultiviewVideo Coding

Muhammad Shafique, Joerg Henkel (Karlsruhe Institute of Technology);Sergio Bampi (Univ. Federal do Rio Grande do Sul); Bruno Zatt (KarlsruheInstitute of Technology); Fábio Leandro Walter (Univ. Federal do Rio Grandedo Sul)

Heterogeneous Multi-Channel: Fine-Grained DRAM Control for Both SystemPerformance and Power Efficiency

Guangfei Zhang (Institute of Computing Tech.); Huandong Wang (LoongsonTechnology Corp., Ltd); Xinke Chen (Institute of Computing Tech.); ShuaiHuang (Loongson Technology Corp., Ltd.); Peng Li (Institute of ComputingTech.)

Joint Management of RAM and Flash Memory with Access PatternConsiderations


16 of 24 5/17/2012 3:28 PM

36.4 888

36.5 897

36.6 907

38.1 913

38.2 918

38.3 924

38.4 930

39.1 936

Po-Chun Huang (National Taiwan Univ.); Yuan-Hao Chang (Academia Sinica);Tei-Wei Kuo (National Taiwan Univ., Academia Sinica)

Hybrid DRAM/PRAM-Based Main Memory for Single-Chip CPU/GPU

Dongki Kim, Sunggu Lee, Sungjoo Yoo (Pohang Univ. of Science andTechnology); Dong Hyuk Woo, DaeHyun Kim (Intel Corp.); Sungkwang Lee(Pohang Univ. of Science and Technology); Jaewoong Chung (Intel Corp.)

Write Performance Improvement by Hiding R Drift Latency in Phase-Change RAM

Youngsik Kim, Sungjoo Yoo, Sunggu Lee (Pohang Univ. of Science andTechnology)

Constructing Large and Fast Multi-Level Cell STT-MRAM Based Cache forEmbedded Processors

Lei Jiang, Jun Yang, Bo Zhao, Youtao Zhang (Univ. of Pittsburgh)

Session 38: Probabilistic Embedded ComputingChair: Vincent Mooney (Georgia Institute of Technology)

Incorrect Systems: It's not the Problem It's the Solution.

Christoph M. Kirsch, Hannes Payer (University of Salzburg)

On Software Design for Stochastic Processors

Joseph Sloan, John Sartori, Rakesh Kumar (Univ. of Illinois at Urbana-Champaign)

What to Do About the End of Moore's Law, Probably!

Krishna Palem (Nanyang Technological Univ., Rice Univ.); AvinashLingamneni (Rice Univ.)

Obtaining and Reasoning About Good Enough Software

Martin Rinard (Massachusetts Institute of Technology)

Session 39: Simulation-Based Verification: New Ways toHarness the Workhorse

Chair: Kerstin Eder (Univ. of Bristol)

Improving Gate-level Simulation Accuracy when Unknowns Exist

Chris Browy, Kai-Hui Chang (Avery Design Systems, Inc.)


17 of 24 5/17/2012 3:28 PM

39.2 941

39.3 947

39.4 955

40.1 962

40.2 968

40.3 974

40.4 980

41.1 988

41.2 994

Automated Feature Localization for Hardware Designs Using CoverageMetrics

Goerschwin Fey (German Aerospace Center); Jan Malburg, Alexander Finder(Univ. of Bremen)

Path Directed Abstraction and Refinement in SAT-Based Design Debugging

Brian Keng, Andreas Veneris (Univ. of Toronto)

Checking Architectural Outputs Instruction-By-Instruction on AccelerationPlatforms

Debapriya Chatterjee (Univ. of Michigan); Anatoly Koyfman, Ronny Morad,Avi Ziv (IBM Haifa Research Lab.); Valeria Bertacco (Univ. of Michigan)

Session 40: Ultra-Low Power Using Subthreshold andNearthreshold Operation

Chair: Mahadev Nemani (Intel Corp.)

Standard Cell Sizing for Subthreshold Operation

Bo Liu, Jose Pineda de Gyvez (Technische Univ. Eindhoven); Jos Huisken,Maryam Ashouei (Holst Centre)

Decoupling Capacitor Design Strategy for Minimizing Supply Noise ofUltra-Low Voltage Circuits

Mingoo Seok (Columbia Univ.)

Regaining Throughput Using Completion Detection for Error-ResilientNear-Threshold Logic

Joseph Crop, Robert Pawlowski, Patrick Chiang (Oregon State Univ.)

Process Variation in Near-Threshold Wide SIMD Architectures

Chaitali Chakrabarti (Arizona State Univ.); Trevor Mudge, Scott Mahlke,Yongjun Park, Mark Woh, Ronald Dreslinski, Sangwon Seo, David Blaauw(Univ. of Michigan)

Session 41: Top Picks of Run-Time Power ManagementTechniques

Chair: Jian-Jia Chen (Karlsruhe Institute of Technology)

Run-Time Power-Down Strategies for Real-Time SDRAM MemoryControllers

Karthik Chandrasekar (Delft Univ. of Technology); Benny Akesson, KeesGoossens (Technische Univ. Eindhoven)

Embedding Statistical Tests for On-Chip Dynamic Voltage and TemperatureMonitoring


18 of 24 5/17/2012 3:28 PM

41.3 1000

41.4 1006

42.1 1012

42.2 1018

42.3 1024

42.4 1031

44.1 1037

44.2 1043

Lionel Vincent (CEA-LETI Minatec); Philippe Maurine (Univ. Montpellier 2);Suzanne Lesecq, Edith Beigne (CEA-LETI Minatec)

Quality-Retaining OLED Dynamic Voltage Scaling for Video StreamingApplications on Mobile Devices

Chun Jason Xue (City Univ. of Hong Kong); Yiran Chen (Univ. of Pittsburgh);Mengying Zhao (City Univ. of Hong Kong); Xiang Chen, Jian Zeng (Univ. ofPittsburgh)

Traffic-Aware Power Optimization for Network Applications on MulticoreServers

Laxmi Bhuyan, Raymond Klefstad, Jilong Kuang (Univ. of California,Riverside)

Session 42: The Dark Side of TestChair: Shreyas Sen (Intel Corp.)

Alternate Hammering Test for Application-Specific DRAMs and anIndustrial Case Study

Rei-Fu Huang (MediaTek, Inc.); Hao-Yu Yang, Mango C.-T. Chao (NationalChiao Tung Univ.); Shih-Chin Lin (United Microelectronics Corp.)

Goal-Oriented Stimulus Generation for Analog Circuits

Jayanand Asok Kumar, Shobha Vasudevan, Seyed Nematollah Ahmadyan(Univ. of Illinois at Urbana-Champaign)

TSV Open Defects in 3D Integrated Circuits: Characterization, Test, andOptimal Spare Allocation

Krishnendu Chakrabarty, Fangming Ye (Duke Univ.)

Small Delay Testing for TSVs in 3-D ICs

Yu-Hsiang Lin, Shi-Yu Huang (National Tsing Hua Univ.); Kun-Han Tsai,Wu-Tung Cheng, Stephen Sunter (Mentor Graphics Corp.); Yung-Fa Chou,Ding-Ming Kwai (Industrial Technology Research Institute)

Session 44: Design Challenges and EDA Solutions forWireless Sensor Networks

Chair: Roman Hermida (Complutense Univ.)

Circuit and System Design Guidelines for Ultra-Low Power Processing

Dongmin Yoon, David Blaauw, Yejoong Kim, Yoonmyung Lee, DennisSylvester (Univ. of Michigan)

Design Exploration of Energy-Performance Trade-Offs for Wireless SensorNetworks


19 of 24 5/17/2012 3:28 PM

44.3 1049

45.1 1055

45.2 1061

45.3 1067

45.4 1074

46.1 1082

46.2 1088

Ivan Beretta (Ecole Polytechnique Fédérale de Lausanne); Francisco Rincon(Univ. Complutense Madrid); Nadia Khaled (Nestlé Research Center); PaoloGrassi (Politecnico di Milano); Vincenzo Rana, David Atienza (EcolePolytechnique Fédérale de Lausanne)

Energy Harvesting and Power Management for Autonomous Sensor Nodes

Jerome Willemin (CEA-LETI); Christian Piguet (Centre Suisse d'Electroniqueet Microtechnique SA); Edith Beigné, Jean-Frederic Christmann, CyrilCondemine (CEA-LETI)

Session 45: Surviving Timing Challenges in NanometerDesigns

Chair: Florentin Dartu (Synopsys, Inc.)

Functional Timing Analysis Made Fast and General

Jie-Hong Roland Jiang, Yi-Ting Chung (National Taiwan Univ.)

Timing Analysis with Nonseparable Statistical and DeterministicVariations

Jeffrey Hemmett, Natesan Venkateswaran, Jeremy Leitzen (IBM Systems andTechnology Group); Jinjun Xiong (IBM T.J. Watson Research Ctr.); EricForeman (IBM Corp.); Debjit Sinha (IBM Systems and Technology Group);Vladimir Zolotov (IBM T.J. Watson Research Ctr.); Chandu Visweswariah(IBM Systems and Technology Group)

Reversible Statistical Max/Min Operation: Concept and Applications toTiming

Debjit Sinha, Natesan Venkateswaran (IBM Systems and Technology Group);Vladimir Zolotov (IBM T.J. Watson Research Ctr.); Jinjun Xiong (IBM T.J.Watson Research Ctr.); Chandu Visweswariah (IBM Systems and TechnologyGroup)

Predicting Timing Violations Through Instruction-Level PathSensitization Analysis

Sanghamitra Roy, Koushik Chakraborty (Utah State Univ.)

Session 46: Special Delivery: Challenges in PackagingChair: Tan Yan (Synopsys, Inc.)

A Chip-Package-Board Co-Design Methodology

Hsu-Chieh Lee, Yao-Wen Chang (National Taiwan Univ.)

Obstacle-Avoiding Free-assignment Routing for Flip-Chip Designs

I-Jye Lin, Chin-Fang Shen, Chen-Feng Chang (Synopsys, Inc.); Yao-WenChang, Yuan-Kai Ho, Hsu-Chieh Lee, Po-Wei Lee (National Taiwan Univ.)


20 of 24 5/17/2012 3:28 PM

46.3 1094

46.4 1100

47.1 1107

47.2 1113

47.3 1119

47.4 1125

48.1 1131

48.2 1137

Clock Tree Synthesis with Methodology of Re-Use in 3-D IC

TingTing Hwang, Fu-Wei Chen (National Tsing Hua Univ.)

Can Pin Access Limit the Footprint Scaling?

Xiang Qiu, Malgorzata Marek-Sadowska (Univ. of California, Santa Barbara)

Session 47: Renovate Analog and Mixed-Signal CircuitSimulations

Chair: Chenjie Gu (Intel Corp.)

Yield Estimation via Multi-Cones

Rouwaida Kanj (American Univ. of Beirut); Rajiv Joshi (IBM T.J. WatsonResearch Ctr.); Zhuo Li, Jerry Hayes (IBM Research - Austin); Sani Nassif(IBM Research - Austin)

Efficient Trimmed-Sample Monte Carlo Methodology and Yield-AwareDesign Flow for Analog Circuits

Wei-Yi Hu, Yi-Kan Cheng, Chin-Cheng Kuo, Yi-Hung Chen, Jui-Feng Kuan(Taiwan Semiconductor Manufacturing Co., Ltd.)

Towards Efficient SPICE-Accurate Nonlinear Circuit Simulation withOn-the-Fly Support-Circuit Preconditioners

Xueqian Zhao, Zhuo Feng (Michigan Technological Univ.)

Sparse LU Factorization for Parallel Circuit Simulation on GPU

Ling Ren, Xiaoming Chen, Yu Wang, Chenxi Zhang, Huazhong Yang (TsinghuaUniv.)

Session 48: Heterogenous Platforms: Challenges andOpportunities

Chair: Norbert Wehn (Univ. of Kaiserslautern)

Is Dark Silicon Useful? Harnessing the Four Horsemen of the ComingDark Silicon Apocalypse

Michael Taylor (Univ. of California at San Diego)

Platform 2012 - A Many-Core Computing Accelerator for Embedded SoCs:Performance Evaluation of Visual Analytics Applications

Luca Benini (Univ. di Bologna, STMicrolectronics); Denis Dutoit, FabienClermidy (STMicroelectronics, CEA-LETI); Germain Haugou, Thierry Lepley,Bruno Jego, Diego Melpignano, Eric Flamand (STMicroelectronics)

Session 50: Hot Chips Running Cool - Energy EfficientNear-Threshold Computing and its Barriers

Chair: David Brooks (Harvard Univ.)


21 of 24 5/17/2012 3:28 PM

50.1 1143

50.2 1149

50.3 1155

50.4 1160

51.1 1163

51.2 1169

51.3 1175

51.4 1181

51.5 1187

51.6 1193

Assessing the Performance Limits of Parallelized Near-ThresholdComputing

Kory Sewell, Trevor Mudge, David Blaauw, Dennis Sylvester, NathanielPinckney, Ronald Dreslinski, David Fick (Univ. of Michigan)

Near-Threshold Voltage (NTV) Design - Opportunities and Challenges

Himanshu Kaul, Mark Anders, Steven Hsu, Amit Agarwal, Ram Krishnamurthy,Shekhar Borkar (Intel Corp.)

Near-Threshold Operation for Power-Efficient Computing? It Depends

Leland Chang, Wilfried Haensch (IBM T.J. Watson Research Ctr.)

Not so Fast my Friend: Is Near-Threshold Computing the Answer forPower Reduction of Wireless Devices?

Matt Severson, Kendrick Yuen, Yang Du (Qualcomm, Inc.)

Session 51: Yielding in an Uncertain WorldChair: Rob Aitken (ARM, Inc.)

Accurate Process-Hotspot Detection Using Critical Design Rule Extraction

Yen-Ting Yu (National Chiao Tung Univ.); Ya-Chung Chan (MstarSemiconductor); Subarna Sinha (Stanford Univ.); Iris Hui-Ru Jiang (NationalChiao Tung Univ.); Charles Chiang (Synopsys, Inc.)

Improved Tangent Space-Based Distance Metric for Accurate LithographicHotspot Classification

Xuan Zeng, Jing Guo, Fan Yang (Fudan Univ.); Subarna Sinha (StanfordUniv.); Charles Chiang (Synopsys, Inc.)

Simultaneous Flare Level and Flare Variation Minimization withDummification in EUVL

Shao-Yun Fang, Yao-Wen Chang (National Taiwan Univ.)

A Novel Layout Decomposition Algorithm for Triple PatterningLithography

Shao-Yun Fang, Yao-Wen Chang, Wei-Yu Chen (National Taiwan Univ.)

PS3-RAM: A Fast Portable and Scalable Statistical STT-RAM ReliabilityAnalysis Method

Wujie Wen, YaoJun Zhang, Yiran Chen (Univ. of Pittsburgh); Yu Wang(Tsinghua Univ.); Yuan Xie (Pennsylvania State Univ.)

Exploiting Narrow-Width Values for Process Variation-Tolerant 3-DMicroprocessors


22 of 24 5/17/2012 3:28 PM

52.1 1203

52.2 1212

52.3 1222

52.4 1229

52.5 1235

52.6 1241

53.1 1250

53.2 1252

Sung Woo Chung, Joonho Kong (Korea Univ.)

Session 52: High-Level Synthesis is Not Just AboutTranslation!

Chair: Satnam Singh (Google, Inc.)

Hardware Synthesis of Recursive Functions through Partial StreamRewriting

Christian Haubelt, Lars Middendorf (Univ. of Rostock); Christophe Bobda(Univ. of Arkansas)

Chisel: Constructing Hardware in a Scala Embedded Language

Jonathan Bachrach, Huy Vo, Brian Richards, Yunsup Lee, Andrew Waterman,Rimas Avizienis, John Wawrzynek, Krste Asanovic (Univ. of California,Berkeley)

Specification and Synthesis of Hardware Checkpointing and RollbackMechanisms

Carven Chan, Sharad Malik, Divjyot Sethi, Daniel Schwartz-Narbonne(Princeton Univ.)

Optimizing Memory Hierarchy Allocation with Loop Transformations forHigh-Level Synthesis

Jason Cong, Peng Zhang, Yi Zou (Univ. of California, Los Angeles)

A Metric for Layout-Friendly Microarchitecture Optimization in High-LevelSynthesis

Jason Cong, Bin Liu (Univ. of California, Los Angeles)

Computer Generation of Streaming Sorting Networks

Marcela Zuluaga (Eidgenössische Technische Hochschule Zürich); Peter Milder(Carnegie Mellon Univ.); Markus Püschel (Eidgenössische TechnischeHochschule Zürich)

Session 53: Wild And Crazy IdeasChair: Farinaz Koushanfar (Rice Univ.)

CrowdMine: Towards Crowdsourced Human-Assisted Verification

Wenchao Li, Sanjit A. Seshia (Univ. of California, Berkeley); Somesh Jha(Univ. of Wisconsin, Madison)

Extracting Design Information from Natural Language Specifications

Ian G. Harris (Univ. of California, Irvine)

Material Implication in CMOS: A New Kind of Logic


23 of 24 5/17/2012 3:28 PM

53.3 1254

53.4 1256

53.5 1258

53.6 1260

54.1 1262

54.2 1268

54.3 1274

54.4 1280

54.5 1288

54.6 1297

Elkim Roa (Purdue Univ.); Wu-Hsin Chen (Purdue University); ByunghooJung (Purdue Univ.)

Boolean Satisfiability Using Noise-Based Logic

Pey-Chang Kent Lin, Ayan Mandal, Sunil Khatri (Texas A&M Univ.)

Cognitive Computing with Spin-Based Neural Networks

Georgios Panagopoulos, Kaushik Roy, Mrigank Sharad (Purdue Univ.);Charles Augustine (Intel Corp.)

Capacitance of TSVs in 3-D Stacked Chips a Problem? Not forNeuromorphic Systems!

Antoine Joubert (CEA-LETI Minatec); Marc Duranton (CEA-LIST); BilelBelhadj (CEA-LETI Minatec); Olivier Temam (INRIA); Rodolphe Héliot(CEA-LETI Minatec)

Session 54: Optimizing Embedded Software for HighPerformance and Reliability

Chair: Rodric Rabbah (IBM Research)

Communication-Aware Mapping of KPN Applications onto HeterogeneousMPSoCs

Jeronimo Castrillon, Andreas Tretter, Rainer Leupers, Gerd Ascheid (RWTHAachen Univ.)

Unrolling and Retiming of Stream Applications onto Embedded MulticoreProcessors

Weijia Che, Karam Chatha (Arizona State Univ.)

Exploiting Spatiotemporal and Device Contexts for Energy-EfficientMobile Embedded Systems

Chris Ohlsen, Sudeep Pasricha, Charles Anderson, Brad Donohoo (ColoradoState Univ.)

EPIMap: Using Epimorphism to Map Applications on CGRAs

Mahdi Hamzeh, Aviral Shrivastava, Sarma Vrudhula (Univ. of California, LosAngeles)

Instruction Scheduling for Reliability-Aware Compilation

Semeen Rehman, Muhammad Shafique, Joerg Henkel (Karlsruhe Institute ofTechnology)

Compiling for Energy Effciency on Timing Speculative Processors

Rakesh Kumar, John Sartori (Univ. of Illinois at Urbana-Champaign)


24 of 24 5/17/2012 3:28 PM

Documents

2012 49th ACM/EDAC/IEEE Design Automation Conference (DAC …toc.proceedings.com/15388webtoc.pdf · 2012. 8. 10. · San Francisco, California, USA 3-7 June 2012 IEEE Catalog Number: