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EE1411
EECS141 1Lecture #8
EE141EE141--Fall 2010Fall 2010Digital Integrated Digital Integrated CircuitsCircuits
Lecture 8Lecture 8LE for DecodersLE for Decoders
EE1412
EECS141 2Lecture #8
AnnouncementsAnnouncementsLab #3 Mon., Lab #4 Fri.Homework #4 due this Thursday
Homework #5 due next Thursday
EE1413
EECS141 3Lecture #8
Class MaterialClass Material
Last lectureGate delay and logical effort
Today’s lectureLogical effort for decoders
Reading (Chapter 6)
EE1414
EECS141 4Lecture #8
DecodersDecoders
EE1415
EECS141 5Lecture #8
Decoder Design ExampleDecoder Design Example
Look at decoder for 256x256 memory block (8KBytes)
EE1416
EECS141 6Lecture #8
Problem SetupProblem SetupGoal: Build fastest possible decoder with static CMOS logic
What we knowBasically need 256 AND gates, each one of them drives one word line
N=8
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EECS141 7Lecture #8
Problem Setup (1)Problem Setup (1)
Each word line has 256 cells connected to itCWL = 256*Ccell + Cwire
Ignore wire for now (include it later in the class)
EE1418
EECS141 8Lecture #8
Problem Setup (2)Problem Setup (2)
Assume that decoder input capacitance is Caddress=4*Ccell
EE1419
EECS141 9Lecture #8
Problem Setup (3)Problem Setup (3)
Each address drives 28/2 AND gatesA0 drives ½ of the gates, A0_b the other ½ of the gates
EE14110
EECS141 10Lecture #8
Problem Setup (4)Problem Setup (4)
Total fanout on each address wire is: ( ) ( )8
7 132
2256128 2 2
4 2cellcellload
in cell cell
CCCF BC C C
= Π = = =
EE14111
EECS141 11Lecture #8
Decoder FanDecoder Fan--OutOutF of 213 means that we will want to use more than log4(213) = 6.5 stages to implement the AND8
Need many stages anywaysSo what is the best way to implement the AND gate?Will see next that it’s the one with the most stages and least complicated gates
EE14112
EECS141 12Lecture #8
88--Input ANDInput AND
LE=10/3 1 ΠLE = 10/3P = 8 + 1
LE=2 5/3ΠLE = 10/3P = 4 + 2
LE=4/3 5/3 4/3 1ΠLE = 80/27P = 2 + 2 + 2 + 1
EE14113
EECS141 13Lecture #8
88--Input ANDInput AND
Using 2-input NAND gates8-input gate takes 6 stages
Total LE is (4/3)3 ≈ 2.4So PE is 2.4*213 – optimal N of ~7.1
EE14114
EECS141 14Lecture #8
Decoder So FarDecoder So Far256 8-input AND gates
Each built out of tree of NAND gatesand inverters
Issue:Every address line hasto drive 128 gates (andwire) right awayCan’t build gates small enough - Forces us to add buffers just to drive address inputs
EE14115
EECS141 15Lecture #8
Look Inside Each AND8 GateLook Inside Each AND8 Gate
EE14116
EECS141 16Lecture #8
PredecodersPredecodersUse a single gate for each of the shared terms
E.g., from A0, A0, A1, and A1, generate four signals: A0A1, A0A1, A0A1, A0A1
In other words, we are decoding smaller groups of address bits first
And using the “predecoded” outputs to do the rest of the decoding
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EECS141 17Lecture #8
Predecoder and DecoderPredecoder and DecoderA0 A1 A4 A5A2 A3
EE14118
EECS141 18Lecture #8
PredecoderPredecoder/Decoder Layout/Decoder Layout
EE14119
EECS141 19Lecture #8
PredecodePredecode OptionsOptionsTwo options for predecoding:
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EECS141 20Lecture #8
PredecodePredecode Options (2)Options (2)Larger predecode usually better:More stages before the long wires
Decreases their effect on the circuit
Fewer long wires switch
Lower powerEasier to fit 2-input gate into cell pitch
CL
1 161 16
256
4 to 16 predecoder
A0 A1 A2A3
A0A1A2A3
EE14121
EECS141 21Lecture #8
What We Now KnowWhat We Now KnowGiven decoder structure, input capacitance, final load
Can size the entire chain using LE for minimum delay
Is this the “best” we can do in terms of power too?
Not necessarily – probably want to reduce sizes – (especially on final decoder inputs)
Is there anything else we can do to improve energy even further?
EE14122
EECS141 22Lecture #8
PowerPower
If we lower the supply voltage, energy from switching capacitors drops quadratically!
But, how does this impact delay? Need to look more closely at transistor behavior…
210 DDLVCE =→
iL
Vin VoutCL
VDD
EE14123
EECS141 23Lecture #8
Next LectureNext Lecture
MOS transistor model
