IEEE Catalog Number: ISBN:

CFP09162-PRT 978-1-4244-3781-8

2009 Design, Automation & Test in Europe Conference & Exhibition (DATE 2009)

Nice, France 20-24 April 2009

Pages 1-561

Table of Contents

Design, Automation and Test in Europe Conference and Exhibition - DATE 2009

Keynote Addresses Has Anything Changed in Electronic Design Since 1983? ........................................................................... 1 M. Muller Embedded Systems Design – Scientific Challenges and Work Directions ................................................... 2 J. Sifakis 2.2 Emerging Interconnection Technologies for Multicore Moderators: P Paulin, STMicroelectronics, FR; G Nicolescu, Polytechnique Montreal, CA A Low-Power Fat Tree-Based Optical Network-on-Chip for Multiprocessor System-on-Chip ...................... 3 H. Gu, J. Xu and W. Zhang SunFloor 3D: A Tool for Networks on Chip Topology Synthesis for 3D Systems on Chips ......................... 9 C. Seiculescu, S. Murali, L. Benini and G. De Micheli User-Centric Design Space Exploration for Heterogeneous Network-on-Chip Platforms .......................... 15 C.-L. Chou and R. Marculescu A Highly Resilient Routing Algorithm for Fault-Tolerant NoCs.................................................................... 21 D. Fick, A. DeOrio, G. Chen, V. Bertacco, D. Sylvester and D. Blaauw 2.3 Applications on Reconfigurable Hardware 1 Moderators: G. Sassatelli, LIRMM, FR; M. Huebner, Karlsruhe U, DE Mapping of a Film Grain Removal Algorithm to a Heterogeneous Reconfigurable Architecture ................ 27 S. Whitty, H. Sahlbach, R. Ernst and W. Putzke-Roeming An ILP Formulation for Task Mapping and Scheduling on Multi-Core Architectures .................................. 33 Y. Yi, W. Han, X. Zhao, A.T. Erdogan and T. Arslan DPR in High Energy Physics ....................................................................................................................... 39 W. Gao, A. Kugel, R. Maenner, N. Abel, N. Meier and U. Kebschull A Flexible Layered Architecture for Accurate Digital Baseband Algorithm Development and Verification ............................................................................................................................................ 45 A. Alimohammad, S.F. Fard and B.F. Cockburn

2.4 Task Allocation for MPSoCs Moderators: J. Teich, University of Erlangen-Nuremberg, DE; P. Marwedel, TU Dortmund. DE Lifetime Reliability-Aware Task Allocation and Scheduling for MPSoC Platforms ..................................... 51 L. Huang, F. Yuan and Q. Xu Integrated Scheduling and Synthesis of Control Applications on Distributed Embedded Systems............ 57 S. Samii, A. Cervin, P. Eles and Z. Peng Towards No-Cost Adaptive MPSoC Static Schedules through Exploitation of Logical-to-Physical Core Mapping Latitude ................................................................................................................................ 63 C. Yang and A. Orailoglu Pipelined Data Parallel Task Mapping/Scheduling Technique for MPSoC ................................................. 69 H. Yang and S. Ha 2.5 Advanced Approaches for Reliability Improvement Moderators: B. Becker, Freiburg U, DE; M. Psarakis, Piraeus U, GR Joint Logic Restructuring and Pin Reordering against NBTI-Induced Performance Degradation .............. 75 K.-C. Wu and D. Marculescu A Self-Adaptive System Architecture to Address Transistor Aging ............................................................ 81 O. Khan and S. Kundu Masking Timing Errors on Speed-Paths In Logic Circuits ........................................................................... 87 M.R. Choudhury and K. Mohanram 2.6 Scheduling and Timing Analysis for Embedded Real-Time Systems Moderators: R. Dick, Northwestern U, US; R. Leupers, RWTH Aachen U, DE WCRT Algebra and Interfaces for Esterel-Style Synchronous Processing ................................................ 93 M. Mendler, R. von Hanxleden and C. Traulsen Reliable Mode Changes in Real-Time Systems with Fixed Priority or EDF Scheduling ............................ 99 N. Stoimenov, S. Perathoner and L. Thiele Improved Worst-Case Response-Time Calculations by Upper-Bound Conditions................................... 105 V. Pollex, S. Kollman, K. Albers and F. Slomka A Generalized Scheduling Approach for Dynamic Dataflow Applications ................................................ 111 W. Plishker, N. Sane and S.S. Bhattacharyya 2.7 System-Level Synthesis and Optimization Moderators: P. Pop, TU Denmark, DK; R. Woods, Queens U Belfast, IE Optimizing Data Flow Graphs to Minimize Hardware Implementation ..................................................... 117 D. Gomez-Prado, Q. Ren, M. Ciesielski, J. Guillot and E. Boutillon Multi-Clock SoC Design Using Protocol Conversion ................................................................................ 123 R. Sinha, P.S. Roop, S. Basu and Z. Salcic A Formal Approach to Design Space Exploration of Protocol Converters ................................................ 129 K. Avnit and A. Sowmya

Model-Based Synthesis and Optimization of Static Multi-Rate Image Processing Algorithms ................. 135 J. Keinert, H. Dutta, F. Hannig, C. Haubelt and J. Teich 2.8 PANEL SESSION – Consolidation, a Modern "Moor of Venice" Tale .......................................... 141 Organizer: M. Casale-Rossi, Synopsys, IT Moderator: G. De Micheli, EPFL, CH Panelists: A. Domic, M. Montalti, M. Muller, J. Sawicki 3.2 Variability and Reliability Aware Energy Management Moderators: M. Miranda, IMEC, BE; W. Dehaene, KU Leuven, BE Variation Resilient Adaptive Controller for Subthreshold Circuits ............................................................. 142 B. Mishra, B.M. Al-Hashimi and M. Zwolinski Minimization of NBTI Performance Degradation Using Internal Node Control ......................................... 148 D.R Bild, G.E. Bok and R.P. Dick Physically Clustered Forward Body Biasing for Variability Compensation in Nanometer CMOS Design ....................................................................................................................................................... 154 A. Sathanur, A. Pullini, L. Benini, G. De Micheli and E. Macii An Event-Guided Approach to Reducing Voltage Noise in Processors .................................................... 160 M.S Gupta, V.J Reddi, G. Holloway, G.-Y. Wei and D.M. Brooks 3.3 Applications on Reconfigurable Hardware 2 Moderators: R. Cottrell, Altera European Technology Centre; C. Heer, Infineon Technologies, DE Design and Implementation of a Database Filter for BLAST Acceleration ............................................... 166 P. Afratis, C. Galanakis, E. Sotiriades, G.-G. Mplemenos, G. Chrysos, I. Papaefstathiou and D. Pnevmatikatos A Software-Supported Methodology for Exploring Interconnection Architectures Targeting 3-D FPGAs ................................................................................................................................................ 172 K. Siozios, V.F. Pavlidis and D. Soudris Priority-Based Packet Communication on a Bus-Shaped Structure for FPGA-Systems .......................... 178 O. Sander, B. Glas, C. Roth, J. Becker and K.D. Mueller-Glaser Exploration of Power Reduction and Performance Enhancement in LEON3 Processor with ESL Reprogrammable eFPGA in Processor Pipeline and as a Co-Processor ................................................. 184 S.Z. Ahmed, J. Eydoux, L. Rouge, J.-B. Cuelle, G. Sassatelli and L. Torres 3.4 EMBEDDED TUTORIAL – High-Level Modeling and Verification Organizer/Moderator: W. Mueller, Paderborn U, DE Functional Qualification of TLM Verification .............................................................................................. 190 N. Bombieri, F. Fummi, G. Pravadelli, M. Hampton and F. Letombe Solver Technology for System-Level to RTL Equivalence Checking ........................................................ 196 A. Koelbl, R. Jacoby, H. Jain and C. Pixley

3.5 System-Level Test and Debug Moderators: F. Novak, Josef Stefan Institute, SI; V. Singh, Indian Institute of Science, IN A High-Level Debug Environment for Communication-Centric Debug ..................................................... 202 K. Goossens, B. Vermeulen and A.B. Nejad Cache Aware Compression for Processor Debug Support ....................................................................... 208 A. Vishnoi, P.R. Panda and M. Balakrishnan Fault Insertion Testing of a Novel CPLD-Based Fail-Safe System ........................................................... 214 G. Griessnig, R. Mader, C. Steger and R. Weiss Test Architecture Design and Optimization for Three-Dimensional SoCs ................................................ 220 L. Jiang, L. Huang and Q. Xu 3.6 Model-Based Design and HW/SW System Integration Moderators: P. Mosterman, The MathWorks, US; E. Villar, Cantabria U, ES A Co-Design Approach for Embedded System Modeling and Code Generation with UML and MARTE ............................................................................................................................................... 226 J. Vidal, F. de Lamotte, G. Gogniat, P. Soulard and J.-P. Diguet Componentizing Hardware/Software Interface Design ............................................................................. 232 K. Hao and F. Xie A UML Frontend for IP-XACT-Based IP Management ............................................................................. 238 T. Schattkowsky, T. Xie and W. Mueller Evaluating UML2 Modeling of IP-XACT Objects for Automatic MP-SoC Integration onto FPGA ............. 244 T. Arpinen, T. Koskinen, E. Salminen, T.D. Hamalainen and M. Hannikainen 3.7 NoC Customization Techniques Moderators: T. Basten, Twente U, NL; S. Yoo, POSTECH (Pohang U of Science and Technology), KR aelite: A Flit-Synchronous Network on Chip with Composable and Predictable Services ........................ 250 A. Hansson, M. Subburaman and K. Goossens Configurable Links for Runtime Adaptive On-Chip Communication ......................................................... 256 M.A. Al Faruque, T. Ebi and J. Henkel Synthesis of Low-Overhead Configurable Source Routing Tables for Network Interfaces ...................... 262 I. Loi, F. Angiolini and L. Benini SCORES: A Scalable and Parametric Streams-Based Communication Architecture for Modular Reconfigurable Systems ........................................................................................................................... 268 A. Jara-Berrocal and A. Gordon-Ross 3.8 HOT TOPIC AND PANEL – Analogue Layout Synthesis – Light at the End of the Tunnel? Organizer/Moderator: H. Graeb, TU Munich, DE Panelists: J. Cessna, G. Goelz, V. Meyer zu Bexten and E. Petrus Analog Layout Synthesis – Recent Advances in Topological Approaches ............................................... 274 H. Graeb, F. Balasa, R. Castro-Lopez, Y.-W. Chang, F.V. Fernandez, P.-H. Lin and M. Strasser

IP1 Interactive Presentations An Accurate Interconnect Thermal Model Using Equivalent Transmission Line Circuit ........................... 280 B. Wang and P. Mazumder Analogue Mixed Signal Simulation Using Spice and SystemC................................................................. 284 T. Kirchner, N. Bannow and C. Grimm Reliability Aware through Silicon Via Planning for 3D Stacked ICs .......................................................... 288 A. Shayan, X. Hu, H. Peng, C.-K. Cheng, W. Yu, M. Popovich, T. Toms and X. Chen A Study on Placement of Post Silicon Clock Tuning Buffers for Mitigating Impact of Process Variation .................................................................................................................................................... 292 K. Nagaraj and S. Kundu Analysis and Optimization of NBTI Induced Clock Skew in Gated Clock Trees ....................................... 296 A. Chakraborty, G. Ganesan, A. Rajaram and D.Z. Pan Bitstream Relocation with Local Clock Domains for Partially Reconfigurable FPGAs ............................. 300 A. Flynn, A. Gordon-Ross and A.D. George Parallel Transistor Level Full-Chip Circuit Simulation ............................................................................... 304 H. Peng and C.-K. Cheng Performance-Driven Dual-Rail Insertion for Chip-Level Pre-Fabricated Design ....................................... 308 F.-W. Chen and Y.-Y. Liu Simulation Framework for Early Phase Exploration of SDR Platforms: A Case Study of Platform Dimensioning ............................................................................................................................................. 312 M. Trautmann, S. Mamagkakis, B. Bougard, J. Declerck, E. Umans, A. Dejonghe, L. Van der Perre and F. Catthoor Fast and Accurate Protocol Specific Bus Modeling Using TLM 2.0 .......................................................... 316 H.W.M. van Moll, H. Corporaal, V. Reyes and M. Boonen Incorporating Graceful Degradation into Embedded System Design ....................................................... 320 M. Glass, M. Lukasiewycz, C. Haubelt and J. Teich Rewiring Using IRredundancy Removal and Addition .............................................................................. 324 C.-C. Lin and C.-Y. Wang 4.2 Power Optimizations Including Reliability and Temperature Moderators: V Mooney III, Georgia Institute of Technology, US; J. Henkel, Karlsruhe U, DE Gate Replacement Techniques for Simultaneous Leakage and Aging Optimization ............................... 328 Y. Wang, X. Chen, W. Wang, Y. Cao, Y. Xie and H. Yang Enabling Concurrent Clock and Power Gating in an Industrial Design Flow ............................................ 334 L. Bolzani, A. Calimera, A. Macii, E. Macii and M. Poncino TRAM: A Tool for Temperature and Reliability Aware Memory Design .................................................... 340 A. Khajeh, A. Gupta, N. Dutt, F. Kurdahi, A. Eltawil, K. Khouri and M. Abadir

4.3 Aerospace Systems, MEMS and Mixed-Signal Applications Moderators: P. Manet, U Catholique de Lovain, BE; P. D’Abramo, Austriamicrosystems, AT Aircraft Integration Real-Time Simulator Modeling with AADL for Architecture Tradeoffs ....................... 346 J. Casteres and T. Ramaherirariny A Low-Cost SEE Mitigation Solution for Soft-Processors Embedded in Systems on Programmable Chips ................................................................................................................................. 352 M. Sonza Reorda, M. Violante, C. Meinhardt and R. Reis Communication Minimization for In-Network Processing in Body Sensor Networks: A Buffer Assignment Technique .............................................................................................................................. 358 H. Ghasemzadeh, N. Jain, M. Sgroi and R. Jafari A MEMS Reconfigurable Quad-Band Class-E Power Amplifier for GSM Standard ................................. 364 L. Larcher, R. Brama, M. Ganzerli, J. Iannacci, M. Bedani and A. Gnudi Power Reduction of A 12-Bit 40-MS/s Pipeline ADC Exploiting Partial Amplifier Sharing ....................... 369 J.A. Díaz-Madrid, H. Neubauer, H. Hauer, G. Doménech-Asensi and R. Ruiz-Merino 4.4 PANEL SESSION – Is the Second Wave of HLS the One Industry Will Surf on? ...................... 374 Organizer: L. Le Toumelin, Texas Instruments, FR Moderator: J. Cong, UCLA, US Panelists: J. Cong, G. Clave, T. Makelainen, Z. Zhang, V. Kathail and J. Kunkel 4.5 Test for Variability, Reliability and Circuit Marginality Moderators: A. Rubio, UP Catalunya, ES; E.J. Marinissen, IMEC, BE Analyzing the Impact of Process Variations on Parametric Measurements: Novel Models and Applications ........................................................................................................................................ 375 S. Reda and S.R. Nassif On Linewidth-Based Yield Analysis for Nanometer Lithography .............................................................. 381 A. Sreedhar and S. Kundu Impact of Voltage Scaling on Nanoscale SRAM Reliability ...................................................................... 387 V. Chandra and R. Aitken 4.6 System Approaches to Flash Memory Management Moderators: S. Yoo, POSTECH (Pohang U of Science and Technology), KR; A. Jerraya, CEA, FR A File-System-Aware FTL Design for Flash-Memory Storage Systems ................................................... 393 P.-L. Wu, Y.-H. Chang and T.-W. Kuo FSAF: File System Aware Flash Translation Layer for NAND Flash Memories ....................................... 399 S.K. Mylavarapu, S. Choudhuri, A. Shrivastava, J. Lee and T. Givargis A Set-Based Mapping Strategy for Flash-Memory Reliability Enhancement ............................................ 405 Y.-S. Chu, J.-W. Hsieh, Y.-H. Chang and T.-W. Kuo

4.7 Novel Design Space Exploration and Power Optimization Techniques Moderators: M. Poncino, Politecnico di Torino, IT; J. Haid, Infineon Technologies, AT Energy Efficient Multiprocessor Task Scheduling under Input-Dependent Variation ............................... 411 J. Cong and K. Gururaj Program Phase and Runtime Distribution-Aware Online DVFS for Combined Vdd/Vbb Scaling ............. 417 J. Kim, S. Yoo and C.-M. Kyung ORION 2.0: A Fast and Accurate NoC Power and Area Model for Early-Stage Design Space Exploration ..................................................................................................................................... 423 A.B. Kahng, B. Li, L.-S. Peh and K. Samadi 4.8 PANEL SESSION – Open Source Hardware IP, Are You Serious? ............................................. 429 Organizer: P. Parrish, Sun Microsystems, US Moderator: S. Mehta, Sun Microsystems, US Panelists: J. Abraham, R. Goldman and J. McLean 5.1 HOT TOPIC – Concurrent SoC Development and End-to-End Planning .................................... 430 Organizer: L. Anghel, TIMA Laboratory, FR Moderator: G. Smith, US 5.2 HOT TOPIC – The Nano-Electronics Challenge – Chip Designers Meet Real Nano-Electronics in 2010s? Organizer/Moderator: S. Fujita, Toshiba, JP Nano-Electronics Challenge - Chip Designers Meet Real Nano-Electronics in 2010s? .......................... 431 S. Fujita MTJ–Based Nonvolatile Logic-in-Memory Circuit, Future Prospects and Issues ..................................... 433 S. Matsunaga, J. Hayakawa, S. Ikeda, K. Miura, T. Endoh, H. Ohno and T. Hanyu Imperfection-Immune VLSI Logic Circuits Using Carbon Nanotube Field Effect Ttransistors .................. 436 S. Mitra, J. Zhang, N. Patil and H. Wei Reconfigurable Circuit Design with Nanomaterials ................................................................................... 442 C. Dong, S. Chilstedt and D. Chen 5.3 Embedded Systems Security Moderators: J. Quevremont, Thales, FR; L. Torres, LIRMM, Montpellier U/CNRS, FR An Architecture for Secure Software Defined Radio ................................................................................. 448 C. Li, A. Raghunathan and N.K. Jha Optimizing the HW/SW Boundary of an ECC SoC Design Using Control Hierarchy and Distributed Storage .................................................................................................................................... 454 X. Guo and P. Schaumont Hardware Aging-Based Software Metering ............................................................................................... 460 F. Dabiri and M. Potkonjak

5.4 Architectural Exploration for MPSoCs Moderators: D. Sciuto, Politecnico di Milano, IT; M. Lajolo, NEC Laboratories, US On-Chip Communication Architecture Exploration for Processor-Pool-Based MPSoC ........................... 466 Y.-P. Joo, S. Kim and S. Ha Combined System Synthesis and Communication Architecture Exploration for MPSoCs ....................... 472 M. Lukasiewycz, M. Streubuehr, M. Glass, C. Haubelt and J. Teich UMTS MPSoC Design Evaluation Using a System Level Design Framework ......................................... 478 D. Densmore, A. Simalatsar, A. Davare, R. Passerone and A. Sangiovanni-Vincentelli 5.5 On-Line Testing and Fault Tolerance Moderators: P. Harrod, ARM, UK; G. Dinatale, LIRMM, FR Fault-Tolerant Average Execution Time Optimization for General-Purpose Multi-Processor System-on-Chips ....................................................................................................................................... 484 M. Vayrynen, V. Singh and E. Larsson Improving Yield and Reliability of Chip Multiprocessors ........................................................................... 490 A. Pan, O. Khan and S. Kundu A Unified Online Fault Detection Scheme via Checking of Stability Violation .......................................... 496 G. Yan, Y. Han and X. Li Statistical Fault Injection: Quantified Error and Confidence ...................................................................... 502 R. Leveugle, A. Calvez, P. Maistri and P. Vanhauwaert 5.6 Performance Analysis Support for the Design of Embedded Real-Time Systems Moderators: P. Pop, TU Denmark, DK; P. Eles, Linkoping U, SE KAST: K-Associative Sector Translation for NAND Flash Memory in Real-Time Systems ...................... 507 H. Cho, D. Shin and Y.I. Eom White Box Performance Analysis Considering Static Non-Preemptive Software Scheduling .................. 513 A. Viehl, M. Pressler, O. Bringmann and W. Rosenstiel Application Specific Performance Indicators for Quantitative Evaluation of the Timing Behavior for Embedded Real-Time Systems ........................................................................................................... 519 F. Koenig, D. Boers, F. Slomka, U. Margull, M. Niemetz and G. Wirrer Response-Time Analysis of Arbitrarily Activated Tasks in Multiprocessor Systems with Shared Resources ..................................................................................................................................... 524 M. Negrean, S. Schliecker and R. Ernst 5.7 Novel Computing and Simulation Approaches Moderators: T. Austin, U of Michigan, US; C. Kozyrakis, Stanford U, US Light NUCA: A Proposal for Bridging the Inter-Cache Latency Gap ......................................................... 530 D. Suarez, T. Monreal, F. Vallejo, R. Beivide and V. Vinals ReSim, A Trace-Driven, Reconfigurable ILP Processor Simulator ........................................................... 536 S. Fytraki and D. Pnevmatikatos

Heterogeneous Coarse-Grained Processing Elements: A Template Architecture for Embedded Processing Acceleration ............................................................................................................................ 542 G. Ansaloni, P. Bonzini and L. Pozzi Algorithms for the Automatic Extension of an Instruction-Set ................................................................... 548 C. Galuzzi, D. Theodoropoulos, R. Meeuws and K. Bertels IP2 Interactive Presentations Dimensioning Heterogeneous MPSoCs via Parallelism Analysis ............................................................. 554 B. Ristau, T. Limberg, O. Arnold and G. Fettweis MPSoCs Run-Time Monitoring through Networks-on-Chip ...................................................................... 558 L. Fiorin, G. Palermo and C. Silvano Assessing Fat-Tree Topologies for Regular Network-on-Chip Design under Nanoscale Technology Constraints............................................................................................................................. 562 D. Ludovici, F. Gilabert, S. Medardoni, C. Gomez, M.E. Gomez, P. Lopez, G.N. Gaydadjiev and D. Bertozzi A Hybrid Packet-Circuit Switched On-Chip Network Based on SDM ....................................................... 566 M. Modarressi, H. Sarbazi-Azad and M. Arjomand SecBus: Operating System Controlled Hierarchical Page-Based Memory Bus Protection ...................... 570 L. Su, S. Courcambec, P. Guillemin, C. Schwarz and R. Pacalet A Link Arbitration Scheme for Quality of Service in a Latency-Optimized Network-on-Chip .................... 574 J. Diemer and R. Ernst Flow Regulation for On-Chip Communication ........................................................................................... 578 Z. Lu, M. Millberg, A. Jantsch, A. Bruce, P. van der Wolf and T. Henriksson Customizing IP Cores for System-on-Chip Designs Using Extensive External Don't Cares .................... 582 K.-H. Chang, V. Bertacco and I.L. Markov Extending IP-XACT to Support an MDE Based Approach for SoC Design .............................................. 586 A. El Mrabti, F. Petrot and A. Bouchhima Overcoming Limitations of the SystemC Data Introspection ..................................................................... 590 C. Genz and R. Drechsler Selective Light Vth Hopping (SLITH): Bridging the Gap between Run-Time Dynamic and Leakage Power Reduction ....................................................................................................................................... 594 H. Xu, R. Vemuri and W.-B. Jone A Power-Efficient Migration Mechanism for D-NUCA Caches .................................................................. 598 A. Bardine, M. Comparetti, P. Foglia, G. Gabrielli and C.A. Prete 6.1.1 PANEL SESSION – Vertical Integration Versus Disaggregation .............................................. 602 Organizer: Y. Zorian, Virage Logic, US Moderator: P. Aycinena, US Panelists: A. Aznar, J.-A. Carballo, R. Madhavan, M. Merced, A. Shubat and R. Yavatkar

6.1.2 Keynote Trends and Challenges in Wireless Application Processors ..................................................................... 603 P. Garnier 6.2 Emerging Hardware: 3D Integration and CNTFET Moderators: Y. Xie, Pennsylvania State U, US; P. Marchal, IMEC, BE System-Level Process Variability Analysis and Mitigation for 3D MPSoCs .............................................. 604 S. Garg and D. Marculescu Co-Design of Signal, Power, and Thermal Distribution Networks for 3D ICs ........................................... 610 Y.-J. Lee, Y.J. Kim, G. Huang, M. Bakir, Y. Joshi, A. Fedorov and S.K. Lim Design of Compact Imperfection-Immune CNFET Layouts for Standard-Cell-Based Logic Synthesis ................................................................................................................................................... 616 S. Bobba, J. Zhang, A. Pullini, D. Atienza and G. De Micheli Novel Library of Logic Gates with Ambipolar CNTFETs: Opportunities for Multi-Level Logic Synthesis ................................................................................................................................................... 622 M.H. Ben Jamaa, K. Mohanram and G. De Micheli 6.3 Design and Security Evaluation of Cryptographic Functions Moderators: M. O’Neill, Queen’s U Belfast, IE; L. Fesquet, TIMA Laboratory, FR Enhancing Correlation Electromagnetic Attack Using Planar Near-Field Cartography ............................ 628 D. Real, F. Valette and M. Drissi Evaluation on FPGA of Triple Rail Logic Robustness against DPA and DEMA ....................................... 634 V. Lomne, P. Maurine, L. Torres, M. Robert, R. Soares and N. Calazans Successful Attack on an FPGA-Based WDDL DES Cryptoprocessor without Place and Route Constraints ................................................................................................................................................ 640 L. Sauvage, S. Guilley, J.-L. Danger, Y. Mathieu and M. Nassar Hardware Evaluation of the Stream Cipher-Based Hash Functions Radiogatun and irRUPT ................. 646 L. Henzen, F. Carbognani, N. Felber and W. Fichtner 6.4 Runtime Checking and Optimization Moderators: D. Pnevmatikatos, TU Crete, GR; L. Pozzi, Lugano U, IT Architectural Support for Low Overhead Detection of Memory Violations ................................................ 652 S. Ghose, L. Gilgeous, P. Dudnik, A. Aggarwal and C. Waxman CASPAR: Hardware Patching for Multi-Core Processors ......................................................................... 658 I. Wagner and V. Bertacco A New Speculative Addition Architecture Suitable for Two's Complement Operations ............................ 664 A. Cilardo Limiting the Number of Dirty Cache Lines ................................................................................................. 670 P. de Langen and B. Juurlink

6.5 EMBEDDED TUTORIAL – Contactless Testing: Possibility or Pipe-Dream? Organizer/Moderator: E.J. Marinissen, IMEC, BE Contactless Testing: Possibility or Pipe-Dream? .................................................................................... 676 E.J. Marinissen, D.Y. Lee, J.P. Hayes, C. Sellathamby, B. Moore, S. Slupsky and L. Pujol 6.6 Fault Tolerance and Energy Issues in Multiprocessor Real-Time Systems Moderators: A. Girault, INRIA Rhone Alpes, FR; L. Almeida, Aveiro U, PT Analysis and Optimization of Fault-Tolerant Embedded Systems with Hardened Processors ................ 682 V. Izosimov, I. Polian, P. Pop, P. Eles and Z. Peng On Bounding Response Times under Software Transactional Memory in Distributed Multiprocessor Real-Time Systems .......................................................................................................... 688 S.F. Fahmy, B. Ravindran and E.D. Jensen An Approximation Scheme for Energy-Efficient Scheduling of Real-Time Tasks in Heterogeneous Multiprocessor Systems ............................................................................................................................ 694 C.-Y. Yang, J.-J. Chen, T.-W. Kuo and L. Thiele 6.7 Analogue Synthesis and Optimization Moderators: T. Kazmierski, Southampton U, UK; L. Hedrich, J W Goethe U Frankfurt/M, DE A Graph Grammar Based Approach to Automated Multi-Objective Analog Circuit Design ...................... 700 A. Das and R. Vemuri Massively Multi-Topology Sizing of Analog Integrated Circuits ................................................................ 706 P. Palmers, T. McConnaghy, M. Steyaert and G. Gielen Improved Performance and Variation Modelling for Hierarchical-Based Optimisation of Analogue Integrated Circuits ..................................................................................................................................... 712 S. Ali, L. Ke, R. Wilcock and P. Wilson Computation of IP3 Using Single-Tone Moments Analysis ...................................................................... 718 D. Tannir and R. Khazaka 6.8 HOT TOPIC AND PANEL – Formal Approaches to Analogue Verification – Now or Never? Moderator: R. Popp, edacentrum, DE Formal Approaches to Analog Circuit Verification .................................................................................... 724 E. Barke, D. Grabowski, H. Graeb, L. Hedrich, S. Heinen, R. Popp, S. Steinhorst and Y. Wang 7.1 PANEL SESSION - ESL Methodology for SoC .............................................................................. 730 Organizer: L. Toda, Mentor Graphics, US Moderator: W. Rhines, Mentor Graphics, US 7.2 HOT TOPIC – The Impact of Non-Volatile Memory on Architecture Design and Tools Organizer/Moderator: Y. Xie, Pennsylvania State U, US An Overview of Non-Volatile Memory Technology and the Implication for Tools and Architectures ........ 731 H. Li and Y. Chen

Power and Performance of Read-Write Aware Hybrid Caches with Non-Volatile Memories .................. 737 X. Wu, J. Li, L. Zhang, E. Speight and Y. Xie Using Non-Volatile Memory to Save Energy in Servers ........................................................................... 743 D. Roberts, T. Kgil and T. Mudge 7.3 On-Chip Communication for Multi-Core Platforms Moderators: V. Zaccaria, Politecnico di Milano, IT; F. Petrot, TIMA Laboratory, FR aEqualized: A Novel Routing Algorithm for the Spidergon Network on Chip ............................................ 749 N. Concer, S. Iamundo and L. Bononi Group-Caching for NoC Based Multicore Cache Coherent Systems ....................................................... 755 W. Zuo, S. Feng, Z. Qi, J. Weixing, L. Jiaxin, D. Ning, X. Licheng, T. Yuan and Q. Baojun A Monitor Interconnect and Support Subsystem for Multicore Processors .............................................. 761 S. Madduri, R. Vadlamani, W. Burleson and R. Tessier 7.4 Non-Functional Properties of MPSoCs Moderators: L. Lavagno, Politecnico di Torino, IT; W. Kruijtzer, NXP Semiconductors, NL A Real-Time Application Design Methodology for MPSoCs ..................................................................... 767 G. Beltrame, L. Fossati and D. Sciuto Adaptive Prefetching for Shared Cache Based Chip Multiprocessors ...................................................... 773 M. Kandemir, Y. Zhang and O. Ozturk CUFFS: An Instruction Count Based Architectural Framework for Security of MPSoCs ......................... 779 K. Patel, S. Parameswaran and R.G. Ragel 7.5 Test Development and On-Line Error Detection Moderators: S. Kundu, Massachusetts U, US; M. Violante, Politecnico di Torino, IT Design as You See FIT: System-Level Soft Error Analysis of Sequential Circuits ................................... 785 D. Holcomb, W. Li and S.A. Seshia Detecting Errors Using Multi-Cycle Invariance Information ...................................................................... 791 N. Alves, K. Nepal, J. Dworak and R.I. Bahar A Novel Approach to Entirely Integrate Virtual Test into Test Development Flow .................................... 797 P. Lu, D. Glaser, G. Uygur and K. Helmreich 7.6 Software Support for MPSoC and Multi-Core Systems Moderators: P. Felber, Neuchatel U, CH; C. Schlaeger, AMD, DE Robust Non-Preemptive Hard Real-Time Scheduling for Clustered Multicore Platforms ......................... 803 M. Lombardi, M. Milano and L. Benini Efficient OpenMP Support and Extensions for MPSoCs with Explicitly Managed Memory Hierarchy ..... 809 A. Marongiu and L. Benini Using Randomization to Cope with Circuit Uncertainty ............................................................................ 815 H. Safizadeh, M. Tahghighi, E.K. Ardestani, G. Tavasoli and K. Bazargan

Process Variation Aware Thread Mapping for Chip Multiprocessors ....................................................... 821 S. Hong, S.H.K. Narayanan, M. Kandemir and O. Ozturk 7.7 Sizing, Placement, Planning and Packaging Moderators: H. Graeb, TU Munich, DE; D. Stroobandt, Ghent U, BE Gate Sizing for Large Cell-Based Designs................................................................................................ 827 S. Held Multi-Domain Clock Skew Scheduling-Aware Register Placement to Optimize Clock Distribution Network .................................................................................................................................. 833 N.MohammadZadeh, M. Mirsaeedi, A. Jahanian and M.S. Zamani Decoupling Capacitor Planning with Analytical Delay Model on RLC Power Grid ................................... 839 Y. Tao and S.K. Lim Package Routability-and IR-Drop-Aware Finger/Pad Assignment in Chip-Package Co-Design .............. 845 C.-H. Lu, H.-M. Chen, C.-N. J. Liu and W.-Y. Shih 7.8 HOT TOPIC – Timing Specification and Analysis in Automotive Systems Organizer: W. Mueller, Paderborn U, DE Moderator: M. Di Natale, Scuola S Anna, IT Learning Early-Stage Platform Dimensioning from Late-Stage Timing Verification ................................. 851 K. Richter, M. Jersak and R. Ernst The Influence of Real-time Constraints on the Design of FlexRay-Based Systems ................................. 858 S. Reichelt, O. Scheickl and G. Tabanoglu Time and Memory Tradeoffs in the Implementation of AUTOSAR Components ..................................... 864 A. Ferrari, M. Di Natale, G. Gentile and P. Gai IP3 Interactive Presentations Systolic Like Soft-Detection Architecture for 4x4 64-QAM MIMO System ................................................ 870 P. Bhagawat, R. Dash and G. Choi Co-Simulation Based Platform for Wireless Protocols Design Explorations ............................................. 874 A. Fourmigue, B. Girodias, G. Nicolescu and E.M. Aboulhamid How To Speed-Up Your NLFSR-Based Stream Cipher ........................................................................... 878 E. Dubrova A High Performance Reconfigurable Motion Estimation Hardware Architecture ...................................... 882 O. Tasdizen, H. Kukner, A. Akin and I. Hamzaoglu Partition-Based Exploration for Reconfigurable JPEG Designs................................................................ 886 P.G Potter, W. Luk and P. Cheung Automated Synthesis of Streaming C Applications to Process Networks In Hardware ............................ 890 S. van Haastregt and B. Kienhuis Distributed Sensor for Steering Wheel Grip Force Measurement In Driver Fatigue Detection ................ 894 F. Baronti, F. Lenzi, R. Roncella and R. Saletti

Making DNA Self-Assembly Error-Proof: Attaining Small Growth Error Rates through Embedded Information Redundancy ........................................................................................................................... 898 S. Garcia and A. Orailoglu Machine Learning-Based Volume Diagnosis ............................................................................................ 902 S. Wang and W. Wei Adaptive Idleness Distribution for Non-Uniform Aging Tolerance in MultiProcessor Systems-on-Chip ....................................................................................................................................... 906 F. Paterna, L. Benini, A. Acquaviva, F. Papariello, G. Desoli and M. Olivieri 8.1 PANEL SESSION – Architectures and Integration for Programmable SoC's ............................ 910 Organizer: G. Schreiner, The MathWorks GmbH, DE Moderator: E. Schubert, ESIC GmbH, DE Panelists: A. Jantsch, P. Urard, F. Schirrmeister, P. Mosterman, L. Le-Toumelin and C. Engbom 8.2 Advanced Low-Power Memory Moderators: A. Macii, Politecnico di Torino, IT; T. Ishihara, Kyushu U, JP Process Variation Aware SRAM/Cache for Aggressive Voltage-Frequency Scaling ............................... 911 A. Sasan (M.A. Makhzan), H. Homayoun, A. Eltawil and F. Kurdahi Single Ended 6T SRAM with Isolated Read-Port for Low-Power Embedded Systems ............................ 917 J. Singh, D.K. Pradhan, S. Hollis, S.P. Mohanty and J. Mathew System-Level Power/Performance Evaluation of 3D Stacked DRAMs for Mobile Applications ............... 923 M. Facchini, T. Carlson, A. Vignon, M. Palcovic, F. Catthoor, W. Dehaene, L. Benini and P. Marchal A Novel DRAM Architecture as a Low Leakage Alternative for SRAM Caches in a 3D Interconnect Context ................................................................................................................................. 929 A. Vignon, S. Cosemans, W. Dehaene, P. Marchal and M. Facchini 8.3 Applications and Thermal Management for Multi-Core Platforms Moderators: L. Anghel, TIMA Laboratory, FR; M. Coppola, STMicroelectronics, FR A Case for Multi-Channel Memories in Video Recording .......................................................................... 934 E. Aho, J. Nikara, P.A. Tuominen and K. Kuusilinna High Level H.264/AVC Video Encoder Parallelization for Multiprocessor Implementation ...................... 940 H.K. Zrida, A. Jemai, A.C. Ammari and M. Abid Temperature-Aware Scheduler Based on Thermal Behavior Grouping in Multicore Systems ................. 946 I. Yeo and E.J. Kim Hardware/Software Co-Design Architecture for Thermal Management of Chip Multiprocessors ............. 952 O. Khan and S. Kundu 8.4 Design Methods for Reconfigurable Systems Moderators: F. Ferrandi, Politecnico di Milano, IT; C. Passerone, Politecnico di Torino, IT Cross-Architectural Design Space Exploration Tool for Reconfigurable Processors ............................... 958 L. Bauer, M. Shafique and J. Henkel

Automatically Mapping Applications to a Self-Reconfiguring Platform ..................................................... 964 K. Bruneel, F. Abouelella and D. Stroobandt OSSS+R: A Framework for Application Level Modelling and Synthesis of Reconfigurable Systems ..................................................................................................................................................... 970 A. Schallenberg, W. Nebel, A. Herrholz, P.A. Hartmann and F. Oppenheimer Design Optimizations to Improve Placeability of Partial Reconfiguration Modules................................... 976 M. Koester, W. Luk, J. Hagemeyer and M. Porrmann 8.5 Debug and Diagnosis Moderators: S. Kajihara, Kyushu Institute of Technology, JP; A. Virazel, LIRMM, FR Automated Data Analysis Solutions to Silicon Debug ............................................................................... 982 Y.-S. Yang, N. Nicolici and A. Veneris Efficient and Accurate Method for Intra-Gate Defect Diagnoses in Nanometer Technology and Volume Data ............................................................................................................................................. 988 A. Ladhar, M. Masmoudi and L. Bouzaida Selection of a Fault Model for Fault Diagnosis Based on Unique Responses.......................................... 994 I. Pomeranz and S.M. Reddy Improving Compressed Test Pattern Generation for Multiple Scan Chain Failure Diagnosis ................ 1000 X. Tang, R. Guo, W.-T. Cheng and S.M. Reddy 8.6 Embedded Application Development and Verification Moderators: S. Hutcheson, Rolls-Royce, UK; W. Ecker, Infineon Technologies, DE A Case Study in Distributed Deployment of Embedded Software for Camera Networks ....................... 1006 F. Leonardi, A. Pinto and L.P. Carloni pTest: An Adaptive Testing Tool for Concurrent Software on Embedded Multicore Processors ........... 1012 S.-W. Chang, K.-Y. Hsieh and J.K. Lee A Generic Platform for Estimation of Multi-Threaded Program Performance on Heterogeneous Multiprocessors ....................................................................................................................................... 1018 A. Sahu, M. Balakrishnan and P.R. Panda Networked Embedded System Applications Design Driven by an Abstract Middleware Environment ............................................................................................................................................ 1024 F. Fummi, G. Perbellini and N. Roncolato 8.7 HOT TOPIC – Health-Care Electronics: The Market, The Challenges, The Progress Organizers/Moderators: G. Gielen, KU Leuven, BE; W. Eberle, IMEC, BE Health-Care Electronics: The Market, the Challenges, the Progress .................................................... 1030 W. Eberle, A.S. Mecheri, T.K.T. Nguyen, G. Gielen, R. Campagnolo, A. Burdett, C. Toumazou and B. Volckaerts

8.8 INVITED INDUSTRIAL SESSION – Industrial System Designs in Multimedia and Communication Moderators: C. Heer, Infineon Technologies, DE; L. Fanucci, Pisa U, IT Design and Implementation of Scalable, Transparent Threads for Multi-Core Media Processor........... 1035 T. Kodaka, S. Sasaki, T. Tokuyoshi, R. Ohyama, N. Nonogaki, K. Kitayama, T. Mori, Y. Ueda, H. Arakida, Y. Okuda, T. Kizu, Y. Tsuboi and N. Matsumoto High Data Rate Fully Flexible SDR Modem ............................................................................................ 1040 F. Kasperski, O. Pierrelee, F. Dotto and M. Sarlotte Cross-Coupling in 65nm Fully Integrated EDGE System on Chip - Design and Cross-Coupling Prevention of Complex 65nm SoC .......................................................................................................... 1045 P.-H. Bonnaud and G. Sommer 9.1 EMBEDDED TUTORIAL – Understanding Multicore Technologies .......................................... 1051 Organizer: A Jerraya, CEA-LETI, FR Moderators: G. Nicolescu, Polytechnique Montreal, CA; A. Jerraya, CEA-LETI, FR 9.2 NoC Performance Optimization Moderators: F. Angiolini, iNOCs; D. Atienza, Madrid Complutense U, ES Latency Criticality Aware On-Chip Communication ................................................................................ 1052 Z. Li, J. Wu, L. Shang, R.P. Dick and Y. Sun In-Network Reorder Buffer to Improve Overall NoC Performance While Resolving the In-Order Requirement Problem ............................................................................................................................. 1058 W.-C. Kwon, S. Yoo, J. Um and S.-W. Jeong An Efficent Dynamic Multicast Routing Protocol for Distributing Traffic in NoCs .................................... 1064 M. Ebrahimi, M. Daneshtalab, M.H. Neishaburi, S. Mohammadi, A. Afzali-Kusha, J. Plosila and H. Tenhunen Priority Based Forced Requeue to Reduce Worst Case Latencies for Bursty Traffic ............................ 1070 M. Millberg and A. Jantsch 9.3 Automotive Networks, Sensing and Communication Moderators: L. Fanucci, Pisa U, IT; O. Bringmann, FZI Forschungszentrum Informatik, DE Optimizations of an Application-Level Protocol for Enhanced Dependability in FlexRay ....................... 1076 W. Li, M. Di Natale, W. Zheng, P. Giusto, A. Sangiovanni-Vincentelli and S.A. Seshia Remote Measurement of Local Oscillator Drifts in FlexRay Networks ................................................... 1082 E. Armengaud and A. Steininger CAN+: A New Backward-Compatible Controller Area Network (CAN) Protocol with up to 16x Higher Data Rates ................................................................................................................................... 1088 T. Ziermann, S. Wildermann and J. Teich Shock Immunity Enhancement via Resonance Damping in Gyroscopes for Automotive Applications ............................................................................................................................................. 1094 E. Marchetti, L. Fanucci, A. Rocchi and M. De Marinis Integration of an Advanced Emergency Call Subsystem into a Car-Gateway Platform ......................... 1100 N. Martínez Madrid, R. Seepold, A. Reina Nieves, J. Saez Gomez, A. los Santos Aransay, P. Sanz Velasco, C. Rueda Morales and F. Ares

9.4 Architectural Synthesis Moderators: P. Ienne, EPF Lausanne, CH; R. Kastner, UC San Diego, US Finite Precision Bit-Width Allocation Using SAT-Modulo Theory ............................................................ 1106 A.B. Kinsman and N. Nicolici HLS-l: High-Level Synthesis of High Performance Latch-Based Circuits ............................................... 1112 S. Paik, I. Shin and Y. Shin Automatic Generation of Streaming Datapaths for Arbitrary Fixed Permutations .................................. 1118 P.A. Milder, J.C. Hoe and M. Pueschel SEU-Aware Resource Binding for Modular Redundancy Based Designs on FPGAs ............................ 1124 S. Golshan and E. Bozorgzadeh 9.5 Advances in Test Pattern Generation Moderators: H. Obermeir, Infineon, DE; N. Nicolici, McMaster U, CA Generation of Compact Test Sets with High Defect Coverage ............................................................... 1130 X. Kavousianos and K. Chakrabarty A Scalable Method for the Generation of Small Test Sets ...................................................................... 1136 S. Remersaro, J. Rajski, S.M. Reddy and I. Pomeranz QC-Fill: An X-Fill Method for Quick-and-Cool Scan Test ........................................................................ 1142 C.-W. Tzeng and S.-Y. Huang 9.6 Model-Based Design for Embedded Systems Moderators: P. Mosterman, The MathWorks, US ; E. Villar, Cantabria U, ES Exploring Parallelizations of Applications for MPSoC Platforms Using MPA ......................................... 1148 R. Baert, E. Brockmeyer, S. Wuytack and T.J. Ashby An MDE Methodology for the Development of High-Integrity Real-Time Systems................................. 1154 S. Mazzini, S. Puri and T. Vardanega Mode-Based Reconfiguration of Critical Software Component Architectures ........................................ 1160 E. Borde, G. Haik and L. Pautet Towards a Formal Semantics for the AADL Behavior Annex ................................................................. 1166 Z. Yang, K. Hu, D. Ma and L. Pi 9.7 Efficient Reduction of Cell and Interconnect Models Moderators: W. Schilders, NXP Semiconductors, NL ; L. Silveira, INESC ID / IST – TU Lisbon, PT On the Efficient Reduction of Complete EM Based Parametric Models ................................................. 1172 J. Fernandez Villena, G. Ciuprina, D. Ioan and L.M. Silveira Efficient Compression and Handling of Current Source Model Library Waveforms ............................... 1178 S. Hatami, P. Feldmann, S. Abbaspour and M. Pedram New Simulation Methodology of 3D Surface Roughness Loss for Interconnects Modeling ................... 1184 Q. Chen and N. Wong

An Efficient Decoupling Capacitance Optimization Using Piecewise Polynomial Models ...................... 1190 X. Wang, Y. Cai, S. X.-D. Tan, X. Hong and J. Relles 9.8 INVITED INDUSTRIAL SESSION – Industrial System Design Flow Moderators: M. Coppola, STMicroelectronics, FR; L. Fanucci, Pisa U, IT An Automated Flow for Integrating Hardware IP into the Automotive Systems Engineering Process.................................................................................................................................................... 1196 J.H. Oetjens, R. Goergen, J. Gerlach and W. Nebel Model Based Design Needs High Level Synthesis - A Collection of High Level Synthesis Techniques to Improve Productivity and Quality of Results for Model Based Electronic Design ........... 1202 S. Perry EMC-Aware Design on a Microcontroller for Automotive Applications ................................................... 1208 P.J. Doriol, Y. Villavicencio, C. Forzan, M. Rotigni, G. Graziosi and D. Pandini IP4 Interactive Presentations Semiformal Verification of Temporal Properties in Automotive Hardware Dependent Software ............ 1214 D. Lettnin, P.K. Nalla, J. Behrend, J. Ruf, J. Gerlach, T. Kropf, W. Rosenstiel, V. Schoenknecht and S. Reitemeyer On the Relationship between Stuck-At Fault Coverage and Transition Fault Coverage ........................ 1218 J. Schat System-Level Hardware-Based Protection of Memories against Soft-Errors ......................................... 1222 V. Gherman, S. Evain, M. Cartron, N. Seymour and Y. Bonhomme A Study of the Single Event Effects Impact on Functional Mapping within Flash-Based FPGAs........... 1226 F. Abate, L. Sterpone, M. Violante and F. Lima Kastensmidt Finite Precision Processing in Wireless Applications .............................................................................. 1230 D. Novo, M. Li, B. Bougard, L. Van der Perre and F. Catthoor A Physical-Location-Aware X-Filling Method for IR-Drop Reduction in At-Speed Scan Test ................. 1234 W.-W. Hsieh, I.-S. Lin and T. Hwang Efficient Reliability Simulation of Analog ICs Including Variability and Time-Varying Stress ................. 1238 E. Maricau and G. Gielen A Generic Architecture of CCSDS Low Density Parity Check Decoder for Near-Earth Applications ............................................................................................................................................. 1242 F. Demangel, N. Fau, N. Drabik, F. Charot and C. Wolinski Property Analysis and Design Understanding ....................................................................................... 1246 U. Kuehne, D. Grosse and R. Drechsler Test Exploration and Validation Using Transaction Level Models .......................................................... 1250 M.A. Kochte, C.G. Zoellin, M.E. Imhof, R. Salimi Khaligh, M. Radetzki, H.-J. Wunderlich, S. Di Carlo and P. Prinetto

10.1.1 Multicore Products for Mass Market Applications Organizer: P. Van der Wolf, NXP Semiconductors, NL Moderators: D. Lattard, CEA-LETI, FR; P. Van der Wolf, NXP Semiconductors, NL Heterogeneous Multi-Core Platform for Consumer Multimedia Applications .......................................... 1254 P. Kollig, C. Osborne and T. Henriksson Multi-Core for Mobile Phones .................................................................................................................. 1260 C.H. (K) van Berkel 10.1.2 Keynote Organizers/Moderators: A. Jerraya, CEA-LETI, FR; P. Van der Wolf, NXP Semiconductors, NL Strategic Directions towards Multicore Application Specific Computing ................................................. 1266 E. Flamand 10.2 Emerging Computation Models and Systems Moderators: H. Patel, UC Berkeley, US; D. Chen, U of Illinois, Urbana Champaign, US Energy-Efficient Spatially-Adaptive Clustering and Routing in Wireless Sensor Networks .................... 1267 H. Long, Y. Liu, X. Fan, R.P. Dick and H. Yang Online Adaptation Policy Design for Grid Sensor Networks with Reconfigurable Embedded Nodes ...................................................................................................................................................... 1273 V. Subramanian, M. Gilberti and A. Doboli Defect-Aware Logic Mapping for Nanowire-Based Programmable Logic Arrays via Satisfiability ......... 1279 Y. Zheng and C. Huang Debugging of Toffoli Networks ................................................................................................................ 1284 R. Wille, D. Grosse, S. Frehse, G.W. Dueck and R. Drechsler Cross-Contamination Avoidance for Droplet Routing in Digital Microfluidic Biochips ............................ 1290 Y. Zhao and K. Chakrabarty 10.3 Efficient Forward Error Correction and Signal Processing Implementations Moderators: A. Baghdadi, Telecome Bretagne, FR; W. Eberle, IMEC, BE Error Correction in Single-Hop Wireless Sensor Networks - A Case Study ........................................... 1296 D. Schmidt, M. Berning and N. Wehn Design of an Application-Specific Instruction Set Processor for High-Throughput and Scalable FFT ........................................................................................................................................... 1302 X. Guan, H. Lin and Y. Fei A Novel LDPC Decoder for DVB-S2 IP ................................................................................................... 1308 S. Mueller, M. Schreger, M. Kabutz, M. Alles, F. Kienle and N. Wehn A Flexible Floating-Point Wavelet Transform and Wavelet Packet Processor ....................................... 1314 A. Guntoro and M. Glesner

10.4 Bursting Performance in Simulation and Debugging Moderators: F. Fummi, Verona U, IT; M. Zwolinski, Southampton U, UK On Hierarchical Statistical Static Timing Analysis ................................................................................... 1320 B. Li, N. Chen, M. Schmidt, W. Schneider and U. Schlichtmann Increasing the Accuracy of SAT-Based Debugging ................................................................................ 1326 A. Suelflow, G. Fey, C. Braunstein, U. Kuehne and R. Drechsler GCS: High-Performance Gate-Level Simulation with GP-GPUs ............................................................ 1332 D. Chatterjee, A. DeOrio and V. Bertacco Trace Signal Selection for Visibility Enhancement in Post-Silicon Validation ......................................... 1338 X. Liu and Q. Xu 10.5.Design-for-Test and Diagnosis Moderators: J. Schloeffel, Mentor Graphics, DE; G. Dintale, LIRMM, FR A New Design-for-Test Technique for SRAM Core-Cell Stability Faults ................................................ 1344 A. Ney, L. Dilillo, P. Girard, S. Pravossoudovitch, A. Virazel, M. Bastian and V. Gouin Test Cost Reduction for Multiple-Voltage Designs with Bridge Defects through Gate-Sizing ................ 1349 S. Khursheed, B.M. Al-Hashimi and P. Harrod A Diagnosis Algorithm for Extreme Space Compaction .......................................................................... 1355 S. Holst and H.-J. Wunderlich 10.6 Memory-Aware Compiler Techniques Moderators: C. Haubelt, Erlangen-Nuremberg U, DE; D. Gajski, UC Irvine, US Thermal-Aware Memory Mapping in 3D Designs ................................................................................... 1361 A.-C. Hsieh and T. Hwang Static Analysis to Mitigate Soft Errors in Register Files .......................................................................... 1367 J. Lee and A. Shrivastava Using Dynamic Compilation for Continuing Execution under Reduced Memory Availability .................. 1373 O. Ozturk and M. Kandemir 10.7 Mixed-Signal and Mixed Technology Design Moderators: M. Ortmanns, Ulm U, DE; C. Grimm, TU Vienna, AT A Design Methodology for Fully Reconfigurable Delta-Sigma Data Converters ..................................... 1379 Y. Ke, J. Craninckx and G. Gielen Optimal Sizing of Configurable Devices to Reduce Variability in Integrated Circuits ............................. 1385 P. Wilson and R. Wilcock An Automated Design Flow for Vibration-Based Energy Harvester Systems ......................................... 1391 L. Wang, T.J. Kazmierski, B.M. Al-Hashimi, S.P. Beeby and D. Zhu Enhanced Design of Filterless Class-D Audio Amplifier ......................................................................... 1397 C.W. Lin, B.-S. Hsieh and Y.C. Lin

11.1 PANEL SESSION – Multicore, Will Startups Drive Innovation? ............................................. 1403 Organizer: A. Jerraya, CEA-LETI, FR Moderator: R. Ernst, TU Braunschweig, DE Panelists: N. Topham, D. Pulley, M. Harrand, J. Goodacre, G. Martin and Y. Tanurhan 11.2 High-Level Power and Thermal Management Moderators: T. Ishihara, Kyushu U, JP ; B. Mishra, Southampton U, UK Effectiveness of Adaptive Supply Voltage and Body Bias as Post-Silicon Variability Compensation Techniques for Full-Swing and Low-Swing On-Chip Communication Channels .................................... 1404 G. Paci, D. Bertozzi and L. Benini Dynamic Thermal Management in 3D Multicore Architectures ............................................................... 1410 A.K. Coskun, J. Ayala, D. Atienza, T. Simunic Rosing and Y. Leblebici Energy Minimization for Real-Time Systems with Non-Convex and Discrete Operation Modes ........... 1416 F. Dabiri, A. Vahdatpour, M. Potkonjak and M. Sarrafzadeh Exploiting Narrow-Width Values for Thermal-Aware Register File Designs ........................................... 1422 S. Wang, J. Hu, S.G. Ziavras and S. W. Chung 11.3 Efficient Implementations for Media Processing Moderators: K. Goossens, NXP Semiconductors and TU Delft, NL; C. Bouganis, Imperial College London, UK Visual Quality Analysis for Dynamic Backlight Scaling in LCD Systems ................................................ 1428 A. Bartolini, M. Ruggiero and L. Benini A Parallel Approach for High Performance Hardware Design of Intra Prediction in H.264/AVC Video Codec ............................................................................................................................................ 1434 M. Shafique, L. Bauer and J. Henkel Efficient Constant-Time Entropy Decoding for H.264 ............................................................................. 1440 N. Iqbal and J. Henkel Predictive Models for Multimedia Applications Power Consumption Based on Use-Case and OS Level Analysis ................................................................................................................................... 1446 P. Bellasi, W. Fornaciari and D. Siorpaes 11.4 Decomposition and Restructuring Techniques for Logic Synthesis Moderators: S. Nowick, Columbia U, US ; F. Fummi, Verona U, IT Algebraic Techniques to Enhance Common Sub-Expression Elimination for Polynomial System Synthesis ................................................................................................................................................. 1452 S. Gopalakrishnan and P. Kalla Sequential Logic Synthesis Using Symbolic Bi-Decompsition ................................................................ 1458 V.N. Kravets and A. Mishchenko On Decomposing Boolean Functions via Extended Cofactoring ............................................................ 1464 A. Bernasconi, V. Ciriani, G. Trucco and T. Villa Register Placement for High-Performance Circuits ................................................................................ 1470 M.-F. Chiang, T. Okamoto and T. Yoshimura

11.5 Test Data Compression Moderators: J. Vial, Infineon, FR; T. Yoneda, Nara Institute of Science and Technology, JP Scalable Adaptive Scan (SAS) ............................................................................................................... 1476 A. Chandra, R. Kapur and Y. Kanzawa LFSR-Based Test-Data Compression with Self-Stoppable Seeds ......................................................... 1482 M. Koutsoupia, E. Kalligeros, X. Kavousianos and D. Nikolos Seed Selection in LFSR-Reseeding-Based Test Compression for the Detection of Small-Delay Defects .................................................................................................................................................... 1488 M. Yilmaz and K. Chakrabarty A Generic Framework for Scan Capture Power Reduction in Fixed-Length Symbol-Based Test Compression Environment ...................................................................................................................... 1494 X. Liu and Q. Xu 11.6 Automating Model Generation and Implementation Moderators: A. Gerstlauer, U of Texas at Austin, US; D. Borrione, TIMA Laboratory, FR Correct-by-Construction Generation of Device Drivers Based on RTL Testbenches ............................. 1500 N. Bombieri, F. Fummi, G. Pravadelli and S. Vinco Buffer Minimization of Real-Time Streaming Applications Scheduling on Hybrid CPU/FPGA Architectures ........................................................................................................................................... 1506 J. Zhu, I. Sander and A. Jantsch A Formal Approach for Specification-Driven AMS Behavioral Model Generation .................................. 1512 S.Mukherjee, A. Ain, S.K. Panda, R. Mukhopadhyay and P. Dasgupta SC-DEVS: An Efficient SystemC Extension for the DEVS Model of Computation ................................. 1518 F. Madlener, H.G. Molter and S.A. Huss 11.7 Advances in Field Programmable Architectures and Applications Moderators: P. Lysaght, Xilinx, US; K. Bertels, TU Delft, NL Exploiting Clock Skew Scheduling for FPGA .......................................................................................... 1524 S. Bae, P. Mangalagiri and N. Vijaykrishnan Accelerating FPGA-Based Emulation of Quasi-Cyclic LDPC Codes with Vector Processing ................ 1530 X. Chen, J. Kang, S. Lin and V. Akella Runtime Reconfiguration of Custom Instructions for Real-Time Embedded Systems ........................... 1536 H.P. Huynh and T. Mitra 11.8 HOT TOPIC – Digital Design at a Crossroads – How to Make Statistical Design Industrially Relevant Organizer/Moderator: M. Dietrich, Fraunhofer IIS/EAS Dresden, DE Digital Design at a Crossroads – How to Make Statistical Design Methodologies Industrially Relevant .................................................................................................................................................. 1542 U. Schlichtmann, M. Schmidt, M. Pronath, V. Gloeckel, H. Kinzelbach, M. Dietrich, U. Eichler and J. Haase

IP5 Interactive Presentations Performance Optimal Speed Control of Multi-Core Processors under Thermal Constraints ................. 1548 V. Hanumaiah, S. Vrudhula and K.S. Chatha Scalable Compile-Time Scheduler for Multi-Core Architectures ............................................................. 1552 M. Pelcat, P. Menuet, S. Aridhi and J.-F. Nezan Distributed Peak Power Management for Many-Core Architectures ...................................................... 1556 J. Sartori and R. Kumar Generating the Trace Qualification Configuration for MCDS from a High Level Language ................... 1560 J. Braunes and R.G. Spallek Dynamic and Distributed Frequency Assignment for Energy and Latency Constrained MP-SoC ......... 1564 D. Puschini, F. Clermidy, P. Benoit, G. Sassatelli and L. Torres A MILP-Based Approach to Path Sensitization of Embedded Software ................................................. 1568 J.C. Costa and J.C. Monteiro An Efficient and Deterministic Multi-Tasking Run-Time Environment for Ada and the Ravenscar Profile on the Atmel AVR ®32 UC3 Microcontroller ............................................................................... 1572 K. Nyborg Gregertsen and A. Skavhaug Toward a Runtime System for Reconfigurable Computers: A Virtualization Approach .......................... 1576 M. Sabeghi and K. Bertels Separate Compilation and Execution of Imperative Synchronous Modules ........................................... 1580 E. Vecchie, J.-P. Talpin and K. Schneider 12.1 PANEL SESSION – Programming MPSoC Platforms: Roadworks Ahead! Organizer: R. Leupers, RWTH Aachen U, DE Moderator: M. de Lange, ACE, NL Programming MPSoC Platforms: Road Works Ahead! ......................................................................... 1584 R. Leupers, S. Ha, A. Vajda, R. Doemer, M. Bekooij and A. Nohl 12.2 Advanced SAT Techniques Moderators: J. Baumgartner, IBM Corporation, US ; G. Cabodi, Politecnico di Torino, IT Faster SAT Solving with Better CNF Generation .................................................................................... 1590 B. Chambers, P. Manolios and D. Vroon Exploiting Structure in an AIG Based QBF Solver .................................................................................. 1596 F. Pigorsch and C. Scholl An Efficient Path-Oriented Bitvector Encoding Width Computation Algorithm for Bit-Precise Verification ............................................................................................................................................... 1602 N. He and M.S. Hsiao

12.3 Baseband Processors for MIMO and UWB Communication Systems Moderators: F. Kienle, TU Kaiserslautern, DE; W. Eberle, IMEC, BE Algorithm-Architecture Co-Design of Soft-Output ML MIMO Detector for Parallel Application Specific Instruction Set Processors ......................................................................................................... 1608 M. Li, R. Fasthuber, D. Novo, B. Bougard, L. Van Der Perre and F. Catthoor A Low-Power ASIP for IEEE 802.15.4a Ultra-Wideband Impulse Radio Baseband Processing ............ 1614 C. Bachmann, A. Genser, J. Hulzink, M. Berekovic and C. Steger ASIP-Based Flexible MMSE-IC Linear Equalizer for MIMO Turbo-Equalization Applications ............... 1620 A.R. Jafri, D. Karakolah, A. Baghdadi and M. Jezequel Implementation of a Reduced-Lattice MIMO Detector for OFDM Systems ............................................ 1626 J. Soler-Garrido, H. Vetter, M. Sandell, D. Milford and A. Lillie 12.4 System Level Simulation and Validation Moderators: I. Harris, UC Irvine, US; V. Bertacco, U of Michigan, US Increased Accuracy through Noise Injection in Abstract RTOS Simulation ............................................ 1632 H. Zabel and W. Mueller Flexible Energy-Aware Simulation of Heterogeneous Wireless Sensor Networks ................................. 1638 F. Fummi, G. Perbellini, D. Quaglia and A. Acquaviva Selective State Retention Design Using Symbolic Simulation ................................................................ 1644 A. Darbari, B.M. Al-Hashimi, D. Flynn and J. Biggs 12.5 Mixed-Signal/RF Testing and DFX Engineering Moderators: J. Machado da Silva, INESC, PT; C. Wegener, Infineon Technologies, DE A Loopback-Based INL Test Method for D/A and A/D Converters Employing a Stimulus Identification Technique .......................................................................................................................... 1650 E. Korhonen and J. Kostamovaara A Novel Self-Healing Methodology for RF Amplifier Circuits Based on Oscillation Principles ............... 1656 A. Goyal, M. Swaminathan and A. Chatterjee An Approach to Linear Model-Based Testing for Nonlinear Cascaded Mixed-Signal Systems ............. 1662 R. Mueller, C. Wegener, H.-J. Jentschel, S. Sattler and H. Mattes Enrichment of Limited Training Sets in Machine-Learning-Based Analog/RF Test ................................ 1668 H.-G. Stratigopoulos, S. Mir and Y. Makris 12.6 Accelerating Verification through Transformation and Abstraction Moderators: J. Marques-Silva, Southampton U, UK; R. Bloem, TU Graz, AT Speculative Reduction-Based Scalable Redundancy Identification ....................................................... 1674 H. Mony, J. Baumgartner, A. Mishchenko and R. Brayton Scalable Liveness Checking via Property-Preserving Transformations ................................................. 1680 J. Baumgartner and H. Mony Speeding up Model Checking by Exploiting Explicit and Hidden Verification Constraints ..................... 1686 G. Cabodi, P. Camurati, L. Garcia, M. Murciano, S. Nocco and S. Quer

Strengthening Properties Using Abstraction Refinement ........................................................................ 1692 M. Purandare, T. Wahl and D. Kroening 12.7 Advances in Multi-Cycle Design and Optimization Moderators: M. Fujita, Tokyo U, JP; V. Kravets, IBM, US Sequential Logic Rectifications with Approximate SPFDs ...................................................................... 1698 Y.-S. Yang, S. Sinha, A. Veneris, R.K. Brayton and D. Smith Variable-Latency Design by Function Speculation ................................................................................. 1704 D. Baneres, J. Cortadella and M. Kishinevsky Fixed Points for Multi-Cycle Path Detection ............................................................................................ 1710 V. D'Silva and D. Kroening Author Index