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8/14/2019 20080701-220- IC
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SUNPLUS
19, Innovation Road I, SIP Hsin Chu 300 Taiwan, R.O.C.
Tel:886-3-5786005 Fax:886-3-5786006http://www.sunplus.com.tw
IC
IC
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IC IC
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IC IC
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I
IC
Integrated Device Manufacturer IDM
Fabless Foundry
Packaging Testing
IC
Implement CAD EDA Vendor Algorithm
ASIC/Design ServiceASIC
COT
Intel,AMD, Lucent,
LSI, Philips,
, .
IDM=Design+Fab
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II
ICu (Algorithm? RTL Coding ? Board? Design Flow?)u Front end / ASIC Serviceu IP
IC u u u
u EDA tool u u
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III Algorithmu SPW/Matlabu C/C++/HDL
Custom Own Tool(COT)
ASIC/Design HouseNetlistFrontEn
dDesi
gnOn
ly
Back end tools
Design Implementationu Verilog/VHDL (HDL)u RTL codingu Schematic Entry
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IC IC
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IC I
IC
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Design Flow
IC II In-House ToolEDA Vendor Tool
In-House Tool
In-House Tool
In-House Tool
EDA Vendor Tool
EDA Standard format
EDA Vendor Tool
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IC III CAD u u u u u
u u
...
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IC IC
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I
uu3C u Microsoft Intel
u
uuu
uu
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II
u IP Reuse Internally u IP Reuse in every possible
case u
IP/Design Outsourcing
uu Design Methodology u /
uu Implementation uu CAD People Design Flow
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III Bottom-Up / Full Custom Designu Schematic Entry Circuit Simulation Manually Layout Post-Layout Simulation
Physical Verification, DRC/ERC/LVS Tape Out
u
u IC
http://c/Documents%20and%20Settings/Administrator/Local%20Settings/Temporary%20Internet%20Files/Content.IE5/C92BKHUJ/cir.jpg8/14/2019 20080701-220- IC
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IV Top-Down Designu Logic Synthesis Logic Simulation
Auto Place & Route, inc, CTS
Static Timing Analysis
Formal Verification InPlace/Timing Optimization, ECO Physical Verification, DRC/ERC/LVS Tape Out
IC
u EDA tool uIC
RTL coding u IC CAD
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IV
Top-Down / APR
Std. cells IOcells APR
Analog
SRAM
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IC IC
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IC IuCPU/DSP/IP/Top-Down Design Engineeru Circuit Design engineeru Layout Engineeru Application Engineeru
CAD EDA/CAD Engineer
u
u System Engineeru Sales Representative u Marketing u Planneru Production Managment u
Product Engineeru .. etc Administration, HR, Finance...
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IC IC
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Top-Down Design EE u / / RTL code EE C/C++ design
flow uEE / EE u 5 uu 5 u
uu ?u debug
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IC IC
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Q A