20070123 FPGAs in a nutshell - RWTH Aachen University · 2009-05-05use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity Timer is Port ... VHDL Code Blink_LED: process

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FPGAs in a Nutshell- Introduction to Embedded Systems-

Dipl.- Ing. Falk Salewski

Lehrstuhl Informatik 11RWTH Aachen

[email protected]

Winter term 06/07

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Contents

HistoryFPGA architectureHardware description languagesVHDLMicrocontroller vs. FPGAFPGA Application AreasSoft CoresOutlook: next lecture

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Programmable logic basics

You can do a lot with just AND- and OR-gates!In the late 70s systems were built with Standard Discrete Logic (fixed function devices where connected together to implement a system)

Idea to reduce space and increase flexibility:

- One chip with two programmable planes

- Provide any combination of „AND“and „OR“ gates, as well as sharing of AND terms across multiple ORs.

- Umbrella term: PLDs

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PLD (CPLD & FPGA)

PLDs = Devices which can be re-programmed to implement any function within the device‘s resources

Complex ProgrammableLogic Device

Field ProgrammableGate Array

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Xilinx Spartan-III Architecture

IOB = Input/Output Block (interface between the package pins and the internal logic)

CLB = Configurable Logic Block (provides functional elements for constructing logic)

DCM = Digital Clock Manager (clock domain control)

FPGA

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Configurable Logic Block (CLB)

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Spartan-IIIArchitecture (3)

Slice- Look Up Tables(LUTs)

for combinatorial logic

- FlipFlopsfor clocked logic

- Control Logicas multiplexers,carry logic, …

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Look Up Tables (LUTs)

LUT = small RAM

Example: AND-Gate (2 input LUT)

Data : function is stored in SRAM (other devices with Flash or Anti fuse available)

LUTs in Spartan family have 4 inputs, the LUTs of two slices can be combined.

A 4-input LUT allows to generate 2^2^4 = 65536 different functions.

DataAddress

111010001000

2 bit input

(address)

1 bitoutput(data)

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Look Up Tables (cont.)

2-input LUT:

2^2=4 input combinations 2^4 different functions possible

4-input LUT:2^4=16 input combinations 2^16 different functions possible

101010101010101011

110011001100110010

111100001111000001

111111110000000000

Output (possible functions)Input

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Spartan III Architecture (4)

Up to 8320 CLBs How many slices?4 x 8320 = 33280 slices!

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Configure the FPGA

Does every component has to be configured on this low level?

No!

FPGAs can be programmed on a higher level with various Hardware Description Languages (HDL).

The Translation to Gate Level is done by tools automatically

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Principle: Design Hardware as if it is Software

Software Design(Microcontroller)1. Specification2. Implementation (e.g.: C or

assembly)

3. Compilation to machine code

4. Load code in program memory of target

5. Functionality is realized by execution of code by CPU(CPU can use certain peripherals as timers )

Hardware Design(CPLD / FPGA)1. Specification2. Implementation in HDL

- Structural description- Behavioral description

3. Automatic transformation in Gate Level Description (Synthesis)

4. Load configuration in target

5. Functionality is implemented in hardware

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Hardware Description Languages (HDLs)

Most important HDL:- VHDL

• Syntax similar to ADA • Mostly used in Europe

- Verilog• Syntax similar to C• Mostly used in USA

- SystemC• C++ library for hardware specific constructs• Quite young, good for Simulation, synthesis still problematic

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VHDL

VHSIC Hardware Description LanguageVHSIC = Very High Speed Integrated Circuits

This VHDL subset is not standardized!

VHDL

VHDL subset

Allows descriptionand simulation of

hardware (original purpose)

Allows automatic synthesis to gate level description

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VHDL crash course

Basic constructs:- Entity: specifies inputs and outputs of each module- Architecture: specifies the structure or the behavior of a

module- Process: can be used for description of the behavior- Signal: can be understood as physical connections - Variable: can be understood as memory cell

Control structures like in other higher programming languages are available.

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VHDL Example

A simple 4bit Timer

clk

reset

countervalue(3:0)

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VHDL Examplelibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Timer isPort ( clk : in std_logic;

reset : in std_logic;countervalue : inout std_logic_vector(3 downto 0));

end Timer;

architecture Behavioral of Timer isbegin

process (clk,reset)begin

if reset='1' thencountervalue <= "0000";

elsif rising_edge(clk) thencountervalue <= countervalue + 1;

end if;end process;

end Behavioral;

entity

architecture

process

clk

resetCounter-

value(3:0)Timer 4bit

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VHDL Exampleentity Timer is

Port ( clk : in std_logic;reset : in std_logic;countervalue : inout std_logic_vector(3 downto 0));

end Timer;





end if;end process;

end Behavioral;

entity

architecture

process

clk

resetCounter-


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VHDL Entity entity Timer is


end Timer;

entity

Defines I/O signals (Ports) of the module:

- in read only- out write only- inout write and read back- buffer write and read (bidirectional)

Ports can be - binary signals (as clk: 1bit)- vectors of signals (as countervalue: 4bit)

Data type of Ports: usually std_logic (later more)

clk

resetCounter-


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end Timer;





end if;end process;

end Behavioral;

entity

architecture

process

clk

resetCounter-


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VHDL Process


process (clk,reset) -- sensitivity list: changing of clk or reset starts processbegin -- (only for clarity, all input values “start” process)

if reset='1' thencountervalue <= "0000"; -- assign initial value

elsif rising_edge(clk) then -- if rising edge of clk signal thencountervalue <= countervalue + 1; -- increment

end if;end process;

end Behavioral;

architecture

clk

resetCounter-


A process is used to describe the behavior of the timer

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end Timer;


Timer: process (clk,reset)begin



end if;end process;

end Behavioral;

entity

architecture

process

clk

resetCounter-


Name can begiven to process

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Data type std_logic (9-value logic type)- Possible values :

• ‘U‘ – uninitialized• ‘X‘ – undefined• ‘0‘ – forcing 0• ‘1‘ – forcing 1• ‘Z‘ – high impedance• ‘W‘ – weak undefined• ‘L‘ – weak 0• ‘H‘ – weak 1 • ‘-‘ – don‘t care

- Signals can be grouped to vector: std_logic_vector(3 downto 0)

Other data types as boolean or integer are known- Can be used for arithmetics only- Usually, subtypes are usefull (integer is 64 bit!)

VHDL Data types

Needed if bus structures have to be realized

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Process 3

Process 2

Process 1

VHDL Architecture

architecture Behavioral of Example_Modul isbegin

TaskA: process (clk,reset)begin

…end process;

TaskB: process (clk,reset,in1)begin

…end process;

out <= in1 and in2;

end Behavioral;

Execution

outside process: parallel

inside process: “sequential”

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Questions?

What is an entity?- What is std_logic?- What is std_logic_vector?

What is an architecture?- How are processes executed within an architecture?

What is a process?- When is a process “executed“?- How is a process executed?

let‘s have a closer look at sequential execution

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Sequential execution (blink two LEDs)

Microcontroller Code

Void blink_LED (int delay){int i=0;PORTA1 = 0;for (i = 0, i<delay, i++);PORTA1 = 1;PORTA2 = 0;for (i = 0, i<delay, i++);PORTA2 = 1;}

Probably working

VHDL Code

Blink_LED: process (delay)variable i : integer:= 0;

beginPORTA1 <= ‘0‘;for i in 0 to delay loop i:=i+1; end loop;PORTA1 <= ‘1‘;PORTA2 <= ‘0‘;for i in 0 to delay loop i:=i+1; end loop;PORTA2 <= ‘1‘;

end process;

The last signal assignment is takenNo delay (no clk) LEDs stay off

Note: variables are assigned with := and signals with <=

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Sequential Execution (2)State machines have to be used to realize clocked sequential behavior!

Blink_LED: process (clk, reset)variable state : std_logic_vector;beginif reset = ‚1‘ then state :=“00“; PORTA1 <=‘1’; PORTA2 <=‘1’; elsif rising_edge(clk) thencase state is

when "00" => PORTA1 <=‘0’; when "01" => PORTA1 <=‘1’; PORTA2 <=‘0’; when "10" => PORTA2 <=‘1’;when others =>

end case;state := state +1;

end if;end process;

Execution speed can be adjusted by clk, e.g. with a timer used as clock divider

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Parallel processes

Example: Frequency measurement (impulses/time unit)

TIMER: process (clk,reset)variable countervalue: std_logic_vector(3 downto 0)

beginif reset='1' then

countervalue <= "0000";elsif rising_edge(clk) then

countervalue <= countervalue + 1;if countervalue = “1110” then

Frequ <= globalcountglobalcount <= “00000000”

end if;end if;

end process;

COUNTER: process (count_in, reset)begin

if reset='1' thenglobalcount <= "00000000";

elsif rising_edge(count_in) thenglobalcount <= globalcount + 1;

end if;end process;

Conflict: globalcountcould be modified in both

processes at the same time! not allowed

FrequFrequ. measure

Clk

Reset

Count_in

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Parallel processes

Example (corrected): Frequency measurement

TIMER: process (clk,reset)variable countervalue: std_logic_vector(3 downto 0)

beginif reset='1' then

countervalue <= "0000";counter_reset <=‘1’;

elsif rising_edge(clk) thencountervalue <= countervalue + 1;if countervalue = “1110” then

Frequ <= globalcountelsif countervalue = “1111” then

counter_reset <=‘1’;else

counter_reset<=‘0’;end if;

end if;end process;

COUNTER: process (count_in, counter_reset)begin

if counter_reset =‘1’thenglobalcount <= "00000000";

elsif rising_edge(count_in) thenglobalcount <= globalcount + 1;

end if;end process;

FrequFrequ. measure

Clk

Reset

Count_in

Additional global signalcounter_reset is used

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Design in VHDL forget the hardware details?

Knowledge of the FPGA architecture is needed for- Optimization of execution speed- Optimization of chip resources needed (area)- Optimization of power consumption- The design of high reliable applications- Complex designs with several clock domains etc.

Tools constantly improve in order to- Support the designer with these issues and to- Automatize different types of optimizations

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ALTERA Design Flow

Source: www.altera.com

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MCU vs. FPGA (functional)

MCUSequential execution is easy- State machine with 100

states no problemLimited to on chip peripherals or on board peripherals- MCU has typically 3 to 5 on-

chip timerUnderstanding the MCU hardware might be a challenge

FPGAParallel execution is easy- Change 100 outputs at a

time no problemAll needed digital hardware in one device- 15 timer no problem

Configuring the FPGA hardware might be a challenge

Decision for the one or the other hardware is application dependent.

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FPGA application areas

Applications of FPGAs include- Digital Signal Processing, - Software Defined Radio (SDR), - Space, aerospace and defense systems, - ASIC prototyping, - Medical imaging, bioinformatics, - Computer vision, speech recognition, - Cryptography,- Computer hardware emulation, - High speed communication,and a growing range of other areas.

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CPULogic

Logic

Logic

FPGA

Soft Cores

In some cases a combination of MCU and FPGA features would be nice HW/SW CoDesignTodays FPGAs have enough resources to - synthesize CPU cores (Soft Cores)- together with parallel logic

These Soft Cores are usually available in VHDL or Verilogcode.

CPU

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Example: 8bit Xilinx Soft Core

For further information see: www.xilinx.com/picoblaze

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Xilinx Picoblaze

57 instructions16 registers (8bit)64 byte data memoryOn Spartan-3 up to 44MIPSResources needed: 96 Spartan-3 slices!

Theoretically, 346 Soft Cores would fit into the largest Spartan 3 (additional resources needed for interconnection)

Usually, the chip internal memory is the bottle neckmore and more FPGAs have additional block RAM

VHDL source code is available on www.xilinx.com/picoblaze

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Further Soft Cores

Altera: NiosII www.altera.com- 32-bit Harvard-RISC- Optional FPU (Floating Point Unit)- Up to 200MHz

Xilinx: Microblaze www.xilinx.com- 32-bit Harvard-RISC- Optional FPU (Floating Point Unit)- 900-2600 LUTs (450-1300 slices)- Up to 200MHz (up to 100MHz, 92 DMIPS on Spartan3)

Lattice: LatticeMico8 www.latticesemi.com- 8-bit Harvard-RISC- 275 LUTs

Chip independent cores from third party suppliers (e.g. 8051-derivatives)

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Next

Questions?

Contents of the next exercise

A comparison: Something to think about until next week

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In the exercise…

Create own VHDL programSimulate this programTest the program on Spartan 3 FPGAUse schematics as alternative programming method

Folie 40Programming cable to

parallel port

6 V

Access to FPGA-Pins CAN board

Jumper: M0&M2: offen, M1: geschlossen

Jumper: closed

LEDsconnectedto FPGA

Power supply forexternalboards

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VHDL sources

Free VHDL Online Tutorial: http://www.aldec.com/Downloads/The Hamburg VHDL archive http://tech-www.informatik.uni-hamburg.de/vhdl/VHDL Tutorial Uni Erlangen-Nürnberghttp://www.vhdl-online.de/tutorial/Online Support from the book „VHDL Eine Einführung“http://nirvana.informatik.uni-halle.de/Pearson/

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A comparison

During this semester you learned about different hardware platforms:- Microcontrollers (MCUs)- Programmable Logic Controllers (PLCs)- Field Programmable Gate Arrays (FPGAs)

What could influence your decision of hardware platform selection?

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Think about the Pro and Cons of the different hardware platforms

Documents

20070123 FPGAs in a nutshell - RWTH Aachen University · 2009-05-05use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity Timer is Port ... VHDL Code Blink_LED: process