2 PLL ARCHITECTURE IJSER · A Phase locked loop (PLL) is a closed loop frequency system that locks the phase of the output signal to the reference signal. The term ‘lock’ refers

International Journal of Scientific & Engineering Research, Volume 5, Issue 5, May-2014 45 ISSN 2229-5518

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Design and Performance Analysis of a Phase Locked Loop using Differential Voltage

Controlled Oscillator Sudatta Mohanty, Madhusmita Panda, Dr Ashis kumar Mal

Abstract— This paper is based on Phase locked-loop (PLL) using Differential Ring VCO in 350 nm CMOS Technology and illustrates the design process of various blocks of the PLL. The PLL is a closed loop system that compares the phase of an output signal with an input reference signal. PLLs are widely used in order to generate well-timed on-chip clocks to be used in high-performance digital systems. The entire circuit is implemented and simulated using Spice File and the tuning characteristics of the VCO was also verified from which the gain of the VCO was calculated . The estimated lock time of the PLL was found to be 10.02ns and the locking frequency was found to be 693 MHz and the gain of the VCO was estimated to be 120.5 MHz/V.

Index Terms— Phase Locked Loop, Phase Frequency Detector, Charge Pump, Voltage Controlled Oscillator, Loop Filter, Locked State, Unlocked State.

—————————— —————————— 1 INTRODUCTION

A Phase locked loop (PLL) is a closed loop frequency system that locks the phase of the output signal to the reference signal. The term ‘lock’ refers to a constant or zero phase difference between two signals. The basic block diagram of the PLL is shown in the Figure 1. It is a closed loop control system in which the output signal is synchronized with the input signal in terms of frequency and phase. The signal from the feedback path is compared with the input reference signal, until the two signals are locked. If there happens to be a phase difference, then it is called the unlocked state, and the signal is sent to each component in the loop to correct the phase difference.

fig 1. The Basic Block Diagram of a PLL

———————————————— • Sudatta Mohanty is currently pursuing masters degree program in VLSI

Design nd Embedded Systems in ITER, S’O’University, Bhubaneswar, India , E-mail: [email protected]

• Madhusmita Panda is currently holding the position of an Assistant Professor in the Department of Electronics and Communication Enginneering in ITER, S’O’University, Bhubaneswar, India,

E-mail: [email protected] • Dr Ashis kumar Mal is currently working in the Department of Electronics

and Communication Enginneering in NIT Durgapur, West Bengal, India, E-mail: [email protected]

2 PLL ARCHITECTURE The major components of the PLL are: (1) The Phase

Frequency Detector (PFD), (2) The Charge Pump(CP), (3) The Loop Filter (LPF), and (4) The Voltage controlled Oscillator (VCO). The input to the PLL is a reference signal whose value depends upon the user. The Phase Frequency Detector (PFD), compares the reference signal, and the feedback path, and generates an error signal.

2.1 Phase Frequency Detector A phase frequency detector (PFD), is a device which

compares the phase of two input signals and provides a signal in the form of phase error. It has two inputs which correspond to two different input signals, usually one from a Differential Ring voltage controlled oscillator and other is a reference source. It has two outputs which instruct the subsequent circuitry on how to adjust to lock onto the phase [1].

fig 2. AND Gate based PFD

PFD CP LPF VCO

÷N

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fig 3. Schematic of AND gate based PFD

fig 4. Output of AND gate Based PDF when Ref

leads Fin

The phase frequency detector (comparator) produces an error output signal based on the phase difference between the phase of the feedback clock and the phase of the reference clock.

2.2 Charge Pump The Charge Pump produces a charge which is

proportional to the error signal. The function of the charge pump is to take the digital Up and Down pulses from the PFD and convert them into an analog control voltage [2].

fig 5. Block Diagram of a basic PFD-CP

The Charge Pump shown in Fig. 3 has only one output, so it is termed as a "single-ended Charge Pump". This Charge Pump consists of a current source, and two switches with inputs directly connected to the outputs of the PFD. The switches control the current from the Charge Pump (Icp) where it is sourced in proportion to the input phase error. The Current is sourced through S1 which is controlled by the ‘Up’ output of the PFD which is therefore termed as the "UP current" (IUP ) with S1being termed as the ‘Up switch’. The Current then passes through switch S2 which is controlled by the "Down" output of the PFD [3]. This sink current is thereby termed as the ‘Down current’ (IDN) with S2 acting as the ‘Down switch’. The Up and Down currents are respectively defined by a current source and current sink to make them constant in order to achieve a desirable loop performance. The combination of S1 and its current source is termed as the ‘Up network’ and the combination of S2 and its current sink is termed the ‘Down network’.

2.3 Loop Filter Loop filter is an important component in PLL, as it

affects and determines the loop stability. It also provides the necessary control voltage that is required to adjust the frequency of the VCO. The Figure below shows the RC network, which includes a resistor in series with the filter capacitor. Each time the charge pump drives the R and C1 combination, a current is injected into the filter, and the control voltage experiences a jump.[2] To suppress this effect, a second capacitor (C2) is added in parallel with the resistor.

fig 6. A 3rd order loop filter

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fig 7. Schematic of the Proposed Charge Pump/LPF

Figure 8 shows the output of the charge pump /LPF when the up signal is produced. When the up signal is produced from the PFD, then the control voltage of the VCO keeps on increasing and when the down signal is produced, then the control voltage of the VCO keeps on decreasing and when there is no phase difference, then the control voltage remains constant.

2.4 Voltage Contolled Oscillator The voltage controlled oscillator is one of the most important building blocks of the PLL. There are many different implementations of VCOs. One of them is a ring oscillator based VCO. The proposed design for VCO in PLL is based on the Ring VCO, which is used in the clock generation subsystem. The main reason of using the ring oscillator is its ability to integrate easily and due to this integrated nature, the ring oscillator is used in clock recovery data process for serial circuit communication [5].

fig 9. Schematic view of ring oscillator

A ring oscillator comprises of a number of delay stages, with the output of the last stage fed back as the input to the first. To achieve oscillation, the ring oscillator must provide a phase shift of 2π and it should have a unity voltage gain at the oscillation frequency. Each delay stage must provide a phase shift of π/N.

Where N is the no of delay stages. The delay cell is a differential pair with loading and bias controls. The self biased techniques are used to reduce jitter and process variations. This arrangement for extended frequency range VCO results in a large gain of the VCO. The above negative feedback scheme combined with advanced

delay cell generates a wide frequency range and low phase noise VCO. . An ideal VCO is a circuit whose output frequency is linear function of its control voltage and this output frequency is represented by the following equation [10] pg 510:

wout = wo + KvcoVcont. (1) Where wo represents the intercept corresponding to Vcont.= 0. and Kvco denotes the gain or sensitivity of the circuit which is expressed in rad/s/V.

Fig 10. Block Diagram of a VCO

The tunable range of the VCO can be determined from the characteristics curve shown below:

Fig 11. Linear Characteristics curve of VCO

The tuning range of VCO can calculated from the graph which is given as: Tuning range = w2-w1 (2) Where w2 = Maximum Frequency and w1= Minimum Frequency and Gain of the VCO is given as: KVCO ≥ w2−w1

V2−V1 (3)

Fig 12. Formulated Characteristics of VCO

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fig 13. The VCO Circuit The output of the above circuit should be differential in nature. As the differential circuits do not yield rail-to-rail outputs, so the differential output has to be converted into a single-ended output.

fig 14. Output of the VCO circuit

The output in the above figure shows the oscillations of the VCO. It can be noted from the figure that, when the input is constant, the output frequency is also constant and when there are variations in the input signal, then the putput frequency also varies.

2.5 Frequency Divider It is one of the most important blocks of the PLL circuit. It is normally used for scaling purposes. It divides the VCO frequency in order to generate a frequency which is comparable with reference frequency. It scales down the frequency of the VCO output signal [5]. The output of the VCO is fed back to the input of the PFD via the frequency divider circuit. A simple D flip flop can act as a frequency divider circuit. The figure of a simple DFF based divide by 2 frequency divider circuit is shown below[5].

fig 15.A simple DFF Circuit

fig 16.Schematic of a simple DFF/ a Frequency Divider circuit

In figure 16, the schematic of a simple divide-by 2 frequency divider is shown. Here four two-input nand gates are used. The truth table of the DFF is given in Table 1:

Table1 Clk

D

Q

QBar

0

0

1

1

1

0

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fig 17.Output of a simple DFF/ a Frequency Divider circuit From the output given in figure 17, it can be clearly noted that , , the output is yielded significantly as per the truth table given in Table 1.

The combined PLL circuit is shown in the figure below

fig 18. The PLL Circuit

The combined circuit of the PLL shown in figure 18 is simulated using Tanner EDA tool whose output in the locked condition is shown in figure 19.

fig 19. PLL Output in Locked State.

The above figure shows the combined output of the PLL

circuit in the Locked state after its complete simulation. As stated above, the locked condition means, there is zero phase difference between the reference and the input frequency signals thus yielding in a constant charge pump output [10].

The Performance Analysis of the entire PLL circuit is shown in Table 2 below:

Table 2

Sl No

Parameters

Simulated Results

1

Vdd 1v

2

Technology 350nm

3 Lock Time 10.02ns

4 Locking Frequency 693 MHz

5 Gain of VCO 120.5MHz/V

Table 2 shows the simulated results of the combined PLL circuit where the locking frequency, lock time, and gain of the VCO are listed for better analysis.

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3 CONCLUSION The presented work describes the operation of the PLL

and its different components. The simulation studies revealed the behavior of the individual components which were found to be as expected. In this paper, a better lock time was presented. The lock time of the PLL was found to be 10.01ns. The lock time of the PLL mainly depends on the PFD architecture used along with the parameters of the charge pump and the loop filter. So, by properly choosing the PFD architecture and adjusting the charge pump current and loop filter component values, a better lock time can be achieved.

4 REFERENCES [1] Yashpal Sen, Nitin Jain, “Design and Implementation of Phase Locked Loop Using Current Starved Voltage Controlled Oscillator,” Advance in Electronic and Electric Engineering. ISSN 2231-1297, Volume 4, 2014, pp. 637-644 © Research India Publications. [2] M.Mano, G.Selva Priya, K. RekhaSwati Shri, “Design and I,mplementation of Modified Charge Pump for Phase Locked Loop,” International Journal of Emerging Technology and Advanced Engineering, ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 3, Issue 12, December 2013. [3] S. B. Rashmi, Siva S. Yellampalli, “Design of Phase Frequency Detector and Charge Pump for High Frequency PLL,” International Journal of Soft Computing and Engineering, vol.2, May 2012 Issue-2, pp 88-92..

[4] V.Lule , V.Nasre, “Area efficient 0.18um CMOS phase frequency detector for high speed PLL”, International Journal of Engineering Scientific and Research Publication, Volume 2, Feb.2012 pp 1-3 [5] Bibhu Prasad Panda, “Design and analysis of an efficient Phase Locked Loop for Fast Phase and Frequency Acquistion,” A thesis submitted by the department of Electronics and Communication Engineering, NIT Rourkela, 2011. [6] S.Williams,H.Thompson,M.Hufford,E.Naviask, “An improved CMOS ring oscillator PLL with Less than 4ps RMS Accumulated Jitter ,” Proceedings of 2004 Custom Integrated Circuits Conference ,SanJose , USA, 2004.151–154. [7] Yalcin, A.E. , P. John, “ A 5.9-GHz voltage controlled ring oscillator in 0.18 um CMOS technology,” IEEE J. Solid-State Circuit, 2004: pp 230-233. [8] Roland .E.Best, “Phase locked loop design and application,” Mcgraw Hill publications, 5th edition 2003. [9] R.J.Baker, H.W.Li, D.E.Boyce, “CMOS Circuit Design, Layout, and Simulation,” IEEE Press Series on Microelectronic Systems, 2002 [10] B. Razavi, “Design of Analog CMOS Integrated Circuits,” Tata McGraw Hill Edition, 2002 [11] SijieZheng and Lili He, “The Mixed-Signal Design of PLL with CMOS Technology,” Department of Electrical Engineering San Jose State University.

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2 PLL ARCHITECTURE IJSER · A Phase locked loop (PLL) is a closed loop frequency system that locks the phase of the output signal to the reference signal. The term ‘lock’ refers