3.3 The 80386

• 80286 introduced the protected mode• 80386 refined the protected mode• 80386 expanded the data registers to 32 bits• A new feature called virtual 8086 mode became available• 80386 Modes:

– Real Mode – Protected Mode– Virtual 8086 Mode

• 386 architecture has become the foundation for the next four generations of Intel processors (P3-P6) and seven different microprocessor chips.

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The 80386Real Mode

• It is the mode which the processor is initiated to, when started

• In this mode the chip is virtually identical to 8086. I.e. it has the following:

– Address space is limited to 1MB using the low order address lines A0-A19.

– The segmented memory addressing scheme is retained (each segment is limited to 64K)

• Two new features are available to the programmer:– Access to the 32-bit registers– The addition of two new segments: F and G to be explained

later

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3

The 80386Protected Mode

• Primary difference from the real mode is in the new addressing mechanism and protection levels in the protected mode

• Each segment may now range from single byte to 4GB (the full physical address space)

• The addresses stored in segment registers are now interpreted as pointers into a descriptor table

• Each segment’s entry in this table is 8 bytes long and identifies :– the 32-bit base address of the segment,– the segment size and – the access rights

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The 80386Protected Mode (continued)

• Memory addresses are calculated by adding the offset specified by the instruction to the segment base address.

• Paging Mechanism:– Translates the 32-bit linear address (segment base plus offset) into a

physical address within a 4K page frame.

• Paging Unit:– Can manage multiple frames, even swapping frames out to disk, such

that 64TB (65,536 GB) of virtual memory is available.

• Protection Mechanism:– Tasks (programs) run in a particular segment and assigned a privilege

level, so programs are protected from each other.

• The main difference between segmentation and paging is the difference in block sizes. (1 byte – 4GB with segmentation). (always 4kB with paging)

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The 80386Virtual 8086 Mode

• 80386 has two modes to run 8086 programs:– Real mode (discussed above)– Virtual 8086 mode

• Virtual 8086 mode allows multiple 8086 programs (and 386 applications) to run independent of each other and simultaneously

• In virtual 8086, each task sees 1MB of address space (which is mapped anywhere in the 4GB of physical memory through paging)

• Real mode limits the 386 to 1MB of physical memory and one 8086 task can run at a time. Moreover, all of protection and memory management features of 386 are turned off.

• 386 can be operated in both virtual 8086 mode and protected mode simultaneously.

• Because each 8086 program is assigned the lowest privilege, access to other programs and segments is not allowed, thus protecting each such task.

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FIGURE 3-10 When operated in Virtual 8086 Mode the 386 can run multiple 8086/88 programs simultaneously.

John UffenbeckThe 80x86 Family: Design,

Programming, and Interfacing, 3e

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The 80386Processor model

• 80386 is divided into 3 units:– Bus Interface Unit (BIU)– Central Processing Unit (CPU)– Memory Management Unit (MMU)

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FIGURE 3-11 The processor model for the 80386 microprocessor consists of the bus interface unit (BIU), central processing unit (CPU), and the memory management unit (MMU).

John UffenbeckThe 80x86 Family: Design,

Programming, and Interfacing, 3e

The 80386The BIU

• Manages the 32-bit address and data buses and various control signals

• Keep instruction queue (now 16 bytes) full

• Two new features have been added:• Address pipelining.• Dynamic Data Bus Sizing

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The 80386The BIU (continued)

Address pipelining:• In this technique the address of the next memory

location is to be accessed is output by the 386 half way through the current bus cycle

• Gives the external memory more address decode time

• Makes it easier for memory to keep up with the two-clock-pulses-per-bus-cycle processor without adding wait state.

• The bus cycle is only two clock cycles (compare to 4 clock cycles in 8086)

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The 80386The BIU (continued)

Dynamic Data Bus Sizing• This allows the 80386 to switch between a 32-bit and 16-

bit data bus “on the fly”.

• The 386 chip can accommodate an external 16-bit memory card or I/O device.

• When the 16-bit mode is selected, the BIU adjusts bus cycle to use only the low 16-bit of the data bus.

• When the bus size is set to 32 bit, 4 memory banks are required.

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The 80386The CPU

• CPU consists of:• Instruction Unit (IU):

• Retrieves instructions from the queue• Decodes them• Stores them in the decoded instruction queue

• Execution Unit (EU):• Contains the ALU and the 8 general-purpose data

registers (now expanded to 32 bits)

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The 80386The MMU

• The MMU has 2 parts:1. Segmentation Unit:2. Paging Unit:

Segmentation Unit• Generates the 8086-style (20 bit) physical address when

the 386 operates in real mode.

• When operated in protected mode, the descriptor registers store the base address, size, and attributes of the various segments

• In effect these registers cache the descriptor tables stored in RAM allowing the processor to switch between tasks very quickly13

The 80386The MMU

Paging Unit:

• Determines the physical address associated with each active segment.

• Allows segments to be divided into 4K pages.

• Typically, only the most current pages are kept in memory with the others swapped out to disk.

• This allows programs whose size is larger than the physical memory to be able to run. This is called “Virtual Memory”

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The 80386Programming Model

• The programming model has 2 parts:1. General-purpose registers

Used by application programs1. Data group2. Pointer and index group3. Status and control flags4. Segment group

2. Special-purpose registers

Used by the operating system1. Control registers2. System address registers3. Debug registers4. Test registers

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16

80386 programming model: The general-purpose registers

General-purpose registers : used by application programmers

John UffenbeckThe 80x86 Family: Design,

Programming, and Interfacing, 3e

17

Special-purpose registers : used by OS

John UffenbeckThe 80x86 Family: Design,

Programming, and Interfacing, 3e

The 80386General-purpose Registers- The Data and

Address Group

• They are the data, pointer and index registers (same as in 8086)

• Each has been extended to 32-bit• To reference the 32-bits use E(A,B,C,D)X• Each of the registers EAX, EBX, ECX, and EDX can be

accessed in four ways. Example:• AL : D0-D7• AH : D8-D15• AX : D0-D15• EAX: D0-D31

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The 80386General-purpose Registers- The Status and

Control Flags

• The 8086 status and control flags have been retained but extended to 32-bits (See figure)

• In addition, 4 more flags are added (VM, RF, NT, IOPL)• VM (Virtual Mode):

• This is a protected mode control flag, • used to switch the processor to virtual 8086 mode

• RF (Resume flag): • Used with the debug registers.• When set, the debug fault is ignored and the next

instruction is executed normally.

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The 80386General-purpose Registers- The Status and

Control Flags• NT (Nested task):

• Used in Protected mode to indicate that the current task was called from another task

• This affects the type of return instruction to be executed when the nested task completes

• IOPL ( I/O Privilege Level):• 2-bit flag• These two Protected Mode control bits identify the

current privilege level (0-3) required to execute I/O instructions

• Allow the operating system to restrict I/O privileges of a task

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FIGURE 3-13 The 80386 flag word is 32 bits long. Four new flags have been added compared to the 8086: VM, RF, NT, and IOPL. (Courtesy of Intel Corporation.)

John UffenbeckThe 80x86 Family: Design,

Programming, and Interfacing, 3e

The 80386General-purpose Registers- The Segment

Group• Two new segment registers have been added : GS and FS.

• Now six different segments can be active at a time.

• All registers are 16-bit (same as 8086).

• Since no instructions default to the GS or FS, the previous segment register assignment still apply.

• Real Mode:• Same addressing mechanism in 8086, segment

registers hold the base address of the segment

• Protected Mode:• Content of segment registers are pointers into a

descriptor table whose entries determine the base address of the segment, its size and attributes22

The 80386Special-purpose Registers

• Not normally used by application programmer.

• Intended to control the processor in protected mode and for testing.

• Three Control Registers:• They are 32-bit : CR0, CR2, CR3

• CR0: is used to enable the paging mechanism, monitor task switching, and select Protected Mode or Real Mode.

• CR2: holds the address of the last instruction to cause a page fault ( page is not in memory and must be loaded from disk)

• CR3: holds the base address of the page table.

• Page table holds the starting address of each page frame and access information about that frame.23

The 80386Special-purpose Registers (continued)

• Four System address Registers (GDTR, IDTR, TR, and LDTR):• Hold information about the descriptor tables used in

Protected Mode.

• Six Debugging Registers:• DR0-3 and DR6-7• Used to set program breakpoints( are addresses where

the program should break (pause) and pass control to a debugging routine and that to allow the programmer to inspect the state of registers to debug the program).

• Two Test Registers (TR6 and TR7):• Used to test RAM in the Translation Lookaside buffer

(TLB).• TLB is used by paging unit to translate virtual memory

addresses into physical addresses

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