2 FPGA Fundamentals

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CHAPTER 2

F P G A F u n d a m e n t a l s2 .1 Ov e rv ie wThis chap te r p rov ides a b r ie f overv iew of p rogram mab le log ic technolog y and h is to ry . I t i sin tend ed for des igners wi th l imi ted program ma ble log ic exper ience . S ince th e pr imary focuso f t h is b o o k is o n r a p i d d e s ig n i m p l e m e n t a t i o n w i t h F P G A t e ch n o l o g y , t h e t e c h n o l o g y o v e r-v iew i s a t a h igher leve l . This ch ap te r p rov ides a h igh- leve l ov erv iew of p rogram mab le log ictechnology . For a mo re de ta i led overv iew o f p rogram mab le log ic, re fe r to The Design Warrior'sGuide to FPGA s by Clive Maxfield.

Program mab le log ic dev ices have the po ten t ia l to imp lem ent a b road range of func-t iona li ty , un l ike the f ixed- func t ion dev ices tha t p receded them . I t i s the f lex ibi li ty inh eren tin FPG A technolog y th a t a llows des ign teams to rap id ly deve lop an d f ie ld complex sys temi m p l e m e n t a t i o n s .

In th i s chap te r , w e wi l l f i rs t r ev iew programm able log ic dev ices in genera l , and then goon to a de ta i led look a t FP G A devices , wi th a n eye toward the i r su i tab i li ty fo r rap id pro to-typ ing and des ign .2.1.1 Ca tegor ies o f Program m able LogicProgram mab le log ic dev ices (PLDs) a re d iv ided in to th ree pr imary a rch i tec tura l g roups:

9 S imp le Program mab le Logic Devices (SPLDs)9 C o m p l e x P r o g r a m m a b l e L o g ic D e v i c es ( C P L D s )9 F i el d P r o g r a m m a b l e G a t e A r r a ys ( F P G A s )Whi le each of these programmable log ic dev ice a rch i tec tures have typ ica l focused ap-

p l ica tions , they a l so have some com m on fea ture over lap wh ich leads to some over lap ofappl ica tions . F igure 2 .1 i l lust rates the o ver lap be tween the th ree P LD technolog ies . Forexample , some appl ica t ions such as address decoding could be implemented in e i ther aC P L D o r a n F P G A . I m p l e m e n t a t i o n w i t h i n a n F P G A a l lo w s th i s f u n c t i o n t o b e in t e g r a te dwi th a la rger range of add i t iona l func t iona l i ty .

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Ch apter 2Programmab le Log ic Dev ices~ , ~ ~ . . _ _

Figure 2.1 PL D categoriesT h e a r c h i t e c t u r e s a r e n o t m u t u a l l y e x c lu s i v e a n d i t is o f t e n p o s si b le t o i m p l e m e n t

t h e s a m e f u n c t i o n a l i t y i n m o r e t h a n o n e d e v i c e t y p e . In g e n e ra l , a n y f u n c t i o n t h a t c a n b ei m p l e m e n t e d i n a s i m p l e r d e v i ce c a n a ls o b e i m p l e m e n t e d w i t h i n a m o r e c o m p l e x d e v i c e .T h e o p p o s i t e i s n o t n e c e s s a r il y t ru e , s in c e m o r e c o m p l e x f u n c t i o n s m a y n o t b e a b l e to b ei m p l e m e n t e d w i t h i n s i m p l e r P L D d e v i c e t y p e s a t a l l . T h e f o l l o w i n g f a c t o r s m a y i n f l u e n c e t h es e l e c t i o n o f a t a r g e t P L D a r c h i t e c t u r e f o r d e s i g n i m p l e m e n t a t i o n .

P L D T a r g e t A r c h i t ec t u r e D e c i s i o n F a c t o r s9 A b i l it y t o i m p l e m e n t re q u i re d f u n c t i o n a l it y w i t h i n a P L D d e v i c e c a t e g o ry9 C o s t to i m p l e m e n t fu n c t i o n a l i ty w i t h i n a s pe c if ic P L D d e v ic e9 E a sy m i g r a t i o n p a t h f ro m p r e v io u s d e s ig n i m p l e m e n t a t i o n ( re u s e)9 N e e d fo r e x p a n s i o n o f f u n c t i o n a l i t y i n t h e f u t u r e9 A b s o l u t e fu n c t i o n i m p l e m e n t a t i o n c o s t o r r e a l- e s ta t e l im i t s9 F a m i l ia r i t y w i t h s p e ci fi c P L D a r c h i t e c t u r e9 P o s s e s si o n o f o r f a m i l i a ri t y w i t h s p e ci fi c P L D d e s ig n a n d i m p l e m e n t a t i o n t o o l s9 A vai l ab i l i ty o f spec if ic pack age type o r s ty leF i g u r e 2 .2 s h o w s t w o P L D c a t e g o r i e s a n d s o m e o f t h e i r r e s p e c t iv e c h a r a c t e r i s t ic s a t a

h i g h l ev e l. T h e s e c h a r a c t e ri s ti c s m u s t b e t a k e n i n t o a c c o u n t w h e n d e c i d in g o n a P L D t e c h -n o l o g y t o t a r g e t . F o r e x a m p l e , i n l a r g e r a p p l i c a ti o n s t h e l a r g e r c a p a c i t y a n d l o w e r g a t e c o s t o fF P G A s c a n i n f l u e n c e d e s ig n e r s t o se l e c t t h e c a t e g o r y o f F P G A s t o i m p l e m e n t t h e i r re q u i r e dd e s i g n f u n c t i o n a l i t y .

C P L D s :More Predic tab le T im ing

SimpleArchitectureFewer Registers

ii J i ii

v e r s u sF P G A s :

Larger CapacityComplexArchitecture

Mo re Registers

Figure 2 .2 PL D categories

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FPGA FundamentalsUlt imate ly the des ign fac tors a f fec t ing PLD arch i tec tura l se lec t ion break down in to the

categories shown in Table 2.1.Tab le 2 .1 Design Factors aFFect ing PL D a rchi tectural se lect ion

Design Catego ryAvailabi l i tyC o s tD e b u gEfficiencyFlexibi l i ty

Design Factor D etai lLong- te rm component ava i lab i l i ty , vendor s tab i l i tyC o m p o n e n t c o s t, i m p l e m e n t a t i o n c o s t, s u p p o rt co s tAccess to technology which makes des ign debug eas ie rEf f ic iency to implement , upda te , modi fy and main ta inAbil i ty to accommodate change, future funct ion expansion

Fami l ia r ity Fami l ia r ity wi th the a rch i tec ture , too lsHis tory

.....O p t i o n sPopular i ty

Pr ior des ign exper ience wi th the a rch i tec ture / too ls ,ava i lab il i ty o f p r io r des ign im plem enta t io n to leverageTools , package , implementa t ion op t ionsPopular a rch i tec tures a re like ly to have b e t te r suppor tand longer avai labi l i ty_Sup por t Access to vend or suppor t s taf f and indus t ry suppor t

_Tra in ing Access to t ra in ing on des ign im plem enta t ionTh e d es ign cons idera t ions l i s ted in Table 2 .1 wi l l be com m on to m any of the e ngineer ing

t rade s tud ies and essen t ia l des ign dec is ions required to imp lem ent a des ign wi th p rogram -mable log ic . As the des ign team addresses eac h of these con s idera t ions , there a re add i t iona ldes ign dec is ions tha t mus t be made . Knowing which PLD technology to ta rge t does no t an-swer wh ich manufac ture r , f ami ly or too l se t to use . Th e f lex ib le na ture o f p rogram mab le log icbr ings wi th i t a wide range of op t ions to eva lua te and ch oose f rom. M any of these dec is ionswil l be affected by a combinat ion of cost and complexity, as i l lustrated in Figure 2.3.

Complexity

F igure 2 .3P L D d e s ig n s p a c es

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C h a p t e r 22 . 1 .2 S P L D D e v ic e O v e r v i e wT h e s i m p le s t P L D d e v i c e a r c h i t e c tu r e s a r e p ro g ra m m a b l e a r ra y lo g ic (P A L ) d e v i c e s a n dprogram ma ble log ic a r ray (PLA ) dev ices . Both o f t hese dev ices a re genera l ly ca tegor i zed in toa fami ly o f log ic dev ices kno w n as simple programmable/og/c devices (S PLDs) . P L A d e v ic earch i t ec tu res a re based on the im plem enta t ion o f two log ic ga t e a rray s t ruc tures . On e a r rayis o f B o o l e a n A N D s a n d t h e o t h e r o f B o o l e a n O R s . C o m b i n e d , t h e s e a rr a ys ar e c ap a b l e o fi m p l e m e n t i n g a su m o f p ro d u c t s t h a t i m p l e m e n t t h e r e q u i r ed B o o l e a n l o gi c e q u a t io n s . T h e s ed e v i ce s a l so h a v e i n p u t a n d o u t p u t b l o c k s a n d l im i t e d p ro g ra m m a b l e i n t e rn a l s ig n a l r o u t i n gp a t h s t h a t c a n s u p p o r t o u t p u t s i g n a l f e e d b a ck . T h e i n p u ts a n d o u t p u t s c a n b e e i t h e r s y n c h ro -n o u s o r a s y n c h ro n o u s ( c l o c k e d o r u n c l o c k e d ) .

W h i l e P L A d e v ic e s al lo w b o t h t h e A N D a n d O R p l a n e s to b e p r o g r a m m e d a P A Ld e v i c e h a s a f ix e d O R p l a n e . T h e t r a d e -o f f b e t w e e n t h e s e t w o a r c h i t e c t u re s is s p e e d o v e rlog ic f lex ib il it y . How ever , b o th o f these dev ices a rch i t ec tu res a re re l a t ive ly fas t and possess ap ro p a g a t i o n d e l a y ( c o m m o n l y r e f e rr e d t o a s T p d ) i n t h e o rd e r o f a f e w n a n o s e c o n d s . F ig u re2.4 show s a s impl if i ed PAL arch i t ec tu re b lock d i agram.

Bo th PA L and PL A dev ices a re re l a t ive ly smal l i n s ize , genera l ly rang ing f rom 8 to 24l og i c ce l l s w i th l ow p in count s on the o rder o f 16 to 28 p ins . The conf igura t ion t echnolog iesu s e d fo r t h e s e d e v ic e s i n c lu d e E P R O M a n d E E P R O M . A p o p u l a r P A L a rc h i t e c tu r e e x a m p l eis t he 22V1 0 . Th e typ ica l ranges o f SPL D charac t e r i s t i cs a re ou t l i ned in Tab le 2 .2 .

, / oM a c ro ; ~ ~ ; ; ~ ~C ell ~ ~ ~ ] ~ [ ~ [ ~ ~ ~ 9 [ ~ ~ --

P r o d u c t, ~ ~ , , ,

M a c r ~ I I i I *

P i n s " " - ~ ~ ~ ~ ~ ~ ~ ~ [ ~

Figure2 .4C P L Dd a t a lo w

C l o c k

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FPG A Fundamenta lsTab le 2 .2

S P L D C h a r a c te r is t icN u m b e r o f p in sN u m b er o f m acro ce ll sNu m ber of f lip- flops (FFs)C on f igura tion t echno logyPower-up s ta tusProgram m abi l i t yP r o g ra m m i n g m e c h a n i s mSize

R a n g e16 to 28 pins8 to 24 logic cells8 to 24 FFsE P R O M , E E P R O MN o n v o l a t i l eC a n be r ep rogram m ed a f te r be ing e rasedG en era l ly p rogram m ed o f f-boardS m a l l

2 . 1 . 3 C P L D D e v i c e O v e r v i e wTh e ne xt group o f PLD dev ices are referred to as com plex program m able logic devices(C PL D s) . C PL D s exp and the r ange o f po ten t i a l func t iona l i ty o f SPL D dev ices since they a reex tens ions o f t he SPL D a rch i t ec tu re w i th ad d i t iona l r e sources . C PL D s can be r ep rogram m edin-c i rcui t .

C PL D co m pone n t s cove r a m idd le g round in t e rm s o f com plex i ty and d ens i ty be tw eenSPL D s and FPG A s . A C PL D in i ts sim ples t fo rm is based on the im p lem e n ta t ion o f m ul -t ip l e SPL D b locks w i th in t e r -b lock rou t ing r e sources and an enh ance d pe r iphe ra l r ing o f I /Oblocks wi th in a s ingle package. Figu re 2 .5 shows a gener ic CPLD archi tec ture .

Macro Macro Macro

S w i t c h F a b r i c

IMacro Macro Macro

. _ . . -

F ig u r e 2 . 5 B a s i c C L P D S t ru c t u r e

Input/Output

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Ch apter 2CP LD de v i ce s c a n po t e n t i a ll y r e p l a ce t hous a nd s o r e ve n t e ns o f t hous a nds o f e qu i va l e n t

logic ga te s . CP LD a rchi t ec tures co nt inu e to evolve an d inc rease in dens i ty , capabil ity , speeda nd a r c h i t e c tu r a l c om pl e x it y . Th e mor e c om pl e x C PLD f a mil ie s ha ve c ha r a c te r is t ic s a nd a t -t r ibutes t r adi t iona l ly a s soc ia ted wi th FPG As . Figure 2 .6 r e fl ect s som e of the des ign dec i s ionst h a t m u s t be m a d e w h e n i m p l e m e n t i n g a d es ig n w i t h a C P L D .

S P L D

P L D C P L D

F P G A

SizeTool SetArchitecture5 V I /O To le ranceLow Vo l t age (3 .3 Vo l ts )Low Power (Zero Power )Package (D IP , PLCC, SSOP, e tc . )

F i g u r e 2 . 6 C P L D d e c i s io n tr e e

T he typica l r anges of CP LD cha rac te r i s ti c s a re out l ined in Table 2 .3 .Tal

C P L D C h a r a c t e r i s t i c. . . . . .N u m b e r o f P i n s

N u m b e r o f M a c ro C e ll sN u m b e r o f F FsConf i gu r a t i on Te c hno l ogyPowe r - up S t a t usPr ogr a mma bi l i t yP r o g r am m i n g M e c h a n i s mSizeE q u i v a le n t G a t e C o u n t

~le 2.3R ~ n g e44 to 3( )0+ pins32 to 500+ logic ce l ls32 to 500+ FFsE E P R O M , E P R O M , F L A S HN o n v o l a t i l eC a n b e re p r o g ra m m e dCa n be p r ogr a mme d i n - c i r c u i tM e d i u m900 to 20 ,000+ equiva lent ga te s

La r ger CPL D de v i ce s c a n i m pl e me n t f unc t iona l it y , wh i c h c ou l d a l so be t a r ge t e d t osmal le r FP G A devices. Des ign t eams wi l l need to de te rm ine i f the t a rge ted C PL D fami ly hast he h e a dr oo m r e qu ir e d f o r f u tu r e p r oduc t i mp l e m e n t a t ions . W hi l e a de si gn ma y c u r r en t l y bei mpl e m e n t e d w i t h i n a CP LD de v i ce , de s igns w i t h p o t e n t i a l f o r si gn if ic a n t fu t u r e e xpa ns i ons hou l d be c ons ide r e d fo r i mp l e me n t a t i on w i t h i n a n FPG A. A r c h i te c t u r al l y , FPGA s t e ndt o be mor e c om pl e x t ha n CPLD s . Th e i mp l e me n t a t i on o f l og ic and s i gnal in t e r c on ne c t i onw i th in CP LD s an d F PG As is s igni fi cantly d i ff e rent, a s i llus t ra ted in Figure 2 .7. For a morede ta i l ed com par i son, r eview th e d a ta shee t s for Xi l inx 's Coo lRu nne r -2 and Vi rt exTM-4 fami -l ie s . FP G A a rchi t ec tures w i ll be presented in m ore de ta i l in the fo l lowing sec tions .

No t i c e t ha t FPG As t e nd t ow a r d da t a - pa t h o r i e n t e d f unc t ions a t t he c os t o f a mo r ec omp l e x a r c h i t e c tu r e . T he mor e c om pl e x a r c h i t e c t u r e r equ i re s mor e a dva nc e d de s ign i mpl e -m e n t a t i o n de c is i ons w i t h t he r e s u lt ing a dva n t a ge s o f h i ghe r I / O c oun t , m or e f le x ib l e rou t i ngand m ore r egi s te r re sources . Howev er , the inc reased com plexi ty i s l a rge ly han dled a t thede s ign i mp l e m e n t a t i on t oo l l e vel a nd is no t t he p r i ma r y re s pons ib i li ty o f t he de s i gn t e a m.

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FPGA Fundamentals

F i g u r e 2 . 7 C P L D t oF P G A c o m p a r i s o n a n n e

2':': D I U I L A I L _ J I 0 N

~:_~.

CPLD Archi tecture

J m m lm H l m lB m l m lR m m m

FPGA Archi tec ture

D u e t o t h e i r a r c h i t e c t u r a l c h a r a c t e r i s t i c s , C PL D s a n d FPG A s a r e o p t i m i ze d t o i m p l e -m e n t s i m i l a r b u t d i f f e r e n t r an g e s o f f u n c t i o n a l i t y e f fi c ie n tl y . C PL D s a r e w e l l s u i te d t oc o m b i n a t o r ia l f u n c t io n s w i t h l i m i t e d r eg i st e r r e q u i re m e n t s , w h i l e F P G A s c a n i m p l e m e n tl ar g er , m o r e r e g i s t e r - in t e n s i v e f u n c t i o n a l i t y . T h e p r i m a r y t r a d e -o f f s fo r PL D t e c h n o l o g y d e c i -s ions inc lude cos t ve r sus dens i ty , I /O capab i l i ty and speed .

Fo r t h e m o s t p a r t, a t s m a l l d e n s i ti e s t h e C PL D w i n s b e c a u s e o f p r i c e. A t h i g h d e n s i t ie s ,the FPGA tends to win due to lower ove ra l l log ic cos t . However , when c ross ing ove r f romC P L D t o FP G A , t h e m i d d l e g r o u n d is g r ay a n d i t b e c o m e s a b a t t l e o f te c h n o l o g i e s a s il l u st r a te din Figu re 2 .8 . F igu re 2 .8 p resen ts a mapp ing o f func t ion a l i ty fo r CP LD and F PG As .

s TequentiaIFunctions

D a t a PathOr ien tedF u n c t i o n sFlexibleRouting

H i g h e r ]IIO Coun tH i g h e rR e g i s t e rC o u n t

F P G A s

R e g i s t e rIn tens ivei p r o m i s e

C o n t r o lF u n c t i o n sState M a c h i n e s

~ ~ ~ L o w e r L o w e rI/O C o u n tSimple R e g i s t e rC o u n t

P r e d i c t a b l eRouting

C o m b i n a t o r i a l F u n c t i o n s

C P L D s

F igu re 2 .8P L D c a teg o r i es

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C h a p t e rThe main t rade-offs for PLDs center around cost versus densi ty , speed, and I /O. Figure

2 .9 shows some of the op era t iona l ca tegor ies o f FP GA devices.M o r e ,~ __-.------- .. _ . ~ F e a t u r eI / ~ ~ ~ ' - P e r f o r m a n c e -~c.......,, Rich( ~ O r i e n t e d / "~ ,

L e s s N ~ ~ ~ F a m i l y / f ~ 7 - ~ M oreL o g ic f " ~ ' ' - - ~ - " " ~ " ~ L o g ~ c-" ( I /0 - ~ L o g i c - I " -

~ ,. / O r i e n t e d ~ .d },Feature LessOpt im ized I/OF ig u r e 2 .9 F P G A a m ily o p t i m i z a t i o n

2 . 1 .4 F P G A D e v i c e O v e r v ie wSince f ie ld p rogram ma ble ga te a r ray (FPG A) dev ices a re the focus of th i s book , we wi l l nowcons ider FP GA arch i tec tures in mo re de ta il . FPG A or field p rogram mab le ga te a r ray dev iceswere in t roduc ed in 1985 by Xi l inx . FPG As w ere deve loped m address the gap be twee nC P L D a n d A p p l i c a ti o n - S p e c i fi c I n t e g r a te d C i r c u i ts ( A S I C ) s ev ic es . T h e s e n e w c o m p o n e n t sprov ided a reduced-cos t log ic p la t fo rm w i th the dens i t ies and I /O capabi l i ti es o f ga te a r raysa n d t h e p r o g r a m m a b l e n a t u r e o f C P L D s . T h e y s u p p o r t e d fa s te r ti m e t o m a r k e t, e n h a n c e ddesign f lexibi l i ty and s implif ied design debug, a l l prerequisi tes of rapid system pro totyp inga n d d e v e l o p m e n t .

FPG As are manufac tu red by mul t ip le man ufac ture rs u t il izing severa l d i f fe ren t t echnolo -g ies. Each ma nufac tu re r o f fe rs d i f fe ren t dev ice " fami l ies" wi th com m on fea tures , vo l tages andlow- leve l dev ice ( IC) geom et r ies . Each d ev ice fami ly d if fe rs in the de ta i ls o f dev ice a rch i tec-tu re , dev ice program m ing technology , in te rna l s ignal rou t ing , power, capac i ty , vo l tage , I /Osuppor t , and packaging . This b road range of implementa t ion i s due to s t rong compet i t ion be-tween man ufac ture rs , and a des ire to d i f fe ren t ia te p roduc ts by ta rge t ing speci fic app l ica t ionsrequi r ing d i f fe ren t fea tures and a rch i tec tures , such as increased on-bo ard me mo ry or speci ficI /O support . Despite these differences, there are also s ignif icant design archi tecture, featureand dev e lop m ent p rocess s imi la ri ti es be twee n the broad ranges of o ffe red dev ices . Table 2 .4provides a l i s t ing of typ ica l FPG A charac te r i s tics .

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FPGA FundamentalsT a b l e 2 . 4

FPGA Character ist icN u m b e r o f P i nsN u m b e r o f L o g ic C e l lsN u m b e r o f F FsC o n f i g u r a t io n T e c h n o l o g yPower-up S ta tusRe p r o g r a m m a b i l i t yP r o g r a m m i n g M e c h a n i s mSizeE q u i va l e nt G a t e C o u n t

Range50+5,000+5,000+Flash , EEPROMS RA M : v o l a t i l e , O T P : n o n v o l a t i l eS RA M : c a n b e r e p r o g r a m m e d , O T P : n oS RA M : c a n b e p r o g r a m m e d i n - c ir c u i tM e d i u m t o L a r ge10 ,000+ equ iva len t ga tes

M anufac ture rs have re f ined the i r o f fe rings wi th f ine- tuned a rch i tec tures a nd func t ionsets that target specif ic applicat ions and funct ional categories . In many cases new featureswere added as technolog y ad vanced . M any of these fea tures were no t o f in te res t to the broadmarke t , so fu r ther component var ia t ions occur red . Fea ture d i f fe rences inc lude dev ice granu-lar i ty , I /O interface support , resource mix ( logic versus regis ter) , logic capaci ty, operat ionals p ee d a n d p o w e r c o n s u m p t i o n .

Most FPGA manufac ture rs o f fe r two main FPGA fami ly ca tegor ies : p e r f o r m a n c e - o p t i m i z e da n d c o s t - o p t i m i z e d . W ithi n these fami lies, the d ev ices have a range of I /O and log ic capabil i -t ies . Som e fami l ies and dev ices wi ll have a h igher ra t io o f log ic - to - I /O and a re refe r red to aslog ic -cen t ric . O the r dev ices wi ll have re la tive ly more I /O tha n log ic and a re re fe rred to asI /O-cen t r ic . F igure 2 .9 i llus tra tes the re la t ionsh ips be tw een these ca tegor ies . These ca tegoriesare metho ds of c la ri fy ing the re la t ive am oun t an d cos t o f ava ilab le resources.

W i t h t h i s c o m p e t i t iv e e n v i r o n m e n t a n d e v o l u t io n b r o u g h t a b o u t b y t e c h n o l o g yadvancements , FPGA resources have cont inued to increase in dens i ty , complex i ty , speed ,and I /O count as well as archi tectural ly , by adding larger , more versat i le blocks of embed-ded RAM, embedded hard and sof t p rocessor cores , ded ica ted hardware mul t ip l ie r s andhigh-speed co m m unic a t ion capabi li t ies . Th ese la rger dev ice s izes, wi th more a rch i tec tura le n h a n c e m e n t s a l o n g w i t h a d v a n c e d F P G A d e s i g n to o l i n te g r a t io n , e x t e n s i v e h a r d w a r edescr ip t ion language (H DL ) usage and th e ava i lab i l ity o f mo re in te l lec tua l p roper ty ( IP) ,addressed la te r in th i s book , a re a l lowing des ign teams to im plem ent increas ing ly com plexdes igns wi th in shor te r schedules .

Th e cur ren t h igh-e nd FP G A fami l ies fea ture m i l lions o f equiva len t ga tes o f func t iona l i tyand h igh-speed in te rfaces capable o f suppor t ing a very broad range of eng ineer ing so lu t ionsi n c lu d i n g n o n t r a d i t i o n a l a p p l ic a t io n s . T h e s e h i g h - e n d F P G A c o m p o n e n t s a r e ca p a b le o fi m p l e m e n t i n g c o m p l e x f u n c ti o n a l it y w h i c h i n t h e p a s t w o u l d o n l y h a v e b e e n p r a c t i ca l w i t hA S I C s o r e x te n s i v e d i s c r e t e - c o m p o n e n t b o a r d d e si gn s .

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C h a p t e r 22 . 1 . 5 F P G A T y p e sT h e r e a r e tw o b r o a d c a t e g o r ie s o f FP G A d e v i c es , reprogrammablea n d one-time programm able( O T P ) d e v i c es . FPG A d e v i c es m u s t b e p r o g r a m m e d a t so m e p o i n t i n t h e d e s ig n p ro c e s s t od e f in e t h e i r f u n c t i o n a l o p e r a t i o n . T h e r e a r e f o u r d i f f e re n t t e c h n o l o g i e s f o r p r o g r a m m i n g( c o n f ig u r i n g ) FP G A s a n d t h e y a r e d e t a i l e d i n T a b l e 2 .5 .

T a b l e 2 . 59Con fiRuration e c k n o l o y o ,S R A M - b a s e d

A n t i - F u s e - b a s e d

E P R O M - b a s e d

E E P R O M - b a s e d

Tecknolof~yO verv iew and FeaturesA n e x t e r n a l d e v ic e ( n o n v o l a t i le m e m o r y o r pP ) p r o g ra m s t h ed e v i c e o n p o w e r u p . A l l o w s f a s t r e c o n f i g u ra t i o n . C o n f i g u r a -t ion i s vo la t i l e . Dev ice can be reconf igu red in -c i rcu i t .C o n f i g u r a t i o n i s s e t by " b u r n i n g " i n t e r n a l f u se s t o i m p l e m e n tt h e d e s i r e d f u n c t io n a l i t y . C o n f i g u r a t i o n is n o n v o l a t i l e a n dc a n n o t b e c h an g e d .C o n f i g u r a t i o n i s s i m i l a r t o E PR O M d e v i c es . C o n f i g u r a t i o n i sn o n v o l a t i l e . D e v i c e m u s t b e c o n f i g u r ed o u t o f c i r c u i t ( o ff -b o a r d ) .C o n f i g u r a t i o n i s s i m i l a r t o E E PR O M d e v i ce s . C o n f i g u r a t i o n isn o n v o l a t i l e . D e v i c e m u s t b e co n f i gu r e d a n d r e c o n f ig u r e d o u to f c i rcu i t (o f f -boa rd ) .

C o n f i g u r i n g v o l a t i l e FPG A s o r SR A M FPG A s t y p i c a l l y t a k e s a f e w h u n d r e d m i l l i s e c o n d so r le ss to c o m p l e t e . T h i s t i m e i s m a i n l y d e p e n d e n t o n t h e s i ze o f t h e p a r t , t h e c o n f ig u r a -t i o n i n t e r f a c e i m p l e m e n t e d a n d t h e s p e e d o f d a t a t r an s f er . H o w e v e r , t h e l e n g t h o f t h ec o n f i g u r a t i o n d e l a y p e r io d o f t e n i s a m i n o r c o n s i d e r a t i o n a t t h e s y s te m d e s ig n l e v e l, w h e nc o m p a r e d t o t h e b e n e f i ts o f b e i n g a b l e t o d y n a m i c a l l y r ec o n f ig u r e t h e F PG A i n - c i r c u it . T h i si s e spec ia l ly the case w he n o the r types o f dev ices , such a s a p rocesso r , a re p rese n t th a t a l sor e q u i re a b o o t - u p .

T o c o n fi g u re a n S R A M FPG A , t h e c o n f i g u r a t i o n d a t a i s u s u a ll y l o a d e d fr o m a n e x t e r -n a l n o n v o l a t i l e c o n f i g u r a t i o n PR O M , a l t h o u g h FP G A s c a n a l s o b e c o n fi g u r ed d i r e c tl y by ap r o c e s s o r o r v i a a d o w n l o a d c a b l e f r o m a PC . O n e - t i m e p r o g r a m m a b l e ( O T P) d e v i c e s , o nt h e o t h e r h a n d , a r e m a d e u p o f t r a d i t i o n a l l o g i c g a t es i n t e r c o n n e c t e d b y e m p l o y i n g a n t i -f u s e t e c h n o l o g y . T h e c o n n e c t i o n s b e t w e e n t h e g a t e s a r e n o t " b l o w n " b u t i n s t e a d m a d e i n t op e r m a n e n t c o n n e c t i o n s . T h e r e f o r e , O T P d e v i c e s c a n n o t b e m o d i f i e d a f t e r t h e y a r e p r o -g r a m m e d . O T P p a r t s p o w e r u p " c o n fi g u r ed " a n d t h u s h a v e t h e a d v a n t a g e o f n o c o n f i g u r a t i o nt i m e o r " i n s t a n t o n " p e r f o r m a n c e . F i g u r e 2 . 1 0 i l l u s t r a t e s a n O T P FPG A i m p l e m e n t a t i o n .T h e I 1 b l o c k r e p r e s e n t s a n i n p u t b l o c k , O 1 - O 3 r e p r e s e n t o u t p u t b l o c k s , a n d t h e w h i t e b o x e sw i t h i n t h e FP G A r e p r e s e n t d e s i g n l o gi c a n d r e g i st e rs . E a c h o f th e f il le d b o x e s r e p r e s e n t s ap e r m a n e n t c o n n e c t i o n i n t e r n a l t o t h e F P G A . T h e s e c o n n e c t i o n p o i n t s d e fi n e t h e s ig n a lr o u t in g a n d i n te r f ac e t o l o gi c an d f i x e d - fu n c t io n b l oc k s. W i t h i n a n o n - O T P c o m p o n e n t ,t h e se c o n n e c t i o n s c a n b e re c on f ig u re d , b u t a r e f ix ed w i t h i n a n O T P c o m p o n e n t . O T P F P G Aa r c h i t e c t u r e d e t a i ls c a n b e f o u n d i n t h e Q u i c k l o g i c a n d A c t e l f a m i l y o f d a t a s h e e t s .

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FPG A Fundamentals

Figure 2.10,O T P F P G A e x am p l e

For r apid prototyping appl i ca t ions , the mos t c r i t i ca l FPGA technology fea ture i s ease off unc t i on de f i n i ti on a nd r e -de f i n it ion . Typ i ca ll y , t he f unc t i on , c on t e n t a nd i mp l e me n t a t i onof t he F PG A wi l l c ha nge num e r ous t i me s ove r the li fe o f t he d e ve l op m e n t a nd i n t e g r a t ioncyc le . For th i s r eason, the conf igura t ion t echnology se lec ted mus t be r eprogrammable r a the rt h a n O T P . ( N o t e t h a t O T P F P G A s a n d n o n - I S P F P G A s m a y h a v e s ig n if ic a n t a p p li ca t io n swi th in s t able , we l l - t e s ted produc t s . )

SR AM -b ased FPG As are often the best design choice for prototyping and developm entprojects. Due t o t he m a ny a dva n t a ge s o f de ve l op i ng de si gns w i t h SRA M - ba s e d FPG As , t h i sbook focuses on deve lopment wi th these devices . I t i s impor tant to r ea l i ze , however , tha ta l mos t a ll o f t he c o nc e p t s a nd a ppr oa c he s p r e s e n t e d w i t h i n t h is book a ls o a pp ly t o OT P a ndn o n - I S P F P G A t e c h n o lo g i es .

Th e F PG A t e c hno l ogy f ie ld ha s e xh i b i te d a tu r bu l e n t h i s to r y w i t h m a ny me r ge rs , ac qu i-s it ions a nd m a r ke t de pa rt u r es . W hi l e a t a ny g i ve n ti me t he r e a re a m e d i um n um be r o f FP G Aman ufac ture r s , the re a re only a few man ufac ture r s w i th s igni f i cant sa le s and sh ipping des igns .I t is i n t e re s t ing t o no t e t ha t no ma jo r FP GA m a nuf a c t u r e r owns t he i r ow n fa b ; t he y a r e a llf ables s and re ly on found ry pa r tne r s to prod uce the i r s i l icon. Table 2 .6 l is ts some o f the l a rg-e s t c u r r e n t p l a yer s in t he FP GA ma r ke t . T he r e l at ive m a r ke t s ha re s o f t he t op f ive ve ndor scon s tant ly f luc tua te based on m any fac tor s. New fami li e s, devices , t echnolog ies and des igni nnova t i ons a re re gu l ar ly a nnou nc e d . Th e i n f o r ma t i on i n th i s t a b le i s no t c om pr e he ns i veand may n ot l is t the fu l l r ange o f any co mp any ' s of fe r ing .

ManufacturerA l t e r a |

Table 2.6TecknoloRyS R A M , F l a sh

Ac t e l An t i f us eLa t t ic e SRA M , F l a shQui c k l og i c An t i f us eX i l i n x S R A M

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C h a p t e r 22 .2 S R A M - B a s e d F P G A A r c h it ec t u reA n FPG A dev ice i s an in tegra ted c ircu i t wi th a centra l array o f l og ic b locks tha t can b e con-nected throug h a conf igurab le in terco nnect rou t ing matr ix . Aro und the per iphery o f the l og icarray is a ring of I /O blocks that can be configured to support d i f ferent interface s tandards.Th i s f l ex ib l e arch i tec ture can be u sed to imp lem ent a wide range o f synchron ous and com bi -natorial d igi ta l logic function s . Figure 2.11 sho ws a s impl i f ied view of a basic FP G A device.

WmlmUmlmmm1UImm

I R | H H H H H H H H H | H | | 8

QN ~

D[2N

DDNND

SFS D~S Q

DS DN DD D@ D

NNDDN[2ND

9NN89DDKIN

DDD[2DK1[- ]

H H H H H H | | H H | | H H H I H

WmimlmEWEEEmm

Figure 2.11 Sim plifiedFPG A block diagram

/ ' o "\ ,~EY~~OIN7

S R A M F P G A s c a n b e c o n fi g u re d a n d r e co n f ig u r e d w i t h t h e I C p e r m a n e n t l y m o u n t e d t othe H W target board . Th i s a l l ows sys tem eng ineers to accom m od ate d es ign fi xes , updates , orfea ture enhan cem ents , wi tho u t cos t ly board re - sp ins or wh i te -wires . Avo id ing the s ign i f icantt ime pena l ty and NRE cos t s a s soc ia ted wi th board re - sp ins or add i t ion o f wires and compo-nents to ex i s t ing hardware i s cr i t i ca l wi th rapid sys tem deve lopment .

F P G A d e v i c e s a re b a s ed o n a n u m b e r o f c o m m o n c o n f ig u r a b le s t r uc tu r es . W h i l e t h e r eare m inor and major var iat ions in the im plem enta t ion o f these structures betw een m anu-facturers and dev ice fami l i es , the s tructures are common to a lmos t a l l ma ins tream FPGAdevices . The fundamenta l FPGA s tructures are as fo l l ows .

F P G A S t r u c t u r e s9 L o g i c B l o c k s9 R o u t i n g M a t r i x & G l o b a l S i gn a l s9 I 1 0 B l o c k s9 C l o c k R e s o u r c e s9 M u l t i p l i e r9 M e m o r y9 A d v a n c e d F e a tu r es

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FPGA Fundamenta ls2 .2 .1 FPGA Log ic Block S truc tureFP G A log ic b locks ma y have d i f fe ren t a rch i t ec tu res w i th in d i f fe ren t fami l ies , even i f t hey a ref ro m t h e s a m e m a n u fa c t u re r . E a c h m a n u fa c t u r e r t e n d s t o c a l l t h e l o w e s t -l e v e l F P G A l og i cb lock b y d i f fe ren t name s inc lud ing log ic ce ll , s li ce, rnacroce ll , and log ic e l em ent (LE) . To c l ar -i fy furth er discussions, the term s l i c e wil l be used to refer to this s t ructure. A t radi t ional s l icewi l l t yp i ca l ly con ta in one o r more N- input l ook-up t ab l es (LUTs) a long wi th one o r more f l i p -f lops, s ignal rout ing muxes, cont rol s ignals and carry logic. Figure 2.12 shows a generic s l ice.In t he a dva nced FP G A fami l ies , the i n t e rna l a rch i t ec tu re o f a s l ice is o f t en qu i t e com pl i ca t ed .

Log ic Block

i i : ! : i i :Figure 2.12 Simplif iedslice arch itecture

E a c h L U T e l e m e n t c a n i m p l e m e n t a n y B o o l e a n fu n c t i o n w i t h N o r f e w er in p u ts . T h es ize and in t e r re l a t i onsh ip o f LUT s wi th in the log ic b lock ca n a f fec t t he resource u t i l i za t iona n d i m p l e m e n t a t i o n o f a d e s ig n . D e s i g n e rs s h o u l d b e f a m i l ia r w i t h t h e d e t a il s o f t h e l o gi cb lock a rch i t ec tu re fo r t he mos t e f f i c i en t des ign implementa t ion . Trad i t i ona l ly , a major i t y o ft h e i m p l e m e n t a t i o n s o f L U T a rc h i t e c t u r e s h a v e fo u r i n p u ts .T h e L U T is s im p l y a m e m o r y e l e m e n t . T h e d e la y t h r o u g h a n L U T is c o n s t a n t r e g a rd -le ss o f t h e B o o l e a n fu n c t i o n i m p l e m e n t e d . T h e L U T d e l a y is f ix e d , s i n c e i t is b a s e d o n am e m o r y e l e m e n t i m p l e m e n t a t i o n . L U T e l e m e n t s m a y a ls o b e u s ed a s m e m o r y e l e m e n t s s u c has FIFOs. Thi s fea tu re wi l l be d i scussed in mo re de t a i l i n t he me mo ry sec t ion o f t h i s chap te r .F i gu re 2 .1 3 i l lu s t ra t e s t h e e q u i v a l e n c e b e t w e e n a B o o l e a n l o g ic g a te i m p l e m e n t a t i o n a n d a nL U T -b a s e d i m p l e m e n t a t i o n o f t h e s a m e fu n c t i o n a l i t y .

I i '

- - - -ZBcD . . . . . .

C o m b i n a t o ri a l L o g i c

B Z

: i . i. . .. . . . . . . . . . . .

D C B A Z0 0 0 0 00 0 0 1 00 0 1 0 0

9 9 91 0 0 1 11 0 1 0 01 0 1 1 01 1 0 0 01 1 0 1 11 1 1 0 01 1 1 1 1

Figure 2.13 Loo k-up table equivalence2 5


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Th e LU T e l em en ts can e i ther f eed o u t o f the s l ice o r in to a reg is ter. R eg i sters are a lsoreferred to as f l i p - f l o p s , o r FFs. FFs are t im e-b ased e l em en ts an d are fun d am en ta l e l em en tso f a ll c lo ck -b ased c i rcu i t s. Th e f l ip s f lo p s can sup p o r t c lo ck en ab l e an d asyn ch ro n o u s s e tan d rese t fun c t i o n al i ty . There are typ ica l ly m an y d i f f eren t p o ten t ia l co n f i g urat i o n s fo r theseflip-flops. For m ore details on a specific de vice family, refer to t he manu facturer device familyd o c u m e n t a t i o n .

In order to support higher levels of functionality, slices may be grouped together by themanufacturer, forming a larger structure. Figure 2.14 illustrates a grouping of slices forming alarger s tructure . The nomenclature , archi tecture , features and s izes o f these larger blocks var-ie s between supplier, family and device. Some example names for these combined logic blockgroups are: tile, configurable logic block (CLB ), logic array block (LAB ), and Meg aLAB . Toclarify further discussions, t he term C L B will be used to refer to m ultislice structures.

. . . . . . . . .~ : ! ! ! i i i ii !! i i i~i! i l li i i i ; i : i i ! ~i } i l ! i ) i i ~: ; i i i ; i l ii !~;! i :ill i ::i~

: i i l .

!i!!i:?i:!!:iii : i i ~

Figure 2.14Simplif ied Xil inx CLB

Finally, these logic tiles or blocks can have different architectures within differentdev ices an d m ay even vary be tween fam i l i e s o f a sp ec i f i c FPGA ven do r . The g en er i c FPGAlogic block goes by different names including: logic cell , slice, macrocell , and logic element.Groups of logic blocks are also called by various names including: configurable logic block(CLB), logic array block, and M egaLAB.

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FPGA Fundamenta ls2 . 2 .2 F P G A R o u t i n g M a t r ix a n d G l o b a l S ig n a lsT h e f u n d a m e n t a l r o u t in g e l e m e n t s fo r a n F P G A a r e t h e h o r i z o n t a l/ v e r ti c a l r o u t in g c h a n n e l sa n d p r o g r a m m a b l e r o u ti n g s w i tc h e s. T h e n u m b e r o f ro u t in g c h a n n e l s v a r i es b e t w e e n F P G Ad e v i c e m a n u fa c t u r e r s a n d f a m i l ie s . T h e fu n c t i o n o f t h e h o r i z o n t a l a n d v e r t i c a l r o u t in g c h a n -n e ls i s t o p r o v i d e a c o n n e c t i o n m e c h a n i s m b e t w e e n r o u t in g s w i tc h e s . T h e r o u t in g s w i tc h i sp ro g ra m m a b l e a n d c a n p ro v i d e e i t h e r 1 8 0- o r 9 0 -d e g re e ro u t i n g p a t h . T h e ro u t i n g s w i t c h e sa r e lo c a t e d b e t w e e n e a c h c o l u m n a n d r o w o f C L B s . T h e s w i tc h e s a re c o n n e c t e d t o t h e C L B sa t t h e i r i n p u t s a n d o u t p u t s w i t h w i r e s e g m e n t s . F ig u re 2 .1 5 s h o w s a t y p i c a l r o u t in g m a t r i x .

| mm m

9 lI l

)Il

__21

I

t~ Slice

RoutingSegments

~ i , ~ S w i t c h Box

Figure 2.15FPG A signal routing

C o n s t r a in t s h a v e a s ig n i fi ca n t im p a c t o n r o u t in g p a t h i m p l e m e n t a t i o n , w h i c h w i l l a f fe c tl o g ic t im i n g . C o n s t r a i n t i m p l e m e n t a t i o n i s a n i m p o r t a n t to p i c a n d w i l l b e a d d re s s e d in a la t -e r c h a p t er . T h e n e x t m e c h a n i s m t h e F P G A e m p l o y s f o r c o n n e c t i n g b o t h s w i tc h e s a n d C L B sis c a r ry c h a i n l og ic . T h e d i r e c t i o n o f t h e c a r ry c h a i n c a n e i t h e r b e v e r t i c a l o r h o r i z o n t a ld e p e n d i n g o n t h e a r c h i t e c tu r a l c o n v e n t i o n o f t h e F P G A d e v i ce . C a r r y c h a i n l o g ic is c o m -m o n l y u s e d t o b u i ld l a rg e ef f ic i e n t s t ru c t u r e s fo r i m p l e m e n t i n g a r i t h m e t i c f u n c t i o n s w i t h i nt h e g e n e ra l l o g ic f ab r ic . F ig u re 2 .1 6 s h o w s a n e x a m p l e o f a c a r ry c h a i n i m p l e m e n t a t i o n .

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Ch apter 2

Figure 2.16 C arry og ic

In para l le l wi th the regula r s igna l rou t ing m at r ix , mos t m anufac ture rs have a lso imple-m ented g loba l low-skew rou t ing resources . These resources a re typ ica l ly l imi ted in q uan t i tyand sho uld be reserved for h igh-per form ance and h igh- load s igna ls . Globa l rou t ing resourcesare o f ten used for c lock and cont ro l s igna ls , which tend to be bo th h igh-per formance andhigh- fanou t . D es igners can a l low the too ls to se lec t the s ignals tha t a re ass igned to g loba lrou t ing resources , o r they c an co nt ro l g loba l ass ignm ents th rough the use of des ign con-s t ra in ts and too l swi tches .2 . 2. 3 F P G A I / O B lo c ksTh e r ing of I /O banks sur round ing the a r ray of CLBs i s used to in te rface the F PG A deviceto ex te rna l c om pon ents . Trad i t iona l ly , the r ing of I /O banks is e i ther s taggered or in - l inearound the FPGA device . The d i f fe rence be tween s taggered and in - l ine I /O i s jus t as then a m e s d e s cr ib e . A t r a d e- o f f m u s t b e m a d e a r c h i t e c t u r a l ly b e t w e e n t h e n u m b e r o f av a i la b l es igna l p ins and th e a m oun t o f resources implem ented w i th in the dev ice . This ra t io i s de te r -m i n e d a n d i m p l e m e n t e d b y t h e m a n u f a c t u r e r a n d w i ll v ar y fr o m d e v i c e t o d e v i ce . F i gu r e2 .1 7 s h o w s a g e n e r ic I / O b a n k i m p l e m e n t a t i o n m e t h o d .

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L OGI CA R R A Y

5 m 4

F i gu re 2 . 17F P G A I / O b a n k s

I / O b l o c k ( I O B ) is a c o m m o n t e r m u s e d t o d e s cr i be a n I / O s t r u c t u r e, a l t h o u g h o t h e rnames may a l so be u sed . An lOB inc ludes inpu t and ou tpu t r eg is te r s , con t ro l s igna ls , muxesand c lock s igna ls . The s igna ls rou ted th rough the I /O b lock can be reg is te red o r un reg is te red .T h e o u t p u t b l o c k m a y a l so su p p o r t t h e i m p l e m e n t a t i o n o f a t h r e e - s t a t e c i r c u i t w i t h i n t h el O B . I n c o n t r a s t , t h e i n p u t r e g i st e rs w i l l n o t h a v e a p a t h t h r o u g h a t h r e e - st a t e d e v i c e. S i n c eC M O S c ircu i ts use pow er in the indeterm ina te s ta te , inp u ts le f t f loa t ing can cause ex trap ow er to be c ons um ed. Thus, unused FPG A inputs should not be left f loating. O n e a p p r o a c h i sto con f igu re unused p ins a s ou tpu ts . F igu re 2 .18 p resen ts a s imp l i f ied lOB a rch i tec tu re .

i I l l . m l i ll u l m I I I I

I DDR iI! !I 3-s tate I

i . = l . m m - = - . I l l , I ~ ' I

I DDR II

,I II u t Ii l , l . = i f , i n I

I - _ - ~ - I

I

F i g u r e 2 . 1 8E x a m p le D D R I O

b l o c k s t r u c t u r e

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Ch apter 2In o rder to in te r face to d i f fe ren t types o f logic, an F PG A device IOB mus t suppor t m ul t i -

p le IO in te r face s tandards . Both s ing le -ended and d i f fe ren t ia l opera t ion a l m odes a re typ ica l lysuppor ted . Examples o f s ing le -ended s tandards inc lude PCI and LVTTL. Examples o f di ffe r-en t ia l s tandards a re LVDS and LV PECL . Due to the large numb er o f s tandards , i t i s essen t ia ltha t FPGA fami ly da ta shee t and appropr ia te app l ica t ion no tes be rev iewed pr io r to hardwaredes ign to guaran tee cor rec t FP GA opera t ion . I t may a l so be necessary to re fe rence spec if ics t an d a r d s s in c e F P G A d o c u m e n t a t i o n m a y n o t r e p e a t s ta n d a r d t e c h n i c a l s p e c if ic a ti o ns .Th e se lec t ion of a spec if ic I /O s tandard can be im plem ented v ia a se lec t ion wi th in th e F PG Atool set . This select ion is typical ly made when assigning pin locat ions to specif ic s ignals . Pinloca t ion ass ignment can s ign i f ican t ly impac t des ign implementa t ion and per formance . P inass ignm ent and p in lock ing i s d i scussed in de ta i l l a te r in th i s book . O the r I /O fea tures ando p e r a t i o n a l m o d e s m a y al so be i m p l e m e n t e d w i t h i n t h e F P G A a n d b e u n d e r t h e c o n t r o l o fthe des ign team. Fol lowing i s a l i st o f po te n t ia l conf igurab le I /O fea tures .

10B Conf igurab l e Fea tures9 Pull-up or pul l-down9 S t a t u s o f " u n u s e d " I / 09 I / 0 s le w r a te9 I / 0 d r iv e s t r e n g t h9 Suppor ted I /0 s tandards9 C h a r a c t e r i s ti c i m p e d a n c e t e r m i n a t i o n

2 . 2 . 4 F P G A C l o c k R e so u rc e sT h e p r i m a r y F P G A e l e m e n t f or h a n d l i n g , m a n a g i n g a n d a d ju s ti n g F P G A l o ca l a n d s ys te mc lo c k s is t h e C L O C K b l o ck . C l o c k m a n i p u l a t i o n c a n b e i m p l e m e n t e d b a s e d o n t w o d i f fe r e n ttechnolog ies : the phase- locked loop (PLL) a nd the de lay lock loop (DLL ) .

PLLs genera te the des ired c lock phase or f requency ou tpu t by making ad jus tm ents to avo l tage-co nt ro l led osc i lla to r . PLLs a re inhere n t ly ana log c i rcu i ts and there fore they per formbet te r w hen suppl ied wi th "c lean" power and ground . I t may be desi rab le to p rov ide sp l i tp lanes to p rov ide i so la ted power and grounds . This can com pl ica te board layout.

DLLs access s igna ls f rom a ca l ib ra ted tapp ed de lay l ine c i rcu i t in te rna l to the FP GA toprod uce the desired clock phase or f requency. DL Ls are digi tal c ircui ts . Figure 2.19 presents agraphica l represen ta t ion of the two technolog ies .

To prov ide wors t -case c lock ing de lays w i th in F PG A devices , bo th g loba l and reg iona lc lock ing tech niques a re used to d isperse c lock ing across the FP G A fabr ic . Glob a l c lock inginc ludes the im plem enta t ion of g loba l stee r ing log ic and buf fe rs fo r d i s t r ibu t ing the c lockw i t h i n t h e F P G A . G l o b a l c l o c k in g t y p i ca l ly b eg i n s in t h e m i d d l e o f t h e d e v i c e a n d t h e nbranche s in to smal le r reg ions. FP GA devices a re typ ica l ly d iv ided in to four o r more c lock-ing reg ions . Regiona l c lock ing can a lso be prov ided to ind iv idua l FPG A reg ions . F igure 2 .20il lustrates this point .

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Figure 2.19PLL and DL L clocking

C l o c k I n

Ph a s e F r eq u n ec yDetector

C l o c k I n

Ph a s e D e t ec to r

! i c h a r ~ P u m p I . .. .. 7 ~i c o , . : o , n ] O e ,a , ,,n e !

v c o - v o w , , ~ o , ~ , , . ~ i m ~ ~ h - - n ~ r u r. . . . . . . . . . . . . . . . . . . . . . . i: 0 Sei i lat~ !

. . . . . . . . . . . . . i . . . . . . . . . . . . . . . . . .. . . . . .

. .. ~ = Analog C i rcu i tC l o c k O u t C l o c k O u t

Figure 2.20Po tent ia l c lockingimplementa t ion

C l o c k . ~ -

~r

~r ,r _ .i w

Differential clocking is typically implemented for global signal distribution and isessential for high-speed mem ory I/O interface (Exam ple D D R2 interface). Th e desirablecharacteristics of differential clocking include faste r edg e rates, improved noise im mu nity,and inherently balanced duty cycles. Differential c locking a lso supports higher frequencyoperation and m ore reliable d ata transmission.3 1


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Chapter 22 . 2 . 5 F P G A MemoryM e mor y r e s ourc e s a re c r i ti c a l f o r m a ny a dva nc e d FP G A a pp l ic a t ions . Th e r e a r e two p r ima r yt ypes o f me m or y w i t h i n FPG As , d i s t r ibu t e d a n d b l oc k m e mor y . D i st r ibu t e d m e mo r y ta ke sa dva n t a ge o f t he f a c t t ha t L UT e l e me n t s a r e i mp l e me n t a t ions o f SR AM me m or y b l ocks .B l oc k m e m o r y i s t h e i m p l e m e n t a t i o n o f d e d i c at e d S R A M m e m o r y b l oc k s w i t h i n t h e F P G A .

M e mo r y e l e me n t s e m be dde d w i t h i n FP GA s a r e usua l ly re f er re d t o a s b l oc k RA M ,e mb e dde d s ys te m b loc ks ( ESB), sys te m RAM , a nd c o n t e n t a ddr e ss a b le me m or y ( CA M ) .Hi ghe r - pe r f o r ma n c e F PG A de v i c es t yp ic a l ly ha ve l a r ger numbe r s o f de d i c a t e d m e mo r y

ba nks i n a dd i t i on t o t he i nhe r e n t d i s tr i bu t e d me m or y f unc t iona l i ty . De d i c a t e d m e mor yb l oc ks in du a l - po r t c on f igu r a t ion m a y s uppor t a s ync hr onous a nd s ync hr onous r e a ds a ndwr i t e s . Othe r potent i a l capabi l i t i e s inc lude pa r i ty , c locking cont ro l and re se t func t iona l -i ty . Th ey c an b e conf igured to suppor t a broad range o f appl i ca t ions . Exam ple appl i ca t ionsi nc lude c a c he f o r a n e mb e dde d FP GA pr oc es s o r co r e o r a F IFO s uppor t ing da t a bu f f e r ing f o ra D S P f u n c t io n .

f ~\ ,( E Y ~ J~ O I N 1

2 .3 A d v a n c e d F P G A F e a tu re sAs F PG A devices and a rchi tec tures cont inue to evolve , ce r t a in advanc ed s t ruc tures wi l l beimp lem ented in s igni fi cant ly d i f fe rent ways by d i f f e rent manufac ture r s. O f ten these adv ancedFP G A s t ruc tures and fea tures a re t a rge ted tow ard ve ry spec ia li zed ap pl i ca tions an d t echno l -ogy spec ia l ti e s. T he com pe t i t ive m arke t of programm able devices encourages manu fac turer sto dev elop and offer fea tures that n o on e e lse offers . Th is a l lows m anufacturers to d i f ferent ia tethe i r produc t s , c l a im supe r ior pe r formance an d deve lop som e use r loya lty to an a rchi t ec turetha t m eets th eir specia lized needs ef fectively.

Som e of the t echno logy a reas wh ere man ufac ture r s a re of fer ing advan ced fea tures inc lude :A d v a n c e d F P G A S t r u c tu r e s a n d Im p l e m e n t a t io n s9 En han ced c l o ck f ea tures9 In te l l ec tual proper ty ( IP)9 Em bed ded processors (hard an d sof t)[] D igital signal proce ssing (block s, tools , design f low )

A dvan ced I / 0 s tandards and pro toco l suppor t2 . 4 S u m m a r yThi s c ha p t e r p r ov i de d a h i gh - le ve l ove r v i e w o f t he p r ima r y c a t egor ie s o f p r og r a mm a bl elogic and the f ac tor s tha t a f f ec t PLD technology se lec t ion . The three PLD ca tegor ie s inc ludeS P L D s , C P L D s a n d F P G A s . T h e c ro s so v e r b e t w e e n C P L D a n d F P G A a p p l ic a ti o n s w asdi scussed. Th e ove r lap be twe en th e two t echn olog ies can be s ignif icant ; how ever , for l arger ,mor e c om pl e x p r o j ec t s, FP GA t e c hno l ogy p r ov i de s ma n y be nef it s. Th e p r i ma r y type s o fFPGAs a nd ma jo r FPGA ma nuf a c t u r e r s we r e p r e s e n t e d . The p r i ma r y FPGA c a t e gor i e s a r eO T P a nd S RA M - ba s e d . SR AM - ba s e d FPG As a re t yp ic a ll y be t t e r s u it e d fo r r a p id s ys te m

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FPGA Fundamentalsp ro t o t y p i n g a p p l i c a ti o n s d u e t o t h e i r r e p ro g ra m m a b i l it y a n d f le x ib i li ty . S i n c e S R A M -b a s e dF P G A s a r e w e ll s u it e d fo r r a p i d s y s te m p ro t o t y p i n g , s p e c ia l a t t e n t i o n w a s fo c u s e d o n t h ea rc h i t e c t u r e o f S R A M -b a s e d F P G A s . T h e s t ru c t u re s i n t ro d u c e d i n th i s c h a p t e r w i ll b e re f-e r e n c e d t h ro u g h o u t t h e r e m a i n d e r o f t h e b o o k . F i g u re 2 .2 1 i l lu s t ra t e s t h e F P G A s t ru c t u re spresen ted in t h i s chap te r .

| H i | H | | | | | H | a I H I lW i - ~ I /O B l o c k s

" ~ " ~ R o u t i n g M a t r ix" ~ " ~ C L B I S l ic e

' ~ " H a r d " P r o c e s s o r C o r e1 3 W ~ M u l t i p l i e r~ ~ M e m o r y

" ~ ~ " S o f t " I P C o r e

~ "Sof t " P r o c e s s o r C o r eNNI ~ C l o c k B l o c k

" H a r d " E t h e rn e t M A C C o r eN N

F i g u r e 2 . 2 1 G e n e r i c F P G A a r c h i t e c t u r e

T h e fu n d a m e n t a l F P G A s t ru c t u r e s p r e s e n t e d i n c l u d e d t h e C L B a n d s l i c e , r o u t i n g m a t r i x ,g loba l s igna l s , I /O b locks , c lock ing resources and memory . The advanced fea tu res , i nc lud ingi n t e ll e c t u a l p ro p e r ty , e m b e d d e d p ro ce s so r s, D S P b l o c k s a n d a d v a n c e d I / O w i l l b e p r e s e n t e di n m o re d e t a i l i n d e d i c a t e d c h a p t e r s l a te r i n t h e b o o k .

T h i s b o o k u s e s t h e t e rm slice t o r e p re s e n t t h e l o w e s t - l e v e l e l e m e n t w i t h i n a n S R A M-b a s ed F P G A . A s lic e is t h e f u n d a m e n t a l e l e m e n t w i t h i n a n S R A M - b a s e d F P G A t h a t i sused to bu i ld l a rger log ic st ruc tures . S l ices may have d i f fe ren t a rch i t ec tu res w i th in d i f fe ren tf a m il ie s , e v e n a m o n g F P G A d e v i c e s f ro m t h e s a m e m a n u fa c t u re r . A l t e rn a t i v e n a m e s fo r as l i ce i nc lude log ic ce l l , macroce l l , and log ic e l ement . The e l ement s making up a s l i ce i nc ludeLUTs, f l i p - f lops , ded ica t ed log ic and rou t ing fo r connec t ing the e l ement s . The LUT i s am e m o ry e l e m e n t u s e d to i m p l e m e n t a n y B o o l e a n fu n c t i o n w i t h N o r f e w e r i n p u ts , w h e re Nis t h e n u m b e r o f in p u t s i n t o t h e L U T . T h e n u m b e r o f i n p u t s to t h e L U T m a y v a ry b e t w e e nmanufac turer , fami ly and dev ice .

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C h a p t e r 2M a n u fa c t u r e r s o f S R A M F P G A s m a y a l s o g ro u p s lic e s i n t o l a rg e r st ru c t u re s t o fo rm m o re

com plex log ic b locks capab le o f p rov id ing a h igher l eve l o f func t iona l i t y . The nam e th a t isused fo r sl ice g roups w i th in th i s book is C L B . As wi th s l i ces , t he nomencla tu re , a rch i t ec tu re ,fea tu res , and s i ze o f t hese l a rger b locks m ay vary be twe en man ufac turer , fam i ly and dev ice .A l t e rn a t i v e n a m e s fo r C L B s in c l u d e tile, lo~c array bloc k a n d MegaLAB.

To bu i ld l a rge log ic s t ruc tures , SRAM FPGAs use ver t i ca l and hor i zon ta l rou t ing s igna l si n a m a t r i x a r r a n g e m e n t t h a t a r e p a i re d w i t h s w i t c h b o x e s a t in t e r s e c ti o n s t o s u p p o r t F P G Ae l e m e n t i n t e r c o n n e c t i o n . T h e s e s w i tc h b o x es o r r o u t i n g s w it c h es c a n i m p l e m e n t b o t h 9 0 -a n d 1 8 0 -d eg re e ro u t i n g c o n n e c t i o n s . S w i t c h b o x e s a re l o c a t e d a t t h e i n t e r s e c t i o n o f ro w sand c o lum ns a nd in t e r faces o f CLBs and s li ces .

S R A M F P G A s i n te r f a c e t o e x t e rn a l c i r c u i tr y v i a a r i n g o f I / O b l o ck s . T h e s e I / O b l o c k sare re fe r red to i n t h i s boo k as IOBs . G ro u p s o f I/ O b l o c k s c a n b e c o l l e c te d i n t o I / O b a n k s .Ind iv idu a l lOBs ha ve the ab i l it y to i n t e r face w i th a wide range of I /O s t andards , wh ich ca nb e s e l ec t e d b y t h e F P G A d e s ig n e r. A v a i l a b le l O B s t a n d ard s m a y b e li m i t e d b a s e d o n t h ec o n f i g u ra t io n o f th e I / O b a n k o f i n d i v id u a l l O B s . T h e p r i m a ry F P G A e l e m e n t f o r h a n d l i n g ,managing and ad jus t ing FPGA loca l and sys t em-leve l c locks i s t he C L O C K b loc k. T o p ro v i d eimproved marg in t iming wi th in FPGAs, g loba l and reg iona l c locks should be u t i l i zed .

S R A M F P G A s h a v e t w o p r im a ry t yp e s o f e m b e d d e d m e m o ry : d i s tr i b u te d a n d b l o c km e m o ry . D i s t r ib u t e d R A M t a k es a d v a n t a g e o f t h e m e m o ry -b a s e d s t ru c tu r e o f L U T s w i t h i nt h e l o gi c f a b ri c; b l o c k R A M s a r e d e d i c a te d m e m o ry b lo c k s p l ac e d w i t h i n t h e F P G A fa br ic .T h e s iz e a n d s u p p o r t e d m o d e s o f o p e ra t i o n fo r b l o c k m e m o r i e s m a y v a ry b e t w e e n m a n u fa c -tu re rs an d dev ice fam i li es .

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2 FPGA Fundamentals