Digital Signal Processor TMS320C6000 1

TMS320C6000 Architecture

Ismail MAJDOUB

● 70 % of the market ==> Texas Instrument

● 30% ==> Motorola, Analog Devices, Lucent Technologies, Nec et Oki.

Intro

TMS320C6474

● 3 cores C64x+

● 1 Ghz per core ==> 3 Ghz per chip

● Up to 24000 MIPS

● Price : 261$

TMS320C6713

● 1 core C67x

● Operating at 225 MHz

● Up to 1800 MIPS

TMS320C6474/C6713 features

C6000 System Block Diagram● The C6000 processor can be divided into three main

parts :

● CPU (or the processor “core”)● Memory● Peripherals

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C6000 System Block Diagram

* The arithmetic operations, such as subtract or add (SUB or ADD), can be performed by all the units, except the .M units

C67x core architecture

Functional Unit Use

.M : Multiplication unit

Used for multiplication operation :

-1 multiplication 32 x 32 bit.

-2 multiplications 16 x 16 bit.

-4 multiplications 8 x 8 bit.

.L : Logical unitUsed for logical and arithmetic operations

(And, Or,…).

.S : Shift unitused for branch, bit

manipulation and arithmetic operations

.D : Data unitused for loading, storing and arithmetic

operations

● The CPU consists of eight independent functional units divided into two data paths,A and B.

● Each path includes 16 X 32bits register [A0-A15] & [B0-B15]

● Each functional unit can read directly from or write directly to the register file within its own path.

● The memory is organized in 3 Levels :

● First Level (L1)

– Near to the CPU– 4KB for L1D and L1P– configured as cache (Default)

● Second Level (L2)

– 256KB– Configurable as cache

** Cache :

● A fast and close memory to the CPU

● Data that is requested by the CPU is moved automatically from slower memories to faster memories where it can be accessed quickly

TMS320C6713 on-chip Memory

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Digital Signal Processor TMS320C6000 9

● Third Level (L3)

– Off-chip(external) memory, can be accessed through the EMIF

TMS320C6713 off-chip Memory

● External memory can be :

– RAM– ROM– Flash

● The CPU is able to perform three simultaneous bus operations: program-read and two data-read/writes.

● Program Data bus is 256 bits => CPU can read 8 simultaneous instructions coded on 32 bits

● Data Data bus is 64 bits => CPU can read/write two operands of 32 bits at the same time.

Internal buses

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● EMIF External Memory Interface provides the necessary interface for accessing external memory.

● DMA Direct Memory Acess allows the movement of data from one place in memory to another place without interfering with the CPU operation.

● Boot Loader boots the loading of code from off-chip memory.

● McBSP Multichannel Buffered Serial Port provides a high-speed multichannel serial communication link.

● HPI Host Port Interface is a parallel port that allows a host processor to directly access the CPU memory space.

● Timer provides two 32-bit counters.

● Power Down unit is used to save power for durations when the CPU is inactive.

Peripherals on a typical C6x processor

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● Code Composer Studio :

● Cross Compiler

Development Tool - IDE