1981 Index IEEE Transactions Computers Vol. C-30 · IEEETransactions on Computers Vol. C-30 ... Braun, Robert D., and Donald D. Givone; Ageneralized algorithm for ... Daniel M., and

1981 IndexIEEE Transactions on Computers

Vol. C-30

This index covers all items-papers, correspondence, reviews,etc.-that appeared in this periodical during 1981, and items from prioryears that were commented upon or corrected in 1981. The index isdivided into an Author Index and a Subject Index, both arrangedalphabetically.

The Author Index contains the primary entry for each item; thisentry is listed under the name of the first author and includes coauthornames, title, location of the item, and notice of corrections and commentsif any. Cross-references are given from each coauthor name to the nameof the corresponding first author. The location of the item is specified bythe journal name (abbreviated), year, month, and inclusive pages.

The Subject Index contains several entries for each item, eachconsisting of a subject heading, modifying phrase(s), first author's name,and enough information to locate the item. For coauthors, title,comments and corrections if any, etc., it is necessary to refer to theprimary entry in the Author Index. Subject cross-references are providedas required by the subject matter. Also provided whenever appropriateare listings under generic headings such as Bibliographies (for any paperwith at least 50 references, as well as papers that are exclusivelybibliographies), Book reviews, and Special issues.

AUTHOR INDEX

A

Abraham, Jacob A., and Daniel D. Gajski; Design of testable structuresdefined by simple loops; T-C Nov 81 875-884

Abu-Sufah, Walid, David J. Kuck, and Duncan H. Lawrie; On theperformance enhancement of paging systems through programanalysis and transformations; T-C May 81 341-356

Ackland, Bryan D., and Neil H. Weste; The edge flag algorithm-A fillmethod for raster scan displays; T-C Jan 81 41-48

Adam, Vladimir, see Suarez, Ricardo E.; T-C Jan 81 79-81Agarwal, Krishna K., see Agrawal, Dharma P.; T-C Feb 81 153-156Agarwal, Vinod K., and Andy S. F. Fung; Multiple fault testing of large

circuits by single fault test sets; T-C Nov 81 855-865Agrawal, Dharma P., and Krishna K. Agarwal; Efficient sorting with

CCD's and magnetic bubble memories (Corresp.); T-C Feb 81153-156

Agrawal, Vishwani D.; An information theoretic approach to digital faulttesting (Corresp.); T-C Aug 81 582-587

Arden, Bruce W., and Hikyu Lee; Analysis of chordal ring network(Corresp.); T-C Apr 81 291-295

Armstrong, James R., and F. G. Gray; Fault diagnosis in a Boolean n

cube array of microprocessors (Corresp.); T-C Aug 81 587-590Armstrong, James R, see Singh, A. D.; T-C Sep 81 671-674Armstrong, James R, see Pomper, Gardner; T-C Sep 81 674-679Avis, David, and Godfried T. Toussaint; An optimal algorithm for

determining the visibility of a polygon from an edge; T-C Dec 81910-914

B

Baba, Takanobu, and Hiroshi Hagiwara; The MPG system: Amachine-independent efficient microprogram generator; T-C Jun 81373-395. Correction, Oct 81 818

Bandyopadhyay, A. K., see Sengupta, A.; T-C Mar 81 237-240

Barbacci, Mario R.; Instruction Set Processor Specifications (ISPS): Thenotation and its applications; T-C Jan 81 26-40

Barbacci, Mario R., see van Dam, A.; T-C Jul 81 513-519Barzilai, Zeev, Jacob Savir, George Markowsky, and Merlin G. Smith;

The weighted syndrome sums approach to VLSI testing (Corresp.);T-C Dec 81 996-1000

Benjauthrit, B., see Reed, I. S.; T-C Jul 79 487-492. Addendum, Jun 81 453

Bentley, J. L., and Th. Ottmann; Algorithms for reporting and countinggeometric intersections; T-C Sep 79 643-647

Comments by Brown, Kevin Q., T-C Feb 81 147-148Biswas, Nripendra N., see Mathialagan, Ayakannu; T-C Feb 81 144-146Bokhari, Shahid H.; On the mapping problem; T-C Mar 81 207-214Bongiovanni, Giancarlo, and C. K. Wong; Tree search in major/minor

loop magnetic bubble memories' T-C Aug 81 537-545Booth, Taylor L.; Editor's notice; T-C Mar 81 169-171Booth, Taylor L., Sr. ed.; In memoriam-Richard E. Merwin; T-C Dec 81

909Bozorgui-Nesbat, Saied, see McCluskey, Edward J.; T-C Nov 81 860-875Brassard, J-P., see Gecsei, Jan; T-C Feb 81 164-168Braun, Robert D., and Donald D. Givone; A generalized algorithm for

constructing checking sequences (Corresp.); T-C Feb 81 141-144Brown, Kevin Q.; Comments on 'Algorithms for reporting and counting

geometric intersections' by Bentley, J. L., and Ottmann, Th.; T-CFeb 81 147-148

Brown, N. C., see Williams, T. W.; T-C Dec 81 987-988Butler, Jon T.; Speed-efficiency-complexity tradeoffs in universal

diagnosis algorithms (Corresp.); T-C Aug 81 590-596Butler, Jon T., Guest ed., and Anthony S. Wojcik Guest ed.; Guest editors'

comments; T-C Sep 81 617-618

C

Canto, M. A., see Dormido, S.; T-C Sep 81 699-703Chang, Hsu, see Lee, D. T.; T-C Jun 81 396405Chang, Oscar, see Suarez, Ricardo E.; T-C Jan 81 79-81Chattopadhyay, D. K., see Sengupta, A.; T-C Mar 81 237-240Choudhury, A. K., see Sengupta, A.; T-C Mar 81 237-240Chu, Wesley W., Guy Fayolle, and David G. Hibbits; An analysis of a

tandem queueing system for flow control in computer networks; T-CMay 81 318-327

Chwa, Kyung-Yong, and S. Louis Hakimi; On fault identification indiagnosable systems; T-C Jun 81 414 422

Clark, Douglas W., Butler W. Lampson, and Kenneth A. Pier; Thememory system of a high-performance personal computer; T-C Oct81 715-733

Clary, James B., see Priester, Robert W.; T-C Nov 81 884-889Cohn, Martin, see Robinson, John P.; T-C Jan 81 17-23Criscione, Donald J., see Dervisoglu, Bulent I.; T-C Oct 81 800-810

D

Daehn, Wilfried, and Joachim Mucha; A hardware approach toself-testing of large programmable logic arrays; T-C Nov 81 829-833

Dao, Tich T.; SEC-DED nonbinary code for fault-tolerantbyte-organized memory implemented with quaternary logic(Corresp.); T-C Sep 81 662-666

DasGupta, S., C. R. P. Iartmann, and L. D. Rudolph; Dual-mode logicfor function-independent fault testing; T-C Nov 80 1025-1029.Correction, Oct 81 819

Davidson, Scott, David Landskov, Bruce D. Shriver, and Patrick W.Mallett; Some experiments in local microcode compaction forhorizontal machines; T-C Jul 81 460-477

Davio, Marc; Kronecker products and shuffle algebra; T-C Feb 81116-125

Davio, Marc, and Jean-Pierre Deschamps; Synthesis of discrete functionsusing 12L technology; T-C Sep 81 653-661

Dervisoglu, Bulent I., and Donald J. Criscione; A hard programmablecontrol unit design using VLSI technology; T-C Oct 81 800-810

Deschamps, Jean-Pierre, see Davio, Marc; T-C Sep 81 653-661Despain, A. M.; Very fast Fourier transform algorithms hardware for

implementation; T-C May 79 333-341Comments by Prakash, S., and Rao, V. V., T-C Jun 81 452

Dias, Daniel M., and J. Robert Jump; Analysis and simulation ofbuffered delta networks; T-C Apr 81 273-282

IEEE T-C 1981 INDEX -2

Dormido, S., and M. A. Canto; Synthesis of generalized parallel counters(Corresp.); T-C Sep 81 699-103

E

El-Dessouki, Ossama Ilbrai, and Wing H. Huen; Distributedenumeration on between computers; T-CSep 80 818-825. Correction,Jan 81 87

Ellis, C.; Concurrent search and insertion in AVL trees; T-C Dec 80811-817

Comments by Gottlieb, A., T-C Oct 81 812English, W. 1; Synthesis of finite state algorithms in a Galois field

GFVI (Corresp.); T-C Mar 81 225-229

F

Fayolle, Guy, see Chu, Wesley W.; T-C May 81 318-327Feng, Tse-Yun, see Wu, Chuan-Lin; T-C May 81 324-332Feng, Tse-Yun, and Chuan-Lin Wu; Fault-diagnosis for a class of

multistage interconnection networks; T-C Oct 81 743-758Finkel, Raphael A., and Marvin H. Solomon; The lens interconnection

strategy; T-C Dec 81 960-965Fisher, Joseph A.; Trace scheduling: A technique for global microcode

compaction; T-C Jul 81 478-490Flynn, M. J., and J. L. Hennessy; Parallelism and representation

problems in distributed systems; T-C Dec 80 1080-1086Comments by Worlton, J., T-C Aug 81 608-609

Franklin, Mark A., and Norman L. Soong; One-dimensional optimizationon multiprocessor systems; T-C Jan 81 61-66

Frnkln, Mark A.; VLSI performance comparison of banyan andcrossbar communications networks; T-C kpr 81 283-291

Frednan, Michael L; Observations concerning the complexity of a classof on-line algebraic problems (Corresp.); T-C Jan 81 83-86

Fujiwara, Hideo; On closedness and test complexity of logic circuits; T-CAug 81 556-562

Fujiwara, Hideo, and-Kozo Kinoshita; A design of programmable logicarrays with universal tests; T-C Nov 81 823-827

Fung, Andy S. F., see Agarwal, Vinod K.; T-C Nov 81 855-865

G

Gajski, Daniel D.; An algorithm for solving linear recurrence systems onparallel and pipelined machines; T-C Mar 81 190-206

Gajsi, Daniel D., see Abraham, Jacob A.; T-C Nov 81 875-884Gecsei, Jan, and J-P. Brassard; The topology of cellular partitioning

networks (Corresp.); T-C Feb 81 164-168Gelerter, David; A DAG-based algorithm for prevention of

store-and-forward deadlock in packet networks; T-C Oct 81 709-715Givone, Donald D, see Braun, Robert D.; T-C Feb 81 141-144Glass, J. M.; An efficient method for improving reliability of a pipeline

FFT; T-C Nov 80 1017-1020. Correction, Oct 81 819Goel, Prabbakar; An implicit enumeration algorithm to generate tests for

combinational logic circuits; T-C Mar 81 215-222Goldstein, Lawrence k., Guest ed., and Thomas W. Williams Guest ed;

Introduction to special issue; T-C Nov 81 821-822Goodman, James R., and Carlo H. Sequin; Hypertree, a multiprocessor

interconnection topology; T-C Dec 81 923-933Gopal, Gita, and J. W. Wong; Delay analysis of broadcast routing in

packet-switching networks; T-C Dec 8f 915-922Goshmg, J. B., see Zurawski, J. H. P.; T-C Sep 81 691-699GottLieb, Allan; Comments on 'Concurrent search and insertion in AVL

trees' by Ellis, C.; T-C Oct 81 812Gray, F. G., see Armstrong, J. R.; T-C Aug 81 587-590Gray, F. G., see Sin*, A.]D.; T-C Sep 81 671-674Gray, F. Gail, see Walters, Stephen M.; T-C Dec 81 953-959Gupta, U. I., D. T. Lee, and J. Y.-T. Leung; An optimal solution for the

channel-assignment problem; T-C Nov 79 807-810Comments by Fersky, 0., et al, T-C Jun 81 454Comments by Rubin, F., T-C Jun 81 455Comments by Lauther, U., T-C Jun 81 455

H

Hagiwara, Hiroshi, see Baba, Takanobu; T-C Jun 81 373-395. Correction,Oct 81 818

Hak1imi S. Louis, see Ntafos, Simeon C.; T-C Jan 81 67-77Hakim, S. Louis, see Chwa, Kyung-Yong; T-C Jun 81 414-422Halats, C, see Van Dam, A.; T- Jul 1 513-519Harada, Takads, see Shirakawa, Isao; T-C Aug 81 572-581Hartley, M. G., see Maritsas, D. G.; T-C Jan 81 78Hartnnn, C. R. P., see DasGupta, S.; T-C Nov 80 1025-1029. Correction,

Oct 81 819Hayes, Alai B.; Stored state asynchronous sequential circuits (Corresp.);

T-C Aug 81 596-604Hayes, John P, see Sridhar, Thirumalai; T-C Aug 81 563-571

Hayes, John P., see Sridhar, Thirumalai; T-C Nov 81 842-854Heines, T. S.; Buffer behavior in computer communication systems; T-C

Aug 79 573-576Comments by Shanthikumar, J. G., T-C Feb 81 157

Hennessy, J. L., see Flynn, M. J.; T-C Dec 80 1080-1086Hibbits, David G., see Chu, Wesley W.; T-C Ma 81 318-327Hill, F. J., R. E. Swanson, M. Masud, and Z. Navabi; Structure

specification with a procedural hardware description language(Corresp.); T-C Feb 81 157-161

Hocker, David G., see Myers, Glenford J.; T-C Jul 81 519-523Holt, Craig S., and James E. Smith; Diagnosis of systems with

asymmetric invalidation; T-C Se 81 679-690Hong, Se June, and Daniel L. Ostapko; A simple procedure to generate

optimum test patterns for parity logic networks (Corresp.); T-C May81 356-358

Hong, Sung Je; Existence algorithms for synchronizing/distinguishingsequences (Corresp.); T-C Mar 81 234-237

Horowitz, Ellis, and Alessandro Zorat; The binary tree as aninterconnection network: Applications to multiprocessor systemsand VLSI; T-C Apr 81 247-233

Huen, Wing H., see EI-Dessouki, Ossama Ibrahim; T-C Sep 80 818-825.Correction, Jan 81 87

Hurst, S. L.; Comments on 'Design of a dynamically programmable logicgate (Corresp.)' by Suarez, R. E., et al.; T-C Dec 81 986-987

I

Ibaraki, Toshihide, Tsunehiko Kameda, and Shunichi Toida; On minimaltest sets for locating single link failures in networks; T-C Mar 81182-190

Imase, Makoto, and Masaki Itoh; Design to minimize diameter onbuilding-block network; T-C Jun 81 439442

Itoh, Masakh, see Imase, Makoto; T-C Jun 81 439-442

J

Jeng, B. Albert, see Silio, Charles B., Jr.; T-C Feb 81 148-153Jenq, Yih-Chyun; Digital convolution algorithm for pipelining

multiprocessor system; T-C Dec 81 966-973Joosten, J., see Van Diam, A.; T-C Jul 81 513-519Jump, J. Robert, see Dias, Daniel M.; T-C Apr 81 273-282

K

Kabat, Waldo C., and Anthony S. Wojcik; On the design of 4-valueddigital systems (Corresp.); T-C Sep 81 666-671

Kameda, Tsunehiko, see Ibaraki, Toshihide; T-C Mar 81 182-190Kanai, Takeo; An imnprovement of reliability of memory system with

skewing reconfiguration (Corresp.); T-C Oct 81 811-812Karpovsky, Mark, and Stephen Y. H. Su; Detection and location of input

and feedback bridging faults among input and output lines; T-C Jun80 523-527. Correction, Jan 81 86

Karpovsky, Mark; An approach for error detection and error correctionin distributed systems computing numerical functions; T-C Dec 81947-953

Kemmerer, Frederick C, see Siegel, Howard Jay; T-C Dec 81 934-947Kerkhoff, Hans G., and Marius L. Tervoert; Multiple-valued logic

charge-coupled devices; T-C Sep 81 644-652Kinoshita, Kozo, see Fujiwara, Hideo; T-C Nov 81 823-827Kishi, T., see Wirsching, J. E.; T-C Apr 81 298-301Kodek, Du§an M.; Conditions for the existence of fast number theoretic

transforms (Corresp.); T-C May 81 359-360Koren, Israel, and Yoram Maliniak; On classes of positive, negative, and

imaginary radix number systems; T-C May 81 312-317Kuck, Davd J., see Abu-Sufah, Walid; T-C May 81 341-356

L

Labetoulle, Jacques, and Guy Pujolle; HDLC throughput and responsetime for bidirectional data flow with nonuniform frame sizes; T-CJun 81 405-413

Lam, Simon S., and Y. C. Luke Lien; Congestion control of packetcommunication networks by input buffer limits-A simulationstudy; T-C Oct 81 733-742

Lampson, Butler W., see Clark, Douglas W.; T-C Oct 81 715-733Landskov, David, see Davidson, Scott; T-C Jul 81 460-477Lauther, U.; Comments on 'An optimal solution for the

channel-assignment problem' by Gupta, U. I., et al; T-C Jun 81 455Lawrie, Duncan , see Yew, Pen-Cung; T-C Apr 81 296-298Lawrie, Duncan H, see Abu-Sufah, Walid; T-C ay 81 341-356Lee, D. T., see Gupta, U. I.; T-C Nov 79 807-810Lee, D. T., Hsu Chan, and C. K. Wong; An on-chip compare/steer

bubble sorter; T-CJun 81 396-405Lee, Hikyu, see Arden, Bruce W.; T-C Apr 81 291-295Letheren, M*, see Van Dam, A.; T-C Juf81 513-519


Leung, J. Y.-T., see Gupta, U. I.; T-C Nov 79 807-8101ev, Gavriela Freund, Nicholas Pippenger, and Leslie G. Valiant; A fast

parallel algorithm for routing m permutation networks; T-C Feb 81

Lewis, T. G., Guest ed., and Bruce D. Shriver Guest ed.; Introduction tospecial issue; T-C Jul 81 457-459

Liaw, Chi-Chang, Stephen Y. H. Su, and Yashwant K. Malaiya;Test-experiments for detection and location of intermittent faults insequential circuits (Corresp.); T-C Dec 81 989-995

Lien, Y. C. Luke, see Lam, Simon S.; T-C Oct 81 733-742Liu, Ming T., see Wu, Shyue B.; T-C Apr 81 254-264

M

Malaiya, Yashwant K., see Liaw, Chi-Chang; T-C Dec 81 989-995Maliniak, Yoram, see Koren, Israel; T-C May 81 312-317Mallett, Patrick W., see Davidson, Scott; T-C Jul 81 460-477Marino, Leonard R.; General theory of metastable operation; T-C Feb 81

107-115Maritsas, D. G., and M. G. Hartley; Comments on 'Revision of the buffer

length derivation for a modified Ek/DIJ system by Maritsas andHartley'; T-C Jan 81 78

Markowsky, George; Syndrome-testability can be achieved by circuitmodification (Corresp.); T-C Aug 81 604-606

Markowsky, George, see Barzilai, Zeev; T-C Dec 81 996-1000Masud, M., see Hill, F. J.; T-C Feb 81 157-161Mathialagan, Ayakannu, and Nripendra N. Biswas; Bit steering in the

mirnimization of control memory in microprogrammed digitalcomputers (Corresp.); T-C Feb 81 144-146

McCluskey, Edward J., and Saied Bozorgui-Nesbat; Design forautonomous test; T-C Nov 81 860-875

McColi, William F.; Planar crossovers (Corresp.); T-C Mar 81 223-225McConnel, Stephen R., and Daniel P. Siewiorek; Synchronization and

voting (Corresp.); T-C Feb 81 161-164Meyer, Gerard G. L.; A fault diagnosis algorithm for asymmetric

modular architectures (Corresp.); T-C Jan 81 81-83Morgan, D. R.; Autocorrelation function of sequential M-bit words taken

from an N-bit shift register (PN) sequence; T-C May 80 408-410Comments by Wustmann, G., T-C Mar 81 241

Mori, Shinsaku, see Tanaka, Mamoru; T-C Mar 81 229-234Mucha, Joachim, see Daehn, Wilfried; T-C Nov 81 829-833Muehldorf, Eugen I., and Anil D. Savkar; LSI logic testing-An

overview; T-C Jan 81 1-17Mueller, Philip T., Jr., see Siegel, Howard Jay; T-C Dec 81 934-947Mufray, Neil V.; Some observations on equivalence handling methods

(Corresp.); T-C May 81 361-162Myers, Glenford J., andDavid G. Hocker; The use of software simulators

in the testinm and debugging of microprogram logic (Corresp.); T-C

N

Narayanaswamy, K., see Seth, Sharad C.; T-C Dec 81 973-977Nassimi, David, and Sartaj Sahni; Data broadcasting in SIMD

computers; T-C Feb 81 101-107Nassimi, David, and Sartaj Sahni; A self-routing Benes network and

parallel permutation algorithms; T-C May 81 332-340Navabi, Z., see Hill, F. J.; F-C Feb 81 157-161Nelson, Victor P., see Thanawastien, Suchai; T-C Aug 81 545-556Ntafos, Simeon C., and S. Louis Hakimi; On structured digraphs and

program testing; T-C Jan 81 67-77

0

Okuda, Noboru, see Shirakawa, Isao; T-C Au 8I 572-581Ostapko, Daniel L., see Hong, Se June; T-C May 81 356-358Ottmann, Th., see Bentley, J. L.; T-C Sep 79643-647Ozaki, Hiroshi, see Shirakawa, IsaoF-AuT 81 572-581Ozawa, Shinji, see Tanaka, Mamoru; T-C Aar 81 229-234

P

Palit, A, see Sengupta, A.; T-C Mar 81 237-240Parker, Alice C., and John J. Wallace; SLIDE: An I/O hardware

descriptive language; T-C Jun 81 423-439Parker, D. Stott, Jr.; Combinatorial merging and Huffman's algorithm;

T-C May 79 365-367. Correction. Jun 81r454Parthasarathy, R., and Sudhakar M. Reddy; A testable design of iterative

logic arrays; T-C Nov 81 833-841Patel, JanakH.; Performance of processor-memory interconnections for- multiprocessors; T-C Oct 81 771-780Persky, C. B. N. Tien, and B. S. Ting; Comments on 'An optimal

solution for the channel-assignment problem' by Gupta, U. I., et al;FT-C Jun 81 454

Pier, Kenneth A., see Clark, Douglas W.; T-C Oct 81 715-733

Pippenger, Nicholas, see Lev, Gavriela Freund; T-C Feb 81 93-100Pomper, Gardner, and James R. Armstrong; Representation of

multivalued functions using the direct cover method (Corresp.); T-CSep 81 674-679

Prakash, S., and V. V. Rao; Comments on 'Very fast Fourier transformalgorithms hardware for implementation' by Despain, A. M.; T-CJun 81 452

Priester, Robert W., and James B. Clary; New measures of testability andtest complexity for linear analog failure analysis; T-C Nov 81884-889

Proskurowski, Andrzej; Minimum broadcast trees (Corresp.); T-C May 81363-366

Pugsley, James H., see Silio, Charles B., Jr.; T-C Feb 81 148-153Pujolle, Guy, see Labetoulle, Jacques; T-C Jun 81 405-413

R

Ramamoorthy, C. V., and Benjamin W. Wah; An optimal algorithm forscheduling requests on interleaved memories for a pipelinedprocessor; T-C Oct 81 787-800

Ramamoorthy, C. V., and Benjamin W. Wah; The degradation in memoryutilization due to dependencies (Corresp.); T-C Oct 81 813-818

Rao, V. V., see Prakash, S.; T-C Jun 81 452Reddy, Sudhakar M, see Parthasarathy, R.; T-C Nov 81 833-841Reddy, Sudhakar M*, see Suk, D. S.; T-C Dec 81 982-985Reed, I. S., T. K. Truong, and B. Benjauthrit; A new hybrid algorithm for

computing a fast discrete Fourier transform; T-C Jul 79 487492.Addendum, Jun 81 453

Robinson, John P., and Martin Cohn; Counting sequences; T-C Jan 8117-23

Rodeh, Michael, see Steinberg, David; T-C Dec 81 977-982Rosenfeld, Azriel, see Wu, Angela Y.; T-C May 81 370-372Rubin, Frank; Comments on 'An optimal solution for the

channel-assignment problem' by Gupta, U. I., et al; T-C Jun 81 455Rudolph, L. D., see DasGupta, S.; T-C Nov 80 1025-1029. Correction, Oct

81 819

S

Saeks, Richard, Alberto Sangiovanni-Vincentelli, and V. Visvanathan;Diagnosability of nonlinear circuits and systems-II: Dynamicalsystems; T-C Nov 81 899-904

Sahni, Sartaj, see Nassimi, David; T-C Feb 81 101-107Sahni, Sartaj, see Nassimi, David; T-C May 81 332-340Sangiovanni-Vincentelli, Alberto, see Visvanathan, V.; T-C Nov 81

889-898Sangiovanni-Vincentelli, Alberto, see Saeks, Richard; T-C Nov 81 899-904Sasao, Tsutomu; Multiple-valued decomposition of generalized Boolean

functions and the complexity of programmable logic arrays; T-C Sep81 635-643

Savir, Jacob; Syndrome-testing of 'syndrome-untestable' combinationalcircuits (Corresp.); T-C Aug 81 606-608

Savir, Jacob, see Barzilai, Zeev; T-C Dec 81 996-1000Savkar, Anil D., see Muehldorf, Eugen I.; T-C Jan 81 1-17Sengupta, A., D. K. Chattopadhyay, A. Palit, A. K. Bandyopadhyay, and

A. K. Choudhury; Realization of fault-tolerant machines-Linearcode application (Confesp.); T-C Mar 81 237-240

S6quin, Carlo H, see Goodman, James R.; T-C Dec 81 923-933Seth, Sharad C., and K. Narayanaswamy; A graph model for

pattern-sensitive faults in random access memories (Corresp.); T-CDec 81 973-977

Shanthikumar, J. G.; Comments on 'The buffer behavior in computercommunication systems' by Heines, T. S.; T-C Feb 81 157

Shanthikumar, J. G.; On the buffer behavior with Poisson arrivals,priority service, and random server interruptions; T-C Oct 81781-786

Shirakawa, Isao, Noboru Okuda, Takashi Harada, Sadahiro Tani, andHiroshi Ozaki; A layout system for the random logic portion of anMOS LSI chip; T-C Aug 81 572-581

Shriver, Bmce D., see Davidson, Scott; T-C Jul 81 460477Shriver, Bruce D., Guest ed, see Lewis, T. G., Guest ed.; T-C Jul 81

457-459Siegel, Howard Jay, Guest ed.; Interconnection networks for parallel and

distributed processing: An overview; F-C Apr 81 245-246Siegel, Howard Jay, Leah J. Siegel, Frederick C. Kemmerer, Philip T.

Mueller Jr., Harold E. Smalfey Jr., and S. Diane Smith; PASM: Apartitionable SIMD/MIMD system for image processing andpattern recognition; T-C Dec 81 934-947

Siegel, Leah J., see Siegel, Howard Jay; T-C Dec 81 934-947Siewiorek, Daniel P., see Thomas, Donald E.; T-C Jan 81 48-61Siewiorek, Daniel P., see McConnel, Stephen R.; T-C Feb 81 161-164Siewiorek, Daniel P., see Snow, Edward A.; T-C Jun 81 443-447Silio, Charles B., Jr., James H. Pugsley, and B. Albert Jeng; Control

memory word width optimization using multiple-valued circuits(Corresp.); T-C Feb 81 148-153


Singh, A. D., F. G. Gray, and J. R. Armstrong; Tree structured sequentialmultiple-valued logic design from universal modules (Corresp.); T-CSep 81 671-674

Smalley, Harold E, Jr., see Siegel, Howard Jay; T-C Dec 81 934-947Smith, Jame E., see Holt, Craig S.; T-C Sep 81 679-690Smith, K. C.; The prospects for multivalued logic: A technology and

applications view; T-C Sep 81 619-634Smith, Merlin G., see Barzilai, Zeev; T-C Dec 81 996-1000Smith, Reid G.; The contract net protocol: High-level communication

and control in a distributed problem solver; T-C Dec 80 1104-1113.Correction, May 81 372

Smith, S. Diane, see Siegel, Howard Jay; T-C Dec 81 934-947Snow, Edward A., and Daniel P. Siewiorek; Implementation and

performance evaluation of computer families (Corresp.); T-C Jun 81443-447

Snyder, Lawrence; Formal models of capability-based protectionsystems; T-C Mar 81 172-181

Solomon, Marvin H., see Finkel, Raphael A.; T-C Dec 81 960-965Soong, Norman L., see Franklin, Mark A.; T-C Jan 81 61-66Sridhar, Thinuala, and John P. Hayes; A functional approach to testing

bit-sliced microprocessors; T-C Aug 81 563-571Sridhar, Thirumalai, and John P. Hayes; Design of easily testable

bit-sliced systems; T-C Nov 81 842-854Stankovic, John A.; The types and interactions of vertical migrations of

functions in a multilevel interpretive system; T-C Jul 81 505-513Steinberg, David, and Michael Rodeh; A layout for the shuffle-exchange

network with O(N2/log3/2N) area (Corresp.); T-C Dec 81 977-982Su, Stephen Y. H., see Karpovsky, Mark; T-C Jun 80523-527. Correction,

Jan 81 86Su, Stephen Y. H, see Liaw, Chi-Chang; T-C Dec 81 989-995Suarez, Ricardo E., Oscar Chang, and Vladimir Adam; Design of a

dynamically programmable logic gate (Corresp.); T-C Jan 81 79-81Comments by Hurst, S. L., T-C Dec 81 986-987

Suk, D. S., and S. M. Reddy; A march test for functional faults insemiconductor random access memories (Corresp.); T-C Dec 81982-985

Surjaatmadja, Jim B.; An algebra for switching circuits (Corresp.); T-CAug 81 609-613

Swanson, R. E*, see Hill, F. J.; T-C Feb 81 157-161T

Takizuka, Takashi, see Tokoro, Mario; T-C Jul81 491-504Tamurn, Eiji, see Tokoro, Mario; T-C Jul81 491-504Tanaka, Mamoru, Shinji Ozawa, and Shinsaku Mori; Rewritable

programmable logic array of current mode logic (Corresp.); T-C Mat81 229-234

Tai,Sadahiro, see Shirakawa, Isao; T-C Aug 81 572-581Tapia, Moiez A., and Jerry H. Tucker; Complete solution of Boolean

equations; T-C Jul 80 662-665. Corrections, Jan 81 87 and Oct 81 812Tervoert, Marius L, see Kerkhoff, Hans G.; T-C Sep 81 644-652Thanawastien, Suchai, and Victor P. Nelson; Interference analysis of

shuffle/exchange networks; T-C Aug 81 545-556Thayse, Andre; P-functions: A new tool for the analysis and synthesis of

binary programs; T-C Feb 81 126-134Thomas, Donald E., and Daniel P. Siewiorek; Measuring designer

performance to verify design automation systems; T-C Jan 81 48-61Thompson, Richard A., see Walters, Stephen M.; T-C Dec 81 953-959Tien, B. N., see Persky, G.; T-C Jun 81 454Ting, B. S., see Persky, G.; T-C Jun 81 454Toida, Shunichi, see Ibaraki, Toshihide; T-C Mar 81 182-190Tokoro, Mario, Eiji Tamura, and Takashi Takizuka; Optimization of

microprograms; T-C Jul 81 491-504Toussaint, Godfried T, see Avis, David; T-C Dec 81 910-914Truong, T. K, see Reed, I. S.; T-C Jul 79 487-492. Addendur, Jun 81 453Tsao, Nai-Kuan; Error complexity analysis of algorithms for matrix

multiplication and matrix chain product; T-C Oct 81 758-771Tucker, Jerry H, see Tapia, Moiez A.; T-C Jul 80 662-6 65. Corrections,

Jan 81 87 and Oct 81 812U

Uehara, Takao, and William M. van Cleemput; Optimal layout orCMOSfunctional arrays; T-C May 81 305-312

Unger, Stephen H.; Double-edge-triggered flip-flops (Corresp.); T-C Jun81 447-451

V

Valint, Leslie G, see Lev, Gavriela Freund; T-C Feb 81 93-100Valiant, Lslie G.; Universality considerations in VLSI circuits; T-C Feb

81 135-140Vanaken, Jerry R., and Gregory L. Zick; The expression processor: A

pipelined, multiple-processor architecture; T-C Aug 81 525-536vanCleemput, William M., see Uehara, Takao; T-C May 81 305-312Van Dam, A., M. Barbacci, C. Halatsis, J. Joosten, and M. Letheren;

Simulation of a horizontal bit-sliced processor using the ISPSarchitecture simulation facility (Corresp.); T-C Jul 81 5f3-519

Visvanathan, V., and Alberto Sangiovanni-Vincentelli; Diagnosability ofnonlinear circuits and systems-I: The dc case; T-C Nov 81 889-898

Visvanathan, V., see Saeks, Richard; T-C Nov 81 899-904

W

Wah, Benjamin W., see Ramamoorthy, C. V.; T-C Oct 81787-800Wah, Benjamin W., see Ramamoorthy, C. V.; T-C Oct 81 813-818Wallace, John J, see Parker, Alice C.; T-C Jun 81 423-439Walters, Stephen M., F. Gail Gray, and Richard A. Thompson;

Self-diagnosing cellular implementations of finite-state machmines;T-C Dec 81 953-959

Wang, Patrick Shen-Pei; Finite-turn repetitive checking automata andsequential/parallel matrix languages (Corresp.); T-C May81 366-370

Weste, Neil H, see Ackland, Bryan D.; T-C Jan 81 41-48Williams, Thomas W., Guest ed., see Goldstein, Lawrence H., Guest ed.;

T-C Nov 81 821-822Williams, Thomas W., and N. C. Brown; Defect level as a function of

fault coverage (Corresp.); T-C Dec 81 987-988Wirsching, J. E., and T. Kishi; CONET: A connection network model

(Corresp.); T-C Apr 81 298-301Wittie, IArry D.; Communication structures for large networks of

microcomputers; T-C Apr 81 264-273Wojcik, Anthony S., see Kabat, Waldo C.; T-C Sep 81 666-671Wojcik, Anthony S., Guest ed., see Butler, Jon T., Guest ed.; T-C Sep 81

617-618Wong, C. K., see Lee, D. T.; T-C Jun 81 396-405Wong, C. K., see Bongiovanni, Giancarlo; T-C Aug 81 537-545Wong, J. W., see Gopal, Gita; T-C Dec 81 915-922Worlton, Jack;, Comments on 'Parallelism and representation problems in

distributed systems' by Hennessy, J. L. and Flynn, M. J.; T-CAug 81608-609

Wu, Angela Y., and Azriel Rosenfeld; SIMD machines and cellulard-graph automata (Corresp.); T-C May 81 370-372

Wu, Chuan-Lin, and Tse-Yun Feng; The universality of theshuffle-exchange network; T-C May 81 324-332

Wu, Chuan-Lin, see Feng, Tse-Yun; T-C Oct 81 743-758Wu, Shyue B., and Ming T. Liu; A cluster structure as an interconnection

network for large multimicrocomputer systems; T-C Apr81 254-264Wustmann, Gerhard; Comments on 'Autocorrelation function of

sequential M-bit words taken from an N-bit shift register (PN)sequence' by Morgan, D. R.; T-C Mar 81 241

Y

Yew, Pen-Chung, and Duncan H. Lawrie; An easily controlled networkfor frequently used permutations (Corresp.); T-C Apr 81 296-298

zZick, Gregory L, see Vanaken, Jerry R.; T-C Aug 81 525-536Zorat, Alessandro, see Horowitz, Ellis; T-C Apr 81 247-253Zurawski, J. H. P., and J. B. Gosling; Design of high-speed digital divider

units; T-C Sep 81 691-699

SUBJECT INDEX

A

Arbiters; cf. Asynchronous sequential mtachinesArithmetic

radix number systems; positive, negative, and imaginary classes;Koren, Israel; T-C May 81 312-317

Arithmetic; cf. Division; Matrices; Multiplication; Negative radixarithmetic

Arrays; cf. Logic arrays; Parallel processingArtificial intellgence

distributed problem solver; contract net protocol; Smith, Reid G.; T-CDec 80 1104-1113. Correction, May 81 372

Asynchronous sequential mhnesmetastable operation theory; Marino, Leonard R; T-C Feb 81 107-115stored-state circuit realization; Hayes, Alan B.; T-C Aug 81 596-604

Automatafinite-state algorithm synthesis in Galois field; English, W. R; T-C Mar

81 225-229synchronizing and distinguishing sequences; existence algorithms;Hong Sung Je; T-C Mar 81 234-23T

Automata; cf. Cellular automata; Sequential machines

B

BibiographiesMPG machine-independent high-level microprogramming language

and its processing system; Baba, Takanobu; T-C Jun 81 373-395.Correction, Oct 81 818

Binary arithmetic; d. ArithmeticBipolar integrted circuits

representation of multivalued functions using direct cover method;algorithm for use with sum and product operators in bipolartechnologies; Pomper, Gardner; T-C Sep 81 674-679

Bipolar integrated circuits, I2Lfour-valued digital system design based on Boolean and Post algebra;

Kabat, Waldo C.; T-C Sep 81 666-67112L multivalued ROM design for microprogrammed computers; wordwidth optimization; Silio, Charles B., Jr.; T-C Feb 81 148-153

multivalued I2L circuit design; Davio, Marc; T-C Sep 81 653-661Bipolr integrated circuits, logic

rewritable programmable logic array of current-mode logic;construction and control; Tanaka, Mamoru; T-C Mar 81 229-234

Boolean algebrafour-valued digital system design based on Boolean and Post algebra;

Kabat, Waldo C.; T-C Sep 81 666-671generalized algebra for switching circuits; Surjaatmad]a, Jim B.; T-CAug 81 609-613

Boolean equationscomplete solution of Boolean equations; necessary and sufficient

conditions.; Tapia, Moiez A.; T-C Jul 80 662-665. Corrections, Jan 8187 and Oct 81 812.

Boolean functions; cf. Logic functionsBroadcasting

modeling of broadcasting by minimum broadcast tree; Proskurowsk4Andrzej; T-C May 81 363-366

Buffer memonesdegradation in memory utilization due to dependencies of accesses

issued by pipelined computer; Ramamoorthy, C. V.; T-C Oct 81813-818

Buffered communication

behavior of system with Poisson arrivals, infinite buffer size andrandom server interruptions; Shanthikumar, J. G.; T-C Oct 81781-786

Buffered communication cf. Packet switchingBuffers

length of buffers for Erlong input; Maritsas, D. G.; T-C Jan 81 78

C

Cache memoriesmemory system for high-performance personal computer; Clark,

Douglas W.; T-C Oct 81 715-733CCD; cf. Charge-coupled devicesCellular automata

processor network modeling by d-graph automaton; equivalence toSiegel's SIMD model; Wu, Angela YI; T-C May 81 370372

self-diagnosing cellular implementations of finite-state machines;Walters, Stephen M.; T-C Dec 81 953-959

Cellular logicgenerating testable structures defined by simple loops; Abraham, Jacob

A.; T-C Nov 81 875-884Cellular logic arrays

bit-sliced microprocessors; test generation based on functional faultmodel; Sridhar, Thirumalai; T-C Aug 81 563-571

easily testable bit-sliced systems design; Sridhar, Thirumalai; T-C Nov81 842-854

mixed-radix number system related to Kronecker product of matricesand perfect shuffle; Davio, Marc; T-C Feb 81 1 16-125

topology of cellular partitioning networks; generalization of triangularpermuting networks; Gecsei Jan; T-C Feb 81 164-168

unilateral iterative arrays of combinational cells; testable design;Parthasarathy, R.; T-C Nov 81 833-841

Charge-oupled devicesmultivalued-logic CCDs; Kerkhoff, Hans G.; T-C Sep 81 644-652

Charge-coupled memonessorting with CCDs and magnetic bubble memories; Agrawal, Dharma

P.; T-C Feb 81 153-156CMOS integrated circuits, logic

optimal la;out of CMOS functional arrays; Uehara, Takao; T-C May

self-testing capability design; McCluskey, Edward J.; T-C Nov 81860-875-

Coding; cf. Error-correcting codes; Error-detecting codes; Gray codes;Huffman codes; Linear codes

Combinational circuit testinggenerating testable structures defined by simple loops; Abraham, Jacob

A.; T-C Nov 81 875-884generation of tests for circuits involved with error correction and

translation functions; Goel, Prabhakar; T-C Mar 81 215-222Huffman's algonrthm for constructing optimal weighted trees; boundson root node weight and application to multiplexer design; Parker,D. Stott, Jr.; T-C May 79 365-367. Correction, Jun 81 454

multiple-fault testing of log c circuits by single-fault test sets; Agarwal,Vinod K; T-C Nov 81 8f5-865


syndrome testing of 'syndrome-untestable' circuits; Savir, Jacob; T-CAug 81 606-608

unilateral iterative arrays of combinational cells; testable design;Parthasarathy, R;F-C Nov 81 833-841

Combinational circuits; d. Cellular logic arrays; Logic arrays;Multivalued logic circuits

Combinational logicdual-mode logic for function-independent fault testing; DasGupta, S.;T-C Nov 80 1025-1029. Correction, Oct 81 819

Communication switching; cf. Interconnection networksCommunication systems; cf. Computer communicationCompilers; cf. Computer language processorsComputation theory

complexity of a class of on-line problems; Fredman, Michael L; T-CJan 81 83-86

Computer arithuetic; cf. ArithmeticComputer communication

buffer behavior with Poisson arrivals, periodic opportunities forservice, and random blocking of service; Shanthikumar, J. G.; T-CFeb 81 157

Computer communication; cf. Multiprocessing, intercommunication;Packet switching; Queued communication

Computer communication protocolshigh-level data link control protocol; performance evaluation;

Labetoulle, Jacques; T-C Jun 81 405413Computer fault diagnosis; cf. Computer testingComputer fault tolerance

numerical function computing by distributed systems; error detectionand error correction; Karpovsky, Mark; T-C Dec 81 947-953

voter design for different signaling conventions in redundant systems;McConnel, Stephen R.; F-C Feb 81 161-164

Computer fault tolerance; cf. Computer reliability; Microcomputer faulttolerance

Computer graphicsgeometric intersections; reporting and counting intersections,

algorithms; Brown, Kevin Q.; T-C Feb 81 147-148raster-scan TV display; edge flag algorithm for color contour filling;

Ackland, Bryan D.; T-C Jan 81 4148visibility of polygon from edge; optimal determination algorithm; Avis,

David; T-C Dec 81 910-914Computer langage rcosMPG maTcine-indaependent high-level microprogramming languageand its processmg system;; Baba, Takanobu; T-C Jun 81 373-393.Correction, Oct 81 818

paging behavior improvement by source program transformations viaoptimizing compiler; Abu-Sufah, Wali; T-C May 81 341-356

Computer lanuageshardware description language for modeling and simulation of

horizontal bit-sliced processor; Van Dam, A.; T-C Jul 81 513-519Instruction Set Processor Specifications (ISPS) description language;

Barbacci Mario R.; T-C Jan 81 26-40sequential/parallel matrix languages; recognition by finite-turn

checking automata; Wang, Patrick Shen-Pei; T-C May 81 366-370SLIDE hardware-descriptive language for description of asynchronous

concurrent intercommunicating processes; Parker, Alice C.; T-C Jun81 423439

Computer languages; cf. Simulation languagesComputer networks; cf. Computer communication; Distributed

computing; Microcomputer networks; MultiprocessingComputer perfomance evaluationbanyan and crossbar communication networks; VLSI performance

characteristics; Franklin, Mark A.; T-C Apr 81 283-291computer families; implementation and performance evaluation; Snow,Edward A.; T-C Jun 81 443-447

congestion control in packet networks by input buffer limits; Lam,Simon S.; T-C Oct 81 733-742

delay analysis of broadcast routing in packet-switching networks;Gopal, Gita; T-C Dec 81 915-922

delta networks in packet communication environment; bufferednetworks, unbuffered networks, and crossbar switches; Dias, DanielM.; T-C Apr 81 273-282

processor-memory interconnections for multiprocessors; performance;Patel, Janak H.; T-C Oct 81 771-780

Computer performance monitoringpaging behavior improvement by source program transformations via

optimizing compiler; Abu-Sufah, Walid; F-C May 81 341-356Computer pipeli processingdegadation in memory utilization due to dependencies of accesses


digital convolution algorithm for pelining multiprocessor system;Jenq, Yih-Chyun; T-C Dec 81 966-973

expression processor capable of exploiting instruction-levelconcurrenc in numerical processing tasks; Vanaken, Jerry R.; T-CAug 81 525-536

linear recurrence system solutions on parallel and pipelined machines;Gajski, Danel D.; T-C Mar 81 1902206

reliability improvement of pipeline FFT; Glass, J. M.; T-C Nov 801017-020. Correction, Oct 81 819


scheduling requests on interleaved memories for pipelined processor;optimal algorithm; Ramamoorthy, C. V.; T-C Oct 81 787-800

Computer programming; cd. Computer languages; Computer softwareComputer reliabilitymemory system with skewing reconfigurations; reliability

improvement; Kanai Takeo; T-C Oct 81 811-812pipelie FFT's, reliability improvement; Glass, J. M.; T-C Nov 80

1017-1020. Correction, Oct 81 819Computer security

capability-based protection system model; Snyder, Lawrence; T-C Mar81 172-181

Computer Society; cd. IEEE Computer SocietyComputer software; cd. Computer languages; MicroprogrammingComputer software design/development

equivalence handling methods; UNION-FIND implementation;Murray, Neil V.; T-C May 81 361-162

paging behavior improvement by source program transformations viawoptimizing compiler; Abu-Sufah, Walid, F-C May 81 341-356

Computer software, language processors; cf. Computer languageprocessors

Computer software performance evaluationhigh-level data link control protocol; performance evaluation;

Labetoulle, Jacques; T-C Jun 81 405-413measuring designer performance to verify design automation systems;

Thomas, Donald E.; T-C Jan 81 48-61Computer software testing

software simulators for testing and debugging large microprogrammedsystems; Myers, Glenford J.; T-C Jul 81 519-523

structured digraphs; graph theoretic problems relating to programtesting; Ntafos, Simeon C.; T-C Jan 81 67-77

Computer testingasymmetric modular architectures; fault diagnosis algorithm; Meyer,

Gerard G. L.; T-C Jan 81 81-83design for testability; special issue foreword; Goldstein, Lawrence H.,

Guest ed.; T-C Nov 81 821-822design for testability; special issue (joint special issue with IEEE

Transactions on Circuits and Systems Nov 81); T-C Nov 81 821-904Computer testing; cd. Computer fault tolerance; Computer performance

evaluation; Computer software testing; Digital system testing; Logiccircuit testing; Memory testing; Microcomputer testing

Computers; cf. Computer pipeline processing; Digital systems;Distributed computing; Logic circuits; Memories; Microcomputers;Microprogranming; WIodular computer systems; Multiprocessing;Parallel processing

Control systems; cd. Multilevel systemsConvolutionDFT computations, Winograd's method extended; cyclic convolutionperformed using Mersenne number-theoretic transform; Reed, L S.;T-C Jul 79 487-492. Addendum, Jun 81 453

digital convolution algorithm for pipelining multiprocessor system;Jenq, Yih-Chyun; T-C Dec 81 966-973

fast number-theoretic transforms; conditions for existence; Kodek,Dusan M.; F-C May 81 359-360

Counting circuitsgeneralized parallel counter synthesis; Dormido, S.; T-C Sep 81 699-703

D

Database systems; cf. Information systemsData communication; cd. Computer communicationData processing; cf. ComputersData secuity; cd. Computer securityDecision procedures; cW. TestingDesign automation

measuring designer performance to verify design automation systems;Thomas, Donald E.; T-C Jan 81 48-61

Digital frdter word-length effectsfast number-theoretic transforms; conditions for existence; Kodek,Dusan M.; T-C May 81 359-360

Digital image processing; cd. Image processingDigital integrated circuits; cf. Bipolar integrated circuitsDigital system testing

asymmetric invalidation assumption in diagnosis theory; Holt, CraigS.; T-C Se 81 679-690

bridging faults between input and output lines; Karpovsky, Mark; T-CJun 80 523-527. Correction, Jan 81 86

defect level as function of fault coverage; Williams, T. W; T-C Dec 81987-988

diagnosability of nonlinear dc circuits and systems; Visvanathan, V.;F-C Nov 81 889-898

diagnosability of nonlinear dynamical systems; Saeks, Richard; T-CNov 81 899-904

fault identification in diagnosable systems; Chwa, Kyung-Yong; T-CJun 81 414-422

information-theoretic approach to circuit testing; Agrawal, VishwaniD.;T-CAug81582-587

multistage interconnection networks; fault diagnosis; Feng, Tse- Yun;T-C Oct 81 743-758

self-testing capability design; McCluskey, Edward J.; T-C Nov 81860-875

speed-efficiency-complexity tradeoffs in universal diagnosisalgorithms; Butler, Jon T; T-C Aug 81 590-596

syndrome testability achievement through circuit modification;Markowsky, George; T-C Aug 81 604-606

syndrome testing in VLSI; weighted syndrome sums approach;Barzilai, Zeev; T-C Dec 81 996-1000

syndrome testing of 'syndrome-untestable' circuits; Savir, Jacob; T-CAug 81.606-608

Digital system testing; cf. Computer testing; Logic circuit testing;Memory testing

Discrete Fourier transformsfast number-theoretic transforms; conditions for existence; Kodek,Dusan M.; T-C May 81 359-360

FFT algorithm requiring no multiplication and having form suitablefor high-performance hardware implementations; Prakash, S.; T-CJun 81 452

reliability improvement of pipeline FFT; Glass, J. M.; T-C Nov 801017-1020. Correction, Oct 81 819

Winograd's method extended; cyclic convolution performed usingMersenne number-theoretic transform; Reed, I. S.; T-C Jul 79487-492. Addendum, Jun 81 453

Displays; cf. Computer graphicsDistributed computing

contract net protocol in distributed problem solver; Smith, Reid G.;T-C Dec 80 1104-1113. Correction, May 81 372

interconnection network for parallel and distributed processing; specialissue; T-C Apr 81 245-301

interconnection networks for parallel and distributed processing;special issue foreword; SiegeL, Howard Jay, Guest ed.; T-C Apr 81245-246


parallelism and representation problems; Worlton, Jack; T-C Aug 81608-609

Divisionhigh-speed digital divider design; Zurawski, J. H. P.; T-C Sep 81

691-699Dynamic progranuing

intermittent fault detection and location in sequential circuits; Liaw,Chi-Chang; T-C Dec 81 989-995

single error correction-double error detection nonbinary code forfault-tolerant byte-organized memory implemented with quaternarylogic; Dao, Tich T.; T-C Sep 81 662-666

E

Error-correcting codeslinear code application to fault-tolerant machines; Sengupta, A.; T-CMar 81 237-240

memory system with skewing reconfigurations; reliabilityimprovement; Kanai, Takeo; T-C Oct 81 811-812



Error-correcting codes; cf. Arithmetic codesError-detecting codes


Estimation; ci. Image processing

F

Fast Fourier transfonrs; cf. Discrete Fourier transformsFault diagnosis; cf. TestingFault tolerance; cf. Computer fault tolerance; Memory fault toleranceFile systems

bubble string comparator for sorting device; Lee, D. T.; T-C Jun 81396-405

Finite-state automata; cf. Sequential machinesFirmware; cf. MicroprogrammingFlip-flops

double-edge-triggered flip-flops; Unger, Stephen H.; T-C Jun 81AA7-45l

Flow controlcomputer networks; tandem queueing system with constant slotted

service times and threshold control; Chu, Wesley W.; T-C May 81318-327

Fourier transforms; cf. Discrete Fourier transforms


G

Galois fieldsDFT computations, Winograd's method extended; cyclic convolution

performed using Mersenne number-theoretic transform; Reed, I. S.;T-C Jul 79 487-492. Addendgu# Jun 81 453

finite-state algorithm synthesis in Galois field; English, W. R.; T-C Afar81 225-229

Geometrygeometric intersections; algorithms for reporting and counting

intersections; Brown, Kevin Q.; T-C Feb 81 147-148visibility of polygon from edge; optimal determination algorithm; Avis,

David; T-C Dec 81 910-914Graph mery

chordal ring graphs for message-connected multimicrocomputers;Arden, Bruce W.; T-C Apr 81 291-295

mapping of problem modules onto array processor as graphisomorphism problem; heuristic algorithm; Bokhari, Shahid H.; T-CMar 81 207-214

nearly optimal graph design of small-diameter switching networks;Imase, Makoto; T-C Jun 81 439-442

networks representable by acyclic directed graph; minimal test sets forsingle link failures; Ibaraki, Toshihide; T-C Mar 81 182-190

pattern-sensitive faults in RAMs; graph model; Seth, Sharad C.; T-CDec 81 973-977

structured digraphs; graph theoretic problems relating to programtesting; Ntafos, Simeon C.; T-C Jan 81 67-77

Graph theory; cf. Layout; TreesGraphic displays; cd. Computer graphicsGray codes

counting sequences with Hamming distance between successive countvalues in desired range; application to circuit testing; Robinson, JohnP.; T-C Jan 81 17-23

H

Huffman codesconstructing optimal weighted trees; bounds on root node weight and

application to multiplexer design; Parker, D. Stott, Jr.; T-C May 79365-367. Correction, Jun 81 454

I2L (integrated injection logic); cf. Bipolar integrated circuits, 12LIC; c. Integrated circuitsIEEE Computer Society

editorial policy; Booth, Taylor L.; T-C Mar 81 169-171Image processing

visibility of polygon from edge; optimal determination algorithm; Avis,David; T-C Dec 81 910-914

Information systems; cf. File systemsInfomation theory

digital- circuit testing; information-theoretic approach; Agrawal,Vishwani D.; T-C Aug 81 582-587

Integrated-circuit interconnections; cf. LayoutIntegrated-circuit testng; cf. Digital system testingIntegrated circuits; cf. Bipolar integrated circuits; CMOS integrated

circuits; Semiconductor logic circuitsIntegrated injection logic; cd. Bipolar integrated circuits, I2LInterconnection networksCONET programmed connection network model and parameter

study; Wirsching, J. E.; T-C Apr 81 298-301delta networks in packet communication environment; buffered

networks, unbuffered networks, and crossbar switches; Dias, DanielM.; T-C Apr 81 273-282

multistage interconnection networks; fault diagnosis; Feng, Tse-Yun;T-C Oct 81 743-758

Interconnection networks; cf. Multiprocessing, interconnection;Permutation networks

Interconnections; cd. LayoutInterleaved memories

degradation in memory utilization due to dependencies of accessesisssued by pipelined computer; Ramamoorthy, C. V.; T-C Oct 81813-818

scheduling requests on interleaved memories for pipelined processor;optimafalgorithm; Ramamoorthy, C. V.; T-C Oct 81 787-800

Iterate logiic arys; cf. Cellular logic arrays

L

Languages; cd. Comyuter languagesLarge-scale integration; cd. Integrated circuitsLayout

channel-assignment problem, optimal solution; Lauther, U.; T-C Jun .81 455

channel-assignment problem; optimal solution; Persky, G.; T-C Jun 81454

channel-assignment problem; optimal solution; Rubin, Frank; T-C Jun81 455

CMOS functional arrays; optimal layout; Uehara, Takao; T-C May 81305-312

hypertree multiprocessor interconnection topology; Goodman, JamesR.; T-C Dec 81 923-933

MIMD multiprocessor; topologies for interconnection; Finkel, RaphaelA.; T-C Dec 81 960-965

MOS LSI chip; layout system for random-logic portion; Shirakawa,Isao; T-C Aug 81 572-581

shuffle-exchange interconnection network layout; Steinberg, David;T-C Dec 81 977-982

topology of cellular partitioning networks; generalization of triangularpermuting networks; Gecsei, Jan; T-C Feb 81 164-168

universal VLSI circuit design; embedding interconnection pattern ofcircuit into two-dimensional minimal-area surface; Valiant, LeslieG.; T-C Feb 81 135-140

Linear codeserror-correcting linear code application to fault-tolerant machines;

Sengupta, A.; T-C Mar 81 237-240Logic arrays

generalized Boolean functions; multivalued decomposition andcomplexity of programmable logic arrays; Sasao, Tsutomu; T-C Sep

hardware approach to self-testing of large programmable logic arrays;Daehn, Wilfried; T-C Nov 81 829-833

optimal layout of CMOS functional arrays; Uehara, Takao; T-C May81 305-312

programmable logic arrays; fault detection in easily testable design;Fujiwara, Hideo; T-C Nov 81 823-827

rewntable programmable logic array of current-mode logic;construction and control; Tanaka, Mamoru; T-C Mar 81 229-234

Logic arrays; cf. Cellular logic arraysLogic circuit fault diagnosisdual-mode logic for function-independent fault testing; DasGupta, S.;T-C Nov 80 1025-1029. Correction, Oct 81 819

Logic circuit fault tolerance; cf. Sequential machine fault toleranceLogic circuit testing

closedness and test complexity under streak-type faults; Fujiwara,Hideo; T-C Aug 81 556-562

counting sequences with Hamming distance between successive countvalues in desired range; application to circuit testing; Robinson, JohnP.; T-C Jan 81 17-23

easily testable bit-sliced systems design; Sridhar, Thirumalai; T-C Nov81 842-854

fault modeling, test pattern generation, and design for testability in LSIcircuits; overview; Muehldorf, Eugen I.; T-C Jan 81 1-17

parity logic networks; optimum test pattern generation; Hong, Se June;T-C May 81 356-358

programmable logic arrays; fault detection in easily testable design;Fujiwara, Hideo; T-C Nov 81 823-827

Logic circuit testing; cf. Combinational circuit testing; Digital systemtesting; Sequential machine testing

Logic circuitsnearly optimal graph design of small-diameter switching networks;

Imase, Makoto; T-C Jun 81 439-442planar crossover circuit realization; McColl, William F.; T-C Mar 81

223-225Logic circuits; cd. Asynchronous sequential machines; Combinational

circuits; Counting circuits; Logic arrays; Logic-in-memory; Logicmodules; Multivalued logic circuits; Semiconductor logic circuits;Sequential machines

Logic designdynamically programmable logic gate; Hurst, S. L.; T-C Dec 81

986-987dynamically programmable logic gate; Suarez, Ricardo E.; T-C Jan 81

79-81Logic design; cf. Logic circuits; Logic modules; Logic partitioningLogic functions

binary program optimization using P-functions; Thayse, Andre; T-CFeb 81 126-134

Logic functions; cf. Boolean functions; Logic circuits; Multivalued logicfunctions

Logic-in-memoryrewritable programmable logic array of current-mode logic;

construction and control; Tanaka, Mamoru; T-C Mar 81 229-234Logic modules

tree-structured sequential multivalued logic design from universalmodules; Singh, A. D.; T-C Sep 81 671-674

Logic paridtoningtopology of cellular partitioning networks; generalization of triangnlarpermuting networks; Gecsei, Jan; T-C Feb 81 164-168

LSI (large-scale integration); cf. Integrated circuits


M

Magnetic bubble memoriessorting device component of bubble string comparators; Lee, D. T.;

T-C Jun 81 396405sorting with CCDs and magnetic bubble memories; Agrawal, Dharma

P.; T-C Feb 81 153-156tree search schemes in major/minor loop bubble memories;

Bongiovanni, Giancarlo; T-C Aug 81 537-545Magnetic memories; cd. Magnetic bubble memoriesMany-valued logic; cd. Multivalued logicMarkov processes

shuffle/exchange networks; interference analysis based on discreteMarkov chain model; Thanawastien, Suchai; T-C Aug 81 545-556

Mathematical programming; cd. Dynamic programmingMatrices

error complexity analysis of algorithms for matrix multiplication andmatrix chain product; Tsao, Nai-Kuan; T-C Oct 81 758-771

mixed-radix number system related to Kronecker product of matricesand perfect shuffle; Davio, Marc; T-C Feb 81 1 F6-125

Matrix factorizationcomplexity of a class of on-line problems; Fredman, Michael L.; T-CJan 81 83-86

Memoriesprocessor-memory interconnections for multiprocessors; performance;

Patel, Janak H.; T-C Oct 81 771-780Memories; ci. Buffer memories; Cache memories; Interleaved memories;

Magnetic memories; Random-access memories; Read-onlymemories; Virtual memories

Memory accessdegradation in memory utilization due to dependencies of accesses


Memory aliocationpartitionable SIMD/MIMD system for image processing and pattern

recogmtion; Siegel, Howard Jay; T-C Dec 81 934-947Memory lault diagnosis; cd. Memory testingMemory fault tolerance


Memory testingfunctional fault detection in RAMs; march test; Suk, D. S.; T-C Dec

81 982-985pattern-sensitive faults in RAMs; graph model; Seth, Sharad C.; T-C

Dec-81 973-977Merging

Huffman's algorithm for constructing optimal weighted trees; boundson root node weight and application to multiplexer design; Parker,D. Stott, Jr.; T-C May 79 365-367. Correction, Jun 81 454

Merging; ci. SortingMerwin, Richard E

obituary; Booth, Taylor L.; T-C Dec 81 909Message switching

chordal ring graphs for message-connected multimicrocomputers;Arden, Bruce W.; T-C Apr 81 291-295

Message switching; ci. Packet switchingMicrocomputer fault tolerance

Boolean n cube array of microprocessors; fault tolerant characteristics;Armstrong, J. R.; T-C Aug 81 587-590

Microcomputer networksBoolean n cube array of microprocessors; fault tolerant characteristics;Armstrong, J. Ri; T-C Aug 81 587-590

chordal ring graphs for message-connected multimicrocomputers;Arden, Bruce W; T-C Apr 81 291-295

cluster structure as conceptual interconnection scheme for largemultimicroprocessor system; Wu, Shyue B.; T-C Apr 81 254-264

distributed enumeration on network computer usingbranch-and-bound technique; El-Dessouki, Ossama Ibrahim; T-CSep 80 818-825. Correction, Jan 81 87

dual-bus hypercubes for cost-effective microcomputer interconnection;Wittie, Larry D.; T-C Apr 81 264-273

Microcomputer testingbit-sliced microprocessors; test generation based on functional fault

model; Sridhar, Thirumalai; T-C Aug 81 563-571Boolean n cube array of microprocessors; fault tolerant characteristics;Armstrong, J. R.; T-C Aug 81 587-590

Microcomputerspartitionable SIMD/MIMD system for image processing and pattern

recognition; Siegel, Howard Jay; T-C Dec 81 934-947Microprocessors; cd. MicrocomputersMicroprogramming

control memory width minimization by bit steering; Mathialagan,Ayakannu; T-C Feb 81 144146

hard-programmable control unit as alternative to traditionalmicroprogrammable unit; Dervisoglu, Bulent I.; T-C Oct 81 800-810

hardware description language for modeling and simulation ofhorizontal bit-sliced processor; Van Dam, A.; T-C Jul 81 513-519

12L multivalued ROM design for microprogrammed computers; wordwidth optimization; Silio, Charles B., Jr.; T-C Feb 81 148-153

microcode compaction methods comparison; Davidson, Scott; T-C Jul81 460-477

MPG machine-independent high-level microprogramng languageand its processing system;; Baba, Takanobu; T-C Jun 81 373-395.Correction, Oct 81 818

optimization of microprograms applicable to microinstruction formatsvarying from horizontal to partially encoded to vertical; Tokoro,Mario; T-C Jul81 491-504

software simulators for testing and debugging larmicroprogrammedsstems; Myers, Glenford J.; T-C Jul81 519-52

tools and techniques; special issue; T-C Jul 81 457-523tools and techniques; special issue introduction; Lewis, T. G., Guest ed.;T-C Jul81 457459

trace scheduling for global microcode compaction; Fisher, Joseph A.;T-C Jul81 478490

vertical migration of functions in multilevel interpretive hierarchy;Stankovic, John A.; T-C Jul 81 505-513

Modular computer systemsasymmetric modular architectures; fault diagnosis algorithm; Meyer,

Gerard G. L; T-C Jan 81 81-83Modular computer systems; cf. Logic modulesMOS integrated circuits, logic

layout system for random-logic portion of MOS LSI chip; Shirakawa,Isao; FT-C Aug 81 572-581

Multilevel systemsvertical migration of functions in multilevel interpretive hierarchy;

Stankovic, John A.; T-C Jul 81 505-513Multiplexing


Multiplicationerror complexity analysis of algorithms for matrix multiplication and

matrix chain product; Tsao, Nai-Kuan; T-C Oct 81 758-771generalized parallel counter synthesis; Dormido, S.; T-C Sep 81 699-703

Multiplication; cd. ConvolutionMultiprocessing

digital convolution algorithm for pipelining multiprocessor system;Jenq, Yih-Chyun; T-C Dec 81 966-973

job scheduling, minimum-resource fixed job scheduling; optimalsolution; Lauther, U.; T-C Jun 81 455

job scheduling, minimum-resource fixed job scheduling; optimalsolution; Persky, G.; T-C Jun 81 454

job scheduling, minimum-resource fixed job scheduling; optimalsolution; Rubin, Frank; T-C Jun 81 455

one-dimensional optimization of multiprocessor systems; Franklin,Mark A.; T-C Jan 81 61-66

Multiprocessing; cf. Distributed computing; Microcomputer networks;Parallel processing

Multiprocessing, interconnectionbanyan and crossbar communication networks; VLSI performance

characteristics; Franklin, Mark A.; T-C Apr 81 283-291binary tree structure related to microprocessor systems and VLSI

circuit design; Horowitz, Ellis; T-C Apr 81 247-253chordal ring graphs for message-connected multimicrocomputers;Arden, Bruce W.; T-C Apr 81 291-295

cluster structure as conceptual interconnection scheme for largemultimicroprocessor system; Wu, Shyue B.; T-C Apr 81 254-264

data broadcasting in SIMD computers; Nassimi, David; T-C Feb 81101107

dual-bus hypercubes for cost-effective microcomputer interconnection;Wittie, Larry D.; T-C Apr 81 264-273

hypertree multiprocessor interconnection topology; Goodman, JamesR.; T-C Dec 81 923-933

interconnection network for parallel and distributed processing; specialissue; T-C Apr 81 245-301

interconnection networks for parallel and distributed processing;special issue foreword; Sieget Howard Jay, Guest ed.; T-C Apr 81245-246

MIMD multiprocessor; topologies for interconnection; Finkel, RaphaelA.; T-C Dec 81 960-96S

mixed-radix number system related to Kronecker product of matricesand perfect shuffle; Davio, Marc; T-C Feb 81 1f6-125

partitionable SIMD/MIMD system for image processing and patternrecognition; Siegel, Howard Jay; T-C Dec 81 934-947

processor-memory interconnections for multiprocessors; performance;Patel, Janak H.; T-C Oct 81 771-780

shuffle-exchange interconnection network layout; Steinberg, David;T-C Dec- 81 977-982

shuffle-exchange networks; capability of realizing every arbitrarypermutation; Wu, Chuan-Lin; T-C May 81 324-332

shuffle/exchange networks; interference analysis based on discreteMarkov chain model; Thanawastien, Suchai; T-C Aug 81 545-556

SLIDE hardware-descriptive language for description of asynchronousconcurrent intercommunicating processes; Parker, Alice C.; T-C Jun81 423-439


Multivalued logicfour-valued digital system design based on Boolean and Post algebra;

Kabat, Waldo C.; T-C Se 81 666-671special section of papers; T-C Sep 81 617-678special section introduction; Butler, Jon T., Guest ed.; T-C Sep 81

617-618tree-structured sequential multivalued logic design from universal

modules; Singh, A. D.; T-C Sep 81 671-674Multivalued logic circuitsCCD implementation; Kerkhoff, Hans G.; T-C Sep 81 644-65212L multivalued ROM design for microprogrammed computers; word

width optimization; Silio, Charles B., Jr., T-C Feb 81 148-153multivalued 12L circuit design; Davio, Marc; T-C Sep 81 653-661review of prospects from standpoint of technology and application;

Smith, K. C.; T-C Sep 81 619-634single error correction-double error detection nonbinary code for

fiault-tolerant byte-organized memory implemented with quaternarylogic; Dao, Tich T.; T-C Sep 81 662-666

Multivalued logic functionsgeneralized Boolean functions; multivalued decomposition and

complexity of programmable logic arrays; Sasao, Tsutomu; T-C Sep81 635-643

representation of multivalued functions using direct cover method;algorithm for use with sum and product operators in bipolartechnologies; Pomper, Gardner; T-C Sep 81 674-679

N

Negative radix arithmeticfinite number representation including positive, negative, andimaginary radix number systems; Koren, Israel; T-C May 81 312-317

Nets; cd. LayoutNetwork topology; cf. LayoutNetworks; cd. Computer networks; Graph theory; Logic circuitsNonlinear systems

diagnosability of nonlinear dc circuits and systems; Visvanathan, V.;T-C Nov 81 889-898

diagnosability of nonlinear dynamical systems; Saeks, Richard; T-CNov 81 899-904

Number-theoretic transformsDFT computations, Winograd's method extended; cyclic convolutionperformed using Mersenne number-theoretic transform; Reed, I. S.;T-C Jul 79 487-492. Addendumn, Jun 81 453

fast number-theoretic transforms; conditions for existence; Kodek,Dusan M.; T-C May 81 359-360

Number theoryfinite number representation including positive, negative, and

imaginary radix number systems; Koren, Israel; T-C May 81 312-317Numerical integration; cf. ConvolutionNumerical methods; cd. Mathematical programming

0

Optical data processing; cd. Image processingOptimization methods

binai7 proram optimization using P-functions; Thayse, Andre; T-C

one-dimensional optimization of multiprocessor systems; Franklin,Mark A.; T-C Jan 81 61-66

Optimization methods; cd. Dynamic programming

p

Packet switchingcongestion control in packet networks by input buffer limits; Lam,

Simon S.; T-C Oct 81 733-742delay analysis of broadcast routing in packet-switching networks;

Gopal, Gita; T-C Dec 81 915-922delta networks in packet communication environment; buffered

networks, unbuffered networks, and crossbar switches; Dias, DanielM.; T-C Apr 81 273-282

store-and-forward deadlock prevention; Gelernter, David; T-C Oct 81709-715

Paged memories; cd. Virtual memoriesParallel processing

concurrent access to dynamically balanced binary search trees; AVLtrees; Gottlieb, Allan; T-C Oct 81 812

generalized parallel counter synthesis; Dormido, S.; T-C Sep 81 699-703iard-programmable control unit as alternative to traditionalmicroprogrammable unit; Dervisoglu, Bulent I.; T-C Oct 81 800-810

mapping of problem modules onto array rocessor as graphisomorphism problem; heuristic algorithm; Bohari4 Shahid H.; T-CMar 81 207-214

microcode compaction using trace scheduling; Fisher, Joseph A.; T-CJul 81 478490

processor network modeling by d-graph automaton; equivalence toSiegel's SIMD model; Wu, Angela Y.; T-C May 81 37-372

routing in permutation networks; fast parallel algorithm; Lev, GavrielaFreund; T-C Feb 81 93-100

Parallel processing; cf. Computer pipeline processing; MultiprocessingPattern recognition

partitionable SIMD/MIMD system for image processing and patternreconition; Siegel, Howard Jay; TC Dec 81 934-947

Permutation networksmultiple-pas control algorithm on S2 networks; II networks; Yew,

Pen-Chung; T-C Apr 81 296-298routing in permutation networks; fast parallel algorithm; Lev, Gavriela

Freund; T-C Feb 81 93-100self-routing Benes network; Nassimi, David; T-C May 81 332-340shuffle-exchange networks; capability of realizing every arbitrary

permutation; Wu, Chuan-Lin; T-C May 81 324-332topology of cellular partitioning networks; generalization of triangularpermuting networks; Gecsei, Jan; T-C Fel 81 164-168

Picture processing; cf. Image processingPipeline processing; cf. Computer pipeline processingProgramming; cf. Computer languages; Computer softwarePseudonoise sequences; cf. Shift-register sequences

QQueued communication

buffer behavior with Poisson arrivals, periodic opportunities forservice, and random blocking of service; Shanthikumar, J. G.; T-CFeb 81 157

high-level data link control protocol; performance evaluation;Labetoulle, Jacques; T-C Jun 81 405-413

tandem queueing system with constant slotted service times andthreshold control; model and analysis; Chu, Wesley W.; T-C May 81318-327

Queueing analysisbehavior of system with Poisson arrivals, infinite buffer size andrandom server interruptions; Shanthikumar, J. G.; T-C Oct 81781-786

buffer length for Erlong input; Maritsas, D. G.; T-C Jan 81 78delay analysis of broadcast routing in packet-switching networks;

Gopal, Gita; T-C Dec 81 915-922

R

RAM; cf. Random-access memoriesRandom-access memories

functional fault detection in RAMs; march test; Suk, D. S.; T-C Dec81 982-985

pattern-sensitive faults in RAMs; graph model; Seth, Sharad C.; T-CDec 81 973-977

Read-only memories12L multivalued ROM design for microprogrammed computers; wordwidth optimization; Silio, Charles B., Jr.; T-C Feb 81 148-153

microprogramming; control memory minimtion by bit steering;Mathialagan, Ayakannu; T-C Feb 81 144-146

Redundant systems; cf. Fault toleranceROM; cf. Read-only memories

S

Schedulingjob scheduling, minimum-resource fixed job scheduling; optimal

solution; Lauther, U.; T-C Jun 81 455job scheduling, minimum-resource fixed job scheduling; optimal

solution; Persky, G.; T-C Jun 81 454job scheduling, minimum-resource fixed job scheduling; optimal

solution; Rubin, Frank; T-C Jun 81 455Semiconductor logic circuitsLSI lopic testing and design for testability; overview; Muehidorf, EugenL ; TCJan 81 1-17

Semiconductor logic circuits; cf. Bipolar integrated circuits; CMOSintegrated circuits; MOS integrated circuits

Semiconductor memories; cf. Bipofar integrated circuits; Charge-coupledmemories; CMOS integrated circuits

Sequential machine fault tolranceerror-correcting linear code application to fault-tolerant machines;

Sengupta, A.; T-C Mar 81 231-240Sequential machine testing

checking sequences for strongly-connected, reduced, synchronous,completely specified deterministic sequential machines; Braun,Robert D.; T-C Feb 81 141-144

hardware approach to self-testing of large programmable logic arrays;Daehn, Wilfried; T-C Nov 81 g29-833

intermittent fault detection and location in sequential circuits; Liaw,Chi-Chang; T-C Dec 81 989-995

IEEE T-C 1981 INDEX - 10

self-diagnosing cellular implementations of finite-state machines;Walters, Stephen M.; T-C Dec 81 953-959

Sequential machinesfinite-turn checking automata; recognition of sequential/parallel

matrix languages; Wan Patrick Shen-Pei; T-C May 81 366-370tree-structured sequential multivalued logic design from universalmodules; Singh, A. D.; T-C Sep 81 671-674

Sequential machines; cd. Asynchronous sequential machinesShift-register sequences

N-bit shift register pseudonoise sequence; autocorrelation function ofsequential M-bit words; Wustmann, Gerhard; T-C Mar 81 241

Signal processing; d. Image processingSimulation languages

extension of AHPL procedural hardware description language; Hill, F.J.; T-C Feb8115-161

Software; cf. Computer softwareSortingbubble string comparator for sorting device; Lee, D. T.; T-C Jun 81

396-405CCDs and magnetic bubble memories for low-cost sorting; Agrawal,Dharma P.; T-C Feb 81 153-156

Sorting; cf. MergingSpecal issues

design for testability; joint special issue with IEEE Transactions on

Circuits and Systems Nov 81; T-C Nov 81 821-904interconnection networks for parallel and distributed processing; T-CApr 81 245-301

microprogramming tools and techniques; T-C Jul 81 457-523multivalued logic circuits; T-C Sep 81 617-678

Stabilityasynchronous sequential machines; metastable operation theory;

Marino, Leonard R.; T-C Feb 81 107-115Store-and-forward networks; cf. Packet switchingSwitching algebra; cf. Boolean algebra; MultivaTued logicSwitching circuits

generalized algebra for switching circuits; Surjaatmadja, Jim B.; T-CAug 81 609-613

Switching circuits; cf. Logic circuitsSwitching functions; cf. Logic functionsSwitching systems; cf. Communication switching; Interconnection

networksSynchronization

voter design for different signaling conventions in redundant systems;McConnel, Stephen R.; T-C Feb 81 161-164

T

Ternary logic; cf. Multivaled logicTesting

analog system failure analysis; measures of testability and testcomplexity; Priester, Robert W.; T-C Nov 81 884-889

networks representable by acyclic directed graph; minimal test sets forsingle link failures; Ibaraki, Toshihide; T-C Mar 81 182-190

Testing; d. Computer software testing; Computer testing; Digital systemtesting; Logic circuit testing; Memory testing

Topology; cf. Network topologyTransforms; cf. Discrete Fourier transforms; Number-theoretic

transformsTrees

binary tree structure related to microprocessor systems and VLSIcircuit design; Horowitz, Ellis; T-C Apr 81 247-253

bubble memories; tree search in major/minor loops; Bongiovanni,Giancarlo; T-C Aug 81 537-545

concurrent access to dynamically balanced binary search trees; AVLtrees; Gottlieb, Allan; T-C Oct 81 812

equivalence handling methods; UNION-FIND implementation;Murray, Neil V.; T-C May 81 361-162


modeling of broadcasting by minimum broadcast tree; Proskurowski,Andrzej; T-C May 81 363-366

tree-structured sequential multivalued logic design from universalmodules; Singh, A. D.; T-C Sep 81 671-674

V

Virtual memoriesmemory system for high-performance personal computer; Clark,

Douglas W.; T-C Oct 81 715-733memory system with skewing reconfigurations; reliability

improvement; Kanai, Takeo; T-C Oct 81 811-812paging behavior improvement by source program transformations via

optimizing compiler; Abu-Sufah, Walid; T-C May 81 341-356VLSI (very large-scale integration); cf. Integrated circuits

W

WFTA (Winograd Fourier transform algorithm); cf. Discrete Fouriertransforms

Documents

1981 Index IEEE Transactions Computers Vol. C-30 · IEEETransactions on Computers Vol. C-30 ... Braun, Robert D., and Donald D. Givone; Ageneralized algorithm for ... Daniel M., and