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17.11.0417.11.04TechnionTechnion
Digital Lab ProjectDigital Lab Project
Xilinx ML310 board based on Xilinx ML310 board based on VirtexII-PRO programmable VirtexII-PRO programmable
devicedevice
Students:Students: Tsimerman Igor Tsimerman Igor Firdman LeonidFirdman Leonid
Supervisor:Supervisor: Rivkin Ina Rivkin Ina
17.11.0417.11.04TechnionTechnion
Digital Lab ProjectDigital Lab Project
AgendaAgenda Project goals Project goals Project resourcesProject resources HW/SW flow charterHW/SW flow charter Project schedule – first & second Project schedule – first & second
semestersemester OpeningsOpenings
17.11.0417.11.04TechnionTechnion
Digital Lab ProjectDigital Lab Project
Project goalsProject goals Studying and investigating Xilinx ML310 Studying and investigating Xilinx ML310
boardboard PS2 user softcore implementationPS2 user softcore implementation Board Ramp-Up with Linux OSBoard Ramp-Up with Linux OS
17.11.0417.11.04TechnionTechnion
Digital Lab ProjectDigital Lab Project
Project goalsProject goals Studying and investigating Xilinx ML310 Studying and investigating Xilinx ML310
boardboard– Studying and making a list of existing board’s Studying and making a list of existing board’s
peripheralsperipherals– Making al list and activation of on board soft cores Making al list and activation of on board soft cores
(using EDK)(using EDK)– Making a list of non-existing / “non-suitable” soft Making a list of non-existing / “non-suitable” soft
cores and finding a ways to activate themcores and finding a ways to activate them
17.11.0417.11.04TechnionTechnion
Digital Lab ProjectDigital Lab Project
Project goalsProject goalsPS2 user softcore implementationPS2 user softcore implementation
Peripherals
Xilinx ML310Xilinx ML310
PS2
Keyboard
Virtex II Pro
Output Device(LCD, Uart …)
PowerPC 405
PS2Softcore
(User Defined)
OPB
Out DevConn.
PLB
Output Devicesoftcore
PLB/OPBBridge
17.11.0417.11.04TechnionTechnion
Digital Lab ProjectDigital Lab Project
Project resourcesProject resources
17.11.0417.11.04TechnionTechnion
Digital Lab ProjectDigital Lab Project
Project resourcesProject resources
17.11.0417.11.04TechnionTechnion
Digital Lab ProjectDigital Lab Project
Project resourcesProject resources
Virtex II Pro FPGAVirtex II Pro FPGA– ~30K ASIC gates~30K ASIC gates
– 136 18x18-bit Multipliers136 18x18-bit Multipliers
– 2448 Kb of on-chip memory2448 Kb of on-chip memory
– 2 Power PC 4.05 CPU core2 Power PC 4.05 CPU core
– 8 DCM (digital clock manager) units8 DCM (digital clock manager) units
17.11.0417.11.04TechnionTechnion
Digital Lab ProjectDigital Lab Project
HW/SW FlowHW/SW Flow
HW BlockDiagram
HW Description
Synthesize P&R
BIT File/Download
HW Flow
SW Flow Chart
Create SWSource
Compile Simulate
ELF File/Download
SW Flow
ISE
Design Debug (HW and SW)
DATA2BRAM
EDK
17.11.0417.11.04TechnionTechnion
Digital Lab ProjectDigital Lab Project
Project schedule Project schedule first semester first semester
Studying the VHDL programming language <~2 weeks>Studying the VHDL programming language <~2 weeks>
Studying Simulation and Synthesis programs (EDK, HDL Studying Simulation and Synthesis programs (EDK, HDL Designer) <~ 4 weeks>Designer) <~ 4 weeks>
Get familiar with the Xilinx ML310 board and Virtex II Pro Get familiar with the Xilinx ML310 board and Virtex II Pro FPGA <~3 weeks>FPGA <~3 weeks>
Keyboard (on PS2) softcore implementation and Keyboard (on PS2) softcore implementation and indication on LCD <~4 weeks>indication on LCD <~4 weeks>
17.11.0417.11.04TechnionTechnion
Digital Lab ProjectDigital Lab Project
Project schedule Project schedule second semester second semester
Xilinx ML310 board Ramp-Up with Linux OS Xilinx ML310 board Ramp-Up with Linux OS <~semester><~semester>
17.11.0417.11.04TechnionTechnion
Digital Lab ProjectDigital Lab Project
OpeningsOpenings
LINUX / Win OS? LINUX / Win OS?
Which peripherals have to be included Which peripherals have to be included in final Ramp-Up process?in final Ramp-Up process?
Second semester – mutual project with Second semester – mutual project with Intel?Intel?