1/7. 2 Carbon-Nanotube-Based Voltage-Mode Multiple-Valued Logic Design Arijit Raychowdhury, Student Member, IEEE, and Kaushik Roy, Fellow, IEEE IEEE

Carbon-Nanotube-Based Voltage-Mode Multiple-Valued Logic Design Arijit Raychowdhury, Student Member, IEEE, and Kaushik Roy, Fellow, IEEE IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 4, NO. 2, MARCH 2005 3

4 AbstractMultivalued logic has always attracted the attention of digital system and logic designers. However, the high-performance and low-power CMOS process, which has been developed over the last two decades, has traditionally assisted successful circuit implementation of binary logic. Consequently, in spite of its large potential multivalued logic design is seldom a circuit designers choice. This paper presents a novel method of multiple-valued logic design using carbon-nanotube field-effect transistors (CNFETs).

5 The geometry-dependent threshold voltage of CNFETs has been effectively used to design a ternary logic family.We have developed a SPICE-compatible model of ballistic CNFETs that can account for varying geometries and operating conditions. SPICE simulations have been performed on the proposed logic gates, and the transfer characteristics as well as transient behavior have been extensively studied. Finally, a comparison in terms of power and performance of the ternary logic family vis--vis traditional complementary field-effect transistor binary logic family has been presented.

6 I. INTRODUCTION DIGITAL circuit design has traditionally been associated with binary logic where the two logic levels are represented by two discrete values of current, voltage or charge. However, for the last couple of decades, multiple-valued logic (MVL) has attracted considerable attention, especially among circuit and system designers [1]. MVL circuits allow more than two levels of logic and, depending on the number of allowed levels, we may have ternary (base=3) or quaternary (base=4) logic styles. [1] S. L. Hurst, Multiple-valued logicIts status and its future, IEEE Trans. Comput., vol. C-33, no. 12, pp. 11601179, Dec. 1984.

7 MVL circuits can reduce the number of operations necessary to implement a particular mathematical function and thus have an advantage in terms of reduced area. This in turn reduces parasitics associated with routing and provides a higher speed of operation. Further, the overall power dissipation can also be reduced by translating a design from the binary to the ternary or quaternary families.

8 MVL circuits have been designed using charge-coupled devices (CCDs) [2], voltage-mode CMOS (VMCL) [3], [4], and current- mode CMOS (CMCL) [5]. Chip area and power dissipation have been shown to be reduced by more than 50% using efficient MVL implementation of a signed 32-b multiplier compared to its fastest binary counterpart [6]. Jain et al. have demonstrated the circuit and system implications of MVL design in [7]. MVL modules have been inserted in binary logic ICs for enhancing performance [8]. [2] J. T. Butler and H. G. Kerkhoff, Multiple-valued CCD circuits, IEEE Comput., vol. 21, no. 4, pp. 2842, Apr. 1988. [3] S. Onneweer, H. Kerkhoff, and J. Bultler, Structural computer-aided design of current-mode CMOS logic circuits, in Proc. 18th Int. Symp. Multiple-Valued Logic, May 1988, pp. 2130. [4] M. Davio and J. P. Deschamps, Synthesis of discrete functions using technology, IEEE Trans. Comput., vol. C-19, no. 9, pp. 653661, Sep. 1981. [5] F. J. Pelayo, A. Preito, A. Lloris, and J. Ortega, CMOS current mode multiple-valued PLAs, IEEE Trans. Circuits Syst., vol. 38, no. 4, pp. 434441, Apr. 1991. [6] M. Kameyama, S. Kawahito, and T. Higuchi, A multiplier chip and multiple-valued bidirectional current mode logic circuits, IEEE Comput., vol. 21, no. 4, pp. 4356, Apr. 1988. [7] A. K. Jain, R. Bolton, and M. H. Abd-el-bar, CMOS multiple valued logic designPart I: Circuit realization, IEEE Trans. Circuits Syst., vol. 40, no. 8, pp. 503514, Aug. 1993. [8] D. A. Rich, A survey of multiple-valued memories, IEEE Trans. Comput., vol. C-35, no. 2, pp. 99106, Feb. 1986.

9 As we progress into an era of nanotechnology, molecular devices are becoming promising alternatives to the existing silicon technology. Carbon-nanotube field-effect transistors (CNFETs) are being extensively studied as possible successors to silicon MOSFETs. Research has started in earnest to understand the device physics of CNFETs as well as to explore possible circuit applications [9]. As CNFETs inherit IV characteristics that are qualitatively similar to silicon MOSFETs, most of the present-day MOS circuits can be translated to a CNFET based design. [9] P. Avouris, J. Appenzeller, V. Derycke, R. Martel, and S.Wind, Carbon nanotube electronics, in Int. Electron Devices Meeting Tech. Dig., 2002, pp. 281284.

10 However, it is only prudent to investigate newer circuit ideas that might be suitable for use with CNFETs because of their inherent characteristics. In this paper, we have investigated the use of carbon- nanotube transistors for voltage-mode MVL circuit synthesis. Carbon nanotubes have bandgaps that depend on the nanotube diameter. The bandgap is a measure of the threshold voltage of the CNFET. In this paper, we have exploited the fact that carbon nanotubes can be configured to have desired threshold voltages depending on their diameter, making it suitable for voltage-mode MVL implementation.

11 The SPICE compatible circuit model of CNFETs that we have developed [10] has been used for the circuit simulations. We have implemented a functionally completeMVLset of operators. The set consists of: literal, complement of literal, cycle, complement of cycle, min, and tsum operators. In the proposed circuits, all of the MVL levels are represented in terms of voltage values considering sufficient noise margin to avoid error in computation. The performance of logic blocks using the proposed MVL gates has been studied and compared with the corresponding binary logic family. Simulation results show that, for equivalent mathematical operations, MVL implementation can give a reduction in power as well as an improvement in the speed of operation. [10] A. Raychowdhury, S. Mukhopadhyay, and K. Roy, Circuit compatible modeling of carbon nanotube FETs in the ballistic limit of performance, in Proc. 3rd IEEE Conf. Nanotechnology, vol. 1214, Aug. 2003, pp. 343346.

12 The remainder of this paper is organized as follows. Section II discusses the basics of MVL and the logic operators for a functionally complete set. The fundamentals of CNFETs with special emphasis on the circuit-compatible model that we have used for our simulations are presented in Section III. Section IV describes a novel circuit realization of MVL using CNFETs and addresses the issues therewith. A detailed study of ternary logic structures and how they compare with binary logic families will be discussed in Section V. Section VI deals with variability and the load-handling capacity of the proposed ternary logic gates. Finally, conclusions and discussions are provided in Section VII.

13 II. BASICS OF MVL Let us consider an r-valued n-variable function f(X), where and each xi can take up values from R={0,1,2,,r-1}. Hence the function f(X) is a mapping. Thus there are different functions possible in the set f. A set of primitive functions [7] which have been implemented in this paper are explained below. The logic gates that would implement each of these functions would be called primitive gates. [7] A. K. Jain, R. Bolton, and M. H. Abd-el-bar, CMOS multiple valued logic designPart I: Circuit realization, IEEE Trans. Circuits Syst., vol. 40, no. 8, pp. 503514, Aug. 1993.

14 Definition 1: A min (minimum) operator is defined as Where belongs to the set R. Example: min(2,3,1)=1. Definition 2: A truncated sum (tsum) operator is defined as Where belongs to the set R. Example: Consider r=3. tsum(1,0,1)=min(1+0+1,2)=2.

15 Example: Consider r=3. Thus, the complement set is given by Table I. Definition 3: A complement of a logic value l is defined as TABLE I TRUTH TABLE OF A COMPLEMENTARY OPERATION

16 Definition 4: A cycle (or a clockwise cycle) of a variable a is defined as Where. Example: Consider r=3. The cycle operator is thus defined as given in Table II. It can thus be noted that and hence the same circuit can be used for both the realizations. TABLE II TRUTH TABLE OF A CYCLE OPERATION

17 Definition 5: A literal of a multivalued variable is defined as where

18 Here and and. Example: Let us consider r=3. Table III shows the logic value of along with,. and. TABLE III TRUTH TABLE OF A LITERAL OPERATION

19 For a ternary logic family, one property of the literal operator that allows reuse of the primitive tsum gate is: for all nontrivial combinations of x and y. By the trivial case, we mean, which is identically equal to a logic value of 1(k=1) or 2(k=2) and, hence, it does not represent any mathematical operation.

20 III. CNFETS AND THEIR SPICE-COMPATIBLE MODELING Before going into the realization of the ternary gates using carbon- nanotube transistors, it will be prudent to present a short description of the transistors themselves and our simulation models. Carbon nanotubes are sheets of graphite rolled into tubes. Depending on their chirality (i.e., the direction in which the graphite sheet is rolled), the single-walled carbon nanotubes can either be metallic or semiconducting. Semiconducting nanotubes have attracted widespread attention from electron device and circuit designers.

21 There has been tremendous interest in CNFETs as potential successors to silicon MOSFETs. CNFETs have been proved to be promising molecular transistors because of their high on current density and moderately high ONOFF ratio. Research has begun in the earnest to harness the potential of CNFETs to design ultrahigh-performance digital integrated circuits. Simultaneously, it is important that novel circuit techniques and circuit ideas are developed using these new devices. This paper is an attempt to successfully implement a completely new voltage-mode MVL family using CNFETs.

22 Let us discuss the two types of carbon-nanotube transistors that are being extensively studied. One of the devices is a tunneling device [see Fig. 1(a) and (b)] and works on the principle of direct tunneling through a Schottky barrier at the sourcechannel junction [11]. [11] J. Guo, S. Datta, and M. Lundstrom, Anumerical study of scaling issues for Schottky barrier carbon nanotube transistors, Phys. Rev. B, Condens. Matter, cond-mat/0 306 199, 2003. Fig. 1. (a) Physical diagram of a Schottky-barrier CNFET. Note that a high K dielectric (ZrO ) has been used. (b) Band diagram of the Scottky-barrier CNFET indicating the tunneling barrier.

23 The barrier width is modulated by the application of gate voltage, and thus the transconductance of the device is dependent on the gate voltage. These devices are fabricated using direct contact of the metal with the semiconducting nanotube and, consequently, they have a Schottky barrier at the metal nanotube junction. Two important aspects of these nanotube transistors are worth mentioning. First, the energy barrier at the Schottky barrier severely limits the transconductance of the nanotube transistors in the ON state and reduces the current delivery capabilitya key metric to transistor performance. Second, Schottky-barrier CNFETs exhibit strong ambipolar characteristics, and this constrains the use of these transistors in conventional CMOS logic families.

24 To overcome these handicaps associated with the Schottky barrier CNFETs, there has been attempts to develop CNFETs which would behave like normal MOSFETs [12][14]. These attempts have met significant success so far and the promise is enormous. The MOSFET-like CNFET [see Fig. 2(a) and (b)] operates on the principle of barrier height modulation by application of the gate potential. Fig. 2. (a) Physical diagram of a MOSFET-like CNFET. Note that a high K dielectric (ZrO ) has been used. (b) Band diagram of the MOSFET-like CNFET indicating the absence of any tunneling barrier. Also, note that the barrier height at the sourcechannel junction is E G /2. [12] A. Javey, J. Guo, Q.Wang, M. Lundstrom, and H. Dai, Ballistic carbon nanotube transistors, Nature, vol. 427, pp. 654657, 2003. [13] A. Javey et al., High-K dielectrics for advanced carbon nanotube transistors and logic, Nature Materials, vol. 1, pp. 241246, 2002. [14] J. Guo, A. Javey, H. Dai, S. Datta, and M. Lundstrom, Predicted Performance advantages of carbon nanotube transistors with doped nanotubes source/drain, Phys. Rev. B, Condens. Matter, cond-mat/0 309 039, 2003.

25 Significant results have been obtained using Pd contacts with the nanotubes [15] and using a four-gate structure [16]. More recently, Guo et al. have presented numerical studies on such MOSFET-like CNFETs [14], and it is evident that: 1) the MOSFET-like CNFETs have unipolar characteristics unlike Schottky-barrier field-effect transistors (FETs); 2) the absence of the Schottky barrier reduces the OFF leakage current; 3) they have more scalability compared to their Schottky-barrier counterparts; and 4) in the ON state the source-to-channel junction has no Schottky barrier and hence significantly higher ON current. Further, it can be assumed that the transport through these CNFETs is ballistic [15], [16]. [14] J. Guo, A. Javey, H. Dai, S. Datta, and M. Lundstrom, Predicted Performance advantages of carbon nanotube transistors with doped nanotubes source/drain, Phys. Rev. B, Condens. Matter, cond-mat/0 309 039, 2003. [15] A. Javey, J. Guo, Q.Wang, M. Lundstrom, and H. Dai, Schottky barrier free nanotube transistors near the ballistic transport, Nature, vol. 424, pp. 654657, 2003. [16] S. J. Wind, J. Appenzeller, and P. Avouris, Lateral scaling in carbonnanotube field-effect transistors, Phys. Rev. Lett., vol. 91, no. 5, pp. ??????, Aug. 2003.

26 In this paper, we will consider the non-Schottky-barrier MOSFET-like unipolar CNFET with ballistic transport as our device of interest. Henceforth, in this paper, the word CNFET will be used to mean such a MOSFET-like device unless otherwise mentioned. Fig. 2(b) shows the band diagram of this device. The source Fermi level for a degenerately doped source can be taken at, the conduction band edge. Inside the intrinsic channel, the Fermi level is in the middle of the bandgap. An important property of these CNFETs is that the bandgap is inversely proportional to the diameter of the nanotube as [9] (1) [9] P. Avouris, J. Appenzeller, V. Derycke, R. Martel, and S.Wind, Carbon nanotube electronics, in Int. Electron Devices Meeting Tech. Dig., 2002, pp. 281284.

27 Thus, for conduction to start, the barrier at the sourcechannel junction that has to be overcome is (e.g., =). As the barrier height determines the threshold potential of an FET, the threshold voltage of the CNFETs can be expressed as (2) This geometry-dependent threshold voltage has been exploited in this study to obtain CNFETs that turn on at different voltages depending on their diameters.

28 In this study, a compact SPICE-compatible model of CNFETs has been used and simulations have been carried out using HSPICE. The details of the modeling technique are available in [10]. The CNFET used has a top gate with a 2-nm layer of ZrO (dielectric constant=25) as the insulator. Both IV and CV characteristics have been efficiently modeled. As a result, dc transfer characteristics and transient characteristics can be easily simulated, and the performance of CNFETs can be estimated. [10] A. Raychowdhury, S. Mukhopadhyay, and K. Roy, Circuit compatible modeling of carbon nanotube FETs in the ballistic limit of performance, in Proc. 3rd IEEE Conf. Nanotechnology, vol. 1214, Aug. 2003, pp. 343346.

29 The computational procedure for CNFETs is described as follows for the convenience of the readers [17]. 1) Consider a particular value of and beginning-of channel control potential. The control voltage is the amount by which the energy bands move up or down due to the application of a gate voltage. 2) Compute the total charge on the nanotube for a given and. The charge at the top of the barrier has contributions from both the source and the drain. All of the states at the barrier top are filled by the source while the states are populated by the drain [17]. [17] J. Guo and M. Lundstrom, Assessment of silicon MOS and carbon nanotube FET performance limits using a general theory of ballistic transistors, in Int. Electron Devices Meeting Tech. Dig., Dec. 2002, pp. 711715

30 Thus (3) where is the number of carriers in the channel, is the source (drain) Fermi level, is the bottom of the conduction band, is the probability that a state with energy E is occupied (FermiDirac distribution), and is the nanotube density-ofstates (DOS). Thus, the total charge for each subband can be thought of as the sum of the charges contributed by the source and the drain, individually. Also, let us assume the source Fermi level as the reference level and, hence, and where q is the electronic charge.

31 3) Drain current for the first subband is obtained as (4) where for i=s,d(5) 4) The gate bias required to produce the assumed based on the electrostatic capacitance relations of the capacitance model is determined as where is the insulator capacitance. (6)

32 5) Finally, we obtain the gate potential required to produce the effective gate bias from (7) where is the flat-band voltage. Thus, we obtain a series of characteristics of the CNFETs. In order to obtain a simplified SPICE-compatible model for the CNFETs, we have used appropriate fitting functions and approximations that have been discussed in [10] and will be omitted in this paper. Fig. 3(a) shows the SPICE-compatible circuit schematic for the ballistic CNFET. The capacitors and and the current source are piecewise, nonlinear, and voltage-dependent. This model is valid for a wide range of nanotube diameters and operating conditions. [10] A. Raychowdhury, S. Mukhopadhyay, and K. Roy, Circuit compatible modeling of carbon nanotube FETs in the ballistic limit of performance, in Proc. 3rd IEEE Conf. Nanotechnology, vol. 1214, Aug. 2003, pp. 343346.

33 Fig. 3. (a) Schematic diagram of the SPICE model.

34 In a manner similar to [10], we derive the expressions for the capacitors as [10] A. Raychowdhury, S. Mukhopadhyay, and K. Roy, Circuit compatible modeling of carbon nanotube FETs in the ballistic limit of performance, in Proc. 3rd IEEE Conf. Nanotechnology, vol. 1214, Aug. 2003, pp. 343346

35 where i=s,d, L is the length of the nanotube,A,B, and are physical fitting parameters, and (9) is the carboncarbon (C-C) bonding energy ( 3 eV), is the C-C bonding distance ( 0.142 nm), is half of the bandgap of the CNFET, and is the surface potential. The current is given by (4).

36 Fig. 3 (b) characteristics of a 0.5-nm nanotube. The SPICE model and self-consistent numerical solutions show a very close match. Numerical device simulations in a manner described in 1)5) have been performed, and the results have been compared with the simulation results of the SPICE-compatible model. Fig. 3(b) show how the two models match in terms of the currentvoltage characteristics.

37 In the remainder of this paper, we have used the SPICEcompatible carbon-nanotube model for all circuit simulations in HSPICE. We have not included any parasitic capacitance or resistance of interconnects, and only the inherent device characteristic with the device capacitance has been used. Series resistances ( and ) represent metal resistances and have been neglected in the current analysis.

38 It is worthwhile to mention that the circuit realizations of the ternary logic family, to be described in the next section, involve dual- transistors. CNFETs provide an opportunity to obtain two distinct s by using two different tube diameters. Any other process technology that allows usage of two reliable threshold voltages can also be used for realizing the logic cells. For example, dual Si technology can be used. CNFETs provide a unique opportunity for control by changing the carbon-nanotube diameter. There is currently worldwide research going on to realize well-controlled carbon nanotubes [18]. Hence, in this paper, we have used a dual-diameter CNFET-based design for the ternary logic implementation. The high integration density is a great incentive to using CNFETs for the complex ternary gates to be described below. [18] Y. Li,W. Kim, Y. Zhang, M. Rolandi, D.Wang, and H. Dai, Growth of single-walled carbon nanotubes from discrete catalytic nanoparticles of various sizes, J. Phys. Chem., vol. 105, p. 11 424, 2001.

39 IV. CIRCUIT REALIZATION OF THE BASIC CELLS Here we have considered ternary logic style (r=3) and explored a novel circuit implementation of such a logic style. In this voltage-mode implementation, the supply voltage has been chosen to be 1.5 V. This ensures sufficient static noise margin (SNM) for all three levels of logic. Here, logic 0 would correspond to a voltage value less than V1 ( ~0.5 V), logic 1 would correspond to a voltage value between V1 and V2 ( ~1 V), and logic 2 would correspond to a voltage value greater than V2 (i.e., between 1 V and ).

40 A. Complement Operator Fig. 4(a) shows the circuit realization of the complement operation. It consists of two CNFET transistors with resistive pullups. One of the transistors (T1) has a diameter 1.4 nm and the other nanotube transistor (T2) has a diameter 0.5 nm. It can be noted that modern fabrication facilities have enabled successful growth of carbon nanotubes with diameters of 0.5 nm and even smaller [19], [20]. As a result, the two transistors have corresponding threshold voltages 300 mv and 840 mV, respectively. The resistors used in the circuit (R) are both 100 k. [19] L. F. Sun, S. S. Xie, W. Liu, W. Y. Zhou, Z. Q. Liu, D. S. Tangi, G. Wang, and L. X. Qian, Creating the narrowest carbon nanotubes, Nature Mater., vol. 403, pp. 384386, Jan. 2000. [20] N.Wang, Z. K. Tang, G. D. Li, and J. S. Chen, Single-walled 4carbon nanotube arrays, Nature Mater., vol. 408, pp. 50??, Nov. 2000.

41 Now consider the input voltage. For small values of, both of the transistors are off. Hence, the output node (OUT) is held at. As increases beyond (300 mV), T1 turns on. Hence, the output voltage is held approximately at until reaches. Once exceeds, the second transistor turns on and the output is pulled down to almost zero. Hence, the voltage at the output node can be written as Fig. 4(b) shows the dc transfer characteristics of the logic block. We obtain three stable states of the output, and it can be efficiently used to implement complementary logic.

42 Fig. 4. Complement operator. (a) Schematic and symbol. (b) Transfer characteristics.

43 B. tsum Operator Fig. 5(a) shows the circuit realization of a two-input tsum operator. The two inputs are IN1 and IN2, and the output is OUT=tsum(IN1,IN2). Let us consider an example to verify the operation of this implementation. Consider a situation where IN1 is held at zero at a logic value of 0. Hence, both of the transistors T1 and T2 are off. Now consider sweeping the voltage at node IN2 from zero to. As in the case of the complement logic block implementation, at first transistors T3 and T4 are off and the output of the logic tree (OUTZ) is held at. Consequently, the complement block output (OUT) goes to zero. Hence, it implements tsum(0,0)=0.

45 Without going into a detailed explanation of all of the different input combinations, it can be noted that this gate implements a fully voltage- mode tsum gate. However, it may be noted that the values of R1 and R2 need to be judiciously decided. In this circuit, when the input vectors (IN1, IN2) are (0, 1), or (1, 0), the output at OUTZ should be a logic 1 and for (1, 1) it should be logic 2. Hence, both of the following situations need to be satisfied:

47 Fig. 5. The tsum operator. (a) Schematic and symbol.

48 Fig. 5. (b) Transfer characteristics.

49 C. MIN Operator The circuit implementation of the min gate can be derived from a binary AND gate [see Fig. 6(a)]. The working principle of the min logic gate is similar to that described above for the other logic blocks. When any one of the two inputs IN1 and IN2 is held at a lowpotential, the pull down network is off, the output OUTZ is held at (logic 2), and OUT is at zero (logic 0). As in the tsum gate, the design of the pull-up resistors R1 and R needs attention. Consider the situations when the input vectors (IN1, IN2) are held at (1, 1), (2, 1) or (1, 2). In all three cases, the output OUTZ (and OUT) should be held at a logic value 1.

52 Fig. 6. MIN operator. (a) Schematic and symbol.

53 Fig. 6. MIN operator. (b) Transfer characteristic.

54 D. Cycle and Complement of the Cycle

56 (a) (b) Fig. 7. (a) and (b) Schematic diagrams of and respectively.

57 Fig. 7. (c) and (d) Transfer characteristics of and. (c) (d)

58 E. Literal Operator

61 Fig. 8. Literal operator. (a)(c) Schematic diagrams of 2[0 (a) 0]; 2[ 1(a)1 ], and 2[ 2(a)2 ] gates, respectively. (d)(f) Transfer characteristics of 2[ 0(a)0 ]; 2[ 1(a)1 ], and 2[ 2(a) 2].

62 V. TRANSIENT ANALYSIS AND COMPARISON WITH THE BINARY LOGIC FAMILY The ternary gates so developed have been used to simulate simple logic blocks. Multiplexers, half adders, and ripple carry full adders have been simulated and their electrical characteristics evaluated. Fig. 9 shows the transient response of a ternary full adder. Table IV gives the average delay, average power, and powerdelay product of a min gate, a tsum gate, and a full adder. In order to evaluate the usefulness of the proposed ternary logic family, it is important to understand how this logic family performs with respect to the binary logic family. We evaluated the performance of ripple carry adders using binary and ternary logic.

63 Fig. 9. Transient characteristics of a ternary ripple carry adder.

64 TABLE IV AVERAGE DELAY, POWER, AND POWERDELAY PRODUCT OF MIN, tsum, AND A FULL ADDER

65 [21] N. H. E. Weste and K. Estraghian, Principles of CMOS VLSI Design: A Systems Perspective. Reading, MA: Addison-Wesley, 1993. In binary logic, two popular circuit implementations are the complementary MOS and the pseudo-NFET logic styles [21]. While the complementary MOS has a distinct advantage in terms of extremely low static power dissipation, the pseudo- NFET logic, on the other hand, is much faster. In this paper, we have compared the delay, power, and powerdelay product of ripple carry adders using binary complementary logic, pseudo- NFET logic, and ternary logic. One of the main advantages in ternary logic comes from the fact that it reduces the number of computations required. Since each signal can assume three distinct values, the number of digits required in a ternary family is times less than that required in binary logic.

66 Thus, if we consider an N-bit binary adder, then the corresponding ternary adder will have digits. Here [x] represents the integer nearest to x and greater than x. Another important consideration is static nose margin (SNM) for the circuits. In order to achieve the same static noise margin for the binary adder as with the ternary adder, we run the ternary adder at a supply of 1.5 V while the binary adders are operated at 1.0 V. This ensures a noise margin of approximately 500 mV for each level of logic in both of the two logic families.

67 With these considerations, we have simulated binary and ternary adders for a wide range of random input vectors. Fig. 10 shows the delay, power, and powerdelay product of the binary and ternary adders. Some important observations are the following. 1) The ternary adder is faster than the binary adder but slower than the pseudo-NFET adder. The limiting factor for the speed of the ternary adders is the use of high resistive pull-ups. However, the relatively high complexity of the ternary gates makes them slower compared to the pseudo-NFET logic. One more thing to note is that the ternary adders require times less computation compared to the binary adders and, when the number of digits increases, the speed advantage over the complementary adders becomes more and more significant.

68 2) The pseudo-NFET adders consume sufficiently higher power than both the binary and the ternary logic families. 3) The powerdelay product of the ternary adder lies in between the binary and the pseudo-NFET logic styles. Thus, the proposed ternary logic is a moderately fast and lowpower solution to digital computation.

69 In the above comparison, as we have already mentioned, the supply voltages are 1 and 1.5 V for the binary and the ternary logic families in order to ensure iso-SNM. However, it will be of interest to note the performance of the same binary complementary adder when it is run at 1.5 V instead of 1 V. Doing so would increase its speed at the expense of higher power dissipation. The pseudo-NFET adder will not be of any added advantage as it will be still faster and still higher in power dissipation. Fig. 11 shows the delay, power, and powerdelay product when the binary complementary adder is run at 1.5 V. We can note that the binary adder becomes faster than the ternary adder but its power dissipation increases a great deal because of the polynomial dependence of switching power over the supply voltage. Thus, the powerdelay product of the 1.5-V complementary adder is more ( 22% on an average) than that of the proposed ternary adder.

70 Fig. 10. (a) Delay, (b) power, and (c) powerdelay product of the complementary binary, pseudo-NFET binary, and the ternary logic families. A1 ;... ;A7 represent seven adders with the number of binary digits (bits) =4, 8, 16, 32, 64, 128, and 256. The number of digits for the corresponding ternary adders is times the number of bits.

71 Fig. 11. (a) Delay, (b) power, and (c) powerdelay product of the complementary binary and the ternary logic families both running at 1.5 V of supply. A1;...;A7 represent seven adders with numbers of binary digits (bits) =4, 8, 16, 32, 64, 128, and 256. The number of digits for the corresponding ternary adders is times the number of bits.

72 In our discussion so far, we have considered nominal designs of the ternary gates. Let us consider variations in the values of the pull-up resistors in our design. If there is a resistor-to-resistor variation, the functionality of the gates would not fail unless (8) for tsum gates or (11) for MIN gates is violated. For the moment, let us consider the more general case of systematic variation of the pull of resistors where all of the resistors change from their nominal values by a constant ratio. If the pull-up resistors increase from their nominal value, then the charging time increases, thereby adversely affecting the delay of the gate. VI. EFFECT OF VARIATIONS AND FAN-OUT ON THE TERNARY GATES

73 If the resistor value decreases, then the standby power increases, thereby increasing the overall average power. The product of the power and the delay (PDP) provides a guideline for the design of the resistors. As an example, let us consider the complement gate which has two pull-up resistors R( 100 K). Fig. 12 shows how a maximum 20% change in the resistor value from its nominal value changes the delay and the average power dissipation of the gate. It can be seen that the nominal value of R has been chosen such that the average PDP is minimized. However, 20% changes in the value of R do not affect functionality of the ternary gates.

74 The same principle (i.e., minimizing PDP) has been adopted while designing all of the other ternary gates. It is worthwhile to note here that the interconnect resistances would not play a significant role in this case. The pull-up resistors are of the order of 100 k and the intrinsic channel resistance of the CNFET for one mode of conduction is (~13k). Typical interconnect resistances would be negligible in comparison. Normal random logic requires supporting fan-out in order to efficiently implement a set of logic functions. Fig. 13 illustrates how the delay of an inverter gate increases as the number of identical fan-outs increase. It can be seen that the ternary gates can drive fan-out loads with a delay penalty as in any binary logic gate.

75 Fig. 12. Variation of delay and PDP of a complementary operator with variation in the value of the pull-up resistor R.

76 Fig. 13. Delay variation of a complementary operator with the number of fan-outs.

77 This paper proposes a novel method for MVL design using CNFETs. It exploits the geometry-dependent threshold voltage of CNFETs and puts forward the use of dual-diameter CNFETs for realization of an MVL circuit. The novelty of this paper lies in the fact that a new voltage-mode ternary logic family has been developed, and its aptness in a CNFET based design has been presented. To the best of our knowledge, for the first time, we have introduced a technique for voltage-mode MVL implementation using carbon-nanotube transistors. VII. CONCLUSION

78 A complete set of operators has been implemented using multidiameter CNFETs. All simulations have been carried out in HSPICE using a circuit-compatible model of the carbon-nanotube transistors. The proposed logic family has been compared with respect to the binary logic family. Both complementary MOS and pseudo-NFET logic styles have been studied for the comparisons. Simulation results show that the proposed family of ternary logic is faster than the corresponding complementary binary logic. In terms of powerdelay product, the proposed family lies in between the binary complementary and the pseudo-NFET families.

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1/7. 2 Carbon-Nanotube-Based Voltage-Mode Multiple-Valued Logic Design Arijit Raychowdhury, Student Member, IEEE, and Kaushik Roy, Fellow, IEEE IEEE