16-BIT MICROCONTROLLER MB90650A Series HARDWARE … · i PREFACE Objectives and Intended Reader Thank you for purchasing Fujitsu semiconductor products. The MB90650A series is a 16-bit

FUJITSU SEMICONDUCTORCONTROLLER MANUAL

F2MC-16L16-BIT MICROCONTROLLER

MB90650A SeriesHARDWARE MANUAL

CM43-10110-3E

F2MC -16L16-BIT MICROCONTROLLER

MB90650A SeriesHARDWARE MANUAL

FUJITSU LIMITED

PREFACE

Objectives and Intended Reader

Thank you for purchasing Fujitsu semiconductor products.

The MB90650A series is a 16-bit microcontroller designed for use in applications in consumer-equipment requiring high-speed real-time processing, and has functions suited for control ofPHS devices, CD-ROMs, and VCRs.

This manual, intended for engineers who develop and design products using MB90650A seriesmicrocontrollers, describes the features and operation of the MB90650A series. Be sure to readthis manual before using this product.

Refer to the F2MC-16L Programming Manual for details of instructions.

Trademark

F2MC is the abbreviation of FUJITSU Flexible Microcontroller.

Other system and product names in this manual are trademarks of respective companies ororganizations.

The symbols ™ and ® are sometimes omitted in this manual.

i

Structure of This Manual

This manual has 25 chapters and appendixes:

CHAPTER 1 "OVERVIEW"

This chapter gives an overview of the MB90650A series.

CHAPTER 2 "CPU"

This chapter explains the CPU functions and their operation.

CHAPTER 3 "INTERRUPTS"

This chapter explains the interrupt functions and operation.

CHAPTER 4 "CLOCKS AND RESETS"

This chapter explains the clock and reset functions and their operation.

CHAPTER 5 "LOW POWER CONTROL CIRCUIT"

This chapter explains the functions and operation of the low power control circuit (CPUintermittent operation, oscillation stabilization wait interval, and clock multiplier).

CHAPTER 6 "LOW POWER MODE"

This chapter explains the functions and operation of low power mode for the MB90650Aseries.

CHAPTER 7 "MEMORY ACCESS MODE"

This chapter explains the functions and operation of the memory access mode.

CHAPTER 8 "I/O PORTS"

This chapter explains the functions of the I/O ports of the device.

CHAPTER 9 "TIMEBASE TIMER"

This chapter explains the functions and operation of the timebase timer.

CHAPTER 10 "WATCHDOG TIMER"

This chapter explains the functions and operation of the watchdog timer.

CHAPTER 11 "WATCH TIMER"

This chapter explains the functions and operation of the watch timer.

CHAPTER 12 "16-BIT I/O TIMER"

This chapter explains the functions and operation of the 16-bit I/O timer.

CHAPTER 13 "8/16-BIT PPG"

This chapter explains the functions and operation of the 8/16-bit PPG.

CHAPTER 14 "8/16-BIT UP/DOWN COUNTER/TIMER"

This chapter explains the functions and operation of the 8/16-bit up/down counter/timer.

CHAPTER 15 "DTP/EXTERNAL INTERRUPT"

This chapter explains the functions and operation of the DTP/external interrupt unit.

CHAPTER 16 "DELAYED INTERRUPT GENERATION MODULE"

This chapter explains the functions and operation of the delayed interrupt generationmodule.

CHAPTER 17 "A/D CONVERTER"

This chapter explains the functions and operation of the A/D converter.

ii

CHAPTER 18 "D/A CONVERTER"

This chapter explains the functions and operation of the D/A converter.

CHAPTER 19 "UART"

This chapter explains the functions and operation of the UART.

CHAPTER 20 "I/O EXTENDED SERIAL INTERFACE"

This chapter explains the functions and operation of the I/O extended serial interface.

CHAPTER 21 "I 2C INTERFACE"

This chapter explains the functions and operation of the I2C interface.

CHAPTER 22 "DTMF GENERATOR"

This chapter explains the functions and operation of the DTMF generator.

CHAPTER 23 "CLOCK MONITOR FUNCTION"

This chapter explains the functions and operation of the clock monitor.

CHAPTER 24 "2M-BIT FLASH MEMORY"

This chapter explains the functions and operation of the 2M-bit flash memory.

CHAPTER 25 "MB90F654A SERIAL PROGRAMMING CONNECTION EXAMPLES"

This chapter provides serial programming connection examples for the case when theAF200 Flash Microcomputer Programmer manufactured by Yokogawa Digital Computer isused.

APPENDIX

The appendixes provide I/O maps, instructions, and other information.

iii

©2001 FUJITSU LIMITED Printed in Japan

• The contents of this document are subject to change without notice. Customers are advised to consultwith FUJITSU sales representatives before ordering.

• The information and circuit diagrams in this document are presented as examples of semiconductordevice applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU isunable to assume responsibility for infringement of any patent rights or other rights of third partiesarising from the use of this information or circuit diagrams.

• The products described in this document are designed, and manufactured as contemplated for generaluse, including without limitation, ordinary industrial use, general office use, personal use, and householduse, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatalrisks or dangers that, unless extremely high safety is secured, could have a serious effect to the public,and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclearreaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medicallife support system, missile launch control in weapon system), or (2) for use requiring extremely highreliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damagesarising in connection with above-mentioned uses of the products.

• Any semiconductor devices have an inherent chance of failure. You must protect against injury,damage or loss from such failures by incorporating safety design measures into your facility andequipment such as redundancy, fire protection, and prevention of over-current levels and otherabnormal operating conditions.

• If any products described in this document represent goods or technologies subject to certainrestrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the priorauthorization by Japanese government will be required for export of those products from Japan.

iv

CONTENTS

CHAPTER 1 OVERVIEW ................................................................................................... 11.1 Features ................................................................................................................................................ 21.2 Models Available .................................................................................................................................... 51.3 Block Diagram ....................................................................................................................................... 61.4 Drawings Showing Package Dimensions .............................................................................................. 71.5 Pin Assignment ...................................................................................................................................... 91.6 Explanation of Pin Functions ............................................................................................................... 111.7 I/O Circuit Types .................................................................................................................................. 181.8 Notes on Device Handling ................................................................................................................... 211.9 OTPROM Programming ...................................................................................................................... 23

CHAPTER 2 CPU ............................................................................................................. 272.1 Memory Space ..................................................................................................................................... 282.2 Addressing ........................................................................................................................................... 302.3 Allocation of Multibyte Data in Memory ............................................................................................... 332.4 Dedicated Registers ............................................................................................................................ 35

2.4.1 Accumulator (A) .............................................................................................................................. 372.4.2 User Stack Pointer (USP) and System Stack Pointer (SSP) .......................................................... 392.4.3 Processor Status (PS) .................................................................................................................... 402.4.4 Program Counter (PC) .................................................................................................................... 432.4.5 Direct Page Register (DPR) ........................................................................................................... 442.4.6 Bank Registers ............................................................................................................................... 45

2.5 General-Purpose Registers ................................................................................................................. 462.6 Prefix Codes ........................................................................................................................................ 48

2.6.1 Restrictions on Prefix Codes .......................................................................................................... 512.7 Memory Map ........................................................................................................................................ 53

CHAPTER 3 INTERRUPTS .............................................................................................. 553.1 Overview of Interrupts .......................................................................................................................... 563.2 Interrupt Causes .................................................................................................................................. 573.3 Interrupt Vectors .................................................................................................................................. 593.4 Hardware Interrupts ............................................................................................................................. 613.5 Software Interrupts .............................................................................................................................. 633.6 Extended Intelligent I/O Service (EI2OS) ............................................................................................. 65

3.6.1 Interrupt Control Register (ICR) ...................................................................................................... 683.6.2 Extended Intelligent I/O Service Descriptor (ISD) .......................................................................... 713.6.3 Registers of Extended Intelligent I/O Service Descriptor (ISD) ...................................................... 723.6.4 Operation of Extended Intelligent I/O Service (EI2OS) ................................................................... 753.6.5 Procedure for Using the Extended Intelligent I/O Service (EI2OS) ................................................. 763.6.6 Processing Time for the Extended Intelligent I/O Service (EI2OS) ................................................. 77

3.7 Exception Processing Interrupts .......................................................................................................... 80

v

CHAPTER 4 CLOCKS AND RESETS ............................................................................. 814.1 Clock Generation Block ...................................................................................................................... 824.2 Clock Supply Map ............................................................................................................................... 834.3 Reset Causes ..................................................................................................................................... 844.4 Operation after a Reset is Cleared ..................................................................................................... 87

CHAPTER 5 LOW POWER CONTROL CIRCUIT ........................................................... 895.1 Overview of Low Power Control Circuit .............................................................................................. 905.2 Block Diagram of Low Power Control Circuit ...................................................................................... 925.3 Low Power Control Circuit Registers .................................................................................................. 93

5.3.1 Low Power Mode Control Register (LPMCR) ................................................................................ 945.3.2 Clock Selection Register (CKSCR) ................................................................................................ 96

5.4 Status Transitions for Clock Selection ................................................................................................ 98

CHAPTER 6 LOW POWER MODE ................................................................................ 1016.1 Low Power Mode .............................................................................................................................. 102

6.1.1 Sleep Mode .................................................................................................................................. 1056.1.2 Pseudo Watch Mode ................................................................................................................... 1066.1.3 Watch Mode ................................................................................................................................. 1076.1.4 Stop Mode ................................................................................................................................... 1086.1.5 CPU Intermittent Operation Function .......................................................................................... 1106.1.6 Main Clock Oscillation Stabilization Wait Interval Setting ............................................................ 1116.1.7 Machine Clock Switching ............................................................................................................. 112

6.2 Transition Conditions for Low Power Mode ...................................................................................... 1136.3 Status Transition Diagrams for Low Power Mode ............................................................................. 117

CHAPTER 7 MEMORY ACCESS MODE ....................................................................... 1237.1 Overview of Memory Access Mode .................................................................................................. 124

7.1.1 Mode Pins .................................................................................................................................... 1257.1.2 Mode Data ................................................................................................................................... 1267.1.3 Memory Space for Each Bus Mode ............................................................................................. 127

7.2 External Memory Access (External Bus Pin Control Circuit) ............................................................ 1307.2.1 External Memory Access (External Bus Pin Control Circuit) Registers ....................................... 1317.2.2 Automatic Ready Function Selection Register (ARSR) ............................................................... 1327.2.3 Higher Address Control Register (HACR) .................................................................................... 1347.2.4 Bus Control Signal Selection Register (ECSR) ........................................................................... 135

7.3 Operation of External Memory Access Control Signals .................................................................... 1387.3.1 Ready Function ............................................................................................................................ 1407.3.2 Hold Function ............................................................................................................................... 142

CHAPTER 8 I/O PORTS ................................................................................................ 1438.1 Overview of I/O Ports ........................................................................................................................ 1448.2 I/O Port Registers ............................................................................................................................. 145

8.2.1 Port Data Register (PDR) ............................................................................................................ 1468.2.2 Port Direction Register (DDR) ...................................................................................................... 1488.2.3 Output Pin Register (ODR) .......................................................................................................... 1508.2.4 Input Resistor Register (RDR) ..................................................................................................... 1518.2.5 Analog Input Enable Register (ADER) ......................................................................................... 153

vi

CHAPTER 9 TIMEBASE TIMER .................................................................................... 1559.1 Overview of Timebase Timer ............................................................................................................. 1569.2 Timebase Timer Control Register (TBTC) ......................................................................................... 1589.3 Operation of Timebase Timer ............................................................................................................ 160

CHAPTER 10 WATCHDOG TIMER ................................................................................. 16110.1 Overview of Watchdog Timer ............................................................................................................ 16210.2 Watchdog Timer Control Register (WDTC) ....................................................................................... 16410.3 Operation of Watchdog Timer ............................................................................................................ 166

CHAPTER 11 WATCH TIMER ......................................................................................... 16711.1 Overview of Watch Timer .................................................................................................................. 16811.2 Watch Timer Control Register (WTC) ................................................................................................ 17011.3 Operation of Watch Timer .................................................................................................................. 172

CHAPTER 12 16-BIT I/O TIMER ...................................................................................... 17312.1 Overview of 16-Bit I/O Timer ............................................................................................................. 17412.2 Block Diagram of 16-Bit I/O Timer ..................................................................................................... 17612.3 16-Bit I/O Timer Registers ................................................................................................................. 17712.4 16-Bit Free-Run Timer ....................................................................................................................... 179

12.4.1 Timer Counter Data Register (TCDT) ........................................................................................... 18012.4.2 Timer Counter Control Status Register (TCCS) ........................................................................... 181

12.5 Output Compare ................................................................................................................................ 18412.5.1 Output Compare Registers (OCCP0 to OCCP3) .......................................................................... 18612.5.2 Output Compare Control Status Registers (OCS0 to OCS3) ....................................................... 187

12.6 Input Capture ..................................................................................................................................... 19012.6.1 Input Capture Data Registers (IPCP0 and IPCP1) ....................................................................... 19212.6.2 Input Capture Control Status Register (ICS01) ............................................................................ 193

12.7 Operation of 16-Bit Free-Run Timer .................................................................................................. 19512.8 Operation of 16-Bit Output Compare ................................................................................................. 19712.9 Operation of 16-Bit Input Compare .................................................................................................... 200

CHAPTER 13 8/16-BIT PPG ............................................................................................ 20313.1 Overview of 8/16-Bit PPG .................................................................................................................. 20413.2 Block Diagram of 8/16-Bit PPG ......................................................................................................... 20513.3 8/16-Bit PPG Registers ...................................................................................................................... 207

13.3.1 PPG0 Operation Mode Control Register (PPGC0) ....................................................................... 20813.3.2 PPG1 Operation Mode Control Register (PPGC1) ....................................................................... 21013.3.3 PPG0/PPG1 Output Pin Control Register (PPGOE) .................................................................... 21313.3.4 Reload Registers (PRLL and PRLH) ............................................................................................ 215

13.4 Operation of 8/16-Bit PPG ................................................................................................................. 21613.4.1 8/16-Bit PPG Operation Modes .................................................................................................... 21713.4.2 8/16-Bit PPG Output Operation .................................................................................................... 21813.4.3 Selecting 8/16-Bit PPG Count Clock ............................................................................................ 22013.4.4 Controlling 8/16-Bit PPG Pulse Output on Pins ............................................................................ 22113.4.5 Write Timing for 8/16-Bit PPG Reload Registers .......................................................................... 22213.4.6 8/16-Bit PPG Interrupts ................................................................................................................ 22313.4.7 Initial Value for Each Hardware .................................................................................................... 224

vii

CHAPTER 14 8/16-BIT UP/DOWN COUNTER/TIMER ................................................... 22514.1 Outline of the 8/16-Bit Up/Down Counter/Timer ............................................................................... 22614.2 Block Diagrams of the 8/16-Bit Up/Down Counter/Timer .................................................................. 22814.3 Registers of the 8/16-Bit Up/Down Counter/Timer ............................................................................ 230

14.3.1 Up/Down Count Registers 0 and 1 (UDCR0 and UDCR1) .......................................................... 23114.3.2 Reload/Compare Registers 0 and 1 (RCR0 and RCR1) .............................................................. 23214.3.3 Counter Status Registers 0 and 1 (CSR0 and CSR1) ................................................................. 23314.3.4 Counter Control Register 0 Higher (CCRH0) ............................................................................... 23614.3.5 Counter Control Register 1 Higher (CCRH1) ............................................................................... 23814.3.6 Counter Control Registers 0 and 1 Lower (CCRL0 and CCRL1) ................................................. 240

14.4 Selecting Count Modes of the 8/16-Bit Up/Down Counter/Timer ...................................................... 24214.5 Reload and Compare Functions of the 8/16-Bit Up/Down Counter/Timer ........................................ 24514.6 Simultaneous Activation of the Reload and Compare Functions of the 8/16-Bit Up/Down

Counter/Timer .................................................................................................................................... 24714.7 Writing Data to the UDCR Register of the 8/16-Bit Up/Down Counter/Timer ................................... 249

CHAPTER 15 DTP/EXTERNAL INTERRUPT UNIT ........................................................ 25315.1 Outline of DTP/External Interrupt Unit .............................................................................................. 25415.2 DTP/External Interrupt Registers ...................................................................................................... 255

15.2.1 DTP/Interrupt Enable Register (ENIR) ......................................................................................... 25615.2.2 DTP/Interrupt Cause Register (EIRR) .......................................................................................... 25715.2.3 Request Level Setting Register (ELVR) ....................................................................................... 258

15.3 Operation of DTP/External Interrupt Unit .......................................................................................... 25915.4 Precautions on Using DTP/External Interrupt Units .......................................................................... 262

CHAPTER 16 DELAYED INTERRUPT GENERATION MODULE .................................. 26516.1 Outline of the Delayed Interrupt Generation Module ........................................................................ 26616.2 Operation of the Delayed Interrupt Generation Module .................................................................... 267

CHAPTER 17 A/D CONVERTER ..................................................................................... 26917.1 Outline of the A/D Converter ............................................................................................................. 27017.2 A/D Converter Registers ................................................................................................................... 272

17.2.1 Control Status Registers (ADCS1 and ADCS2) ........................................................................... 27317.2.2 Data Registers (ADCR1 and ADCR2) ......................................................................................... 278

17.3 A/D Converter Operation .................................................................................................................. 27917.3.1 Conversion Using I2OS ................................................................................................................ 28117.3.2 Example of Activation of I2OS in Single Mode ............................................................................. 28217.3.3 Example of I2OS Activation in Continuous Mode ......................................................................... 28417.3.4 Example of I2OS Activation in Stop Mode ................................................................................... 286

17.4 Notes on Using the A/D Converter .................................................................................................... 28817.5 Conversion Data Protection Function ............................................................................................... 289

CHAPTER 18 D/A CONVERTER ..................................................................................... 29118.1 Outline of the D/A Converter ............................................................................................................. 29218.2 D/A Converter Registers ................................................................................................................... 29418.3 D/A Converter Operation .................................................................................................................. 296

viii

CHAPTER 19 UART ......................................................................................................... 29719.1 Outline of the UART ........................................................................................................................... 29819.2 Block Diagram of the UART ............................................................................................................... 29919.3 UART Registers ................................................................................................................................. 300

19.3.1 Serial Mode Register (SMR) ......................................................................................................... 30119.3.2 Serial Control Register (SCR) ...................................................................................................... 30319.3.3 Serial Input Data Register (SIDR)/Serial Output Data Register (SODR) ...................................... 30619.3.4 Serial Status Register (SSR) ........................................................................................................ 30719.3.5 Communication Prescaler Control Register (CDCR) .................................................................... 310

19.4 UART Baud Rates ............................................................................................................................. 31219.5 UART Operation ................................................................................................................................ 315

19.5.1 Asynchronous Mode ..................................................................................................................... 31619.5.2 CLK Synchronous Mode ............................................................................................................... 317

19.6 UART Flags and Interrupt Generation Sources ................................................................................. 31919.6.1 Set Timings of UART Interrupts and Flags ................................................................................... 320

19.7 UART Application Example and Notes on Use .................................................................................. 323

CHAPTER 20 I/O EXTENDED SERIAL INTERFACE ...................................................... 32720.1 Outline of the I/O Extended Serial Interface ...................................................................................... 32820.2 I/O Extended Serial Interface Registers ............................................................................................ 329

20.2.1 Serial Mode Control Status Register (SMCS) .............................................................................. 33020.2.2 Serial Shift Data Register (SDR) .................................................................................................. 334

20.3 Operation of the I/O Extended Serial Interface .................................................................................. 33520.3.1 Shift Clocks ................................................................................................................................... 33620.3.2 Operation States of the I/O Extended Serial Interface ................................................................. 33720.3.3 Start/Stop Timing of Shift Operations ........................................................................................... 33920.3.4 Serial Data I/O Timing .................................................................................................................. 34220.3.5 I/O Extended Serial Interface Interrupt Functions ........................................................................ 343

CHAPTER 21 I2C INTERFACE ........................................................................................ 34521.1 Outline of the I2C Interface ................................................................................................................ 34621.2 I2C Block Diagram ............................................................................................................................. 34721.3 I2C Interface Registers ...................................................................................................................... 348

21.3.1 Bus Status Register (IBSR) .......................................................................................................... 34921.3.2 Bus Control Register (IBCR) ........................................................................................................ 35221.3.3 Clock Control Register (ICCR) ..................................................................................................... 35521.3.4 Address Register (IADR) .............................................................................................................. 35721.3.5 Data Register (IDAR) .................................................................................................................... 358

21.4 I2C Interface Operation ...................................................................................................................... 35921.4.1 I2C Interface Transfer Flow .......................................................................................................... 36121.4.2 I2C Interface Mode Transitions ..................................................................................................... 363

CHAPTER 22 DTMF GENERATOR ................................................................................. 36522.1 Outline of the DTMF Generator ......................................................................................................... 36622.2 DTMF Generator Registers ............................................................................................................... 367

22.2.1 DTMF Control Register (DTMC) ................................................................................................... 36822.2.2 DTMF Data Register (DTMD) ....................................................................................................... 370

22.3 DTMF Generator Operation ............................................................................................................... 371

ix

CHAPTER 23 CLOCK MONITOR FUNCTION ................................................................ 37323.1 Outline of the Clock Monitor Function ............................................................................................... 37423.2 Clock Output Allowed Register (CLKR) ............................................................................................ 375

CHAPTER 24 2M-BIT FLASH MEMORY ........................................................................ 37724.1 Outline of the 2M-Bit Flash Memory ................................................................................................. 37824.2 Sector Configuration of the 2M-Bit Flash Memory ............................................................................ 37924.3 Flash Memory Control Status Register (FMCS) ............................................................................... 38024.4 Activating the Flash Memory Automatic Algorithm ........................................................................... 38324.5 Confirming the Automatic Algorithm Execution Status ..................................................................... 384

24.5.1 Data Polling Flag (DQ7) ............................................................................................................... 38624.5.2 Toggle Bit Flag (DQ6) .................................................................................................................. 38824.5.3 Timing Limit Exceeded Flag (DQ5) .............................................................................................. 38924.5.4 Sector Erase Timer Flag (DQ3) ................................................................................................... 390

24.6 Detailed Explanation of Flash Memory Write/Erase ......................................................................... 39124.6.1 Flash Memory Read/Reset Status ............................................................................................... 39224.6.2 Flash Memory Data Write ............................................................................................................ 39324.6.3 Flash Memory Total Data Erase (Chip Erase) ............................................................................. 39524.6.4 Flash Memory Arbitrary Data Erase (Sector Erase) .................................................................... 39624.6.5 Flash Memory Sector Erase Temporary Stop .............................................................................. 39824.6.6 Flash Memory Sector Erase Restart ............................................................................................ 399

24.7 Flash Memory Program Example ..................................................................................................... 400

CHAPTER 25 MB90F654A SERIAL PROGRAMMING CONNECTION EXAMPLES ..... 40525.1 Basic Configuration of MB90F654A Serial Programming Connections ............................................ 40625.2 Serial Programming Connection Example (When the User’s Power Supply Is Used) ...................... 40825.3 Serial Programming Connection Example (When Power Is Supplied

From the Programmer Power Supply) ............................................................................................... 41025.4 Example of the Minimum Connection Configuration of the Flash Microcomputer Programmer

(When the User’s Power Supply Is Used).......................................................................................... 41225.5 Example of the Minimum Connection Configuration of the Flash Microcomputer Programmer

(When Power Is Supplied From the Programmer Power Supply)...................................................... 414

APPENDIX .......................................................................................................................... 417APPENDIX A I/O MAP ................................................................................................................................ 418APPENDIX B INTERRUPT VECTORS ...................................................................................................... 424APPENDIX C PIN STATES FOR EACH CPU STATE ............................................................................... 426APPENDIX D OUTLINE OF INSTRUCTIONS ............................................................................................ 429

D.1 Types of Instructions ...................................................................................................................... 430D.2 Addressing ..................................................................................................................................... 431D.3 Direct Addressing ........................................................................................................................... 433D.4 Indirect Addressing ......................................................................................................................... 440D.5 Execution Cycle Count ................................................................................................................... 447D.6 Effective Address Fields ................................................................................................................. 450D.7 How to Use the Instruction Tables ................................................................................................. 451D.8 F2MC-16L Instruction Tables ......................................................................................................... 454D.9 Instruction Maps ............................................................................................................................. 467

INDEX...................................................................................................................................489

x

CHAPTER 1 OVERVIEW

This chapter gives an overview of the MB90650A series.

1.1 "Features"

1.2 "Models Available"

1.3 "Block Diagram"

1.4 "Drawings Showing Package Dimensions"

1.5 "Pin Assignment"

1.6 "Explanation of Pin Functions"

1.7 "I/O Circuit Types"

1.8 "Notes on Device Handling"

1.9 "OTPROM Programming"

1

CHAPTER 1 OVERVIEW

1.1 Features

The MB90650A series is a 16-bit microcontroller designed for use in applications in consumer-equipment requiring high-speed real-time processing, and has functions suited for control of PHS devices, CD-ROMs, and VCRs.

Features

The instruction set of the MB90650A series uses the FMC series AT architecture and also hasadditional instructions for supporting a high-level language. The addressing mode has beenextended, the multiply/divide instructions have been enhanced, and the bit manipulationinstructions have been improved. The chip also has a 32-bit accumulator that enables

processing of long-word data. This series contains the I2CBUS interface that facilitatescommunication between equipment, and is suitable for car audio and VCR systems.

Minimum execution time: 62.5 ns/4 MHz source oscillation is multiplied by 4 (PLL clock multiplication system)

Maximum memory space: 16 MB

Instruction set optimized for controller applications

• Data types that can be handled: Bit, byte, word, and long word

• Standard addressing mode: 23 types

• Enhanced high-precision arithmetic operations by employing a 32-bit accumulator

Instruction set supporting a high-level language (C) and multitasking

• System stack pointer

• Instruction set symmetry and barrel shift instruction

Increased execution speed: 4-byte instruction queue

Powerful interrupt functions

• Programmable priority levels: 8

• External interrupt inputs: 8

Data transfer function

• Intelligent I/O service

• Up to 16 channels

• DTP request inputs: 8

Size of built-in ROM and ROM type

• EPROM: 128 KB

2

1.1 Features

• FLASH: 256 KB

• MASKROM: 64, 128, and 256 KB

Built-in RAM size: 3, 5, and 8 KB

General-purpose ports

• Up to 79 ports

• Input pull-up resistors: 24

• Output open drains that can be set: 8

• Output open drains: 4

A/D converter (RC successive approximation system): 8 channels

• Resolution: 10 bits

• Conversion time: 5.2 µs (minimum)

D/A converter: 2 channels

• Resolution: 8 bits

DTMF: 1 channel

I2C interface: 1 channel

UART: 1 channel

I/O extended serial interface: 2 channels

8/16-bit U/D counter: 1 channel (with 8-bit x 2-channel and 16-bit x 1- channel mode functions)

8/16-bit PPG: 1 channel (8-bit x 2-channel and 16-bit x 1-channel mode functions)

16-bit I/O timer: 1 channel

• 16-bit free-run timer x 1 channel

• 16-bit input capture x 2 channels

• 16-bit output compare x 4 channels

Built-in 2-system clock generator

3

CHAPTER 1 OVERVIEW

Timebase counter/watchdog timer: 18 bits

Low power mode

Sleep, stop, CPU intermittent operation mode, and pseudo watch mode

Package: LQFP-100/QFP100

CMOS technology

4

1.2 Models Available

1.2 Models Available

Table 1.2-1 "Models Available in the MB90650A Series" lists the models available in the MB90650A series. All models have the same functions; however, ROM and RAM sizes vary with the model.

Models Available

Purchase of FUJITSU Ltd. I2C components conveys a license under the Philips I2C Patent Right

to use these components in an I2C system, provided that the system conforms to the I2CStandard Specification as defined by Philips.

Note:

The MB90V650A can only be used on a single power supply. To use the component on a 2-system power supply (3 V and 5 V), contact the Engineering Department.

Table 1.2-1 Models Available in the MB90650A Series

MB90V650A MB90VP653A MB90652A MB90653A MB90654A MB90F654A

ROM size - OTPROM 128KByte

Mask ROM 64KByte

Mask ROM 128KByte

Mask ROM 256KByte

FLASH ROM 256KByte

RAM size 6kByte 5kByte 3kByte 5kByte 8kByte 8kByte

Development NOW NOW NOW NOW Scheduled development

Scheduled development

5

CHAPTER 1 OVERVIEW

1.3 Block Diagram

Figure 1.3-1 "Device Block Diagram" is a block diagram of the device.

Block Diagram of the Device

Figure 1.3-1 Device Block Diagram

F

F

M

C

UARTB

U

S

I2C interface

Clock control circuit

CPU F2MC16L series core

ROM

RAMInterrupt controller

8 + 8 PPG (output switch) x 1 channel

U/D counter 8bit x 2(16bit x 1)Communication

prescaler

Clock output control register

External interruptI/O extendedserial interface x 2 channels I/O timer

A/D converter (10 bits)

16-bit input capture x 2 channels16-bit output compare x 4 channels

16-bit free-run timer

D/A converter (8 bits)

DTMF generator

I/O port

General block diagram

P00 to 07 (8): With input pull-up resistor setting registerP10 to 17 (8): With input pull-up resistor setting registerP60 to 67 (8): With input pull-up resistor setting registerP40 to 46 (7): With open drain setting registerP47, P70 to 72 (4): Open drain

X0, X1RSTX

X0A, X1A

SIN0SOT0SCK0

SIN1, 2SOT1, 2SCK1, 2

AVCCVARH, LAVSSADTGAN0 to 7

DAO0, 1DVRHDVSS

PPG00, 01PPG10, 11

AIN0, 1BIN0, 1ZIN0, 1

CKOT

IRQ0 to 7

OUT0, 1OUT2, 3

IN0, 1

SCLSDA

DTMF2

2

8

6

8 8 8 8 8 8 8 5 7 8 3

P00

P07

P10

P17

P20

P27

P30

P37

P40

P47

P50

P57

P60

P67

P70

P74

P80

P86

P90

P97

PA0

PA2

16

6

1.4 Drawings Showing Package Dimensions

1.4 Drawings Showing Package Dimensions

Two types of package are provided for the MB90650A series.

Package Dimensions (FPT-100P-M05)

Figure 1.4-1 Dimensions of LQFP-100P

100-pin plastic LQFP Lead pitch 0.50 mm

Package width package length

14.0 14.0 mm

Lead shape Gullwing

Sealing method Plastic mold

Mounting height 1.70 mm MAX

Weight 0.65g

100-pin plastic LQFP(FPT-100P-M05)

(FPT-100P-M05)

C 2000 FUJITSU LIMITED F100007S-3c-5

14.00±0.10(.551±.004)SQ

16.00±0.20(.630±.008)SQ

1 25

26

51

76 50

75

100

0.50(.020) 0.20±0.05(.008±.002)

M0.08(.003)0.145±0.055

(.0057±.0022)

0.08(.003)

"A"

INDEX.059

+.008+0.201.50(Mounting height)

0.50±0.20(.020±.008)0.60±0.15

(.024±.006)

0.25(.010)

0.10±0.10(.004±.004)

Details of "A" part

(Stand off)

Dimensions in mm (inches).

Pins width and pins thickness include plating thickness.

7

CHAPTER 1 OVERVIEW

Package Dimensions (FPT-100P-M06)

Figure 1.4-2 Dimensions of QFP-100P

100-pin plastic QFP Lead pitch 0.65 mm

Package width package length

14.00 20.00 mm

Lead shape Gullwing

Sealing method Plastic mold

Mounting height 3.35 mm MAX

100-pin plastic QFP(FPT-100P-M06)

(FPT-100P-M06)

C 2001 FUJITSU LIMITED F100008S-c-4-4

1 30

31

50

5180

81

100

20.00±0.20(.787±.008)

23.90±0.40(.941±.016)

14.00±0.20(.551±.008)

17.90±0.40(.705±.016)

INDEX

0.65(.026) 0.32±0.05(.013±.002)

M0.13(.005)

"A"

0.17±0.06(.007±.002)

0.10(.004)

Details of "A" part

(.035±.006)0.88±0.15

(.031±.008)0.80±0.20

0.25(.010)3.00

+0.35

+.014.118

(Mounting height)

0.25±0.20(.010±.008)(Stand off)

Dimensions in mm (inches).

Note: Pins width and pins thickness include plating thickness.

8

1.5 Pin Assignment

1.5 Pin Assignment

Figures 1.5-1 and 1.5-2 show the pin assignment for the device.

Pin Assignment (FPT-100P-M05)

Figure 1.5-1 Pin Assignment of LQFP-100P

IRQ

7

IRQ

61 0 1 0

T1

T0

1 0 N1

N1

N1/

N0

N0

N0/ G1

G1

OT

G0

G0

K2

T2

N2

T3

Q5

Q4

Q3

Q2

OU

OU

IN IN ZI

BI

AI

ZI

BI

AI

PP

PP

CK

PP

PP

SC

SO

SI

OU

IR IR IR IR

TX

1/ 0/ 7/ 6/ 5/ 4/ 3/ 2/ 1/ 0/ 7/ 6/ 5/ 4/ 3/ 2/ 1/ 0/ 6/ 5/ 4/ 3/ 2/

RS

PA

PA

P9

P9

P9

P9

P9

P9

P9

P9

P6

P6

P6

P6

P6

P6

P6

P6

NC

P8

P8

P8

P8

P8

PA2/ OUT2 TESTX1A MD2X0A MD1Vss MD0

X0 P81/ IRQ1X1 P80/ IRQ0

Vcc P57/ AN7P00/ AD00 P56/ AN6P01/ AD01 P55/ AN5P02/ AD02 P54/ AN4P03/ AD03 VssP04/ AD04 P53/ AN3P05/ AD05 P52/ AN2P06/ AD06 P51/ AN1P07/ AD07 P50/ AN0P10/ AD08 AVssP11/ AD09 AVR-P12/ AD10 AVR+P13/ AD11 AVccP14/ AD12 P74/ DAO1P15/ AD13 P73/ DAO0P16/ AD14 DVSSP17/ AD15 DVRH

P20/ A16 P72P21/ A17 P71/ SCL

18

19

20

21

22

23

LE

DX

ss

LX

HX

RQ

KX

DY

LK

N0

T0

K0

N1

T1

c K1

TG

47

DA

A A A A A A A R VW

RW

R HH

A R CS

IS

OS

CS

IS

OV

cS

CA

D P S

22/

23/

24/

25/

26/

27/

30/

31/

2/ 3/ 34/

5/ 36/

37/

0/ 1/ 2/ 3/ 4/ 5/ 6/ 70/

P P P P P P P P

P3

P3 P

P3 P P

P4

P4

P4

P4

P4

P4

P4 P

Package code (molding) FPT-100P-M05

LQFP-100

Figure 1.5-1 Pin assignment of LQFP-100P

9

CHAPTER 1 OVERVIEW

Pin Assignment (FPT-100P-M06)

Figure 1.5-2 Pin Assignment of LQFP-100P

7 6

RQ

RQ

I I1 0 1 0

T2

T1

T0

1 0 N1

N1

N1

N0

N0

N0

G1

G1

OT

G0

G0

K2

T2

N2

T3

Q5

Q4

Q3

Q2

OU

OU

OU

IN IN ZI

BI

AI

ZI

BI

AI

PP

PP

CK

PP

PP

SC

SO

SI

OU

IR IR IR IR

A A 2 TX

1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 6 5 4 3 2 ST 2

X0

X1

PA

RS

PA

PA

P9

P9

P9

P9

P9

P9

P9

P9

P6

P6

P6

P6

P6

P6

P6

P6

NC

P8

P8

P8

P8

P8

TE

MD

Vss MD1X0 MD0X1 P81 IRQ1

Vcc P80 IRQ0P00 AD00 P57 AN7P01 AD01 P56 AN6P02 AD02 P55 AN5P03 AD03 P54 AN4P04 AD04 VssP05 AD05 P53 AN3P06 AD06 P52 AN2P07 AD07 P51 AN1P10 AD08 P50 AN0P11 AD09 AVssP12 AD10 AVRP13 AD11 AVRP14 AD12 AVccP15 AD13 P74 DAO1P16 AD14 P73 DAO0P17 AD15 DVSS

16

17

18

19

20

21

22

23

LE

DX

ss

LX

HX

RQ

KX

DY

LK

N0

T0

K0

N1

T1

c K1

TG

47

DA

CL

72

RH

A A A A A A A A A R VW

RW

R HH

A R CS

IS

OS

CS

IS

OV

cS

CA

D P S S PD

V

20

21

22

23

24

25

26

27

30

31

2 3 34

5 36

37

0 1 2 3 4 5 6 70

71

P P P P P P P P P P

P3

P3 P

P3 P P

P4

P4

P4

P4

P4

P4

P4 P P

QFP-100

Package code (molding) FPT-100P-M06

10

1.6 Explanation of Pin Functions


Tables 1.6-1 to 1.6-4 explain the pin functions.

Explanation of Pin Functions

Table 1.6-1 Explanation of Pin Functions

LQFP QFP Pin name Circuit Function

80 82 X0 A Oscillation pin

81 83 X1 A Oscillation pin

50 52 TEST C Test input pin. Always set this pin to constant H-level.

75 77 RSTX B Reset input pin

83 to 90 85 to 92 P00 to P07 D(STBC)

General-purpose I/O ports.The pull-up resistor setting register (RDR0) can be used to add the pull-up resistor (RD07-00 = 1) (D07-00 = 1: Disabled when output is set).

AD00 to AD07

In external bus mode, these pins function as the lower data input-output/lower address output (AD0 to 07) pins.

91 to 98 93 to 100

P10 to P17 D(STBC)

General-purpose I/O ports.The pull-up resistor setting register (RDR1) can be used to add the pull-up resistor (RD17-10 = 1) (D17-10 = 1: Disabled when output is set).

AD08 to AD15

When the external bus width is 16 bits, these pins function as the upper data input-output/middle address output (AD08 to AD15).

99 to 6 1 to 8 P20 to P27 *H

(STBC)

General-purpose I/O ports. In external bus mode, these pins function as the A16 to A23 pins if the corresponding bits of the HACR register are 0.

A16 to A23 In external bus mode, these pins function as the upper address output (P20 to P27) if the corresponding bits of the HACR register are 1.

7 9 P30 *H

(STBC)

General-purpose I/O port. In external bus mode, this pin functions as the ALE pin.

ALE This pin functions as the address fetch enable signal.

8 10 P31 *H

(STBC)

General-purpose I/O port. In external bus mode, this pin functions as the RDX pin.

RDX This pin functions as read strobe output (RDX).

11

CHAPTER 1 OVERVIEW

10 12 P32 *H

(STBC)

General-purpose I/O port. In external bus mode, this pin functions as the WRX pin if the WRE bit of the EPCR register is 1.

WRLX This pin functions as write strobe output for the lower portion of data (WRLX).

11 13 P33 *H

(STBC)

General-purpose I/O port. When the external bus width is 16 bits, this pin functions as the WRHX pin if the WRE bit of the EPCR register is 1.

WRHX This pin functions as write strobe output for the upper portion of data (WRHX).

12 14 P34 *H

(STBC)

General-purpose I/O port. In external bus mode, this pin functions as the HRQ pin if the HDE bit of the EPCR register is 1.

HRQ This pin functions as the hold request input (HRQ) pin.

13 15 P35 *H

(STBC)

General-purpose I/O port. In external bus mode, this pin functions as the HAKX pin if the HDE bit of the EPCR register is 1.

HAKX This pin functions as the hold acknowledge output (HAKX) pin.

14 16 P36 *H

(STBC)

General-purpose I/O port. In external bus mode, this pin functions as the RDY pin if the RYE bit of the EPCR register is 1.

RDY This pin functions as the external ready input (RDY) pin.

15 17 P37 *H

(STBC)

General-purpose I/O port. In external bus mode, this pin functions as the CLK pin if the CKE bit of the EPCR register is 1.

CLK This pin functions as the machine cycle clock output (CLK) pin.

16 18 P40 *G

(STBC)

General-purpose I/O port. The pin functions as the serial input (SIN0) when UART0 operates.The open drain control setting register (ODR4) causes this pin to become the open drain output port (OD40 = 1) (D40 = 0: Disabled when input is set).

SIN0 This pin functions as the UART0 serial input (SIN0).

17 19 P41 *F

(STBC)

General-purpose I/O port. If the SOE bit of the UMC register is 1, data from this pin is fetched as data of the SOTO pin.The open drain control setting register (ODR4) causes this pin to become the open drain output port (OD41 = 1) (D41 = 0: Disabled when input is set).

SOT0 This pin functions as the UART0 serial data output pin (SOT0).

Table 1.6-1 Explanation of Pin Functions (Continued)


12


18 20 P42 *G

(STBC)

General-purpose I/O port. If UART0 operates in external shift clock mode, data from this pin is fetched as clock input (SCK0). If the SOE bit of the UMC register is 1, data from this pin is fetched as data of the SCK0 pin.The open drain control setting register (ODR4) causes this pin to become the open drain output port (OD42 = 1) (D42 = 0: Disabled when input is set).

SCK0 This pin functions as the UART0 serial clock I/O pin (SCK0).

19 21 P43 *G

(STBC)

General-purpose I/O port. During extended I/O serial operation, the pin is used as serial input (SIN1). The open drain control setting register (ODR4) causes this pin to become the open drain output port (OD43 = 1) (D43 = 0: Disabled when input is set).

SIN1 This pin functions as serial input of extended I/O serial data.

20 22 P44 *F

(STBC)

General-purpose I/O port. If the SOE bit of the UMC register is 1, this pin functions as the SOT1 pin.The open drain control setting register (ODR4) causes this pin to become the open drain output port (OD44 = 1) (D44 = 0: Disabled when input is set).

SOT1 This pin functions as the extended I/O serial data output pin (SOT1).

22 24 P45 *G

(STBC)

General-purpose I/O port. If extended I/O serial operates in the extended shift clock mode, the data from this pin is fetched as clock input (SCK1). If the SOE bit of the UMC register is 1, data from this pin is fetched as data of the SCK1 pin.

SCK1 This pin functions as the extended I/O serial clock I/O pin (SCK1).

23 25 P46 *G

(STBC)

General-purpose I/O port.The open drain control setting register (ODR4) causes this pin to become the open drain output port (OD46 = 1) (D46 = 0: Disabled when input is set).

ADTG This pin functions as the external trigger input pin for the A/D converter.

24 26 P47 *J

(NMOS/H)

Open drain I/O port (STBC)

36 to 3941 to 44

38 to 4143 to 46

P50 to P57 K(STBC)

General-purpose I/O ports

AN0 to AN7 When the A/D converter operates, the data from these pins is fetched as analog input (AN0 to AN7).



13

CHAPTER 1 OVERVIEW

25 27 P70 *J

(NMOS/H) (STBC)

Open drain I/O port

SDA Data I/O pin for I2C interface. This function is enabled if operation of the I2C interface is enabled. While the I2C interface is operating, set the port output to Hi-Z (PDR = 1).

26 28 P71 *J

(NMOS/H) (STBC)

Open drain I/O port

SDA Clock I/O pin for I2C interface. This function is enabled if operation of the I2C interface is enabled. While the I2C interface is operating, set the port output to Hi-Z (PDR = 1).

27 29 P72 *J

Open drain I/O port (STBC)

30 32 P73 L(STBC)

General-purpose I/O port. If the DAE0 bit of the D/A control register (DACR) is 1, this pin becomes the D/A output pin.

DAO0 When the D/A converter operates, this pin becomes the D/A output 0 pin.

31 33 P74 L(STBC)

General-purpose I/O port. If the DAE1 bit of the D/A control register (DACR) is 1, this pin becomes the D/A output pin.

DAO1 When the D/A converter operates, this pin becomes the D/A output 1 pin.

45 47 P80 I General-purpose I/O ports

IRQ0 Data on the pin is fetched as external interrupt request input-output 0.













14


55 57 P86 H General-purpose I/O port. This function is always enabled (STBC).

OUT3 Output compare channel 3 event output

56 58 DTMF M DTMF output pin

57 59 P60 E(STBC)

General-purpose I/O port. The pull-up resistor setting register (RDR6) can be used to add the pull-up resistor (RD60 = 1) (D60 = 1: Disabled when output is set).

SIN2 This pin becomes the extended I/O serial data input pin (SIN2).

58 60 P61 D(STBC)

General-purpose I/O port. If the SOE bit of the UMC register is 1, this pin functions as the SOT1 pin. The pull-up resistor setting register (RDR6) can be used to add the pull-up resistor (RD61 = 1) (D61 = 1: Disabled when output is set.)

SOT2 This pin functions as the extended I/O serial data output pin (SOT2).

59 61 P62 E(STBC)

General-purpose I/O port. If extended I/O serial functions in external shift clock mode, the data from this pin is fetched as clock input (SCK2). If the SOE bit of the UMC register is 1, data from this pin is used as data of the SCK1 pin. The pull-up resistor setting register (RDR6) can be used to add the pull-up resistor (RD62 = 1) (D62 = 1: Disabled when output is set).

SCK2 This pin functions as the extended I/O serial clock I/O pin (SCK2).

60 62 P63 D(STBC)


PPG00 When PPG output is enabled, this pin functions as PPG00 output.

61 63 P64 D(STBC)



62 64 P65 D(STBC)


CKOT When CKOT operates, this pin functions as CKOT output.



15

CHAPTER 1 OVERVIEW

63 65 P66 D(STBC)



64 66 P67 D(STBC)



65 67 P90 I General-purpose I/O port

AIN0 Data from this pin is fetched as 8/16-bit up/down timer channel 0 input.

IRQ6 Data from this pin is fetched as interrupt request input.

66 68 P91 I(STBC)

General-purpose I/O port

BIN0 Data from this pin is fetched as 8/16-bit up/down timer channel 0 input.

67 69 P92 I(STBC)


ZIN0 Data from this pin is fetched as 8/16-bit up/down timer channel 0 input.

68 70 P93 I General-purpose I/O port

AIN1 Data from this pin is fetched as 8/16-bit up/down timer channel 1 input.

IRQ7 Data from this pin is fetched as interrupt request input.

69 71 P94 I(STBC)


BIN1 Data from this pin is fetched as 8/16-bit up/down timer channel 1 input.

70 72 P95 I(STBC)


ZIN1 Data from this pin is fetched as 8/16-bit up/down timer channel 1 input.

71 73 P96 I(STBC)


IN0 Data from this pin is fetched as input capture channel 0 trigger input.

72 74 P97 I(STBC)


IN1 Date from this pin is fetched as input capture channel 1 trigger input.



16


73 75 PA0 H(STBC)



74 76 PA1 H(STBC)



76 77 PA2 H(STBC)



77 79 X0A A 32 MHz oscillation input pin

78 80 X1A A 32 MHz oscillation input pin

32 34 AVCC - Power supply pin for A/D converter

35 37 AVSS - Power supply pin for A/D converter

33 35 AVRH - External reference power supply pin for A/D converter

34 36 AVRL - External reference power supply pin for A/D converter

28 30 DVRH - External reference power supply pin for D/A converter

29 31 DVSS - Power supply pin for D/A converter

47 to 49 49 to 51 MD0 to MD2 C Input pin for specifying the operation mode. Connect this pin directly to VCC or VSS.

82 84 VCC1 - Power supply (3 V) input pin

21 23 VCC2 - Power supply (3 V/5 V) input pin (for P20-P47 and P70-P72 power supply)

9, 40, 79 11, 42, 81

VSS - Power supply (0 V) input pin

* : VSS 2 5 V systemSTBC: With standby control



17

CHAPTER 1 OVERVIEW

1.7 I/O Circuit Types

Table 1.7-1 "I/O Circuit Types" lists the I/O circuit types.

I/O Circuit Types

Table 1.7-1 I/O Circuit Types

Type Circuit Remarks

A • Oscillation feedback resistor: About 1 MΩ (High-speed oscillation

• Oscillation feedback resistor: About 10 MΩ (Low-speed oscillation

B • Hysteresis input with pull-upResistor: About 50 kΩ

C • Hysteresis input port

D • Input with pull-up resistor control• CMOS level I/O

Resistor: About 50 kΩ

X1, X1A

X0, X0A

Standby control signal

HYS

HYS

CTL

CMOS

18

1.7 I/O Circuit Types

E • Input with pull-up resistor control• CMOS level output• Hysteresis input

Resistor: About 50 kΩ

F • Input with pull-up resistor control• With open-drain control• With open-drain control

G • Input with pull-up resistor control• Hysteresis input• With open-drain control

H • Input with pull-up resistor control

I • CMOS level output• Hysteresis input

Table 1.7-1 I/O Circuit Types (Continued)


CTL

HYS

Open drain control signal

CMOS

Open drain control signal

HYS

CMOS

HYS

19

CHAPTER 1 OVERVIEW

J • Hysteresis input• N-ch open-drain output

K • CMOS level I/O • Analog input

L • CMOS level I/O • Analog output• Also served as DA output.

M • DTMF analog output

Table 1.7-1 I/O Circuit Types (Continued)


Digital output

HYS

CMOS

Analog input

DA output

CMOS

OPAMP

20

1.8 Notes on Device Handling

1.8 Notes on Device Handling

This section provides notes on device handling that must be observed to prevent latch-up and malfunctions.

Notes on Device Handling

Latch-up prevention and power-on

A CMOS IC may latch up for the following reasons:

• If a voltage higher than VCC or lower than VSS is applied to an input or output pin

• If a voltage exceeding the rating is applied between VCC and VSS

• If power is supplied to AVCC before a voltage is applied to VCC

• If a voltage (DVSS) higher than a voltage (AVSS) is applied (be sure that DVSS = AVSS.)

Always turn on the power to analog circuits at the same time as turning on power to VCC or afterturning on the power to digital circuits (Turn off the power after or at the same time that thepower to analog circuits is turned off.)

If a latch-up occurs, the power-supply current may increase rapidly, resulting in thermal damageto the elements. Make sure that devices do not latch up.

Treatment of unused pins

If an unused pin is left open, the device may malfunction. To avoid this, pull the pin up or down.

Notes on using external clock

To use an external clock, drive both X0 and X1 pins with opposite phases.

Figure 1.8-1 "Using an External Clock" shows how to use an external clock.

Figure 1.8-1 Using an External Clock

Handling of power-supply pins (V CC and VSS)

If there are several VCC and VSS pins, the device is designed to have pins of the same potentialconnected within the device to prevent such behavior as latch-up. However, be sure to connectall pins to an external power supply or ground to reduce unnecessary radiation, to prevent a risein the ground level from causing strobe signals to malfunction, and to satisfy the total outputcurrent standard. The current source should be connected to the VCC and VSS pins of thisdevice with minimum impedance.

We also recommend connecting a capacitor of about 0.1 µF close to the device between VCCand VSS as a bypass capacitor.

MB90650A Series

X0

X1

21

CHAPTER 1 OVERVIEW

Crystal oscillator

Noise near the X0 or X1 pin or the X0A or X1A pin may cause the device to malfunction. A PCboard should be designed so that the X0 and X1 pins, X0A and X1A pins, crystal oscillator (orceramic oscillator), and bypass capacitor to the ground are placed as close to one another aspossible. Moreover, ensure as far as possible that the wiring connecting them does notintersect other wiring. Using a PC board artwork to surround the X0 and X1 pins and X0A andX1A pins with ground potential is strongly recommended in the interest of stable operation canbe expected.

Initialization by power-on reset

The device contains internal registers that can only be initialized by power-on reset. To initializethese registers, turn off the power and then turn it on again to perform a power-on reset.

2-power supply system

The MB90650A series usually uses the 3 V power supply as the main power supply. However,P20 to P27, P30 to P37, P40 to P47, and P70 to 72 can be interfaced as a 5 V power systemseparately from the main 3 V power supply by setting VCC1 = 3V and VCC2 = 5 V. Note thatonly a 3V power supply can be used for the analog power supply (A/D and D/A).

If subclock mode is not used

Even if subclock mode is not used, connect an oscillator to the X0A and X1A pins.

22

1.9 OTPROM Programming


The MB90P653AOTPROM functions are equivalent to the MBM27C1000A functions in EPROM mode. A dedicated adapter socket enables data writing with the general-purpose EPROM programmer.However, the MB90P653AOTPROM does not support the electronic signature (device identification code) mode.

OTPROM Programming

Dedicated adapter socket

Programming procedure

• Set the EPROM programmer to MBM27C1000A.

Load program data to EPROM programmer address*1 to 1FFFFh. (The ROM addresses in

operation mode, address*2 to FFFFFFh, correspond to address*1 to 1FFFh in EPROMprogramming mode.)

To specify option data, load data to the addresses specified under "(6) bit map of the PROMoption."

Package name Compatible adapter Manufacturer

LQFP-100 ROM-100SQF-32DP-16L Sanhayato Corporation

QFP-100 ROM-100QF-32DP-16L

23

CHAPTER 1 OVERVIEW

Memory space configuration in EPROM mode is as follows.

The PROM mirror area of bank 00 becomes 48 KB (mirror area of FF4000h to FFFFFFh).

• Set the adapter socket to MB90P653A and then mount the adapter socket on the EPROMprogrammer. Ensure that the device and adapter socket have the correct orientation.

• Perform programming.

Note:

• Because the mask ROM product (MB90653A) does not have EPROM mode, data cannot beread with the EPROM programmer.

• To purchase the EPROM programmer, contact our sales department.

Program mode

In MB90P653A, all bits are set to 1 at shipment from Fujitsu or after erasure. To enterinformation, set only the bits that are to be modified to 0. A value of 1 cannot be electricallywritten.

PROM

PROM

FFFFFFh

FE0000h

010000h

004000h

000000h

1FFFFFh

00000h

PROM

Normal operation mode EPROM mode

Mirror

Model Address* 1 Address* 2 Number of bytes

MB90P653A 00000h FE0000h 128Kbyte

24


Recommended screening conditions

As pre-assembly screening procedure for products that do not have an OTPROMmicrocomputer program, we recommend high-temperature aging.

Programming yield

Due to the nature of the device, we cannot test all bits in order to identify products withoutOTPROM microcomputer program prior to shipment. We can therefore not guarantee aprogramming yield of 100%.

Program and verification

High-temperature aging+150 C, 48H

Read

Assembly

25

CHAPTER 1 OVERVIEW

26

CHAPTER 2 CPU

This chapter explains the CPU functions and their operation.

2.1 "Memory Space"

2.2 "Addressing"

2.3 "Allocation of Multibyte Data in Memory"

2.4 "Dedicated Registers"

2.5 "General-Purpose Registers"

2.6 "Prefix Codes"

2.7 "Memory Map"

27

CHAPTER 2 CPU

2.1 Memory Space

The F2MC-16L CPU core is a 16-bit CPU designed for use in applications requiring high-speed real-time processing, such as in consumer equipment and on-board

products. The F 2MC-16L instruction set, designed for use in controller applications, enables fast and highly efficient control.

The F2MC-16L contains a 32-bit accumulator that enables 16-bit data as well as 32-bit data to be processed (some of the instructions can also process 32-bit data). The device has a memory space of up to 16 MB (expandable) and can be accessed using the linear pointer or bank addressing method. The instruction set has been enhanced by adding instructions supporting a high-level language, extending the addressing mode, making the multiply/divide instructions more powerful, and improving the bit

manipulation instructions based on the F 2MC-8L AT architecture. This section

describes the features of the F 2MC-16L CPU.

Features of the CPU

Minimum execution time: 62.5 ns (4 MHz oscillation / multiplied by 4)

Maximum memory space: 16 MB: Accessed by linear or bank addressing.

Instruction set optimized for controller applications

Support of various data types: Bit, byte, word, and long word

Extended address modes: 23

Enhanced high-precision arithmetic operations (for 32 bit data) by 32-bit accumulator

Powerful interrupt function

Priority levels: 8 levels (programmable)

CPU-independent automatic data transfer function

Extended intelligent I/O service: Up to 16 channels

Instruction set supporting a high level language (C) and multitasking

System stack pointer, instruction set symmetry, and barrel shift instruction

Increased execution speed: 4-byte instruction queue

28

2.1 Memory Space

Memory Space

All data, programs, and I/O related items managed by the F2MC-16L CPU are allocated in the

16-MB memory space of the F2MC-16L CPU. The CPU is able to access the resources byusing the 24-bit address bus to access these addresses.

Figure 2.1-1 Sample of the Relationship between the F 2MC-16L System and the Memory Map

FFFFFFH

FF0000H

F2 MC-16L 810000H

CPU800000H

0000C0H

0000B0H

000020H

000000H[Device]

Program

Data

Interrupt

Peripheral circuitGeneral-

purpose port

(For 128 KB)

Program area

Data area

Interrupt controller

Peripheral circuitGeneral-purpose port

29

CHAPTER 2 CPU

2.2 Addressing

The following two addressing methods are available for the F 2MC-16L:• Linear addressing: All 24-bit addresses can be specified by instructions.• Bank addressing: The upper 8 bits of the address are specified by a bank register

for the processing objective, and the lower 16 bits of the address are specified by the instruction.

Linear Addressing

The following two linear addressing methods are available:

• 24-bit operand specification: A 24-bit address is directly specified in the operand.

• Indirect specification with a 32-bit register: The lower 24 bits of a 32-bit general-purposeregister are specified as an address.

Figure 2.2-1 Example of Specification of a 24-bit Operand in Linear Addressing

Figure 2.2-2 Example of Indirect Specification with a 32-bit Register in Linear Addressing

JMPP 123456H

17452DH17 452D JMPP 123456H

123456H

12 3456

Values of old program counter + program bank

Values of new program counter + program bank

Next instruction

MOV A,@RL1+7

XXXX 090700H 3A

RL1 240906F9

003A

+7

Old AL

New AL

(Upper 8 bits are ignored.)

30

2.2 Addressing

Bank Addressing

In bank addressing, the 16 MB memory space is divided into 256 64-KB banks. The bank thatcorresponds to each of these memory spaces is specified in the following five bank registers:

Program bank register (PCB): Initial value: FF H at reset

The 64-KB bank specified in the PCB is called the program (PC) space. Instruction codes,vector tables, and immediate data are mainly stored in this space.

Data bank register (DTB): Initial value: 00 H at reset

The 64-KB bank specified in the DTB is called the data (DT) space. The control and dataregisters for readable and writable data items and internal and external peripherals are mainlystored in this space.

User stack bank register (USB): Initial value: 00 H at reset

System stack bank register (SSB): Initial value: 00 H at reset

The 64-KB bank specified in the USB or SSB is called the stack (SP) space. This space isaccessed for stack accesses by push or pop instructions or to save interrupt registers. Whetherthe USB or SSB is used depends on the S flag value in the condition code register.

Additional bank register (ADB): Initial value: 00 H at reset

The 64-KB bank specified in the ADB is called the additional (AD) space. Data that did not fit inthe DT space is mainly stored in this space.

To improve the efficiency of instruction codes, each instruction has the following defined defaultspace for each addressing method. To use a space other than the default space, include aprefix code identifying a bank before the instruction. This enables accesses to the bank spacethat corresponds to the specified prefix code.

The DTB, USB, SSB, and ADB are initialized to 00H at a reset, and the PCB is initialized to thevalue specified by the reset vector. After the reset, DT, SP, and AD spaces are allocated inbank 00H (000000H to 00FFFFH), and the PC space is allocated in the bank specified by thereset vector.

Table 2.2-1 Default Spaces

Default space Addressing

Program space PC indirect, program access, branching

Data space Addressing using @RW0, @RW1, @RW4, and @RW5, @A, addr16, dir

Stack space

Addressing using PUSHW, POPW, @RW3, and @RW7

Additional space Addressing using @RW2 and @RW6

31

CHAPTER 2 CPU

Figure 2.2-3 Example of Bank Addressing of Each Space

FFFFFFH

FF0000H FFH :

B3FFFFH

B30000H B3H :

92FFFFH

920000H 92H :

68FFFFH

680000H 68H :

4BFFFFH

4B0000H 4BH :

000000H

Phy

sica

l add

ress

(For 128 KB)

(For 128 KB)

Program space

Additional space

User stack space

Data space

System stack space

Program bank register (PCB)

Additional bank register (ADB)

User stack bank register (USB)

Data bank register (DTB)

System stack bank register (SSB)

32

2.3 Allocation of Multibyte Data in Memory

2.3 Allocation of Multibyte Data in Memory

Multibyte data is written to memory space sequentially in ascending order of addresses. For 32-bit data, first the lower 16 bits are transferred, followed by the upper 16 bits.If a reset signal is input immediately after the low-order section of the data was written, the high-order section of the data may not be written. Retaining data correctly requires that a reset signal be input after the high-order section of the data has been written.

Allocation of Multibyte Data in Memory Space

As shown in Figure 2.3-1 "Sample Location of Multibyte Data in Memory Space", the lower 8bits of multibyte data are located at address n, and subsequent data is located at address n + 1,address n + 2, address n + 3, and so on, in the memory space in this sequence.

Figure 2.3-1 Sample Location of Multibyte Data in Memory Space

Multibyte data is written to memory sequentially in ascending order of addresses. In case of 32-bit data, first the lower 16 bits are transferred, then the upper 16 bits.

If a reset signal is input immediately after the low-order section of the data is written, the high-order section of the data may not be written.

MSB LSBH 01010101 11001100 11111111 00010100

01010101

11001100

11111111

00010100

L

Address n

33

CHAPTER 2 CPU

Multibyte Data Access

As shown in Figure 2.3-2 "Sample Access of Multibyte Data (Executing MOVWA, 080FFFFH)",all data accesses are generally made within a bank. For an instruction that accesses multibytedata, the address following FFFFH is 0000H in the same bank.

Figure 2.3-2 Sample Access of Multibyte Data (Executing MOVWA, 080FFFF H)

H

?? ??

8 0 FFFFH 01H

23H 01H

800000H 23H

L

AL before execution

AL after execution

34

2.4 Dedicated Registers


F2MC-16L registers can be classified into dedicated registers, which are located in the CPU, and general-purpose registers, which are located in memory. Dedicated registers are implemented in dedicated hardware whose use is restricted by the CPU architecture. General-purpose registers exist together with system RAM in the CPU address space. In the same way as dedicated registers, general-purpose registers can be accessed without specifying an address. In the same way as for ordinary memory, the user can specify for what purpose the register is to be used.

Dedicated Registers

The following 11 types of F2MC-16L dedicated register are available:

Accumulator (A = AH:AL)

Accumulator consisting of two 16-bit registers (The two registers can also be used as a 32-bitaccumulator.)

User stack pointer (USP)

16-bit pointer that points to the user stack area

System stack pointer (SSP)

16-bit pointer that points to the system stack area

Processor status (PS)

16-bit register that indicates the system status

Program counter (PC)

16-bit register that has the address containing the program

Program bank register (PCB)

8-bit register that indicates the program (PC) space

Data bank register (DTB)

8-bit register that indicates the data (DT) space

User stack bank register (USB)

8-bit register that indicates the user stack space

System stack bank register (SSB)

8-bit register that indicates the system stack space

Additional bank register (ADB)

8-bit register that indicates the additional (AD) space

35

CHAPTER 2 CPU

Direct page register (DPR)

8-bit register that indicates a direct page

Figure 2.4-1 Dedicated Registers

AH AL

USP

SSP

PS

PC

DPR

PCB

DTB

USB

SSB

ADB

8bit16bit

32bit

Accumulator

User stack pointer

System stack pointer

Processor status

Program counter

Direct page register

Program bank register

Data bank register

User stack bank register

System stack bank register

Additional data bank register

36


2.4.1 Accumulator (A)

The accumulator (A) consists of two 16-bit arithmetic operation registers (AH and AL). The accumulator is used to temporarily store the results of an arithmetic operation and for data transfer. For 32-bit data processing, the AH register and AL register are combined. For word processing of 16-bit data and byte processing of 8-bit data, only the AL register is used.

Accumulator (A)

A variety of arithmetic operations can be performed on data in the accumulator (A) with data in

memory and registers (Ri, RWi, and RLi). As with the F2MC-8, in F2MC-16L, when data of wordlength or less is transferred to the AL register, pre-transfer data is also automatically transferredfrom the AL register to the AH (data retention function). The data retention function andarithmetic operations between the AL register and the AH register increase processingefficiency.

When data of byte length or less is transferred to the AL register, data is extended to 16 bits bysign extension or zero extension, and is stored in the AL register. Data in the AL register can behandled as word-length or byte-length data.

When an arithmetic operation instruction for byte-processing is executed on the contents of theAL register, the system ignores the upper 8 bits of the AL register. The upper 8 bits of thearithmetic operation results become all zeros.

The accumulator (A) is not initialized by a reset, and its initial value immediately after a reset isundefined.

Figure 2.4-2 Example of 32-bit Data Transfer

MOVL A,@RW1+6

MSB LSB

XXXXH XXXXH A61540H 8FH 74H

A6153EH 2BH 52HDTB A6H +6

8F74H 2B52H RW1 15H 38H

AH AL

(Instruction that performs a long-word read operation using the address obtained by adding an 8-bit offset to the contents of RW1. The read value is stored in the accumulator (A).)

A before execution

A after execution

Memory space

37

CHAPTER 2 CPU

Figure 2.4-3 Example of AL-AH Transfer

MOVW A,@RW1+6

MSB LSB

XXXXH 1234H A61540H 8FH 74H

A6153EH 2BH 52HDTB A6H

+6

1234H 2B52H RW1 15H 38H

AH AL

(Instruction that performs a word-length read using the result of the RW1 contents + an 8-bit offset as the address and stores the read value in the accumulator (A))

A before execution

A after execution

Memory space

38


2.4.2 User Stack Pointer (USP) and System Stack Pointer (SSP)

The user stack pointer (USP) and system stack pointer (SSP) are 16-bit registers that indicate the memory addresses to which data is saved and from which data is returned when push and pop instructions or subroutines are executed.

User Stack Pointer (USP) and System Stack Pointer (SSP)

The user stack pointer (USP) and system stack pointer (SSP) are used by stack instructions.When the S flag in the processor status register is 0, the USP register can be used. When theS flag is 1, the SSP register can be used (see Figure 2.4-4 "Stack Operation Instruction andStack Pointer (Example of PUSHW A if the S Flag is 0)" and Figure 2.4-5 "Stack OperationInstruction and Stack Pointer (Example of PUSHW A if the S Flag is 1)").

Since the S flag is set to 1 when an interrupt is accepted, register data is always saved to thememory location indicated by the SSP at an interrupt. The SSP is used for interrupt routinestack operations, and the USP is used for all other types of stack operation. When separationof the stack space is not necessary, use only the SSP. The upper 8 bits of the address that willbe used for the stack operation are indicated in the sequence SSP --> SSB and USP --> USB.The initial value of the USP register and that of the SSP register are undefined after a reset.

Figure 2.4-4 Stack Operation Instruction and Stack Pointer (Example of PUSHW A if the S Flag is 0)

Figure 2.4-5 Stack Operation Instruction and Stack Pointer (Example of PUSHW A if the S Flag is 1)

Note:

Use an even-numbered address as a value to be set for the stack pointer.

MSB LSB

AL A624H USB C6H USP F328H C6F326H XX XX

SSB 56 SSP 1234

AL A624H USB C6H USP F326H

SSB 56H SSP 1234H C6F326H A6H 24H

Before execution

S flag

S flag

After executionThe user stack is used because the S flag is 0.

AL A624H USB C6H USP F328H 561232H XX XX

1 SSB 56H SSP 1234H

AL A624H USB C6H USP F328H 561232H A6H 24H

1 SSB 56H SSP 1232H

Before execution

S flag

S flag

After execution

The system stack is used because the S flag is 1.

39

CHAPTER 2 CPU

2.4.3 Processor Status (PS)

The processor status register (PS) contains bits for controlling CPU operation and bits for indicating the CPU status.

Processor Status (PS)

The upper bits of the processor status register (PS) consist of the register bank pointer (RP) thatpoints to the first address of the register bank and the interrupt level mask register (ILM). Thelower bits of the PS consists of the condition code register (CCR) that consists of flags that areset or reset as result of instruction execution and by interrupts.

Figure 2.4-6 Configuration of the Processor Status Register (PS)

Condition Code Register (CCR)

Figure 2.4-7 Configuration of the Condition Code Register (CCR)

Interrupt enable flag (I)

For interrupt requests other than software interrupts, when the I flag is 1, interrupts are enabled.When the I flag is 0, interrupts are masked, and cleared by a reset.

Stack flag (S)

When the S flag is 0, the USP can be used as the stack operation pointer. When the S flag is 1,the SSP can be used. The S flag is set when an interrupt is accepted or when a reset occurs.

Sticky bit flag (T)

The T flag is set to 1 when the data shifted out by carry contains at least one 1 after executionof a logical right shift instruction or arithmetic right shift instruction. Otherwise, the T flag is setto 0. The T flag is also set to 0 when the shift amount is zero.

Negative flag (N)

The N flag is set when the MSB of an arithmetic operation result is 1, and is cleared when theMSB is 0.

15 13 12 8 7 0

PS ILM RP CCR

000 00000 -01XXXXXInitial value X: Undefined value

7 6 5 4 3 2 1 0

- I S T N Z V C : CCR

- 0 1 X X X X XInitial value X: Undefined value

40


Zero flag (Z)

The Z flag is set when an arithmetic operation result is all zeros. Otherwise, the Z flag iscleared.

Overflow flag (V)

The V flag is set if a signed numeric value overflows because of an arithmetic operation, and iscleared if no overflow occurs.

Carry flag (C)

The C flag is set if an overflow or underflow of the MSB occurs because of an arithmeticoperation, and is cleared if neither overflow nor underflow occurs.

Register Bank Pointer (RP)

The register bank pointer (RP) is the register that indicates the relationship between a general-

purpose register of the F2MC-16L and the address in the internal RAM where the general-purpose register is allocated. This register indicates the first memory address of the general-purpose register bank currently being used according to the conversion formula [000180H +(RP) x 10H]. The RP contains five bits that can store a value from 00H to 1FH. The registerbank can be allocated in memory in the range from 000180H to 00037FH.

However, even if this range is used, the register cannot be used as general-purpose register ifthe address is not located in internal RAM. PR is initialized to all zeros by a reset. Although aninstruction can transfer an 8-bit immediate value to the RP, only the lower 5 bits of the data areactually used.

Figure 2.4-8 Configuration of the Register Bank Pointer (RP)

Interrupt Level Mask Register (ILM)

The interrupt level mask register (ILM) contains 3 bits which indicate the level of the CPUinterrupt mask. Only an interrupt request with a level higher than the level indicated by these 3bits is accepted. As listed in Table 2.4-1 "Level Priority Indicated in the Interrupt Level MaskRegister (ILM)", a level of 0 is defined to be highest and a level of 7 is defined to be lowest. Therequest value of an interrupt to be accepted must be smaller than the value currently stored inthe ILM. When an interrupt is accepted, the ILM is set to the value of the respective interruptlevel. Thereafter, interrupts with the same or lower level are not accepted. The ILM is initializedto all zeros by a reset. Although an interrupt can transfer an 8-bit immediate value to the ILM,only the lower 3 bits of the data are actually used.

B4 B3 B2 B1 B0 : RP

0 0 0 0 0Initial value

41

CHAPTER 2 CPU

Figure 2.4-9 Configuration of Interrupt Level Mask Register (ILM)

ILM2 ILM1 ILM0 : ILM

0 0 0Initial value

Table 2.4-1 Level Priority Indicated in the Interrupt Level Mask Register (ILM)

ILM2 ILM1 ILM0 Level value Allowed interrupt level

0 0 0 0 Prohibited interrupts

0 0 1 1 0 only

0 1 0 2 Level with a value smaller than 1






42


2.4.4 Program Counter (PC)

The program counter (PC) is a 16-bit counter that indicates the lower 16 bits of the memory address of the instruction code to be executed by the CPU. The program bank register (PCB) indicates the upper 8 bits of the address.

Program Counter (PC)

The contents of the program counter (PC) are updated by conditional branch instructions,subroutine call instructions, interrupts, and resets. The PC can also be used as a bus pointerfor accessing operands.

Figure 2.4-10 Program Counter Configuration

PCB FEH PC ABCDH

FEABCDHNext instruction to be executed

43

CHAPTER 2 CPU

2.4.5 Direct Page Register (DPR)

The direct page register (DPR) specifies addr8 to addr15 of the operand address when a direct addressing instruction is executed. The DPR has a length of 8 bits. The DPR is initialized to 01 H at a reset. The DPR can be read and written via instructions.

Direct Page Register (DPR) (initial value: 01 H)

Figure 2.4-11 "Generation of a Physical Address with Direct Addressing" shows the generationof a physical address with direct addressing.

Figure 2.4-11 Generation of a Physical Address with Direct Addressing

DTB register DPR register

MSB LSB

Direct address during instruction

24 bit physical address

44


2.4.6 Bank Registers

The following five types of bank register are available:• Program counter bank register (PCB) <initial value: Value in reset vector>• Data bank register (DTB) <initial value: 00 H>

• User stack bank register (USB) <initial value: 00 H>

• System stack bank register (SSB) <initial value: 00 H>

• Additional data bank register (ADB) <initial value: 00 H>

Bank Registers

Bank registers indicate the individual memory banks where the PC space, DT space, SP space(user), SP space (system), and AD space are allocated. All bank registers are of byte length.The PCB is initialized to 00H by a reset vector. The other bank registers can be read andwritten. The PCB can be read, but cannot be written.

The PCB is rewritten when the JMPP, CALLP, RETP, RETIQ, and RETF instructions that canbranch anywhere within the 16 MB space are executed and when an interrupt occurs.

See Section 2.1 "Memory Space" for the operation of each register.

45

CHAPTER 2 CPU

2.5 General-Purpose Registers

As with ordinary memory, the user can specify how the general-purpose registers are used. General-purpose registers exist together with RAM in the CPU address space. In the same way as dedicated registers, general-purpose registers can be accessed without specifying an address.

General-Purpose Registers

The general-purpose registers of the F2MC-16L are allocated in main memory at the addresses000180H to 00037FH (maximum address). The register bank pointer (RP) specifies at which ofthese addresses the currently used register bank is allocated. The following three types ofregister exist in each bank. These registers are not independent but are related as follows.

• R0 to R7: 8-bit general-purpose register

• RW0 to RW7: 16-bit general-purpose register

• RL0 to RL3: 32-bit general-purpose register

Figure 2.5-1 General-Purpose Registers

The relationship between the upper and lower bytes of the byte register and word register canbe represented with the following formula:

PW(i + 4) = R(i x 2 + 1) x 256 + R(i x 2) [i = 0 to 3]

The relationship between the upper and lower bytes of Rli and RW can be represented with thefollowing formula:

RL(i) = RW(i x 2 + 1) x 65536 + RW(i x 2) [i = 0 to 3]

MSB LSB16bit

000180H + RPx10HRW0

RL0RW1

RW2RL1

RW3

R1 R0 RW4RL2

R3 R2 RW5

R5 R4 RW6RL3

R7 R6 RW7

First address of general-purpose register

Lower

Upper

46

2.5 General-Purpose Registers

Register Bank

A register bank consists of 8 words, which can be used for general-purpose registers (byteregisters R0 to R7, word registers RW0 to RW7, and long-word registers RL0 to RL3). Thoseregisters can be used for a variety of arithmetic operations and as pointers for variousinstructions. RL0 to RL3 can also be used as a linear pointer for directly accessing the entirememory space. Table 2.5-1 "Register Bank Functions" lists register functions, and Table 2.5-2"Relationship between Registers" lists the relationship between registers. The contents of theregister bank, like the contents of ordinary RAM, are not initialized by a reset. The status beforea reset is retained. At power-on, however, the contents are undefined.

Note:

• R0 can also be used as a barrel shift counter and a normalization instruction counter.

• RW0 can also be used as a string instruction counter.

Table 2.5-1 Register Bank Functions

Register Function

R0 to R7 Used as an operand in a variety of instructions.

RW0 to RW7 Used as a pointer or operand in a variety of instructions.

RL0 to RL3 Used as a long pointer or operand in a variety of instructions.

Table 2.5-2 Relationship between Registers

RW0RL0

RW1

RW2RL1

RW3

R0RW4

RL2R1

R2RW5

R3

R4RW6

RL3R5

R6 RW7

R7

47

CHAPTER 2 CPU

2.6 Prefix Codes

Three types of prefix code are available: Bank select prefix, common register bank prefix, and flag change suppression prefix.These prefix codes can be placed before an instruction to modify the operation.

Bank Select Prefix

The memory space used for data access is defined for each addressing method. If a bankselect prefix is placed before an instruction, the memory space used for data access by theinstruction can be arbitrarily selected regardless of the addressing method.

Table 2.6-1 "Bank Select Prefixes" lists the bank select prefixes and selected memory spaces.

To use a bank select prefix, be careful when using the following instructions:

String instructions [MOVS, MOVSW, SCEQ, SCWEQ, FILS, FILSW]

Use the bank register specified in the operand regardless of whether a prefix is used.

Stack operation instructions [PUSHW, POPW]

Use the system stack bank (SSB) or user stack bank (USB) in accordance with the value of theS flag regardless of whether a prefix is used.

I/O access instruction [MOV A, io/MOV io, A/MOVX A, io/MOVW A, io/MOVW io, A/MOV io, #imm8 MOVW io, #imm16/ MOVB A, io:bp/MOVB io:bp, A/SETB io:bp/CLRB io:bp BBC io:bp, rel/BBS io:bp, rel/WBTC, WBTS]

The I/O space in the bank is used regardless of whether a prefix is used.

Flag change instructions [AND CCR, #imm8, OR CCR, #imm8]

Although processing of the instruction itself is not affected, the effect of the prefix extends to thenext instruction.

POPW ps

The system stack bank (SSB) or user stack bank (USB) is used in accordance with the value ofthe S flag regardless of whether a prefix is used.

Table 2.6-1 Bank Select Prefixes

Bank select prefix Selected space

PCB Program space

DTB Data space

ADB Additional space

SPB The system stack space or user stack space is used in accordance with the contents of the stack flag.

48

2.6 Prefix Codes

MOV ILM, #imm8

Although processing of the instruction itself is not affected, the effect of the prefix extends t thenext instruction.

RETI

The system stack bank (SSB) is used regardless of whether a prefix is used.

Common Register Bank Prefix (CMR)

To facilitate data exchange between multiple tasks, a reasonably simple means of accessingthe predefined same register bank is necessary regardless of the value of the current registerbank pointer (RP). If the common register bank prefix (CMR) is placed before an instruction thataccesses a register bank, all registers accessed by the instruction can be changed to accessesto the common bank accesses (register bank selected when RP = 0) at 000180H to 00018FH.This is regardless of the value of the current register bank pointer (RP).

For the common register bank prefix (CMR), be careful when using the following instructions:


If an interrupt request occurs during execution of a string instruction with a prefix code added,the prefix becomes invalid for the string instruction after return from the interrupt, resulting in amalfunction. Do not add the CMR prefix to a string instruction [MOVS, MOVSW, SCEQ,SCWEQ, FILS, FILSW].

Flag change instructions [AND CCR, #imm8, OR CCR, #imm8, POPW PS]


MOV ILM, #imm8


Flag Change Suppression Prefix (NCC)

The flag change suppression prefix code (NCC) is used to suppress unnecessary flag changes.By placing a flag change suppression prefix code before an instruction that suppressesunnecessary flag changes, flag changes accompanying the execution of the instruction aresuppressed.

When using the flag change suppression prefix (NCC), be careful when using the followinginstructions:


If an interrupt request occurs during execution of a string instruction with a prefix code added,the prefix becomes invalid for the string instruction after return from the interrupt, resulting in amalfunction. Do not add the NCC prefix to the string instruction [MOVS, MOVSW, SCEQ,SCWEQ, FILS, FILSW].

Flag change instructions [AND CCR, #imm8, OR CCR, #imm8, POPW PS]


Interrupt instructions [INT #vct8, INT9, INT addr16, INTP addr24, RETI]

The condition code register (CCR) changes according to the definition of the instructionregardless of whether a prefix is used.

49

CHAPTER 2 CPU

JCTX @A

The condition code register (CCR) changes according to the definition of the instructionregardless of whether a prefix is used.

MOV ILM, imm8


50

2.6 Prefix Codes

2.6.1 Restrictions on Prefix Codes

The following restrictions are imposed apply to the use of prefix codes:• Interrupt or hold requests are not accepted during the execution of prefix codes and

interrupt or hold suppression instructions.• If a prefix code is placed before an interrupt or hold instruction, the effect of the

prefix code is delayed.• If consecutively placed prefix codes become inconsistent, the last prefix code is

valid.

Prefix Codes and Interrupt/Hold Suppression Instructions

Table 2.6-2 "Prefix Codes and Interrupt/Hold Suppression Instructions" lists the instructions forsuppression of interrupt or hold instructions and prefix codes to which restrictions apply.

Interrupt/hold suppression

As shown in Figure 2.6-1 "Interrupt/Hold Suppression", an interrupt or hold request generatedduring the execution of instructions with prefix codes or interrupt/hold instructions is notaccepted. The interrupt or hold is not processed until the first instruction that is without prefix orthat is not an interrupt/hold suppression instruction is executed.

Figure 2.6-1 Interrupt/Hold Suppression

Delay of the effect of prefix codes

As shown in Figure 2.6-2 "Interrupt/Hold Suppression Instructions and Prefix Codes", if a prefixcode is placed before an interrupt/hold suppression instruction, the prefix code takes effect withthe first instruction executed after the interrupt/hold suppression instruction.

Table 2.6-2 Prefix Codes and Interrupt/Hold Suppression Instructions

Prefix code Interrupt/hold suppression instructions (instructions that delay the effect of the

prefix code)

Instructions that does not accept interrupt and hold request

PCBDTBADBSPBCMRNCC

MOV ILM, #imm8 OR CCR, #imm8 AND CCR, #imm8 POPW PS

(a)

Interrupt suppression instruction

Interrupt request generated

(a) Ordinary instruction

Interrupt accepted

51

CHAPTER 2 CPU

Figure 2.6-2 Interrupt/Hold Suppression Instructions and Prefix Codes

Consecutive Prefix Codes

As shown in Figure 2.6-3 "Consecutive Prefix Codes", if consecutive inconsistent prefix codes(PCB, ADB, DTB, and SPB) are specified, the last prefix code is valid.

Figure 2.6-3 Consecutive Prefix Codes

MOV A,FFH NCC MOV ILM,#imm8 ADD A,01H

CCR:XXX10XX CCR:XXX10XX

Interrupt suppression instruction

NCC does not cause the CCR to change.

ADB DTB PCB ADD A,01H

Prefix code

Prefix code PCB is valid.

52

2.7 Memory Map

2.7 Memory Map

This section describes MB90650A memory space, I/O space, and interrupt number allocations.

Memory Space

As shown in Figures 2.7-1 and 2.7-2, the memory space of the MB90650A is divided into threetypes of areas. The type depends on which of the three modes is in use.

Figure 2.7-1 MB90650A Memory Space Allocation in Each Mode (MB90650A to MB90653A)

FFFFFFH

FE0000H

010000H

002000H

000100H

0000C0H

000000H

RAM RAM RAM

Single-chip Internal ROM external bus External ROM external bus

ROM area ROM area

Address #1

Address #2

Address #3

ROM area(FF bank image)

ROM area(FF bank image)

Register Register Register

Peripheral Peripheral Peripheral

: Internal

: External

: Access not allowed

Model Address #1 Address #2 Address #3

MB90652A

MB90653A

MB90P653A

MB90V650A

FF0000H

FE0000H

FE0000H

(FE0000H)

004000H

004000H

004000H

004000H

000CFFH

0014FFH

0014FFH

0018FFH

53

CHAPTER 2 CPU

Figure 2.7-2 MB90650A Memory Space Allocation in Each Mode (MB90654A)

Note:

In the MB90F654A/654A model, the allocation of the RAM area is changed from 2000H to2100H.

The contents of ROM in the FF bank can be referenced as an image in the upper region ofthe 00 bank. This is implemented so as to use the small model of the C compiler moreeffectively. Since the lower 16 bits become the same, the tables in ROM can be referencedwithout specifying "Far" in the pointer declaration. For example, when 00C000H is accessed,the contents of the ROM at FFC000H are actually accessed.

Since the ROM area in the FF bank exceeds 48 KB, not all areas can be referenced as animage from the 00 bank. An image of FF4000H to FFFFFFH can be referenced via the 00bank, but an image of FE0000H to FF3FFFH can be referenced only via the FE and FFbanks.

FFFFFFH

010000H

002100H

000100H

0000C0H

000000H

RAM RAM RAM


MB90654A

MB90F654A

FC0000H

FC0000H

004000H

004000H

0020FFH

0020FFH

Single-chip Internal ROM external bus External ROM external bus

Address #1

Address #2

(Address #3)

ROM area ROM area

ROM area (FF bank image)

ROM area (FF bank image)

Register Register Register


: Internal

: External


54

CHAPTER 3 INTERRUPTS

This chapter explains the interrupt functions and operation.

3.1 "Overview of Interrupts"

3.2 "Interrupt Causes"

3.3 "Interrupt Vectors"

3.4 "Hardware Interrupts"

3.5 "Software Interrupts"

3.6 "Extended Intelligent I/O Service (EI2OS)"

3.7 "Exception Processing Interrupts"

55


3.1 Overview of Interrupts

The F2MC-16L provides interrupt functions that interrupt the processing currently being executed and transfer control to a separately defined program.

Overview of Interrupts

The interrupt functions can be divided into the following four types:

• Hardware interrupt function: Interrupt processing triggered by the occurrence of an eventinvolving internal peripherals

• Software interrupt function: Interrupt processing triggered by a software event generationinstruction

• Extended intelligent I/O service (EI2OS): Transfer processing triggered by the occurrence ofan event involving internal peripherals

• Exception: Interrupt processing triggered by the occurrence of an operation exception item

56

3.2 Interrupt Causes

3.2 Interrupt Causes

Table 3.2-1 "Interrupt Causes, Interrupt Vectors, and Interrupt Control Registers" Interrupt causes, interrupt vectors, and interrupt control registers

Interrupt Causes

Table 3.2-1 Interrupt Causes, Interrupt Vectors, and Interrupt Control Registers

Interrupt causeIIOS clear

Interrupt vector Interrupt control register

Number Address Number Address

Reset X # 08 FFFFDCH - -

INT9 instruction X # 09 FFFFD8H - -

Exception X # 10 FFFFD4H - -

A/D converter O # 11 FFFFD0H ICR00 0000B0H

Time base timer interval timer interrupt

X # 12 FFFFCCH

DTP0 (external interrupt 0) O # 13 FFFFC8H ICR01 0000B1H

16-bit free run timer (I/O timer) overflow

O # 14 FFFFC4H

Extended I/O serial 1 O # 15 FFFFC0H ICR02 0000B2H

DTP1 (external interrupt 1) O # 16 FFFFBCH

Extended I/O serial 2 O # 17 FFFFB8H ICR03 0000B3H

DTP2 (external interrupt 2) O # 18 FFFFB4H

DTP3 (external interrupt 3) O # 19 FFFFB0H ICR04 0000B4H

8/16-bit PPG0 counter borrow O # 20 FFFFACH

8/16-bit U/D counter 0 compare O # 21 FFFFA8H ICR05 0000B5H

8/16-bit U/D counter 0 underflow, overflow, up/down inversion

O # 22 FFFFA4H

8/16-bit PPG1 counter borrow O # 23 FFFFA0H ICR06 0000B6H

DTP4/5 (external interrupt 4/5) O # 24 FFFF9CH

Output compare (channel 2) match (I/O timer)

O # 25 FFFF98H ICR07 0000B7H


O # 26 FFFF94H

57


Note:

In case of peripherals that have two interrupt causes for the same interrupt number, the IIOSinterrupt clear signal clears both interrupt request flags.

Clock prescaler X # 27 FFFF90H ICR08 0000B8H

DTP6 (external interrupt 6) O # 28 FFFF8CH

8/16-bit U/D counter 1 compare O # 29 FFFF88H ICR09 0000B9H


O # 30 FFFF84H

Input capture (channel 0) fetch (I/O timer)

O # 31 FFFF80H ICR10 0000BAH


O # 32 FFFF7CH


O # 33 FFFF78H ICR11 0000BBH


O # 34 FFFF74H

Flash memory write/erase completion

X # 35 FFFF70H ICR12 0000BCH


UART0 reception completion * # 37 FFFF68H ICR13 0000BDH

UART0 send completion * # 39 FFFF60H ICR14 0000BEH

I2C interface X # 41 FFFF58H ICR15 0000BFH

Delayed interrupt X # 42 FFFF54H

O: The IIOS interrupt clear signal clears the interrupt request flag.*: The IIOS interrupt clear signal clears the interrupt request flag. There is a stop request.X: The IIOS interrupt clear signal does not clear the interrupt request flag.

Table 3.2-1 Interrupt Causes, Interrupt Vectors, and Interrupt Control Registers (Continued)




58

3.3 Interrupt Vectors

3.3 Interrupt Vectors

Table 3.3-1 "Interrupt Vectors" lists the interrupt vectors for this device.

Interrupt Vectors

Table 3.3-1 Interrupt Vectors

Software interrupt

instruction

Vector address

L

Vector address

M

Vector address

H

Mode register

Interrupt No.

Hardware interrupt

INT 0 FFFFFCH FFFFFDH FFFFFEH Not used #0 None

: : : : : : :

INT 7 FFFFE0H FFFFE1H FFFFE2H Not used #7 None

INT 8 FFFFDCH FFFFDDH FFFFDEH FFFFDF #8 (RESET vector)

INT 9 FFFFD8H FFFFD9H FFFFDAH Not used #9 None

INT 10 FFFFD4H FFFFD5H FFFFD6H Not used #10 <Exception>

INT 11 FFFFD0H FFFFD1H FFFFD2H Not used #11 A/D

INT 12 FFFFCCH FFFFCDH FFFFCEH Not used #12 None

INT 13 FFFFC8H FFFFC9H FFFFCAH Not used #13 External interrupt #0

INT 14 FFFFC4H FFFFC5H FFFFC6H Not used #14 16-bit free-run timer

INT 15 FFFFC0H FFFFC1H FFFFC2H Not used #15 Extended I/O serial 1

INT 16 FFFFBCH FFFFBDH FFFFBEH Not used #16 External interrupt #1

INT 17 FFFFB8H FFFFB9H FFFFBAH Not used #17 Extended I/O serial 2

INT 18 FFFFB4H FFFFB5H FFFFB6H Not used #18 External interrupt #2

INT 19 FFFFB0H FFFFB1H FFFFB2H Not used #19 External interrupt #3

INT 20 FFFFACH FFFFADH FFFFAEH Not used #20 PPG0 borrow

INT 21 FFFFA8H FFFFA9H FFFFAAH Not used #21 8/16 U/D 0 compare

INT 22 FFFFA4H FFFFA5H FFFFA6H Not used #22 8/16 U/D 0 other

INT 23 FFFFA0H FFFFA1H FFFFA2H Not used #23 PPG1 borrow

INT 24 FFFF9CH FFFF9DH FFFF9EH Not used #24 External interrupt #4/5

INT 25 FFFF98H FFFF99H FFFF9AH Not used #25 Output compare #2

INT 26 FFFF94H FFFF95H FFFF96H Not used #26 Output compare #3

INT 27 FFFF90H FFFF91H FFFF92H Not used #27 Watch prescaler

59


INT 28 FFFF8CH FFFF8DH FFFF8EH Not used #28 External interrupt #6

INT 29 FFFF88H FFFF89H FFFF8AH Not used #29 8/16 U/D 1 compare

INT 30 FFFF84H FFFF85H FFFF86H Not used #30 8/16 U/D 1 other

INT 31 FFFF80H FFFF81H FFFF82H Not used #31 Input capture #0

INT 32 FFFF7CH FFFF7DH FFFF7EH Not used #32 Input capture #1

INT 33 FFFF78H FFFF79H FFFF7AH Not used #33 Output compare #0

INT 34 FFFF74H FFFF75H FFFF76H Not used #34 Output compare #1

INT 35 FFFF70H FFFF71H FFFF72H Not used #35 Reserved (disabled)

INT 36 FFFF6CH FFFF6DH FFFF6EH Not used #36 External interrupt #7

INT 37 FFFF68H FFFF69H FFFF6AH Not used #37 UART reception completion

INT 38 FFFF64H FFFF65H FFFF66H Not used #38 None

INT 39 FFFF60H FFFF61H FFFF62H Not used #39 UART transmission completion

INT 40 FFFF5CH FFFF5DH FFFF5EH Not used #40 None

INT 41 FFFF58H FFFF59H FFFF5AH Not used #41 I2C interface

INT 42 FFFF54H FFFF55H FFFF56H Not used #42 Delayed interrupt

INT 43 FFFF50H FFFF51H FFFF52H Not used #43 None

: : : : : : :

INT 254 FFFC04H FFFC05H FFFC06H Not used #254 None

INT 255 FFFC00H FFFC01H FFFC02H Not used #255 None

Table 3.3-1 Interrupt Vectors

Software interrupt

instruction

Vector address

L

Vector address

M

Vector address

H

Mode register

Interrupt No.

Hardware interrupt

60

3.4 Hardware Interrupts

3.4 Hardware Interrupts

The hardware interrupt function temporarily interrupts the program being executed by the CPU and transfers control to a user-defined interrupt processing program in response to an interrupt request signal from internal peripherals.

Overview of Hardware Interrupts

The interrupt level of the interrupt request is compared with the interrupt level mask register(ILM) in the CPU processor status register (PS). The contents of the I flag in the processorstatus (PS) are then referenced through hardware. If they match the condition for interruptoccurrence, a hardware interrupt is generated.

When a hardware interrupt occurs, the CPU executes the following processing:

• Saving the contents of the PC, PS, AH, AL, PCB, DTB, ADB, and DPR registers of the CPUon the system stack.

• Setting the interrupt level mask register (ILM) in the processor status register (PS). Theinterrupt level automatically becomes the same as the interrupt level currently beingrequested.

• Fetching the contents of the corresponding interrupt vector and branching to the vector.

Hardware Interrupt Configuration

Hardware interrupts are implemented on the following three parts of the system configuration:

Internal peripherals

Interrupt enable bit and interrupt request bit: Controls interrupt requests from peripherals.


Interrupt control register (ICR): Sets the interrupt level and simultaneously determines thepriority of requested interrupts.

CPU

Interrupt enable flag (I) and interrupt mask register (ILM): Compares the request interrupt levelwith the current interrupt level and identifies the interrupt enable status.

Microcode: Operational step of interrupt processing

Interrupt processing is implemented via the peripheral control register for internal peripherals,the interrupt control register (ICR) for the interrupt controller, and the contents of the conditioncode register (CCR) for the CPU. Settings at these three locations must be made via softwarebefore hardware interrupts can be used. See Section 3.6.1 "Interrupt Control Register (ICR)" fordetails about the interrupt control register (ICR).

Interrupt Suppression Instruction

The F2MC-16L supports interrupt suppression instructions that ensure that an instruction doesnot detect whether a hardware interrupt request exists. See Section 2.6.1 "Restrictions onPrefix Codes."

61


Multiple Interrupts

The F2MC-16L CPU supports multiple interrupts. During execution of interrupt processing incases where a subsequent interrupt with a level higher than the interrupt level of the currentinterrupt occurs, the instruction currently being executed is terminated and control is thentransferred to the subsequent interrupt. When the interrupt of the higher level ends, the CPUreturns to the previous interrupt processing. During execution of interrupt processing in caseswhere interrupt processing with a level equal to or lower than the current interrupt occurs, a newinterrupt request is retained until the current interrupt processing ends, unless the contents ofinterrupt level mask register (ILM) and the I flag in the condition code register (CCR) arechanged by an instruction. The extended intelligent I/O service cannot be used for thegeneration of multiple interrupts. During processing of an extended intelligent I/O service, allother interrupt requests and extended intelligent I/O service requests are retained.

Saving Registers onto the Stack at Interrupt

Figure 3.4-1 Register Saved onto the Stack

MSB LSB

H

SSP

AH

AL

DPR ADB

DTB PCB

PC

PS SSP

L

Word (16 bits)

(Value of SSP before an interrupt occurs)

(Value of SSP after an interrupt occurs)

62

3.5 Software Interrupts

3.5 Software Interrupts

The software interrupt function transfers control from the program being executed by the CPU to a user-defined interrupt-processing program in response to the execution of a dedicated instruction.

Overview of Software Interrupts

Software interrupts are generated when a software interrupt instruction is generated. When asoftware interrupt occurs, the CPU executes the following processing:

• Saving the contents of the PC, PS, AH, AL, PCB, DTB, ADB, and DPR registers on thesystem stack in the CPU.

• Setting the I flag in the condition code register (CCR). Interrupts are automatically disabled.

• Fetching the contents of the corresponding interrupt vector and branching to the vector.

There is no interrupt request flag or enable flag for software interrupt requests. Whenever theINT instruction is executed, a software interrupt request is generated.

Since the INT instruction does not have interrupt levels, the interrupt level mask register (ILM) isnot updated. During the execution of the INT instruction, the I flag in the condition code register(CCR) is cleared, and subsequent interrupt requests are retained.

Software Interrupt Configuration

All configuration elements for implementing software interrupts are located in the CPU.

CPU

Microcode: Operational step of interrupt processing

For using a software interrupt, the corresponding instruction must be executed.

As listed in Table 3.3-1 "Interrupt Vectors", the interrupt vector of software interrupts shares theinterrupt area with the area for hardware interrupts. For example, interrupt request number INT11 is used for the A/D converter interrupt of the hardware interrupt as well as for softwareinterrupt INT #11. The A/D converter and INT #11 call the same interrupt processing routine.

63


Software Interrupt Operation

When the CPU fetches and executes a software interrupt instruction, the software interruptprocessing microcode is activated. The software interrupt processing microcode saves thecontents of the dedicated registers (PS, PC, PCB, DTB, ADB, DPR, and 12 bytes of A) on thesystem stack indicated by the system stack registers SSB and SSP. The microcode then loadsthe interrupt vectors to the program counter (PC and PCB) and sets the I flag in the conditioncode register (CCR) to 0 and the S flag to 1.

Figure 3.5-1 "Processing from Generation to Release of a Software Interrupt" shows softwareinterrupt processing from the generation of a software interrupt to the completion of interruptprocessing.

Figure 3.5-1 Processing from Generation to Release of a Software Interrupt

Note on Software Interrupts

When the program bank register (PCB) is FFH, the vector area of the CALLV instructionoverlaps the INT #vct8 instruction table. When creating the software, be sure to prevent theCALLV instruction and INT #vct8 instruction from using the same address.

PS I S

IR

RAM

F2MC-16L.CPUF2MC-16L bus

Save

Register file

MicrocodeQueue

B unit

Fetch

Instruction bus

PS: Processor statusI: Interrupt enable flag in CCRILM: Interrupt level mask register in PSIR: Instruction registerB unit: Bus interface unit

A software interrupt instruction is executed.The contents of the dedicated registers in the CPU are saved to the register file in accordance with the microcode that corresponds to the software interrupt instruction.The RETI instruction in the user interrupt processing routine completes interrupt processing.

64

3.6 Extended Intelligent I/O Service (EI2OS)

3.6 Extended Intelligent I/O Service (EI 2OS)

The extended intelligent I/O service (EI 2OS) is a type of hardware interrupt operation and automatically transfers data between I/O and memory. Traditionally, data transfer between I/O and memory has been performed by the interrupt-processing program.

EI2OS can perform this data transfer in the same way as in a direct memory access (DMA).

Overview of Extended Intelligent I/O Service (EI 2OS)

Compared to traditional data transfer performed by the interrupt-processing program, the

extended intelligent I/O service (EI2OS) provides the following advantages:

• The total size of the program can be reduced because it is no longer necessary to code atransfer program.

• Saving registers is not necessary and the transfer speed is increased because internalregisters are not used for transfer.

• Transfer can be interrupted with the extended intelligent I/O service, enabling to surpress thetransfer of unnecessary data.

• Incrementing or no update can be selected for the buffer address.

• Incrementing or no update can be selected for the I/O register address (if the buffer addressis updated)

When data transfer by EI2OS terminates, a termination condition is set in the S1 and S0 bits inthe interrupt control register (ICR). Processing then automatically branches to the interrupt

processing routine. The type of EI2OS termination condition can be determined by checking the

EI2OS status (ICR: S1, S0) using the interrupt processing program.

To implement EI2OS, the hardware is allocated in two separate locations. Each of the twoblocks contain the following register and descriptor:

Interrupt control register (ICR)

This register is located in the interrupt controller, activates EI2OS, specifies the EI2OS channel,

and displays the EI2OS termination status.

Extended intelligent I/O service descriptor (ISD)

This descriptor, located in RAM, is an 8-byte data item that stores the transfer mode, I/Oaddress, transfer count, and buffer address. The descriptor handles 16 channels. The channelis specified by the interrupt control register (ICR).

65


Operation of Extended Intelligent I/O Service (EI 2OS)

Figure 3.6-1 "Extended Intelligent I/O Service (EI2OS) Operation" shows the operation of the

EI2OS.

Figure 3.6-1 Extended Intelligent I/O Service (EI 2OS) Operation

by IOA

CPUby ICS

ISD

by BAP

by DCT

Memory space

I/O register

Buffer

Peripheral

Interrupt request

I/O register

Interrupt control register


Notes- The area that can be specified by IOA is from 000000H to 00FFFFH.- The area that can be specified by BAP is from 000000H to FFFFFFH.- The maximum transfer count that can be specified by DCT is 65536.

I/O requests transfer.The interrupt controller selects the descriptor.The transfer source and transfer destination are read from the descriptor.Transfer is performed between I/O and memory.The interrupt cause is automatically cleared.

66


Extended Intelligent I/O Service (EI 2OS) Structure

The EI2OS is implemented via the following four configuration elements:

Internal peripherals

Interrupt enable bit and interrupt request bit: Controls interrupt requests from peripherals.


ICR: Sets the interrupt level, simultaneously determines the priority of interrupt requests, and

selects EI2OS operation.

CPU

I and ILM: Compares the request interrupt level and current interrupt level, and identifies theinterrupt enable status.

Microcode: Operational step for EI2OS processing

RAM

Descriptor: Contains EI2OS transfer information.

67


3.6.1 Interrupt Control Register (ICR)

The interrupt control register is located within the interrupt controller and corresponds to all I/O operations related to interrupt functions. This register has the following three functions:• Setting the interrupt level of the corresponding peripheral function.

• Selecting ordinary interrupts or the extended intelligent I/O service (EI 2OS) as interrupts of the corresponding peripheral function.

• Selecting an extended intelligent I/O service (EI 2OS) channel.Do not use a read-modify-write instruction to access this register. Otherwise, a malfunctioning may occur.

Interrupt Control Register (ICR)

Figure 3.6-2 Interrupt Control Register (ICR)

Note:

The ICS3 to ICS0 bits are valid only when the extended intelligent I/O service (EI2OS) has

been activated. To activate EI2OS, set the ISE bit to 1. To not activate EI2OS, set the ISE

bit to 0. When EI2OS is not activated, setting ICS3 to ICS0 bits is optional.

ICS1 and ICS0 bits are valid only for writing. S1 and S0 bits are valid only for reading.

[Bits 15 to 12, 7 to 4] EI 2OS channel selection bits (ICS3 to ICS0)

These bits are the extended intelligent I/O service (EI2OS) channel selection bits.

These write-only bits specify the EI2OS channel. The address of the extended intelligent I/Oservice descriptor (ISD) in memory is determined based on the value set here. The ICS bitsare initialized to "0000" at a reset.

15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0

B0H to BFH ICS3 ICS2 ICS1 ICS0 ISE IL2 IL1 IL0

(W) (W) (W) (W) (W) (W) (W) (W)(0) (0) (0) (0) (0) (1) (1) (1)

15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0

S1 S0 ISE IL2 IL1 IL0

(-) (-) (R) (R) (R) (R) (R) (R)(-) (-) (0) (0) (0) (1) (1) (1)

B0H to BFH

Interrupt control register (ICR)

Bit No.

Bit No.

Address:

Address:

Read/write

Read/write

Initial value

Initial value

Writing

Reading

68


[Bits 13 and 12, 5 and 4] EI 2OS status (S0 and S1)

These bits are extended intelligent I/O service (EI2OS) status bits.

These are read-only bits. Checking these bits after EI2OS termination allows to determinethe termination conditions. These bits are initialized to 0 at a reset.

Table 3.6-1 Correspondence between the EI2OS Channel Selection Bits and Descriptor Addresses

ICS3 ICS2 ICS1 ICS0 Selected channel Descriptor address

0 0 0 0 0 000100H

0 0 0 1 1 000108H

0 0 1 0 2 000110H

0 0 1 1 3 000118H

0 1 0 0 4 000120H

0 1 0 1 5 000128H

0 1 1 0 6 000130H

0 1 1 1 7 000138H

1 0 0 0 8 000140H

1 0 0 1 9 000148H

1 0 1 0 10 000150H

1 0 1 1 11 000158H

1 1 0 0 12 000160H

1 1 0 1 13 000168H

1 1 1 0 14 000170H

1 1 1 1 15 000178H

Table 3.6-2 Relationship between EI 2OS Status Bits and the EI 2OS Status

S1 S0 EI2OS status

0 0 Reserved

0 1 Stop status due to count termination

1 0 Reserved

1 1 Stop status due to a request from internal peripherals

69


[Bits 11 and 3] EI 2OS enable bit (ISE)

This bit enables the extended intelligent I/O service (EI2OS).

If this bit is 1 when an interrupt request is generated, EI2OS is activated. If this bit is 0 whenan interrupt request is generated, the corresponding interrupt sequence is activated. When

EI2OS terminates (triggered by count termination or a request from internal peripherals), the

ISE bit is set to 0. If the corresponding internal peripherals do not have the EI2OS function,the ISE bit must be set to 0 via software. This bit, which can be both read and written, isinitialized to 0 at a reset.

[Bits 10 to 8, 2 to 0] interrupt level setting bits (IL0, IL1, IL2)

These are the interrupt level setting bits.

These bits specify the interrupt level of the corresponding internal peripherals. These bits,which can be both read and written, are initialized to level 7 (no interrupts) at a reset.

Table 3.6-3 Correspondence between Interrupt Level Setting Bits and Interrupt Levels

IL2 IL1 IL0 Interrupt level

0 0 0 0 (highest priority)

0 0 1 1

0 1 0 2

0 1 1 3

1 0 0 4

1 0 1 5

1 1 0 6 (lowest priority)

1 1 1 7 (no interrupts)

70


3.6.2 Extended Intelligent I/O Service Descriptor (ISD)

The extended intelligent I/O service descriptor is located in internal RAM at 000100 H to

00017FH, and consists of the following elements:

• Control data for data transfer• Status data• Buffer address pointer

Extended Intelligent I/O Service Descriptor (ISD)

The extended intelligent I/O service descriptor (ISD) is located in internal RAM at 000100H to00017FH, and consists of the following elements:

• Control data for data transfer

• Status data

• Buffer address pointer

Figure 3.6-3 "Structure of Extended Intelligent I/O Service Descriptor" shows the structure of theextended intelligent I/O service descriptor.

Figure 3.6-3 Structure of Extended Intelligent I/O Service Descriptor

H

000100H + 8 ICS

L

Data counter upper 8 bits (DCTH)

Data counter lower 8 bits (DCTL)

I/O address pointer upper 8 bits (IOAH)

I/O address pointer lower 8 bits (IOAL)

EI2OS status (ISCS)

Buffer address pointer upper 8 bits (BAPH)

Buffer address pointer middle 8 bits (BAPM)

Buffer address pointer lower 8 bits (BAPL)First ISD address

71


3.6.3 Registers of Extended Intelligent I/O Service Descriptor (ISD)

The extended intelligent I/O service descriptor (ISD) consists of the following registers:• Data counter (DCT)• I/O register address pointer (IOA)

• EI2OS status register (ISCS)• Buffer address pointer (BAP)

Data Counter (DCT)

The data counter (DCT) is a 16-bit register that serves as a counter for the data transfer count.After each data transfer, the counter is decremented by 1. When the counter reaches zero,

EI2OS terminates.

Figure 3.6-4 Configuration of Data Counter (DCT)

I/O Register Address Pointer (IOA)

The I/O register address pointer (IOA) is a 16-bit register that indicates the lower address (A15to A0) of the I/O register used to transfer data to and from the buffer. The upper bits of theaddress (A23 to A16) are all zeros. Any I/O from 000000H to 00FFFFH can be specified by thisaddress.

Figure 3.6-5 Configuration of I/O Register Address Pointer (IOA)

15 14 13 12 11 10 9 8

B15 B14 B13 B12 B11 B10 B09 B08 DCTH

(X) (X) (X) (X) (X) (X) (X) (X)

7 6 5 4 3 2 1 0

B07 B06 B05 B04 B03 B02 B01 B00 DCTL

(X) (X) (X) (X) (X) (X) (X) (X)

Data counter upper Bit No.

Bit No.

Initial value

Initial value

Data counter lower

15 14 13 12 11 10 9 8

A15 A14 A13 A12 A11 A10 A09 A08 IOAH

(X) (X) (X) (X) (X) (X) (X) (X)

7 6 5 4 3 2 1 0

A07 A06 A05 A04 A03 A02 A01 A00 IOAL

(X) (X) (X) (X) (X) (X) (X) (X)

Bit No.

Bit No.

Initial value

Initial value

I/O address pointer upper bits

I/O address pointer lower bits

72


Extended Intelligent I/O Service (EI 2OS) Status Register (ISCS)

The EI2OS status register (ISCS) is an 8-bit register. The ISCS indicates update/fixed for thebuffer address pointer and I/O register address pointer, the transfer data format (byte or word),and transfer direction.

Figure 3.6-6 Configuration of EI 2OS Status Register (ISCS)

[Bits 7 to 5] Reserved bits

Always set these bits to 0.

[Bit 4] IF

Specify update/fixed for the I/O register address pointer (IOA).

[Bit 3] BW

Specify the transfer data length.

[Bit 2] BF

Specify update/fixed for the buffer address pointer (BAP).

Note:

Only the lower 16 bits of the buffer address pointer change. The buffer address pointer canonly be incremented.

7 6 5 4 3 2 1 0

IF BW BF DIR SE

(R/W) (R/W) (R/W) (R/W) (R/W)(X) (X) (X) (X) (X) (X) (X) (X)

(R/W) (R/W) (R/W)

Bit No.

Initial value

EI2OS status register (ISCS)

Read/write

Reserved Reserved Reserved

Table 3.6-4 IF Bit Functions

IF Function

0 After data transfer, the I/O register address pointer is updated (incremented).

1 After data transfer, the I/O register address pointer is fixed.

Table 3.6-5 BW Bit Functions

BW Function

0 Byte

1 Word

Table 3.6-6 BF Bit Functions

BF Function

0 After data transfer, the buffer address pointer is updated (incremented).

1 After data transfer, the buffer address pointer is fixed.

73


[Bit 1] DIR

Specify the data transfer direction.

[Bit 0] SE

Control termination of the extended intelligent I/O service (EI2OS) by a request from internalperipherals.

Buffer Address Pointer (BAP)

The buffer address pointer (BAP) is a 24-bit register that stores the address used by the

intelligent I/O service (EI2OS) for the next transfer. Since one independent BAP exists for each

EI2OS channel, each EI2OS channel can transfer data between any address in the 16 MBspace and the I/O units.

Note:

If the BF bit in the EI2OS status register (ISCS) is set to "update", only the lower 16 bits(BAPH, BAPL) of the BAP change; the upper 8 bits (BAPH) do not change.

Table 3.6-7 DIR Bit Functions

DIR Function

0 I/O address pointer --> buffer address pointer

1 Buffer address pointer --> I/O address pointer

Table 3.6-8 EI2OS Termination Control Bit

SE Setting

0 Not terminated by a request from internal peripherals.

1 Terminated by a request from internal peripherals.

74


3.6.4 Operation of Extended Intelligent I/O Service (EI 2OS)

If an interrupt request is generated by a peripheral function and EI 2OS activation is set

in the corresponding interrupt control register (ICR), the CPU uses the EI 2OS to transfer data. When the specified data transfer count terminates, the hardware interrupt is automatically processed.

Processing Procedure of the Extended Intelligent I/O Service (EI 2OS)

Figure 3.6-7 "Operational Flow of Extended Intelligent I/O Service (EI2OS)" shows the flow of

EI2OS operation based on the internal microcode of the CPU.

Figure 3.6-7 Operational Flow of Extended Intelligent I/O Service (EI 2OS)

RETI

NO

YES

S1, S0="01"orS1, S0="11"

S1, S0="00"

Software processing Hardware processing

Start

Initialization

Set the system stack area

Set the EI2OS descriptor

Initialize the peripheral function

Set the interrupt control register (ICR)

Set internal peripherals to operation start. Set the interrupt enable bit.

Set the ILM and I in the PS

Execute the user program(Interrupt request) and (ISE=1)

Transfer data

Determine whether to end counting or to branch to aninterrupt with a terminationrequest from peripherals

(Branch to interrupt vector)

Set the extended intelligentI/O service again (switch channels)

Process data in the buffer

ISE: EI2OS enable bit in the interrupt control register (ICR)S1, S0: EI2OS status of the interrupt control register (ICR)

75


3.6.5 Procedure for Using the Extended Intelligent I/O Service (EI2OS)

Before the extended intelligent I/O service (EI 2OS) can be used, the system stack area,

extended intelligent I/O service (EI 2OS) descriptor, peripheral function, and interrupt control register (ICR) must be set up.

Procedure for Using the Extended Intelligent I/O Service (EI 2OS)

Figure 3.6-8 "Procedure for Using the Extended Intelligent I/O Service (EI2OS)" shows the

EI2OS software and hardware processing.

Figure 3.6-8 Procedure for Using the Extended Intelligent I/O Service (EI 2OS)

-1

NO

NO NO

NO

NO

NO

NO

YES

YES

YES

YES

YES

YES

YES

ISE 1

DIR 1

IF 0

BF 0

DCT 00

SE 1

Interrupt request generated by peripheral function

Read ISD/ISCS Interrupt sequence

Termination request from peripheral

function

Data indicated by data(data transfer)

Memory indicated by BAP

Data indicated by BAP(data transfer)

Memory indicated by IOA

Update value by BW Update IOA

Update BAP

Decrement DCT

Update value by BW

EI2OS termination processing

Set S1 and S0 to 00 Set S1 and S0 to 01 Set S1 and S0 to 11

Clear interrupt request from the peripheral function Clear ISE to 0

Return to CPU operationInterrupt sequence

ISD: EI2OS descriptorISCS: EI2OS status registerIF: IOA update/fixed selection bit in the EI2OS status register (ISCS)BW: Transfer data length specification bit in the EI2OS status register (ISCS)BF: BAP update/fixed selection bit in the EI2OS status register (ISCS)DIR: Data transfer direction specification bit in the EI2OS status register (ISCS)SE: EI2OS termination control bit in the EI2OS status register (ISCS)

DCT: Data counterIOA: I/O register address pointerBAP: Buffer address pointerISE: EI2OS enable bit in the interrupt control register (ICR)S1, S0: EI2OS status in the interrupt control register (ICR)

76


3.6.6 Processing Time for the Extended Intelligent I/O Service (EI2OS)

The time required for processing the extended intelligent I/O service (EI 2OS) changes in accordance with the following factors:

• EI2OS status register (ISCS) setting• Address (area) pointed to by the I/O register address pointer (IOA)• Address (area) pointed to by the buffer address pointer (BAP)• External data bus length for external access• Transfer data length

Because the hardware interrupt is activated when data transfer by EI 2OS terminates, the interrupt handling time is added.

Processing Time (One Transfer Time) for the Extended Intelligent I/O Service (EI 2OS)

When data transfer continues

The EI2OS processing time for data transfer continuation is listed in Table 3.6-9 "Execution

Time of Extended Intelligent I/O Service" based on the EI2OS status register (ISCS) setting.

As listed in Table 3.6-10 "Data Transfer Interpolation Value for EI2OS Execution Time",

interpolation is necessary depending on conditions during EI2OS execution.

Table 3.6-9 Execution Time of Extended Intelligent I/O Service

EI2OS termination control bit (SE) setting Terminates due to termination request from

the peripheral

Ignores termination request from the

peripheral

OA update/fixed selection bit (IF) setting Fixed Update Fixed Update

BAP address update/fixed selection bit (BF) setting

Fixed 32 34 33 35

Update 34 36 35 37

Unit: Machine cycle (one machine cycle corresponds to one clock cycle of the machine clock (φ)).

77


When the data counter (DCT) count terminates (final data transfer)

Because the hardware interrupt is activated when data transfer using EI2OS terminates, the

interrupt handling time is added. The EI2OS processing time when counting terminates iscalculated using the following formula:

The interrupt handling time depends on the type of address the stack pointer points to. Table3.6-11 "Interpolation Value (Z) for the Interrupt Handling Time" lists the interpolation value (Z)for the interrupt handling time.

For termination via a termination request from the peripheral function (I/O)

When data transfer using EI2OS is terminated before completion due to a termination requestfrom the peripheral function (I/O) (ICR: S1, S0 = 11), the data transfer is not performed and a

hardware interrupt is issued. The EI2OS processing time is calculated using the followingformula. Z in the formula represents the interpolation value for the interrupt handling time (seeTable 3.6-11 "Interpolation Value (Z) for the Interrupt Handling Time").

Table 3.6-10 Data Transfer Interpolation Value for EI 2OS Execution Time

I/O register address pointer

Internal access External access

B/even Odd B/even 8/odd

Buffer address pointer Internal access B/even 0 +2 +1 +4

Odd +2 +4 +3 +6

External access B/even +1 +3 +2 +5

8/odd +4 +6 +5 +8

B: Byte data transfer8: External bus using the 8-bit word transferEven: Even-numbered address word transferOdd: Odd-numbered address word transfer

EI2OS processing time when counting terminates =

EI2OS processing time when data is transferred + (21 + 6 x Z) Machine cycles

Interrupt handling time

Table 3.6-11 Interpolation Value (Z) for the Interrupt Handling Time

Type of address the stack pointer points to Interpolation value (Z)

External 8-bit +4

External even-numbered address +1

External odd-numbered address +4

Internal even-numbered address 0

Internal odd-numbered address +2

78


EI2OS processing time for termination before completion = 36 + 6 x Z machine cycles

Note

One machine cycle corresponds to one clock cycle of the machine clock (φ).

Interrupt Processing Time

The time required from generation of an interrupt to acceptance of the interrupt to transfer ofcontrol is the instruction cycle θ.

Since the point at which an interrupt is accepted is only the final cycle of each instruction, thefollowing time is required from generation of an interrupt to transfer of control to the interruptprocessing routine:

The instruction cycle ( can be expressed by the following formula:

θ = 24 + 6 x Table 2.1.12.5 cycle

The range of θ is 24 cycles less or equal θ less or equal 48 cycles.

The operation from the generation of an interrupt to the transfer of control to the processingroutine requires (a) + (b) instruction cycles. If an interrupt request is generated immediatelyafter the instruction that executes the POPW RW0, RW1, ... RW7 instructions (45 cycles) starts,the operation requires the longest instruction cycle (45 + θ).

CPUoperation

Ordinary instructionexecution

Interrupt handlingInterrupt processing program

Interrupt wait time

Interrupt request generation

Sampling wait (a)

(*1)

instruction cycle (b)

*1 indicates the final instruction cycle. This symbol indicates that the interrupt is sampled here.

79


3.7 Exception Processing Interrupts

In the F 2MC-16L, any attempt to execute an undefined instruction results in exception processing.Exception processing is basically the same as processing for an interrupt. When the generation of an exception is detected at the instruction boundary, ordinary processing is interrupted and exception processing is executed. Generally, exception processing occurs as a result of an unexpected operation. Exception processing should be used only to start up recovery software for debugging or recovery from an emergency.

Generation of Exception due to Attempt to Execute an Undefined Instruction

The F2MC-16L handles all codes that are not defined in the instruction map as undefinedinstructions. When an attempt to executed an undefined instruction is made, processingequivalent to the INT #10 software interrupt instruction is executed. The contents of the AL, AH,DPR, DTB, ADB, PCB, PC, and PS registers are saved to the system stack. The I flag in thecondition code register (CCR) is set to 0 and the S flag is set to 1. Processing branches to theroutine indicated by the vector of interrupt number 10. The program counter (PC) value savedto the stack is the exact address where the undefined instruction is stored. For instructioncodes of two bytes or more, the code identified as undefined is stored at this address. Althoughthe RETI instruction can be used to return control from exception processing, this is of no usebecause the exception will recur.

80

CHAPTER 4 CLOCKS AND RESETS

This chapter explains the clock and reset functions and their operation.

4.1 "Clock Generation Block"

4.2 "Clock Supply Map"

4.3 "Reset Causes"

4.4 "Operation after a Reset is Cleared"

81


4.1 Clock Generation Block

The clock generation block controls such operations of the internal clock as sleep, clock, and stop modes and PLL clock multiplication. The internal clock is also called the machine clock. One internal clock cycle is regarded as one machine cycle. A clock generated by source oscillation is called an oscillation clock, and a clock generated by the internal VCO oscillation is called a PLL clock.

Note on the Clock Generation Block

Although an oscillation clock of 3 MHz to 16 MHz can be generated when the operating voltageis 5 V, the maximum operating frequency for the CPU and peripheral circuits is 16 MHz. If thefrequency multiplier rate exceeds the maximum operating frequency specified, devices will notoperate correctly. For example, if a source oscillation of 16 MHz is generated, only a multiplierof 1 can be specified.

The minimum operating frequency for VCO oscillation is 4 MHz, and an oscillation lower thanthis frequency cannot be specified either.

Figure 4.1-1 Block Diagram of the Clock Generation Block

S Q

S QR

RS Q

R 1 2 3 4

1/2 1/2048 1/4 1/4 1/8

X0/ X1

ResetInterrupt

Clock modeSleep mode transition

Stop mode transition

Machine clock

Machine clock selector

PLL multiplier

Oscillation stabilization wait interval selector

Timebase timer

Watchdog interval selector

Watchdog timer

Watchdog reset

82

4.2 Clock Supply Map

4.2 Clock Supply Map

Figure 4.2-1 "Clock Supply Map" shows the clock supply map.

Clock Supply Map

Figure 4.2-1 Clock Supply Map

Oscillationcircuit

Oscillation clock Timebase timer output

Timebase timer 8/16-bit PPG 0/1

Multiplier selection 8-bit A/D converter

8/16-bit up/down counter

Machine clock

PLL multiplier circuit

SelectorPLL clock

Main clock

CPU clock

16-bit reload timer 0

Communication prescaler

I/O extended serial interface 0

I/O extended serial interface 0

16-bit free-run timer 2

Output compare 2

16-bit reload timer 1

A/D converter

LCD controller

Input capture

16-bit free-run timer 1

Output compare 1

Clock monitor function

CPU

UART

X0

X1

TI0

SCK0

SCK1

SCK2

TI1

1/2

1 2 3 4

83


4.3 Reset Causes

There are four possible causes for a reset:• Power-on reset• Watchdog timer overflow• External reset request via the RSTX pin• Software reset request

Reset Causes

At recovery from stop mode and power-on, operation starts after the oscillation stabilization wait

interval has elapsed. When a reset cause occurs, the F2MC-16L immediately stops theprocessing currently being executed and waits for the reset to be cleared. The initial state of themachine clock and watchdog function depends on the reset cause.

A reset cause can be identified based on the values of the reset cause bits in the watchdogtimer control register.

Note:

In other than stop mode, external reset input is sampled by the internal clock. When anexternally supplied clock is stopped, reset input is not accepted.

A flip-flop is associated with each reset cause. The contents of the flip-flops can be obtained byreading the watchdog timer control register. If it is necessary to identify the cause of a resetafter the reset has been cleared, the value read from the watchdog timer control register shouldbe processed by the software and a branch made to the appropriate program.

Table 4.3-1 Reset Causes

Reset Cause Machine clock Watchdog timer Oscillation stabilization

wait

Power-on When the power is turned on Main clock Stop Yes

Watchdog timer Watchdog timer overflow Main clock Stop Yes

External pin L level input to RSTX pin Previous state retained

Previous state retained

No

Software The RST bit in STBYC is set to 0.



No

• In stop mode, a reset is input after the oscillation stabilization wait interval has elapsed regardless of the reset cause.

• The oscillation stabilization wait interval for a power-on reset is fixed to an oscillation clock count of 218 for evaluation products and an oscillation clock count of 217 for FLASH/MASK products. The oscillation stabilization wait interval for other resets is determined based on the value of WS1/WS0 in the clock selection register (CKSCR).

84

4.3 Reset Causes

Figure 4.3-1 Block Diagram of Reset Cause Bits

Figure 4.3-2 Watch Dog Timer Control Register (WDTC)

When multiple reset causes occur at the same time, the corresponding reset cause bits of thewatchdog timer control register are set to 1. If an external reset request and watchdog timerreset are generated at the same time, both the ERST bit and WRST bit are set to 1.

However, for a power-on reset, if the PONR bit is set to 1, all other reset causes are undefined.Consequently, write the software so that it will ignore all reset cause bits except the PONR bit ifit is 1.

Note:

The reset cause bits are cleared only when the watchdog timer control register is read. Anybit that corresponds to a reset cause that has already occurred once remains set to 1 evenwhen another reset cause occurs.

RSTX=L

F/F F/F F/F F/FS R R R RS S S

RSTX pin

Power-onNo periodic clear

RST bit set

Power-on generationdetection circuit

External reset requestdetection circuit

Watchdog timer reset generation detectioncircuit

STBYC, RST bit write detection circuit

WTC register

Delaycircuit

Internal data bus

Reading of WTC register

7 6 5 4 3 2 1 0

0000A8H PONR ERST SRST WTE WT1 WT0 WDTC

(-) (R) (R) (R) (W) (W)(X) (X) (X) (X) (X) (1) (1)

(W)(1)

(R)

WRSTAddress:

Bit No.

Read/writeInitial value

Table 4.3-2 Correspondence between Reset Cause Bits and Reset Causes

Reset cause PONR WRST ERST SRST

Power-on reset 1 - - -

Watchdog timer * 1 * *

External pin * * 1 *

RST bit * * * 1

*: Previous value retained

85


See CHAPTER 10 "WATCHDOG TIMER" for details about the watchdog timer control registerconfiguration and reset cause bits.

Figure 4.3-3 Status at Power-On Reset

Vcc (power supply)

Oscillation Status

Power-on resetMain clock

Subclock

Oscillation StopMain clock oscillation stabilization wait

Main clock operation executable

Subclock oscillationstabilization wait

Subclock operation executable

218 count for main clock oscillation

Main clock mode

Subclock mode Divide-by-2 main clock operationfor subclock mode request

216 count for subclock oscillation

86

4.4 Operation after a Reset is Cleared

4.4 Operation after a Reset is Cleared

When a reset cause is cleared, the F 2MC-16L immediately outputs the address containing the reset vector and fetches the reset vector and mode data. The reset vector and mode data are allocated in the four bytes from FFFFDC H to FFFFDFH. After

the reset is cleared, the reset vector and mode data are transferred to the appropriate registers by the hardware.

Operation after a Reset is Cleared

After the reset vector and mode data are read, the bus mode is specified by mode data.

Figure 4.4-1 Storage Location and Destination of Reset Vector and Mode Data

Note:

The mode register is undefined immediately after a reset. Store any mode data in memoryspace to ensure that the write operation is performed.

FFFFDFH

FFFFDEH

FFFFDDH

PCBFFFFDCH

PC

Memory space

F2MC-16L CPU coreMode

register

Mode data

Reset vector bits 23 to 16Micro-ROM

Reset sequenceReset vector bits 15 to 8

Reset vector bits 7 to 0

87


88

CHAPTER 5 LOW POWER CONTROL CIRCUIT

This chapter explains the functions and operation of the low power control circuit (CPU intermittent operation, oscillation stabilization wait interval, and clock multiplier).

5.1 "Overview of Low Power Control Circuit"

5.2 "Block Diagram of Low Power Control Circuit"

5.3 "Low Power Control Circuit Register"

5.4 "Status Transition for Clock Selection"

89


5.1 Overview of Low Power Control Circuit

The low power control circuit mainly uses the low power mode as operating mode. The CPU intermittent operation function and oscillation stabilization wait interval can be set in accordance with the settings of the register bits.Within the block diagram for the entire device, the low power control circuit is a part of the clock control circuit (see Section 1.4 "Drawings Showing Package Dimensions").

Operation Modes of Low Power Control Circuit

The operation modes of the low power control circuit consist of PLL clock mode, PLL sleepmode, PLL watch mode, pseudo watch mode, main clock mode, main sleep mode, main watchmode, main stop mode, subclock mode, subclock sleep mode, subclock watch mode, andsubclock stop mode. The other operation mode besides PLL clock mode is low power mode.

CPU Intermittent Operation Function

The CPU intermittent operation function stops the supply of the clock signal to the CPU for acertain period to access a register, internal memory, and internal peripherals and delays internalbus cycle activation. While high-speed clock pulses are supplied to internal peripherals, theCPU execution rate is reduced, enabling processing with low power. The CG1 and CG0 bits ofthe low power mode control register (LPMCR) are used to select the number of halt cycles forthe clock supplied to the CPU.

The instruction execution time using the CPU intermittent operation function can be calculatedas follows: Obtain a correction value by multiplying the number of times instructions that accessa register, internal memory, and internal peripherals are executed, by the number of halt cycles.Add this correction value to the normal execution time.

Main Clock Oscillation Stabilization Wait Interval Setting

The WS1 and WS0 bits of the clock selection register (CKSCR) are used to select the mainclock oscillation stabilization wait interval when stop mode is released. Select the oscillationstabilization wait interval in accordance with the type and characteristics of the oscillation circuitand oscillation element connected to the X0 and X1 pins.

These bits are only initialized at a power-on reset. When a power-on reset occurs, these bitsare initialized to "11." The main clock oscillation stabilization wait time at power-on is

approximately a count of 217 source oscillations for a FLASH/MASK product and approximately

a count of 218 source oscillations for an evaluation product.

90

5.1 Overview of Low Power Control Circuit

Machine Clock Switching

Switching between main clock and PLL clock

Writing the MCS bit of the clock selection register (CKSCR) switches between the main clockand PLL clock.

When the MCS bit is 1 and set to 0, the switch from the main clock to a PLL clock occurs after

the PLL clock oscillation stabilization interval (212 machine clock cycles).

When the MCS bit is 0 and set to 1, the switch from the PLL clock to the main clock occurswhen the edges of the PLL clock and main clock coincide (after 1 to 8 PLL clock cycles).

Even when the MCS bit is rewritten, machine clock switching does not occur immediately. Tooperate the peripherals that rely on the machine clock, verify beforehand that machine clockswitching has been executed, by referencing the MCM bit of the clock selection register(CKSCR).

Switching between main clock and subclock

A write operation for setting the SCS bit of the clock selection register (CKSCR) switchesbetween the oscillation clock and subclock.

When the SCS bit is 1 and set to 0, the switch from the oscillation clock to subclock occurswhen the edge of the subclock signal is detected.

When the SCS bit is 0 and set to 1, the switch from the subclock to the oscillation clock occursafter the oscillation stabilization wait interval of the oscillation clock.

Even when the SCS bit is rewritten, machine clock switching does not occur immediately. Tooperate the peripherals, verify beforehand that they rely on the machine clock.

Machine clock initialization

The MCS bit and SCS bit of the clock selection register (CKSCR) are not initialized by theresets caused by the external pin and the RST bit of the low power mode control register(LPMCR). They are initialized to 1 by other resets.

91


5.2 Block Diagram of Low Power Control Circuit

This section contains the block diagram of the low power control circuit.

Block Diagram of Low Power Control Circuit

Figure 5.2-1 Block Diagram of Low Power Control Circuit

CKSCR

MCM

MCS 1 2 3 4

CKSCR

CS1

CS0 0/9/17/33

LPMCR

CG1

CG0

LPMCR

SLP

STP

RST

CKSCR210

WS1 213

215

WS0 217*212 214 216 219

LPMCR

SPL

LPMCR

RST

WDGRST

SCM

SCS

CKSCR

1/2 S

TMD

SCM SLEEP

MSTP

STOP

Subclockswitch control

Divide-by-4 subclock(oscillation)

PLLmultiplier circuit

Main clock (oscillation)

CPU clock generation

CPU clock

CPU clock selector

intermittent cycle selection

CPU intermittent operation functionCycle count selection circuit

Peripheralclock generation

Peripheral clock

Standby control circuit

Main clock oscillation stopSubclock oscillation stop

Clear

Interrupt request or RST

Oscillationstabilizationwait intervalselector

Clock input

Timebase timer

Pin high-impedance control circuit Pin Hi-Z

Internal reset generation circuit

RSTX pin

Internal RST

To watchdog timer

*218 at power-on

F2M

C-16L bus

92

5.3 Low Power Control Circuit Registers


There are two types of registers for the low power control circuit:• Low power mode control register• Clock selection register

Low Power Control Circuit Register

Figure 5.3-1 Low Power Control Circuit Register

7 6 5 4 3 2 1 0

Address : 0000A0H STP SLP SPL RST TMD CG1 CG0 LPMCR

(W) (W) (R/W) (W) (W) (R/W) (R/W)(0) (0) (0) (1) (1) (0) (0) (0)

15 14 13 12 11 10 9 8

Address : 0000A1H SCM MCM WS1 WS0 SCS MCS CS1 CS0 CKSCR

(R/W) (R) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)(1) (1) (1) (1) (1) (1) (0) (0)

(-)

Low power mode control register Bit No.


Clock selection register


Bit No.

93


5.3.1 Low Power Mode Control Register (LPMCR)

This section explains the location and bit functions of the low power mode control register (LPMCR).

Low Power Mode Control Register (LPMCR)

Figure 5.3-2 Low Power Mode Control Register (LPMCR)

[Bit 7] STP

Setting this bit to 1 causes the mode to switch to pseudo watch mode (CKSCR: MSC = 0and SCS = 1) or stop mode (CKSCR: MCS = 1 or SCS = 0). Setting this bit to 0 has noeffect on operation. This bit is cleared to 0 by a reset or by release of the watch or of thestop mode. This bit can be only written. The read value of this bit is always 0.

[Bit 6] SLP

Setting this bit to 1 causes the mode to switch to sleep mode. Setting this bit to 0 has noeffect on operation. This bit is cleared to 0 by a reset or by release of sleep or stop mode.

If the STP bit and SLP bit are both set to 1 at the same time, the mode switches to pseudowatch mode or stop mode. This bit can be only written. The read value of this bit is always0.

[Bit 5] SPL

When this bit is 0, the level of the external pins in watch mode and stop mode is retained.When this bit is 1, the status of the external pins in watch mode and stop mode changes tohigh-impedance. This bit is cleared to 0 by a reset. This bit can be read and written.

[Bit 4] RST

Setting this bit to 0 generates an internal reset signal of 3 machine cycles. Setting this bit to1 has no effect on operation. The read value of this bit is always 1.

[Bit 3] TMD

Setting this bit to 0 causes the mode to switch to watch mode. Setting this bit to 1 has noeffect on operation. This bit is cleared to 1 by a reset or by release of watch or stop mode.This bit can be only written. The read value of this bit is always 1.

[Bits 2 and 1] CG1 and CG0

These bits set the number of clock halt cycles for the CPU intermittent operation function.

These bits are initialized to "00" by a power-on reset or watchdog timer reset. Other resetsdo not initialize these bits. These bits can be read and written.

7 6 5 4 3 2 1 0

Address : 0000A0H STP SLP SPL RST TMD CG1 CG0 LPMCR

(W) (W) (R/W) (W) (W) (R/W) (R/W)(0) (0) (0) (1) (1) (0) (0) (0)

(-)

Low power mode control register Bit No.


94


Table 5.3-1 "CG Bit Setting" lists the CG bit setting.

[Bit 0] Unused bit

Set this bit to 0.

Note:

If the device is not equipped with DRAMC, SSR does not function.

Access to the Low Power Mode Control Register

When word-length is used to write to the low power mode control register, even-numberedaddresses must be used. Writing with odd-numbered addresses to switch to low power modemay cause a malfunction.

Table 5.3-1 CG Bit Setting

CG1 CG0 Number of CPU clock halt cycles

0 0 0 cycle (CPU clock = peripheral clock)

0 1 9 cycles (CPU clock = peripheral clock = 1:3 to 4 approx.)



95


5.3.2 Clock Selection Register (CKSCR)

This section explains the location and bit functions of the clock selection register (CKSCR).

Clock Section Register (CKSCR)

Figure 5.3-3 Clock Section Register (CKSCR)

[Bit 15] SCM

This bit indicates whether the main clock or subclock has been selected as the machineclock. When this bit is 0, the subclock has been selected. When this bit is 1, the oscillationclock has been selected. If SCS = 1 and SCM = 0, the main clock oscillation stabilizationwait interval is in effect.

[Bit 14] MCM

This bit indicates whether the main clock or a PLL clock has been selected as the machineclock. When this bit is 0, a PLL clock has been selected. When this bit is 1, the main clockhas been selected. If MCS = 0 and MCM = 1, the PLL clock oscillation stabilization wait

interval is in effect. The PLL clock oscillation stabilization wait interval is fixed to 212 mainclock cycles.

[Bits 13 and 12] WS1 and WS0

These bits set an oscillation stabilization wait interval for the main clock after stop mode isreleased.

These bits are initialized to "11" by a power-on reset, but other resets do not initialize them.These bits can be read and written.

Table 5.3-2 "WS Bit Setting" lists the WS bit setting.

15 14 13 12 11 10 9 8

Address : 0000A1H SCM MCM WS1 WS0 SCS MCS CS1 CS0 CKSCR

(R/W) (R) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)(1) (1) (1) (1) (1) (1) (0) (0)

Clock selection register Bit No.


Table 5.3-2 WS Bit Setting

WS1 WS0 Oscillation stabilization wait interval (when the source oscillation is 4 MHz)

0 0 About 256 µs (210 count for source oscillation)

0 1 About 1.02 ms (212 count for source oscillation)

1 0 About 8.19 ms (215 count for source oscillation)

1 1 About 32.77 ms (217 count for source oscillation)*

*: About 65.54 ms (218 count for source oscillation) at power-on

96


[Bit 11] SCS

This bit specifies whether the main clock or subclock is selected as the machine clock.Setting this bit to 0 selects the subclock. Setting this bit to 1 selects the main clock. If thisbit is 0 and set to 1, the oscillation stabilization wait interval for the main clock starts. As aresult, the timebase timer is automatically cleared. When the subclock is selected, the signalsubclock is used unchanged as the operating clock signal. (The operating clock has afrequency of 8 kHz when the oscillation frequency is 32 kHz.) If both SCS bit and MCS bitare 0, priority is given to SCS and the subclock is selected.

This bit is initialized to 1 by a power-on reset, watchdog timer reset, external reset, orsoftware reset.

[Bit 10] MCS

This bit specifies whether the main clock or a PLL clock is selected as the machine clock.Setting this bit to 0 selects a PLL clock. Setting this bit to 1 selects the main clock. If this bitis 1 and set to 0, the oscillation stabilization wait interval for the PLL clock starts. As a result,the timebase timer is automatically cleared. The oscillation stabilization wait interval for the

PLL clock is fixed to 212 main clock cycles.

When the main clock is selected, the operating clock frequency is the frequency of the mainclock divided by 2. (The operating clock frequency is 2 MHz when the oscillation frequency is4 MHz.)

This bit is initialized to 1 by a power-on reset or watchdog timer reset.

Note:

When the MCS bit is 1, set it to 0 only when the timebase timer interrupt is masked by theTBIE bit of the timebase timer control register (TBTC) or the interrupt level mask register(ILM).

For 8 machine cycles after the MCS bit is set to 1, setting this bit to 0 may be disabled.Write the bit after 8 machine cycles have passed.

[Bits 9 and 8] CS1 and CS0

These bits select a PLL clock multiplier. These bits are not initialized by resets triggered bythe external pin and the RST bit. They are initialized to "00" by a power-on reset.

When the MCS bit is 0, writing these bits is suppressed. Write the CS bits after setting theMCS bit to 1 (main clock mode). These bits can be read and written.

Table 5.3-3 "CS Bit Setting" lists the CS bit setting.

Table 5.3-3 CS Bit Setting

CS1 CS0 Machine clock (when the oscillation frequency is 4 MHz)

0 0 4 MHz (operating frequency = frequency of oscillation clock)

0 1 8 MHz (operating frequency = frequency of oscillation clock x 2)



97


5.4 Status Transitions for Clock Selection

Figures 5.4-1 and 5.4-2 show the status transitions for clock selection.

Status Transitions for Clock Selection

Figure 5.4-1 Status Transition Diagram 1 for Clock Selection

PLLxSCS=1, MCS=1

CS1/0=xx

PLL1

PLL2

PLL3

PLL4

SCM=1, MCM=1SCS=1, MCS=0

CS1/0=xxSCM=1, MCM=1

SCS=1 or MCS=1

CS1/0=00SCM=1, MCM=1

SCS=0 or MCS=1


SCS=0 or MCS=1


SCS=0 or MCS=1


SCS=1, MCS=0


SCS=1, MCS=0


SCS=1, MCS=0


SCS=1, MCS=0


SCS=1, MCS=0


SCS=0, MCS=x

SCM=1SCM=1

PLLx

Power-on

Main Main

Main

Main

Main

MainMain subclock

subclock

PLL1: Multiplied by 1




The MCS bit is cleared and the SCS bit is set.The PLL clock oscillation stabilization wait ends with CS1 and CS0 = 00.The PLL clock oscillation stabilization wait ends with CS1 and CS0 = 01.The PLL clock oscillation stabilization wait ends with CS1 and CS0 = 10.The PLL clock oscillation stabilization wait ends with CS1 and CS0 = 11.The MCS bit is set or the SCS bit is cleared.PLL clock and main clock synchronization timing with SCS = 1PLL clock and main clock synchronization timing with SCS = 0The main clock oscillation stabilization wait ends with MCS = 0.

98

5.4 Status Transitions for Clock Selection

Figure 5.4-2 Status Transition Diagram 2 for Clock Selection

SCS=1, MCS=1

MCM=1SCM=1

SCS=0

MCM=1SCM=1

SCS=1

MCM=1SCM=0

SCS=1

MCM=1SCM=0

SCS=1, MCS=x


SCS=1, MCS=0


PLLx

PLLx

Power-on

Main Main subclock

subclock Main

subclock

Main

subclock

The SCS bit is cleared.Subclock edge detection timingThe SCS bit is set.The main clock oscillation stabilization wait ends with SCS = 1.PLL clock and main clock synchronization timing with SCS = 0The main clock oscillation stabilization wait ends with MCS = 0.

99


100

CHAPTER 6 LOW POWER MODE

This chapter explains the functions and operation of low power mode for the MB90650A series.

6.1 "Low Power Mode"

6.2 "Transition Conditions for Low Power Mode"

6.3 "Status Transition Diagrams for Low Power Mode"

101


6.1 Low Power Mode

The operation modes consist of PLL clock mode, PLL sleep mode, PLL watch mode, pseudo watch mode, main clock mode, main sleep mode, main watch mode, main stop mode, subclock mode, subclock sleep mode, subclock watch mode, and subclock stop mode. The other operation mode besides PLL clock mode is low power mode.

Low Power Mode

Main clock mode and main sleep mode

The main clock and main sleep modes use the main clock for operation. A clock frequency thatis one-half that of the oscillation clock is used for the operating clock, and the PLL clock isstopped.

Subclock mode and subclock sleep mode

The subclock and subclock sleep modes use only the subclock for operation. The subclockfrequency divided by 4 is used as the frequency of the operating clock. The main clock and PLLclock are stopped in this mode.

PLL sleep mode and main sleep mode

The PLL sleep and main sleep modes cause only the operating clock for the CPU to stop whilethe clocks other than the CPU clock continue to operate.

Pseudo watch mode

In pseudo watch mode, only the watch timer and timebase timer operate.

PLL watch mode, main watch mode, and subclock watch mode

In PLL watch, main watch, and subclock watch mode, only the watch timer operates. Thesemodes use only the subclock for operation and cause the main clock and PLL clock to stop.The operation of the watch modes is the same except for the following differences: The PLLwatch mode switches to PLL clock mode, the main watch mode switches to main clock modeand the subclock watch mode switches to subclock mode on return after an interrupt.

Main stop mode and subclock stop mode

The main stop and subclock stop modes cause the source oscillation to stop and enable data tobe retained with the power consumption levels kept to a minimum. The operation of the stopmodes is the same except that the main stop mode switches to main clock mode and thesubclock stop mode switches to subclock mode on return after interrupt.

CPU intermittent operation function

The CPU intermittent operation function intermittently operates the clock supplied to the CPU toaccess a register, internal memory, internal peripherals, and external bus. While high-speedclock pulses are supplied to internal peripherals, the rate of CPU execution is reduced, enablingprocessing with power consumption levels kept low.

102

6.1 Low Power Mode

Low Power Mode Operating States

Table 6.1-1 "Low Power Mode Operating States" lists the states of the chips in each operationmode.

Table 6.1-1 Low Power Mode Operating States

State Transition condition

Subclock oscillation

Main clock oscillation

Clock CPU Peripheral

Pin Release method

Subclock SCS=0MCS=x

Active Inactive Active Active Active Active ResetInterrupt

Subclock sleep

SCS=0MCS=xSLP=1

Active Inactive Active Inactive Active Active ResetInterrupt

Main sleep

SCS=1MCS=1SLP=1

Active Active Active Inactive Active Active ResetInterrupt

PLL sleep SCS=1MCS=0SLP=1

Active Active Active Inactive Active Active ResetInterrupt

Pseudo watch

(SPL = 0)

SCS=1MCS=0STP=1

Active Active Inactive Inactive Inactive Hold ResetInterrupt

Pseudo watch

(SPL = 1)

SCS=1MCS=0STP=1

Active Active Inactive Inactive Inactive HI-Z ResetInterrupt

Watch (SPL = 0)

SCS=xMCS=xTMD=0

Active Inactive Inactive Inactive Inactive Hold ResetInterrupt

Watch (SPL = 1)

SCS=xMCS=xTMD=0

Active Inactive Inactive Inactive Inactive HI-Z ResetInterrupt

Stop (SPL = 0)

MCS=1or SCS=0

STP=1

Inactive Inactive Inactive Inactive Inactive Hold ResetInterrupt

Stop (SPL = 1)

MCS=1or SCS=0

STP=1

Inactive Inactive Inactive Inactive Inactive HI-Z ResetInterrupt

103


Low Power Mode Control Register (LPMCR)

Clock Selection Register (CKSCR)

Figure 6.1-1 LPMCR/CKSCR

Access to the Low Power Mode Control Register

Switching to low power mode (including stop mode and sleep mode) is performed by writing tothe low power mode control register. Only the instructions listed in Table 6.1-2 "Instructions toBe Used for Switching to Low Power Mode" should be used for this purpose.

Note:

Switching to low power mode using an instruction not listed in Table 6.1-2 "Instructions to BeUsed for Switching to Low Power Mode" may cause a malfunction. However, any instructioncan be used to control functions of the low power mode control registers other than switchingto low power mode.

When word-length is used for writing to the low power mode control register, even-numberedaddresses must be used. Writing with odd-numbered addresses to switch to low powermode may cause a malfunction.

7 6 5 4 3 2 1 0

Address: 0000A0H STP RST TMD CG1 CG0 LPMCR

(W) (R/W) (W) (W) (R/W)(0) (0) (0) (1) (1) (0) (0)

(R/W)(0)

(W)

SPL

(-)

SLP

Bit No.


15 14 13 12 11 10 9 8

0000A1H SCM WS0 SCS MCS SC1 CKSCR

(R) (R/W) (R/W) (R/W) (R/W)(1) (1) (1) (1) (1) (0) (0)

(R/W)(1)

(R)

WS1

(R/W)

MCM CS0

Bit No.


Address:

Table 6.1-2 Instructions to Be Used for Switching to Low Power Mode

MOVMOVMOVMOVWMOVWMOVW

io,#imm8io,A@RLi+disp8,Aio,#imm16io,A@RLi+disp8,A

MOVMOVMOVPMOVWMOVWMOVPW

dir,#imm8dir,Aaddr24,Adir,#imm16dir,A addr24,A

MOVMOV

MOVWMOVW

eam,#imm8addr16,A

eam,#imm16addr16,A

MOVMOV

MOVWMOVW

eam,Rieam,A

eam,RWieam,A

SETB io:bp SETB dir:bp SETB addr16:bp

104

6.1 Low Power Mode

6.1.1 Sleep Mode

Sleep mode causes only the clock supplied to the CPU to stop while the CPU stops and peripheral circuits continue to operate.

Switching to Sleep Mode

Setting the SLP bit and TMD bit of the low power mode control register (LPMCR) to 1 and theSTP bit of the LPMCR to 0 causes the standby control circuit to switch to sleep mode.

If an interrupt request is generated when the SLP bit of the low power mode control register(LPMCR) is set to 1, the standby control circuit does not switch to sleep mode. If the CPU doesnot accept the interrupt, the CPU executes the next instruction. If the CPU accepts theinterrupt, CPU operation immediately branches to the interrupt processing routine.

In sleep mode, the contents of dedicated registers, such as accumulators, and internal RAM areretained.

Release of Sleep Mode

The standby control circuit releases sleep mode on input of a reset or generation of an interrupt.When sleep mode is released by a reset cause, the microcontroller is placed in the reset stateon release from sleep mode.

If an interrupt request of level 7 or higher is issued from a peripheral circuit and internalperipherals during sleep mode, the standby control circuit releases sleep mode. After sleepmode is released, the CPU handles the interrupt in the same way as any other normal interrupt.When an interrupt is accepted in accordance with the settings of the I flag of the condition coderegister (CCR), interrupt level mask register (ILM), and interrupt control register (ICR), the CPUexecutes interrupt processing. When the interrupt is not accepted, the CPU resumes executionwith the instruction that follows the instruction in which switching to sleep mode was specified.

Note:

When interrupt processing is executed, the CPU normally executes the instruction thatfollows the instruction in which switching to sleep mode was specified, then proceeds tointerrupt processing. If the switch to sleep mode occurs at the same time as the acceptanceof an external bus hold request, however, the CPU may proceed to interrupt processingbefore executing the next instruction.

105


6.1.2 Pseudo Watch Mode

Pseudo watch mode stops all microcontroller operations other than source oscillation (main clock and subclock), watch timer, and timebase timer. All other chip functions are stopped.

Switching to pseudo watch mode

Setting the SCS bit of the clock selection register (CKSCR) to 1, the MCS bit of CKSCR to 0and the TMD bit and STP bit of the low power mode control register (LPMCR) to 1 causes thestandby control circuit to switch to pseudo watch mode.

Whether the I/O pins retain the state they had immediately before switching to pseudo watchmode or enter high-impedance state is selected via the SPL bit of the low power mode controlregister (LPMCR).

If an interrupt request is generated when the STP bit of the low power mode control register(LPMCR) is set to 1, the standby control circuit does not switch to pseudo watch mode.

In pseudo watch mode, the contents of dedicated registers such as accumulators and internalRAM are retained.

Release of Pseudo Watch Mode

The standby control circuit releases pseudo watch mode on input of a reset or generation of aninterrupt. If pseudo watch mode is released by a reset cause, the microcontroller is placed inthe reset state after release from pseudo watch mode.

For return from pseudo watch mode, the standby control circuit releases pseudo watch mode,and then enters the PLL clock oscillation stabilization wait state. If release from pseudo watchmode is triggered by a reset cause, the reset sequence proceeds using the main clock.

If an interrupt request of level 7 or higher is issued from a peripheral circuit during pseudo watchmode, the standby control circuit releases pseudo watch mode. After pseudo watch mode isreleased, the CPU handles the interrupt in the same way as any other normal interrupt. Whenan interrupt is accepted in accordance with the settings of the I flag of the condition coderegister (CCR), interrupt level mask register (ILM), and interrupt control register (ICR), the CPUexecutes the instruction that follows the standby write instruction and then processes theinterrupt When the interrupt is not accepted, the CPU resumes execution with the instructionthat follows the instruction in which switching to pseudo watch mode was specified.

106

6.1 Low Power Mode

6.1.3 Watch Mode

Watch mode stops all microcontroller operations other than subclock oscillation and watch timer. All chip functions stop.

Switching to Watch Mode

Setting the TMD bit of the low power mode control register (LPMCR) to 0 causes the standbycontrol circuit to switch to watch mode.

Whether the I/O pins retain the state they had immediately before switching to pseudo watchmode or enter high-impedance state is selected via the SPL bit of the low power mode controlregister (LPMCR).

If an interrupt request is generated when the TMD bit of the low power mode control register(LPMCR) is set to 1, the standby control circuit does not switch to watch mode.

In watch mode, the contents of dedicated registers, such as accumulators, and internal RAMare retained.

Release of Watch Mode

The standby control circuit releases watch mode on input of a reset or generation of aninterrupt. If watch mode is released by a reset cause, the microcontroller is placed in the resetstate after release from watch mode.

For return from subclock watch mode, the standby control circuit releases watch mode andimmediately switches to subclock mode. If release from subclock watch mode is triggered by areset cause, the reset sequence proceeds using the subclock.

For return from main watch mode and PLL watch mode, the standby control circuit releaseswatch mode, and then enters the main clock oscillation stabilization wait state. If release fromwatch mode is triggered by a reset cause, the reset sequence proceeds using the subclock.

If an interrupt request of level 7 or higher is issued from a peripheral circuit during watch mode,the standby control circuit releases watch mode. After watch mode is released, the CPUhandles the interrupt in the same way as any other interrupt. When an interrupt is accepted inaccordance with the settings of the I flag of the condition code register (CCR), interrupt levelmask register (ILM), and interrupt control register (ICR), the CPU executes the instruction thatfollows the standby write instruction and then processes the interrupt. When the interrupt is notaccepted, the CPU resumes execution with the instruction that follows the instruction in whichswitching to watch mode was specified.

Note:

• When interrupt processing is executed, the CPU normally executes the instruction thatfollows the instruction in which switching to watch mode was specified, then proceeds tointerrupt processing. If the switch to watch mode occurs at the same time an external bushold request is accepted, however, the CPU may proceed with interrupt processing beforeexecuting the next instruction.

• When watch mode is released, the standby control circuit enters the PLL clock oscillationstabilization wait state. If the PLL clock is not used, change the MCS bit to 1 with theinstruction that is executed immediately after the reset or return from the interrupt.

107


6.1.4 Stop Mode

Stop mode causes the source oscillation (main clock and subclock) to stop. All chip functions stop. This mode enables data to be retained with power consumption kept to a minimum.

Switching to Stop Mode

Setting the SCS bit of the clock selection register (CKSCR) to 0 or setting the MCS bit ofCKSCR to 1 and setting the STP bit of the low power mode control register (LPMCR) to 1causes the standby control circuit to switch to stop mode.

Selection of whether the I/O pins retain the state they had immediately before switching topseudo watch mode or enter high-impedance state is subject to the SPL bit of the low powermode control register (LPMCR).

If an interrupt request is generated when the STP bit of the low power mode control register(LPMCR) is set to 1, the standby control circuit does not switch to stop mode.

In stop mode, the contents of dedicated registers, such as accumulators, and internal RAM areretained.

In stop mode, the external bus hold function is deactivated, and hold requests are not acceptedwhen input. If a hold request is input during switching to stop mode, the HAKX signal may notbe set to low when the bus is in Hi-Z state.

Release of Stop Mode

The standby control circuit releases stop mode on input of a reset or generation of an interrupt.If stop mode is released by a reset cause, the microcontroller is placed in reset state afterrelease from stop mode.

For return from subclock stop mode, the standby control circuit enters the subclock oscillationstabilization wait state, then releases stop mode. If release from stop mode is triggered by areset cause, the reset sequence proceeds after the subclock oscillation stabilization wait intervalhas elapsed.

For return from main stop mode, the standby control circuit enters the main clock oscillationstabilization wait state, then releases stop mode. If release from stop mode is triggered by areset cause, the reset sequence proceeds after the main clock oscillation stabilization waitinterval has elapsed.

If an interrupt request of level 7 or higher is issued from a peripheral circuit during stop mode,the standby control circuit releases stop mode. After subclock stop mode is released, the CPUhandles the interrupt in the same way as any other interrupt after the subclock oscillationstabilization wait interval has elapsed. When an interrupt is accepted in accordance with thesettings of the I flag of the condition code register (CCR), interrupt level mask register (ILM),and interrupt control register (ICR), the CPU executes the instruction that follows the standbywrite instruction and the processes the interrupt. When the interrupt is not accepted, the CPUresumes execution with the instruction that follows the instruction in which switching to stopmode was specified.

After main stop mode is released, the CPU handles the interrupt in the same way as any otherinterrupt after the main clock oscillation stabilization wait interval specified via the WS1 andWS0 bits of the clock selection register (CKSCR) has elapsed. When an interrupt is accepted inaccordance with the settings of the I flag of the condition code register (CCR), interrupt levelmask register (ILM), and interrupt control register (ICR), the CPU executes the instruction that

108

6.1 Low Power Mode

follows the standby write instruction and then processes the interrupt. When the interrupt is notaccepted, the CPU resumes execution with the instruction that follows the instruction in whichswitching to stop mode was specified.

Note:

When interrupt processing is executed, the CPU normally executes the instruction thatfollows the instruction in which switching to stop mode was specified, then proceeds withinterrupt processing. If the switch to stop mode occurs at the same time an external bushold request is accepted, however, the CPU may proceed with interrupt processing beforeexecuting the next instruction.

109


6.1.5 CPU Intermittent Operation Function

The CPU intermittent operation function enables processing to be executed with power consumption levels kept low.

CPU Intermittent Operation Function

The CPU intermittent operation function halts the clock supplied to the CPU for a certain period,to access a register, internal memory, internal peripherals, or the external bus. Internal buscycle activation is therefore delayed. While high-speed clock pulses are supplied to internalperipherals, the rate of CPU execution is reduced, enabling processing with power consumptionlevels kept low. The CG1 and CG0 is used to select the number of halt cycles of the clock to besupplied to the CPU.

External bus operation uses the same clock as that used for peripherals.

Instruction execution time using the CPU intermittent operation function can be calculated asfollows: Obtain a correction value by multiplying the number of times instructions that access aregister, internal memory, internal peripherals, and external bus are executed by the number ofhalt cycles. Add this correction value to the normal execution time.

Peripheral clock

CPU clock

Halt cycle for intermittent operation Internal bus activation cycle

110

6.1 Low Power Mode

6.1.6 Main Clock Oscillation Stabilization Wait Interval Setting

The WS1 bit and WS0 bit are used to select the main clock oscillation stabilization wait interval when stop mode is released.

Main Clock Oscillation Stabilization Wait Interval Setting

Select the oscillation stabilization wait interval in accordance with the types and characteristicsof the oscillation circuits and oscillation elements connected to the X0 and X1 pins.

Only a power-on reset initializes these bits. When a power-on reset occurs, these bits areinitialized to "11". At power-on, the main clock oscillation stabilization wait interval is

approximately a count of 218 source oscillations.

111


6.1.7 Machine Clock Switching

Writing the MCS bit and SCS bit of the CKSCR register switches the machine clocks. This section also explains machine clock initialization.

Switching between Main Clock and PLL Clock

Writing the MCS bit of the CKSCR register switches between the main clock and PLL clock.

When the MCS bit is 1 and set to 0, the switch from the main clock to a PLL clock occurs afterthe PLL clock oscillation stabilization interval (212 machine clocks).

When the MCS bit is 0 and 1 is written to it, the switch from the PLL clock to the main clockoccurs when the edges of the PLL clock and main clock coincide (after 1 to 8 PLL clocks).

Even when the MCS bit is rewritten, machine clock switching does not occur immediately. Tooperate the peripherals that rely on the machine clock, verify beforehand that machine clockswitching has been performed by referencing the MCM bit.

Switching between Main clock and Subclock

Writing the SCS bit of the CKSCR register switches between the oscillation clock and subclock.

When the SCS bit is 1 and set to 0, the switch from the main clock to subclock occurs when theedge of the subclock is detected.

When the SCS bit is 0 and set to 1, the switch from the subclock to main clock occurs after theoscillation stabilization wait interval of the main clock.

Even when the SCS bit is rewritten, machine clock switching does not occur immediately. Tooperate the peripherals that rely on the machine clock, verify in advance that machine clockswitching has been performed by referencing the SCS bit.

Machine Clock Initialization

The MCS bit and SCS bit are not initialized by the resets triggered by the external pin and theRST bit. They are initialized to 1 by other resets.

112

6.2 Transition Conditions for Low Power Mode


In low power mode, transition to and from statuses is based on the conditions set in the clock selection register and low power mode control register.

Transition Conditions for Low Power Mode

Table 6.2-1 "Transition Conditions" lists transition conditions.

The meanings of the codes in the table are explained below.

• MCS: MCS bit (clock selection register) (when MSC = 0, PLL clock mode is selected.)

• SCS: SCS bit (clock selection register) (when SCS = 0, subclock mode is selected.)

• STP: STP bit (low power mode control register) (when STP = 1, stop mode is selected.)

• SLP: SLP bit (low power mode control register) (when SLP = 1, sleep mode is selected.)

• TMD: TMD bit (low power mode control register) (when TMD = 0, watch mode is selected.)

• MCM: MCM bit (clock selection register) (when MCM = 0, the PLL clock is busy.)

• SCM: SCM bit (clock selection register) (when SCM = 0, subclock is busy.)

• SCD: Subclock oscillation stop (when SCD = 1, subclock oscillation stops.)

• MCD: Main clock oscillation stop (when MCD = 1, main clock oscillation stops.)

• PCD: PLL clock oscillation stop (when PCD = 1, PLL clock oscillation stops.)

Table 6.2-1 Transition Conditions

Status before transition Transition condition Status after transition

Power-on 01 Main clock oscillation stabilization wait interval ends.

Main clock mode

Main clock oscillation stabilization

05 Main clock oscillation stabilization wait interval ends.

Main clock mode

Main clock mode 06 SCS = 0 is written. MS transition mode

07 SCS = 1 and MCS = 0 are written. MP transition mode

31 TMD = 1, STP = 0, and SLP = 1 are written. Main sleep

32 TMD = 0 is written. Main watch transition

33 TMD = 1 and STP = 1 are written. Main stop

113


PLL clock mode 21 SCS = 0 is written. PS transition mode

20 SCS = 1 and MCS = 1 are written. PM transition mode

59 TMD = 1, STP = 0, and SLP = 1 are written. PLL sleep

58 TMD = 0 is written. PLL watch transition P

57 TMD = 1 and STP = 1 are written. Pseudo watch transition

Subclock mode 10 SCS = 1 and MCS = 1 are written. SM transition mode

12 SCS = 1 and MCS = 0 are written. SP transition mode

11 Reset activation Main clock oscillation stabilization

42 TMD = 1, STP = 0, and SLP = 1 are written. Subclock sleep

43 TMD = 0 is written. Subclock watch

44 TMD = 1 and STP = 1 are written. Subclock stop

PM transition mode 13 PLL clock to main clock switch timing wait ends. Main clock mode

38 TMD = 1, STP = 0, and SLP = 1 are written. PM transition sleep

39 TMD = 0 is written & PLL clock to main clock switch wait ends.

Main watch transition

40 TMD = 1 and STP = 1 are written and PLL clock to main clock switch wait ends.

Main stop

SM transition mode 02 Main clock oscillation stabilization wait interval ends.

Main clock mode

03 Reset activation or interrupt Main oscillation stabilization

04 SCS = 0 is written. Subclock mode

27 TMD = 1, STP = 0, and SLP = 1 are written. SM transition sleep

28 TMD = 0 is written and main clock oscillation stabilization wait interval ends.

Main watch

29 TMD = 1 and STP = 1 are written and main clock oscillation stabilization wait interval ends.

Main stop

Table 6.2-1 Transition Conditions (Continued)


114


MP transition mode 16 PLL clock oscillation stabilization wait interval ends.

PLL clock mode

14 SCS = 1 and MCS = 1 are written. Main clock mode

15 SCS = 0 is written. MS transition mode

68 TMD = 1, STP = 0, and SLP = 1 are written. MP transition sleep

70 TMD = 0 is written. PL watch transition M

69 TMD = 1 and STP = 1 are written. Pseudo watch mode

SP transition mode 17 Main clock oscillation stabilization wait ends. MP transition mode

18 MCS = 1 is written. SM transition mode

19 Reset activation Main oscillation stabilization

75 TMD = 1, STP = 0, and SLP = 1 are written. SP transition sleep

76 TMD = 0 is written. PLL watch

78 TMD = 1 and STP = 1 are written and main clock oscillation stabilization wait ends.

Pseudo watch mode

MS transition mode 09 Main clock to subclock switch timing wait ends. Subclock mode

08 Reset activation Main clock mode

51 TMD = 1, STP = 0, and SLP = 1 are written. MS transition sleep

52 TMD = 0 is written and main clock to subclock switch wait ends.

Subclock watch

53 TMD = 1 and STP = 1 are written and main clock to subclock switch wait ends.

Subclock stop

PS transition mode 23 PLL clock to main clock switch timing wait ends. MS transition mode

22 SCS = 1 is written. PM transition mode

56 TMD = 1, STP = 0, and SLP = 1 are written. SP transition sleep

Main sleep 26 Interrupt or reset activation Main clock mode

SM transition sleep 24 Main clock oscillation stabilization wait ends. Main sleep

25 Interrupt or reset activation SM transition mode

PM transition sleep 34 PLL clock to main clock switch timing wait ends. Main sleep

35 Interrupt or reset activation PM transition mode

PLL sleep 63 Interrupt or reset activation PLL clock mode

MP transition sleep 66 PLL clock oscillation stabilization wait ends. PLL sleep

67 Interrupt or reset activation MP transition mode



115


SP transition sleep 73 Main clock oscillation stabilization wait ends. MP transition sleep

74 Interrupt or reset activation SP transition mode

Subclock sleep 46 Interrupt or reset activation Subclock mode

MS transition sleep 49 Main clock to subclock switch timing wait ends. Subclock sleep

50 Interrupt or reset activation MS transition mode

SP transition sleep 54 PLL clock to main clock switch timing wait ends. MS transition sleep

55 Interrupt or reset activation PS transition mode

Main watch 30 Interrupt or reset activation SM transition mode

Main watch transition 36 Main watch

37 Interrupt or reset activation Main clock mode

PLL watch 77 Interrupt or reset activation SP transition mode

PLL watch transition M 72 Main clock to subclock switch timing wait ends. PLL watch

71 Interrupt or reset activation MP transition mode

PLL watch transition P 65 PLL watch transition M

64 Interrupt or reset activation PLL clock mode

Subclock watch 47 Interrupt or reset activation Subclock mode

Main stop 41 Interrupt or reset activation Main clock oscillation stabilization

Pseudo watch 62 Interrupt or reset activation MP transition mode

Pseudo watch transition 61 PLL clock to main clock switch timing wait ends. Pseudo watch mode

60 Interrupt or reset activation PLL clock mode

Subclock stop 48 Interrupt Subclock oscillation stabilization


Subclock oscillation stabilization

45 Subclock oscillation stabilization wait ends. Subclock mode




116

6.3 Status Transition Diagrams for Low Power Mode


Figure 6.3-1 "Status Transition Diagram A for Low Power Mode" to Figure 6.3-4 "Status Transition Diagram D for Low Power Mode" provide status transition diagrams for low power mode. The status transition diagrams show a step-by-step transition of events that occur simultaneously to simplify the explanation. In reality, status transition takes place immediately.

Status Transition Diagram for Low Power Mode

The status diagram shows that, if MSC = 1 and SLP = 1 are set at the same time in PLL clockmode, transition to PM transition mode is followed by transition to PM transition sleep. In reality,transition from PLL clock mode to PM transition sleep takes place immediately. The statusdiagream shows also that, if a reset is activated in subclock sleep mode, transition to subclockmode is followed by transition to a main clock oscillation stabilization period. In reality, transitionfrom subclock sleep mode to the main clock oscillation stabilization period takes placeimmediately.

117


Figure 6.3-1 Status Transition Diagram A for Low Power Mode

03SCS=1,MCS=1, SCS=1,MCS=1, SCS=1,MCS=1,STP=0,SLP=0, STP=0,SLP=0, STP=0,SLP=0,TMD=1 TMD=1 TMD=1SCM=1,MCM=1, SCM=0,MCM=1, 04 SCM=1,MCM=1,SCD=0,MCD=0, SCD=0,MCD=0, SCD=0,MCD=0,PCD=1 PCD=1 PCD=102

01 05

10

11

SCS=1,MCS=1, SCS=1,MCS=x, SCS=0,MCS=x,STP=0,SLP=0, 06 STP=0,SLP=0, 09 STP=0,SLP=0,TMD=1 TMD=1 TMD=1SCM=1,MCM=1, 08 SCM=1,MCM=1, SCM=0,MCM=1,SCD=0,MCD=0, SCD=0,MCD=0, SCD=0,MCD=1,PCD=1 PCD=1 PCD=1

07 12

18 19

13 15

SCS=1,MCS=1, 14 SCS=1,MCS=0, SCS=1,MCS=0,STP=0,SLP=0, STP=0,SLP=0, 17 STP=0, SLP=0,TMD=1 TMD=1 TMD=1SCM=1,MCM=0, SCM=1,MCM=1, SCM=0,MCM=1,SCD=0,MCD=0, SCD=0,MCD=0, SCD=0,MCD=0,PCD=1 PCD=1 PCD=1

16

2320

SCS=1,MCS=0, 22 SCS=0,MCS=x,STP=0,SLP=0, STP=0,SLP=0,TMD=1 21 TMD=1SCM=1,MCM=0, SCM=1,MCM=0,SCD=0,MCD=0, SCD=0,MCD=0,PCD=0 PCD=0

Power-on reset SM transition mode Main clock oscillation stabilization period

Main clock mode MS transition mode Subclock mode

PM transition mode MP transition mode SP transition mode

PLL clock mode PS transition mode

118


Figure 6.3-2 Status Transition Diagram B for Low Power Mode

SCS=1,MCS=1, SCS=1,MCS=1,STP=0,SLP=1, STP=0,SLP=1,TMD=1 TMD=1 26SCM=0,MCM=1, 24 SCM=1,MCM=1,SCD=0,MCD=0, SCD=0,MCD=0,PCD=1 PCD=1

25

27 31

28SCS=1,MCS=1, SCS=1,MCS=1, SCS=1,MCS=1,STP=0,SLP=0, STP=0,SLP=0, STP=0,SLP=0,TMD=1 TMD=0 TMD=1SCM=0,MCM=1, 30 SCM=0,MCM=1, SCM=1,MCM=1,SCD=0,MCD=0, SCD=0,MCD=1, SCD=0,MCD=1,PCD=1 PCD=1 PCD=1

3229 03 33

3734 36 05

SCS=1,MCS=1, SCS=1,MCS=1, SCS=1,MCS=1,STP=0,SLP=1, STP=0,SLP=0, STP=0,SLP=0,TMD=1 TMD=0 TMD=1SCM=1,MCM=0, SCM=1,MCM=1, SCM=1,MCM=1,SCD=0,MCD=0, SCD=0,MCD=0, SCD=0,MCD=0,PCD=0 PCD=1 PCD=1

35

38

39

SCS=1,MCS=1, SCS=1,MCS=1, 41STP=0,SLP=0, STP=1,SLP=0,TMD=1 40 TMD=1SCM=1,MCM=0, SCM=1,MCM=1,SCD=0,MCD=0, SCD=1,MCD=1,PCD=0 PCD=1

SM transition sleep Main sleep

SM transition mode Main watch Main clock mode

PM transition sleep Main watch transition Main clock oscillation stabilization interval

PM transition mode Main stop

119


Figure 6.3-3 Status Transition Diagram C for Low Power Mode

45 80SCS=0,MCS=x, SCS=1,MCS=x, SCS=1,MCS=x,STP=0,SLP=0, STP=0,SLP=0, STP=0,SLP=0,TMD=1 TMD=1 TMD=1SCM=0,MCM=1, SCM=0,MCM=1, SCM=1,MCM=1,SCD=0,MCD=1, 44 SCD=0,MCD=1, SCD=0,MCD=0,PCD=1 PCD=1 PCD=1

42 43

46 48 79

SCS=1,MCS=x, SCS=1,MCS=x, SCS=0,MCS=x,STP=0,SLP=1, 47 STP=0,SLP=0, STP=1,SLP=0,TMD=1 TMD=0 TMD=1SCM=0,MCM=1, SCM=0,MCM=1, SCM=0,MCM=1,SCD=0,MCD=1, SCD=0,MCD=1, SCD=1,MCD=1,PCD=1 PCD=1 PCD=1

49 5253

51SCS=0,MCS=x, SCS=0,MCS=x,STP=0,SLP=1, STP=0,SLP=0,TMD=1 TMD=1SCM=1,MCM=1, SCM=1,MCM=1,SCD=0,MCD=0, SCD=0,MCD=0,PCD=1 50 PCD=1

2354

56SCS=1,MCS=x, SCS=0,MCS=x,STP=0,SLP=1, STP=0,SLP=0,TMD=1 TMD=1SCM=1,MCM=0, SCM=1,MCM=0,SCD=0,MCD=0, SCD=0,MCD=0,PCD=0 55 PCD=0

Subclock mode Subclock oscillation stabilization interval

Main clock oscillation stabilization interval

Subclock sleep Subclock watch Subclock stop

MS transition sleep MS transition mode

PM transition sleep PM transition mode

120


Figure 6.3-4 Status Transition Diagram D for Low Power Mode

60SCS=1,MCS=0, SCS=1,MCS=0, 61 SCS=1,MCS=0,STP=0,SLP=0, STP=1,SLP=0, STP=1,SLP=0,TMD=1 57 TMD=1 TMD=1SCM=1,MCM=0, SCM=1,MCM=1, 62 SCM=1,MCM=1,SCD=0,MCD=0, 58 SCD=0,MCD=0, SCD=0,MCD=0,PCD=0 PCD=0 PCD=1

59

63

SCS=1,MCS=0, SCS=1,MCS=0,STP=0,SLP=1, STP=0,SLP=0,TMD=1 TMD=0SCM=1,MCM=0, SCM=1,MCM=0,SCD=0,MCD=0, SCD=0,MCD=0,PCD=1 PCD=0

65

16

66 69

68 71SCS=1,MCS=0, SCS=1,MCS=0, SCS=1,MCS=0,STP=0,SLP=1, STP=0,SLP=0, STP=0,SLP=0,TMD=1 TMD=1 TMD=0SCM=1,MCM=1, 67 SCM=1,MCM=1, 70 SCM=1,MCM=1,SCD=0,MCD=0, SCD=0,MCD=0, SCD=0,MCD=0,PCD=0 PCD=0 PCD=1

7873 17 72

75 77SCS=1,MCS=0, SCS=1,MCS=0, SCS=1,MCS=0,STP=0,SLP=1, STP=0,SLP=0, STP=0,SLP=0,TMD=1 TMD=1 TMD=0SCM=0,MCM=1, SCM=0,MCM=1, SCM=0,MCM=1,SCD=0,MCD=0, SCD=0,MCD=0, SCD=0,MCD=1,PCD=1 74 PCD=1 76 PCD=1

PLL clock mode Pseudo watch transition

Pseudo watch mode

PLL sleep PLL watch transition P

MS transition sleep MP transition mode PLL watch transition M

SP transition sleep SP transition mode PLL watch

121


122

CHAPTER 7 MEMORY ACCESS MODE

This chapter explains the functions and operation of the memory access mode.

7.1 "Overview of Memory Access Mode"

7.2 "External Memory Access (External Bus Pin Control Circuit)"

7.3 "Operation of External Memory Access Control Signals"

123


7.1 Overview of Memory Access Mode

The F2MC-16L supports a variety of modes for controlling access method and access areas.

Overview of Memory Access Mode

Operating modes

The operating modes control the operating status of the device. An operating mode is specifiedby the mode pin (MDx) and the M1 and M0 bits of mode data. Selecting the operating modesenables start of normal operation and writing to EPROM.

Bus modes

The bus modes control the operation of internal ROM and external access functions. A busmode is specified by the contents of mode pin (MDx) and Mx bit of mode data. The mode pin(MDx) specifies a bus mode to read reset vector and mode data. The Mx bit of mode dataspecifies a bus mode for normal operation.

Access modes

The access modes control the external data bus width. An access mode is specified by themode pin (MDx) and the S0 bit of mode data. Selecting an access mode specifies whether theexternal data bus has a width of 8 or 16 bits.

Table 7.1-1 Memory Access Mode

Operating mode Bus mode Access mode (external data bus width)

RUN Single-chip -

Internal ROM external bus

8 bits

16 bits

External ROM external bus

8 bits

16 bits

Flash write - -

Tests - -

124


7.1.1 Mode Pins

Three external pins, MD2 to MD0, can be combined to specify the operation listed in Table 7.1-2 "Mode Pins and Modes".

Mode Pins

Table 7.1-2 Mode Pins and Modes

Mode pin setting Mode name Reset vector access area

External data bus width

Remarks

MD2 MD1 MD0

0 0 0 External vector mode 0 External 8 bits

0 0 1 External vector mode 1 External 16 bits 16-bit bus width access for reset vector

0 1 0 External vector mode 2 External 16 bits 8-bit bus width access for reset vector

0 1 1 Internal vector mode External (Mode data) Reset sequence and subsequent sequence are controlled by mode data.

1 0 0 Setting not allowed

1 0 1

1 1 0 Flash serial write - -

1 1 1 Flash memory mode - - Mode for using the parallel writer

Note: • Even though external vector mode 0 is selected, the IOBS and LMBS bits of the bus control signal selection register are initially set to 0. The external data bus width is 16 bits in the area from 0000C0H to 0000FFH and area from 002000H to 7FFFFFH.To set the external data bus width to 8 bits in these areas, set the IOBS and LMBS bits of the bus control signal selection register to 1. If external vector mode 1 is selected, the HMBS bit is set to 0 and a bus width of 16 bits is used for access.

• Serial write operations to flash memory cannot be performed with the settings of mode pins alone. Other pins must also be set. For details, see the connection example for flash serial write.

125


7.1.2 Mode Data

The mode data is located in main memory at FFFFDF H, and is used to control the CPU

operation. During execution of the reset sequence, the mode data is fetched and stored in the mode register of the device. The values of the mode register can only be changed during the reset sequence.The settings in this register take effect after the reset sequence.Always set reserved bits to 0.

Mode Data

Figure 7.1-1 Structure of Mode Data

[Bits 6 and 7] M1 and M0 (bus mode setting bit)

M1 and M0 bits specify the operating modes after the reset sequence. Table 7.1-3 "Functionof Bus Mode Setting Bits (M1 and M0)" lists the relationship between M1 and M0 bits andfunctions.

[Bit 3] S0 (access mode setting bit)

The S0 bit specifies the bus mode or access mode after the reset sequence. Table 7.1-4"Function of Access Mode Setting Bit (S0)" lists the relationship between the S0 bit andfunction.

7 6 5 4 3 2 1 0

M1 S0M0Mode data

Bit No.

Reserved Reserved Reserved Reserved Reserved

Function extension bit (reserved area)The various mode setting bits

Bus mode setting bit

Table 7.1-3 Function of Bus Mode Setting Bits (M1 and M0)

M1 M0 Function

0 0 Single-chip mode

0 1 Internal ROM external bus mode

1 0 External ROM external bus mode

1 1 Setting not allowed

Table 7.1-4 Function of Access Mode Setting Bit (S0)

S0 Function

0 External data bus 8-bit mode

1 External data bus 16-bit mode

126


7.1.3 Memory Space for Each Bus Mode

Figure 7.1-2 "Relationship between Access Areas and Physical Addresses in Each Bus Mode" shows the correspondence between the access areas and physical addresses in each bus mode.

Memory Space for Each Bus Mode

As listed in Table 7.1-2 "Mode Pins and Modes", the ROM contents in the FF bank can bereferenced as an image in the upper region of the 00 bank. This is implemented so as to usethe small model of the C compiler more effectively. Since the lower 16 bits become the same,the tables in ROM can be referenced without specifying "Far" in the pointer declaration.

For example, when 00C000H is accessed, the contents of the ROM at FFC000H are actuallyaccessed. Since the ROM area in the FF bank exceeds 48 KB, not all areas can be referencedvia an image in the 00 bank. Only ROM data at FF4000H to FFFFFFH can be referenced via animage from 004000H to 00FFFFH. We recommend storing the ROM data table in the area fromFF4000H to FFFFFFH.

127


Figure 7.1-2 Relationship between Access Areas and Physical Addresses in Each Bus Mode

FFFFFFH

ROM

ROM

RAM

ROM

ROM

RAM RAM

FE0000H

010000H

002000H

000100H

0000C0H

000000H

004000H

Address #1 for each model

Address #2 for each model

Address #3for each model


Single-chip Internal ROM external bus

External ROMexternal bus

: Internal access

: External access


Note: The "Address for each model" depends on the model.


MB90652A

MB90653A

MB90P653A

MB90V650A

MB90654A

MB90F654A

FF0000H

FE0000H

FE0000H

(FE0000H)

FC0000H

FC0000H

004000H

004000H

004000H

004000H

004000H

004000H

000CFFH

0014FFH

0014FFH

0018FFH

0020FFH

0020FFH

128


Example of Recommended Settings for Memory Space in each Bus Mode

Table 7.1-5 "Example of Recommended Mode Pin and Mode Data Settings" contains anexample of recommended mode pin and mode data settings.

The input-output signals for external pins connected in memory access mode depend on themode.

Table 7.1-5 Example of Recommended Mode Pin and Mode Data Settings

Setting example MD2 MD1 MD0 M1 M0 S0

Single-chip mode 0 1 1 0 0 X

Internal ROM external bus mode with 16-bit bus 0 1 1 0 1 1

Internal ROM external bus mode with 8-bit bus 0 1 1 0 1 0

External ROM external bus mode with 16-bit bus and vector 16-bit bus width

0 0 1 1 0 1

External ROM external bus mode with 16-bit bus and vector 8-bit bus width

0 1 0 1 0 1

External ROM external bus mode with 8-bit bus 0 0 0 1 0 0

Table 7.1-6 Operation of External Pins in Various Modes

Pin name Function

Single-chip External bus extended EPROM programming

8-bit 16-bit

P07 to 00 Port AD07 to 00 D07 to 00

P17 to 10 A15 to 08 AD15 to 08 A15 to 08

P27 to 20 A23 to 16 A07 to 00

P30 ALE A16

P31 RDX CEX

P32 WRX* WRLX* OEX

P33 Port WRHX* PGMX

P34 HRQ* Unused

P35 HAKX*

P36 RDY*

P37 CLK*

*: The upper address bits and WRX, WRLX, WRHX, HRQ, HAKX, RDY, and CLK can be used as ports depending on the selected functions. For details, see Section 7.2 "External Memory Access (External Bus Pin Control Circuit)."

129


7.2 External Memory Access (External Bus Pin Control Circuit)

The external bus pin control circuit controls the external bus pins for extending the CPU address and data buses externally.

External Memory Access (External Bus Pin Control Circuit)

To access external memory and peripherals, the F2MC-16L supplies the following address,data, and control signals:

• CLK (P37): Machine cycle clock (KBP) output

• RDY (P36): External ready input pin

• WRHX (P33): Write signal for upper 8 bits of data bus

• WRLX (P32): Write signal for lower 8 bits of data bus

• RDX (P31): Read signal

• ALE (P30): Address latch enable signal

Block Diagram of External Memory Access (External Bus Pin Control Circuit)

Figure 7.2-1 "Block Diagram of External Memory Access (External Bus Pin Control Circuit)"provides a block diagram of external memory access (external bus pin control circuit).

Figure 7.2-1 Block Diagram of External Memory Access (External Bus Pin Control Circuit)

P3P2

P1 P3P0

P0

RB

P0 data

P0 direction

Data control

Address control

Access controlAccess control

130


7.2.1 External Memory Access (External Bus Pin Control Circuit) Registers

The following three types of registers are available for external memory access (external bus pin control circuit):• Automatic ready function selection register• Higher address control register • Bus control signal selection register

External Memory Access (External Bus Pin Control Circuit) Register

Figure 7.2-2 External Memory Access (External Bus Pin Control Circuit) Register

15 14 13 12 11 10 9 8

0000A5H IOR1 IOR0 HMR1 HMR0 LMR1 LMR0 ARSR

(W) (W) (W) (W) (-) (-) (W) (W)(0) (0) (1) (1) (-) (-) (0) (0)

7 6 5 4 3 2 1 0

0000A6H E23 E22 E21 E20 E19 E18 E17 E16 HACR

(W) (W) (W) (W) (W) (W) (W) (W)(0) (0) (0) (0) (0) (0) (0) (0)

15 14 13 12 11 10 9 8

0000A7H CKE RYE HDE IOBS HMBS WRE LMBS ECSR

(W) (W) (W) (W) (W) (W) (W) (-)(0) (0) (0) (0) (0) (0) (0) (-)

Automatic ready function selection registerBit No.

Bit No.

Bit No.

Address:

Address:

Address:

Read/write

Read/write

Read/write

Initial value

Initial value

Initial value

131


7.2.2 Automatic Ready Function Selection Register (ARSR)

The automatic ready function selection register (ARSR) is used to set the automatic wait time for memory access to each area during external access.

Automatic Ready Function Selection Register (ARSR)

Figure 7.2-3 Configuration of Automatic Ready Function Selection Register

[Bits 15 and 14] IOR1 and IOR0

The IOR1 and IOR0 bits specify the automatic wait function for external access to the areafrom 0000C0H to 0000FFH. Table 7.2-1 "Function of Automatic Wait Function SpecificationBits (IOR1 and IOR0)" lists the settings made by the various combinations of IOR1 and IOR0bits.

[Bits 13 and 12] HMR1 and HMR0

The HMR1 and HMR0 bits specify the automatic wait function for external access to the areafrom 800000H to FFFFFFH. Table 7.2-2 "Function of Automatic Wait Function SpecificationBits (HMR1 and HMR0)" lists the settings made by combining the HMR1 and HMR0 bits.

15 14 13 12 11 10 9 8

0000A5H IOR1 IOR0 HMR1 HMR0 LMR1 LMR0 ARSR

(W) (W) (W) (W) (-) (-) (W) (W)(0) (0) (1) (1) (-) (-) (0) (0)

Bit No.

Address:


Automatic ready function selection register

Table 7.2-1 Function of Automatic Wait Function Specification Bits (IOR1 and IOR0)

IOR1 IOR0 Function

0 0 Automatic wait disabled [initial value*]

0 1 1-machine cycle automatic wait (external access)



*: The initial value is 00B.

132


[Bits 9 and 8] LMR1 and LMR0

The LMR1 and LMR0 bits specify the automatic wait function for external access to the areafrom 002000H to 7FFFFFH. Table 7.2-3 "Function of Automatic Wait Function SpecificationBits (LMR1 and LMR0)" lists the settings made by combining the LMR1 and LMR0 bits.

Table 7.2-2 Function of Automatic Wait Function Specification Bits (HMR1 and HMR0)

HMR1 HMR0 Function

0 0 Automatic wait disabled



1 1 3-machine cycle automatic wait (external access) [initial value*]


Table 7.2-3 Function of Automatic Wait Function Specification Bits (LMR1 and LMR0)

LMR1 LMR0 Function

0 0 Automatic wait disabled [initial value*]





133


7.2.3 Higher Address Control Register (HACR)

The higher address control register (HACR) is used to control the external output of address pins (A19 to A16). The bits correspond to addresses A19 to A16 and control address output pins as shown in Figure 7.2-4 "Configuration of Higher Address Control Register".

Higher Address Control Register (HACR)

Figure 7.2-4 Configuration of Higher Address Control Register

The higher address control register (HACR) cannot be accessed when the device is in single-chip mode. In single-chip mode, all pins function as I/O ports regardless of the value of thisregister.

All bits of the higher address control register are write-only bits. The value read from these bitsis 1.

These bits are initialized to 0 by a reset.

Note:

To set this register to control external output, always set DDR = 0.

7 6 5 4 3 2 1 0

0000A6H E23 E22 E21 E20 E19 E18 E17 E16 HACR

(W) (W) (W) (W) (W) (W) (W) (W)(0) (0) (0) (0) (0) (0) (0) (0)

Bit No.

Address:


Higher address control register

Table 7.2-4 Function of Higher Address Control Register (Bits E16 to E23)

E16 to 23 Function

0 The corresponding pin becomes the address output (AXX) [initial value].

1 The corresponding pin becomes an IO port (PXX).

134


7.2.4 Bus Control Signal Selection Register (ECSR)

The bus control signal selection register (ECSR) is used to set the function that controls bus operation in external bus mode. This register cannot be accessed when the device is in single-chip mode. In single-chip mode, all pins function as I/O ports regardless of the value of this register. All bits of the bus control signal selection register are write-only. The value read from these values is 1.

Bus Control Signal Selection Register (ECSR)

Figure 7.2-5 Configuration of Bus Control Signal Selection Register

[Bit 15] CKE

The CKE bit controls output of the external clock (CLK) as listed in Table 7.2-5 "Function ofExternal Clock (CLK) Output Control Bit (CKE)".

[Bit 14] RYE

The RYE bit controls input of external ready (RDY) as listed in Table 7.2-6 "Function ofExternal Ready (RDY) Input Control Bit (RYE)".

15 14 13 12 11 10 9 8

0000A7H CKE RYE HDE IOBS HMBS WRE LMBS ECSR

(W) (W) (W) (W) (W) (W) (W) (-)(0) (0) (0) (0) (0) (0) (0) (-)

Bit No.

Address:


Bus control signal selection register

Table 7.2-5 Function of External Clock (CLK) Output Control Bit (CKE)

CKE Function

0 I/O port (P37) operation (clock output disabled) [initial value]

1 Clock signal (CLK) output enabled

Table 7.2-6 Function of External Ready (RDY) Input Control Bit (RYE)

RDY Function

0 I/O port (P36) operation (external ready input disabled) [initial value]

1 External ready (RDY) input enabled

135


[Bit 13] HDE

The HDE bit enables or disables I/O operations of the pins related to the hold function. TheHDE bit is set to control hold request input pin (HRQ) and hold acknowledge output pin(HAKX) as listed in Table 7.2-7 "Function of Hold-Related Pin I/O Enable Bit (HDE)".

[Bit 12] IOBS

The IOBS bit specifies the data bus size for external access to the area from 0000C0H to0000FFH in external data bus 16-bit mode. This bit is set for control as listed in Table 7.2-8"Bus Size Specification Bit (IOBS)".

The IOBS bit is initialized to 0 by a reset.

[Bit 11] HMBS

The HMBS bit specifies the data bus size for external access to the area from 800000H toFFFFFFH in external data bus 16-bit mode. This bit is set for control as listed in Table 7.2-9"Function of Bus Size Specification Bit (HMBS)".

The HMBS bit is initialized to 0 by a reset if external vector mode 2 is selected. This bit isinitialized to 1 by a reset when another mode is selected.

[Bit 10] WRE

The WRE bit controls output of an external write signal (WRHX and WRLX pins in 16-bit busmode and WRX pin in 8-bit bus mode) as listed in Table 7.2-10 "Function of External WriteSignal Output Control Bit (WRE)".

In external data bus 8-bit mode, P33 functions as the I/O port regardless of the value set inthis bit.

The WRE bit is initialized to 0 by a reset. To set this register to control external output,always set DDR = 0.

Table 7.2-7 Function of Hold-Related Pin I/O Enable Bit (HDE)

HDE Function

0 I/O port (P35 and P34) operation (hold function I/O disabled) [initial value]

1 Hold request (HRQ) or hold acknowledge (HAKX) output enabled

Table 7.2-8 Bus Size Specification Bit (IOBS)

IOBS Function

0 Access with 16-bit bus width [initial value]

1 Access with 8-bit bus width

Table 7.2-9 Function of Bus Size Specification Bit (HMBS)

HMBS Function



136


[Bit 9] LMBS

The LMBS bit specifies the data bus size for external access to the area from 002000H to7FFFFFH in external data bus 16-bit mode. This bit is set for control as listed in Table 7.2-11"Function of Bus Size Specification Bit (LMBS)".

The LMBS bit is initialized to 0 by a reset.

Note:

• To set the WRE bit to enable the WRHX and WRLX functions in 16-bit bus mode, place P33and P32 in input mode (set bits 3 and 2 of DDR3 to 0).

• To set the WRE bit to enable the WRX function in 8-bit bus mode, place P32 in input mode(set bit 2 of DDR3 to 0).

• Even if the RYE and HDE bits are set to enable RDY and HRQ inputs, the I/O port functionof the port becomes effective. Always write 0 (input mode) to DDR3 corresponding to theport.

Table 7.2-10 Function of External Write Signal Output Control Bit (WRE)

WRE Function

0 I/O port (P33 and P32) operation (write signal output disabled) [initial value]

1 Write strobe signal (WRHX and WRLX or WRX only) output enabled

Table 7.2-11 Function of Bus Size Specification Bit (LMBS)

LMBS Function



137


7.3 Operation of External Memory Access Control Signals

When the ready function is not used, external memory is accessed in three machine cycles. In external 16-bit bus mode, when both a peripheral chip with a bus width of 8 bit and one with a bus width of 16 bit are concurrently connected to the external data bus, the access function for an 8-bit data bus can be used to read from, or write to the chip with the 8-bit data bus.

External Memory Access Control Signal

Since access with a data bus width of 8 bit is performed using the lower eight bits of the databus, the peripheral chip with the 8-bit bus should be connected to the lower eight bits of the databus.

The HMBS, LMBS, and IOBS bits of EPCR are used to specify whether to access with 16-bit or8-bit data bus width in external 16-bit bus mode.

Only address output and ALE assert output may be performed, and when RDX, WRX, WRLX,and WRHX are not asserted, the actual bus operation may not be performed. Be sure toprevent a peripheral chip from being accessed with the ALE signal alone.

Figure 7.3-1 "Timing Chart for External Memory Access (in External 8-bit Bus Mode)" is thetiming chart for external memory access (in external 8-bit bus mode), and Figure 7.3-2 "TimingChart for External Memory Access (in External 16-bit Bus Mode)" is the timing chart for externalmemory access (in external 16-bit bus mode).

Figure 7.3-1 Timing Chart for External Memory Access (in External 8-bit Bus Mode)

P37/CLK

P33/WRHX

P32/WRLX

P31/RDX

P30/ALE

P27 20/A23 16

P17 10/A15 08

P07 00/AD07 00

to

to

to

to

to

to

Read Write Read

(Port data)

Read address

Read address

Read address

Read address

Read address Read address

Write address

Write address

Write address

Read data Write data

138


Figure 7.3-2 Timing Chart for External Memory Access (in External 16-bit Bus Mode)

P37/CLK

P33/WRHX

P32/WRLX

P31/RDX

P30/ALE

P27 20/A23 16

P17 10/AD15 08

P07 00/AD07 00

P37/CLK

P33/WRHX

P32/WRLX

P31/RDX

P30/ALE

P27 20/A23 16

P17 10/AD15 08

P07 00/AD07 00

P37/CLK

P33/WRHX

P32/WRLX

P31/RDX

P30/ALE

P27 20/A23 16

P17 10/AD15 08

P07 00/AD07 00

Byte read with 8-bit bus Byte write with 8-bit busEven-numbered address

byte readEven-numbered address

byte write

Read address

Read address

Read address

Invalid

Write address

Write address

Write address

(Undefined)


Read address

Read address

Read address

Read address

Read address

Read address

Read address

Read address

Read address

Write address

Write address

Write address (Undefined)

Write address

Write address

Write address



Invalid

Read address

Read address

Read address

Read address

Read address

Read address

Odd-numbered address byte read

Odd-numbered addressbyte write

Even-numbered word read Even-numbered word write

to

to

to to

to

to

to

to

to to

to

to

Make the external circuit settings so that data is always read in words.Depending on the settings for the P36/RYD pin or the automatic ready function selection register (ARSR), access to low-speed memory and peripheral circuits is enabled.

to

to

to

to

to

to

139


7.3.1 Ready Function

Depending on the settings of the P36/RDY pin or automatic ready function selection register (ARSR), access to low-speed memory and peripheral circuits is enabled.When the RYE bit of the bus control signal selection register (EPCR) is set to 1, the wait state is retained while the L level is input to the P36/RDY pin during access to the external area. This allows extending the access cycle.

Ready Function

Figure 7.3-3 Timing Chart for Ready Function

The F2MC-16L provides two types of auto-ready functions for external memory. When accessto the external areas at lower addresses 002000H to 7FFFFFH and at upper addresses 800000Hto FFFFFFH occurs, the auto-ready function can extend the access cycle by automatically

P37/CLK

P33/WRHX

P32/WRLX

P31/RDX

P30/ALE

P27 20/A23 16

P17 10/AD15 08

P07 00/AD07 00

P36/RDY

P37/CLK

P33/WRHX

P32/WRLX

P31/RDX

P30/ALE

P27 20/A23 16

P17 10/AD15 08

P07 00/AD07 00

to

to

to to

to

to

to

to

to to

to

to

Read address

Read address

Read address

Write address

Write address

Write address

Read address

Read address

Read address

Write address

Write address

Write address


Write data

Even-numbered address word read Even-numbered address word write

Even-numbered address word write Even-numbered address word read

RDY pin fetch

Cycle extended by auto-ready

140


inserting wait cycles of one to three machine cycles without the need for an external circuit.This function is activated in accordance with the settings of the LMR1 and LMR0 bits of ARSR(external area at lower address) and HRM1 and HRM0 bits of ARSR (external area at upperaddress).

The F2MC-16L provides the auto-ready function for external I/O independently of the auto-readyfunction for memory. When access to the external area at addresses 0000C0H to 0000FFHoccurs, the auto-ready function can extend the access cycle by automatically inserting waitcycles of one to three machine cycles without the need for an external circuit. This function isactivated in accordance with the settings of the IOR1 and IOR0 bits of ARSR.

If the RYE bit of EPCR is set to 1, after the wait cycles inserted by the auto-ready functions forexternal memory and external I/O are completed, the wait cycles continue while the L level isinput to the P36/RDY pin.

141


7.3.2 Hold Function

When the HDE bit of the bus control signal selection register (EPCR) is set to 1, the external bus hold function can be activated by using the P34/HRQ and P35/HAKX pins.

Hold Function

When the H level is input to the P34/HRQ pin, the hold state is entered at the end of a CPUinstruction (at the end of processing for one item of element data in case of a string instruction).In the hold state, the L level is output from the P35/HAKX pin, and the following pins are set tohigh impedance state:

• Address output: P27/A23 to P20/A16

• Address/data I/O: P17/D15 to P00/D00

• Bus control signal: P30/ALE, P31/RDX, P32/WRLX, P33/WRHX

This enables the external circuits to use the external bus. Inputting the L level to the P34/HRQpin causes the P35/HAKX pin to output the H level, restores the external pin state, and restartsCPU operation. A hold request input is not accepted in stop mode.

Figure 7.3-4 "Timing Chart for the Hold Function (in External Bus 16-bit Mode)" is the timingchart for the hold function (in external bus 16-bit mode).

Figure 7.3-4 Timing Chart for the Hold Function (in External Bus 16-bit Mode)

P37/CLK

P34/HRQ

P35/HAKX

P33/WRHX

P32/WRLX

P31/RDX

P30/ALE

P27 20/A23 16

P17 10/AD15 08

P07 00/AD07 00

to

to

to to

to

to

Read cycle Hold cycle Write cycle

(Address) (Address)

(Address)

(Address)


142

CHAPTER 8 I/O PORTS

This chapter explains the functions of the I/O ports of the device.

8.1 "Overview of I/O Ports"

8.2 "I/O Port Registers"

143

CHAPTER 8 I/O PORTS

8.1 Overview of I/O Ports

Input or output can be specified for each pin of each port in accordance with the setting of the port direction register (DDR) when the corresponding peripheral is not set up to use the pin.

Overview of I/O Ports

When the port data register (PDR) is read at input, the level value of the pin is read. If the PDRis read at output, the latch value of the PDR is read. This applies also when the register is readwith the read-modify-write instruction.

When the PDR is read and the I/O port is used as control output, data output as the controloutput is read regardless of the value of the port direction register (DDR).

Before the setting is changed from input to output, a read-modify-write instruction (such as a bitset instruction) may be used to store output data in the PDR. In this case, note that data to beread is data input from the pin instead of the latch value of the PDR.

Figure 8.1-1 "Block Diagram of I/O Port" is a block diagram of an I/O port.

Figure 8.1-1 Block Diagram of I/O Port

Internal data bus

Data register read

PinData register

Data register write

Direction register

Direction register write

Direction register read

144

8.2 I/O Port Registers


Figure 8.2-1 "I/O Port Registers" shows the bit configuration of the I/O port registers.

I/O Port Registers

Figure 8.2-1 I/O Port Registers

15 / 7 14 / 6 13 / 5 12 / 4 11 / 3 10 / 2 9 / 1 8 / 0

Address : 000000 H P07 P06 P05 P04 P03 P02 P01 P00 Port 0 data register (PDR0)







Address : 000007 H P74 P73 P72 P71 P70 Port 7 data register (PDR7)

Address : 000008 H P86 P85 P84 P83 P82 P81 P80 Port 8 data register (PDR8)


Address : 00000AH PA2 PA1 PA0 Port A data register (PDRA)

15 / 7 14 / 6 13 / 5 12 / 4 11 / 3 10 / 2 9 / 1 8 / 0

Address : 000010 H D07 D06 D05 D04 D03 D02 D01 D00 Port 0 direction register (DDR0 )




Address : 000014 H D46 D45 D44 D43 D42 D41 D40 Port 4 direction register (DDR4 )



Address : 000017 H D74 D73 Port 7 direction register (DDR7 )

Address : 000018 H D86 D85 D84 D83 D82 D81 D80 Port 8 direction register (DDR8 )


Address : 00001AH DA2 DA1 DA0 Port A direction register (DDRA)

15 14 13 12 11 10 9 8

Address : 00001BH OD46 OD45 OD44 OD43 OD42 OD41 OD40 Port 4 pin register (ODR4)

15 / 7 14 / 6 13 / 5 12 / 4 11 / 3 10 / 2 9 / 1 8 / 0

Address : 00001CH RD0 7 RD06 RD05 RD04 RD03 RD02 RD01 RD00 Port 0 resistor register (RDR0)

Address : 00001DH RD1 7 RD16 RD15 RD14 RD13 RD12 RD11 RD10 Port 1 resistor register (RDR1)

Address : 00001EH RD6 7 RD66 RD65 RD64 RD63 RD62 RD61 RD60 Port 6 resistor register (RDR6)

15 14 13 12 11 10 9 8

Address : 00001FH ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 Port 5

Bit No.

Bit No.

Bit No.

Bit No.

analog input enable register(ADER)

145

CHAPTER 8 I/O PORTS

8.2.1 Port Data Register (PDR)

Figure 8.2-2 "Port Data Register (PDR)" shows the detailed bit configuration of the port data register (PDR).

Port Data Register (PDR)

Figure 8.2-2 Port Data Register (PDR)

Note that an R/W operation for an I/O port differs slightly from an R/W operation for memorywith respect to the following items:

7 6 5 4 3 2 1 0

P07 P06 P05 P04 P03 P02 P01 P00 Undefined R/W*

000000H

15 14 13 12 11 10 9 8


H

7 6 5 4 3 2 1 0


H

15 14 13 12 11 10 9 8

P37 P36 P35 P34 P33 P32 P31 P30 Undefined R/WH

7 6 5 4 3 2 1 0

P47 P46 P45 P44 P43 P42 P41 P40 1XXXXXXX R/W*

H

15 14 13 12 11 10 9 8


H

7 6 5 4 3 2 1 0


H

15 14 13 12 11 10 9 8

P74 P73 P72 P71 P70 XX111 R/W*

H

7 6 5 4 3 2 1 0

P86 P85 P84 P83 P82 P81 P80 Undefined R/W*

H

15 14 13 12 11 10 9 8


H

7 6 5 4 3 2 1 0

PA2 PA1 PA0 Undefined R/W*

H

PDR 0

Initial value Access

*: The R/W operation for an I/O port is slightly different from an R/W operation for memory.

address :

address :PDR 1

000001

PDR 2000002address :






PDR 8000008

PDR 9000009

PDR A00000A

address :

address :

address :

bit No.

bit No.

bit No.

bit No.

bit No.

bit No.

bit No.

bit No.

bit No.

bit No.

bit No.

146


Input mode

• Read: The corresponding pin level is read.

• Write: Data is written to the output latch.

Output mode

• Read: The latch value of the data register is read.

• Write: Data is output to the corresponding pin.

147

CHAPTER 8 I/O PORTS

8.2.2 Port Direction Register (DDR)

Figure 8.2-3 "Port Direction Register (DDR)" shows the bit configuration of the port direction register (DDR).

Port Direction Register (DDR)

Figure 8.2-3 Port Direction Register (DDR)

7 6 5 4 3 2 1 0

DDR0 D07 D06 D05 D04 D03 D02 D01 D00 00000000000010

15 14 13 12 11 10 9 8

DDR1 D17 D16 D15 D14 D13 D12 D11 D10 00000000000011

7 6 5 4 3 2 1 0

DDR 2 D27 D26 D25 D24 D23 D22 D21 D2 0 00000000000012

15 14 13 12 11 10 9 8

DDR3 D37 D36 D35 D34 D33 D32 D31 D30 00000000000013

7 6 5 4 3 2 1 0

DDR4 D46 D45 D44 D43 D42 D41 D40 0000000000014

15 14 13 12 11 10 9 8

DDR5 D57 D56 D55 D54 D53 D52 D51 D50 00000000000015

7 6 5 4 3 2 1 0

DDR6 D67 D66 D65 D64 D63 D62 D61 D60 00000000000016

15 14 13 12 11 10 9 8

DDR7 D74 D73 00000017

7 6 5 4 3 2 1 0

DDR8 D86 D85 D84 D83 D82 D81 D80 0000000000018

15 14 13 12 11 10 9 8

DDR9 D97 D96 D95 D94 D93 D92 D91 D90 00000000000019

7 6 5 4 3 2 1 0

DDRA DA2 DA1 DA0 000

R / W

R / W

R / W

R / W

R / W

R / W

R / W

R / W

R / W

R / W

R / W00001A

H

H

H

H

H

H

H

H

H

H

H

Bit No.

Bit No.

Bit No.

Bit No.

Bit No.

Bit No.

Bit No.

Bit No.

Bit No.

Bit No.

Bit No.

Initial value Access

B

B

B

B

B

B

B

B

B

B

BAddress:

Address:

Address:

Address:

Address:

Address:

Address:

Address:

Address:

Address:

Address:

148


If the pins function as port, the corresponding pins are controlled as follows:

• 0: Input mode

• 1: Output mode

The bit is initialized to 0 by a reset.

Ports 47 and 70 to 72 have no DDR. Data on these ports is always valid. To use P70 and P71

as I2C pins, set the value of the PDR to 1. (To use P70 and P71 as ports 70 and 71, stop I2C.)

These ports have open drain output format. If they are used as input ports, it is necessary toturn off the output transistor, set the value of the output data register to 1, and add a pull-upresistor to the external pins.

149

CHAPTER 8 I/O PORTS

8.2.3 Output Pin Register (ODR)

Figure 8.2-4 "Bit Configuration of the Output Pin Register (ODR)" shows the bit configuration of the output pin register (ODR), while Figure 8.2-5 "Block Diagram of the Output Pin Register (ODR)" shows its block diagram.

Output Pin Register (ODR)

Figure 8.2-4 Bit Configuration of the Output Pin Register (ODR)

Block Diagram of Output Pin Register (ODR)

Figure 8.2-5 Block Diagram of the Output Pin Register (ODR)

Note on Output Pin Register (ODR)

The output pin register (ODR: R/W enabled) controls the open drain in output mode.

• 0: Standard output port in output mode

• 1: Open-drain output port in output mode

The value in this register has no meaning in input mode (output Hi-Z).

Whether input mode or output mode is effective is determined by the contents of the directionregister (DDR).

When the port is used for the external bus, this function is disabled. Do not write data to thisregister.

7 6 5 4 3 2 1 0

0D46 0D45 0D44 0D43 0D42 0D41 0D40Address: 00001BH

Bit No. Port 4 pin register (ODR4)

Initial value -0000000H

Data register

Direction register

Pin register

Port I/O

Bus

150


8.2.4 Input Resistor Register (RDR)

Figure 8.2-6 "Bit Configuration of the Input Resistor Register (RDR)" shows the bit configuration of the input resistor register (RDR). Figure 8.2-7 "Block Diagram of Input Resistor Register (RDR)" shows its block diagram.

Input Resistor Register (RDR)

Figure 8.2-6 Bit Configuration of the Input Resistor Register (RDR)

Block Diagram of Input Resistor Register (RDR)

Figure 8.2-7 Block Diagram of Input Resistor Register (RDR)

7 6 5 4 3 2 1 0

RD07 RD06 RD05 RD04 RD03 RD02 RD01 RD0000001CH 00000000B

15 14 13 12 11 10 9 8

RD17 RD16 RD15 RD14 RD13 RD12 RD11 RD1000001DH 00000000B

7 6 5 4 3 2 1 0

RD67 RD66 RD65 RD64 RD63 RD62 RD61 RD6000001EH 00000000B

Bit No.

Bit No.

Bit No.

Address:

Address:

Address:

Port 0 resistor register (RDR0)



Initial value

Initial value

Initial value

Data register

Direction register

Resistor register

Bus

Pull-up resistor (about 50 k )

Port I/O

151

CHAPTER 8 I/O PORTS

Note on Input Resistor Register (RDR)

The input resistor register (RDR: R/W enabled) controls the pull-up resistor in input mode.

• 0: No pull-up resistor in input mode

• 1: Pull-up resistor in input mode

The value in this register has no meaning in output mode (no pull-up resistor).

Whether input or output mode applies is determined by the direction register (DDR).

In stop mode, no pull-up resistor is specified (high impedance) for LPMCR: SPL = 1.

152


8.2.5 Analog Input Enable Register (ADER)

Figure 8.2-8 "Bit Configuration of the Analog Input Enable Register (ADER)" shows the bit configuration of the analog input enable register (ADER).

Analog Input Enable Register (ADER)

Figure 8.2-8 Bit Configuration of the Analog Input Enable Register (ADER)

The analog input enable register (ADER) controls the pins of port 5 as follows:

• 0: Port input mode

• 1: Analog input mode

The bits of the ADER register are initialized to 1 at a reset.

15 14 13 12 11 10 9 8

ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE000001FH 11111111B

R/W R/W R/W R/W R/W R/W R/W R/W

Bit No.

Address:

Initial value

Read/write

153

CHAPTER 8 I/O PORTS

154

CHAPTER 9 TIMEBASE TIMER

This chapter explains the functions and operation of the timebase timer.

9.1 "Overview of Timebase Timer"

9.2 "Timebase Timer Control Register (TBTC)"

9.3 "Operation of Timebase Timer"

155


9.1 Overview of Timebase Timer

The timebase timer consists of an 18-bit timer and a circuit that controls interval interrupts. The timebase timer uses the oscillation clock regardless of the setting of the MCS and SCS bits in the clock selection register (CKSCR).

Timebase Timer Registers

Figure 9.1-1 Timebase Timer Registers

15 14 13 12 11 10 9 8

0000A9H TBIE TBOF TBR TBC1 TBC0 TBTC

(-) (-) (R/W) (R/W) (R/W) (R/W)(1) (-) (-) (0) (0) (0) (0)

(W)(1)

(-)

Timebase timer control register

Address:

Bit No.


Reserved

156

9.1 Overview of Timebase Timer

Block Diagram of the Timebase Timer

Figure 9.1-2 Block Diagram of the Timebase Timer

TBTC2

TBC1 22

TBC0 2TBTRES 2 2 2 2

TBR

TBIE AND

TBOF

WDTC

WT1OF WDGRST

WT0 CLR CLR

WTE

12

14

16

1912 1614 19

PONR

WRST

ERST

SRST

2222WTRES

210

1415

14

132152 13210

WTC

WDCS AND

WTR

WTIE

WTOF

SCE

WTC1

WTC0

SRQ

AND SRQ

SRQ

WDTC

SCM

Oscillation clock

Selector

Clock input

Timebase timer

Timebaseinterrupt

2-bit counterSelector

Watchdog reset generation circuit

To internal reset generation circuit

F2M

C-16L bus

Power-on reset subclock stop

SelectorWatch timer

Subclock divided by 4

Clock input

Watchinterrupt

From power-on generation

RSTX pin

From RST bit of STBYC register

157


9.2 Timebase Timer Control Register (TBTC)

The timebase timer control register (TBTC) controls the operation of the timebase timer and the interval interrupt time.

Timebase Timer Control Register (TBTC)

Figure 9.2-1 Configuration of the Timebase Timer Control Register (TBTC)

Note:

Access with read-modify-write instructions causes a malfunction. Do not access this registerwith these instructions.

[Bit 15] Reserved bit

Be sure to set this bit to 1.

[Bits 14 and 13] Not used

Bits 14 and 13 are not used.

[Bit 12] TBIE

The TBIE bit enables interval interrupts from the timebase timer. When this bit is 1,interrupts are enabled. When this bit is 0, interrupts are disabled. This bit is initialized to 0by a reset. This bit can be read and written.

[Bit 11] TBOF

The TBOF bit is an interrupt request flag bit. When the TBIE bit is 1 and the TBOF bit is setto 1, an interrupt request is generated. This bit is set to 1 at each interval set by the TBC1and TBC0 bits. This bit is cleared by writing 0, by a transition to stop mode, or by a reset.Setting this bit to 1 with a write operation has no effect.

During reading with a read-modify-write instruction, 1 is returned for this bit.

[Bit 10] TBR

The TBR bit is used to clear all bits of the timebase timer counter. When this bit is set to 0,the timebase counter is cleared. Setting this bit to 1 with a write operation has no effect onoperation. Read operations return 1 for this bit.

[Bits 9 and 8] TBC1 and TBC0

The TBC1 and TBC0 bits set the interval time for the timebase timer. These bits areinitialized to "00" by a reset. These bits can be read and written.

15 14 13 12 11 10 9 8

0000A9H TBIE TBOF TBR TBC1 TBC0 TBTC

(-) (-) (R/W) (R/W) (R/W) (R/W)(1) (-) (-) (0) (0) (0) (0)

(W)(1)

(-)

Timebase timer control register

Address:

Bit No.


Reserved

158

9.2 Timebase Timer Control Register (TBTC)

Table 9.2-1 "Interval Time Settings for the Timebase Timer" lists the setting of interval timefor the timebase timer.

Table 9.2-1 Interval Time Settings for the Timebase Timer

TBC1 TBC0 Interval time when the source oscillation frequency is 4 MHz

0 0 1.024 ms

0 1 4.096 ms

1 0 16.384 ms

1 1 131.072 ms

159


9.3 Operation of Timebase Timer

The timebase timer provides clocks to the watchdog timer, is used as the oscillation stabilization wait interval timer for the oscillation clock, and has an interval timer function that can generate interrupts at a given interval.

Timebase Counter

The timebase timer consists of the 18-bit counter that counts the pulses of the oscillation clockthat is used to implement the machine clock. It continues with counting as long as theoscillation clock is input.

The timebase timer counter is cleared by a power-on reset, transition to stop mode, andtransition from oscillation clock to PLL clock in accordance with the setting of the MCS bit of theclock selection register (CKSCR). The timebase timer counter is also cleared by transition fromoscillation clock to subclock in accordance with the setting of the SCS bit of the clock selectionregister (CKSCR) and by setting the TBR bit of the timebase timer control register (TBTC) to 0.

The watchdog timer and interval interrupt that use timebase timer output are affected byclearing the timebase timer counter.

Interval Interrupt Function for Timebase Timer

The carry signal of the timebase timer counter causes interrupt generation in given intervals.The TBOF flag is set each time the interval specified by the TBC1 and TBC0 bits of thetimebase timer control register (TBTC) has elapsed. This flag is set based on the time the lasttimebase timer was cleared.

On transition from oscillation clock mode to PLL clock mode, the timebase timer is cleared touse the timebase timer as the oscillation stabilization wait timer for the PLL clock.

On transition from oscillation clock mode to subclock mode, the timebase timer is cleared to usethe timebase timer as the oscillation stabilization wait timer for the oscillation clock.

On transition to stop mode, the timebase timer is set up to be used as the oscillationstabilization wait timer later on, and the TBOF flag is cleared at the same time that modetransition occurs.

160

CHAPTER 10 WATCHDOG TIMER

This chapter explains the functions and operation of the watchdog timer.

10.1 "Overview of Watchdog Timer"

10.2 "Watchdog Timer Control Register (WDTC)"

10.3 "Operation of Watchdog Timer"

161


10.1 Overview of Watchdog Timer

The watchdog timer consists of a 2-bit watchdog counter that uses the carry signal of the 18-bit timebase timer or 15-bit watch timer as the clock source, a control register, and a watchdog reset control block.

Watchdog Timer Registers

Figure 10.1-1 Watchdog Timer Registers

7 6 5 4 3 2 1 0

0000A8H PONR - WRST ERST SRST WTE WT1 WT0 WDTC

(R) (-) (R) (R) (R) (W) (W) (W)(X) (X) (X) (X) (X) (1) (1) (1)

Address:

Watchdog timer control register

Bit No.


162

10.1 Overview of Watchdog Timer

Block Diagram of Watchdog Timer

Figure 10.1-2 Block Diagram of Watchdog Timer

TBTC2

TBC1 22


TBR

TBIE AND

TBOF

WDTC

WT1OF WDGRST

WT0 CLR CLR

WTE

12141619

12 1614 19

PONR

WRST

ERST

SRST

2222WTRES

210

1415

14

132152 13210

WTC

WDCS AND

WTR

WTIE

WTOF

SCE

WTC1

WTC0

SRQ

AND SRQ

SRQ

WDTC

SCM

Oscillation clock

Selector

Selector

Selector

Clock input

Clock input

Timebase timer

Timebaseinterrupt

2-bit counter Watchdog reset generation circuit


F2M

C-16L bus


Watch timer


Watchinterrupt


RSTX pin


163


10.2 Watchdog Timer Control Register (WDTC)

The watchdog timer control register (WDTC) consists of bits that are used for various types of control related to the watchdog timer and bits that identify reset causes.

Watchdog Timer Control Register (WDTC)

Figure 10.2-1 Watchdog Timer Control Register (WDTC)

[Bits 7 to 3] PONR, WRST, ERST, and SRST

These are flag bits that indicate reset causes. When a reset occurs, these bits are set aslisted in Table 10.2-1 "Reset Cause Bits and Reset Causes". After the WDTC register isread, these read-only bits are all cleared to 0. At power-on, the contents of reset cause bitsother than the PONR bit cannot be guaranteed. Therefore, when the PONR bit is 1, ignorethe contents of bits other than the PONR bit.

[Bit 2] WTE

When the watchdog timer is in the stopped state, setting this bit to 0 activates the watchdogtimer. Subsequent write operations for setting this bit to 0 clear the watchdog timer. Settingthis bit to 1 has no effect on operation.

The watchdog timer is placed in stopped state by a power-on reset or watchdog timer reset.The value returned for read operations of this bit is 1.

[Bits 1 and 0] WT1 and WT0

These are write-only bits used to select the watchdog timer interval.

Only data written at watchdog timer activation is valid. Data written at other times is ignored.The clock input to the watchdog timer is selected in accordance with the result of an AND

7 6 5 4 3 2 1 0

0000A8H PONR - WRST ERST SRST WTE WT1 WT0 WDTC

(R) (-) (R) (R) (R) (W) (W) (W)(X) (X) (X) (X) (X) (1) (1) (1)

Address:

Watchdog timer control register

Bit No.


Table 10.2-1 Reset Cause Bits and Reset Causes

Reset cause PONR WRST ERST SRST

Power-on 1 X X X

Watchdog timer * 1 * *

External pin * * 1 *

RST bit c * * 1

*: Retains the previous value.

164

10.2 Watchdog Timer Control Register (WDTC)

operation of the WDCS bit of the watch timer control register (WTC) and the SCM bit of theclock selection register (LPMCR). When WDCS is 1 and the oscillation clock is selected asthe machine clock, the timebase timer interval is selected. When WDCS is 0 or the subclockis selected, the watch timer interval is selected.

Table 10.2-2 "WT1 and WT0 (Interval Selection Bit)" shows the settings for the interval.

Note:

The maximum interval is defined by the value when the timebase counter or watch counter isreset during watchdog timer operation.

Table 10.2-2 WT1 and WT0 (Interval Selection Bit)

WDCSSCM

WT1 WT0 Interval*

Minimum Maximum

1 0 0 About 3.58 ms About 4.61 ms



1 1 1 About 458.75 ms About 589.82 ms

0 0 0 About 0.438 s About 0.563 s

0 0 1 About 3.50 s About 4.50 s

0 1 0 About 7.0 s About 9.0 s

0 1 1 About 14.0 s About 18.0 s

*: If WDCS/SCM is 1, the interval time is set to the same value as when the source oscillation frequency is 4 MHz. If WDCS/SCM is 0, the interval time is set to the same value as when the source oscillation frequency is 32 kHz.

165


10.3 Operation of Watchdog Timer

The watchdog timer function can detect when a program runs out of control. If the WTE bit of the watchdog timer is not set to 0 within the specified time because the program ran out of control, the watchdog timer generates a watchdog reset.

Activating the Watchdog Timer

The watchdog timer is activated when the WTE bit of the watchdog timer control register(WDTC) is set to 0. At the same time, the watchdog timer interval is set in accordance with thesettings of the WT1 and WT0 bits of the watchdog timer control register (WDTC). Only datawritten at the time of activation is valid for the interval setting.

Preventing Watchdog Timer Reset

When the watchdog timer is activated, the 2-bit watchdog counter must be periodically clearedby program. Specifically, the WTE bit of the watchdog timer control register (WDTC) must beperiodically set to 0. The watchdog timer consists of a 2-bit watchdog counter that uses thecarry signal of the timebase timer as the source clock. When the timebase timer is cleared, thewatchdog timer interval may exceed the setting time.

Figure 10.3-1 "Operation of the Watchdog Timer" shows the operation of the watchdog timer.

Figure 10.3-1 Operation of the Watchdog Timer

Stopping the Watchdog Timer

Once the watchdog timer is activated, it is only initialized and stopped by a power-on reset orwatchdog reset.

The watchdog counter is cleared by an external pin or software reset; however, this does notstop the watchdog timer function.

Clearing the Watchdog Counter

The watchdog counter is cleared by writing the WTE bit of the watchdog timer control register(WDTC), reset generation, or transition to sleep mode or stop mode.

00 01 10 00 01 10 11 00

Timebase

Watchdog

WTE write

Watchdog activation Watchdog clearing

Watchdog reset generation

166

CHAPTER 11 WATCH TIMER

This chapter explains the functions and operation of the watch timer.

11.1 "Overview of Watch Timer"

11.2 "Watch Timer Control Register (WTC)"

11.3 "Operation of Watch Timer"

167


11.1 Overview of Watch Timer

The watch timer consists of a 15-bit timer and a circuit that controls interval interrupts. The watch timer uses the subclock regardless of the settings of the MCS and SCS bits in the clock selection register (CKSCR).

Watch Timer Registers

Figure 11.1-1 Watch Timer Control Register (WTC)

7 6 5 4 3 2 1 0

0000AAH WDCS SCE WTIE WTOF WTR WTC2 WTC1 WTC0 WTC

(R/W) (R) (R/W) (R/W) (R/W)(R) (R/W) (R/W)(1) (X) (0) (0) (0)(0) (0) (0)

Watch timer control register

Address:Bit No.


168

11.1 Overview of Watch Timer

Block Diagram of the Watch Timer

Figure 11.1-2 Block Diagram of the Watch Timer

TBTC2

TBC1 22


TBR

TBIE AND

TBOF

WDTC

WT1OF WDGRST

WT0 CLR CLR

WTE

12141619

12 1614 19

PONR

WRST

ERST

SRST

2222WTRES

210

1415

14

132152 13210

WTC

WDCS AND

WTR

WTIE

WTOF

SCE

WTC1

WTC0

SRQ

AND SRQ

SRQ

WDTC

SCM

Oscillation clock

Selector

Selector

Selector

Clock input

Clock input

Timebase timer

Timebaseinterrupt

2-bit counter Watchdog reset generation circuit


F2M

C-16L bus


Watch timer


Watchinterrupt


RSTX pin


169


11.2 Watch Timer Control Register (WTC)

The watch timer control register (WTC) controls the operation of the watch timer and the interval interrupt time.

Watch Timer Control Register (WTC)

Figure 11.2-1 Watch Timer Control Register

[Bit 7] WDCS

The WDCS bit specifies whether the clock signal of the watch timer or timebase timer isused as the clock input to the watchdog timer when the oscillation clock is selected as themachine clock. When the oscillation clock is selected as the machine clock, the clock signalof the watch timer can be selected if WDCS is 0. The clock signal of the timebase timer canbe selected if WDCS is 1.

This bit is initialized to 1 by a power-on reset.

Note:

Since timebase timer output and watch timer output are asynchronous, the watchdog timercounter may be incremented if WDCS is set to 1. If WDCS is set to 1, the watchdog timermust be cleared before and after the clock mode is changed.

[Bit 6] SCE

The SCE bit indicates when the subclock oscillation stabilization wait interval has elapsed.When this bit is 1, the oscillation stabilization interval is currently in progress. The oscillation

stabilization interval is fixed to 214 cycles (subclock). This bit is initialized to 0 by a power-onreset, watchdog reset, or transition to stop mode.

[Bit 5] WTIE

The WTIE bit enables the interval interrupts generated by the watch timer. When this bit is1, the interrupt is enabled. When this bit is 0, the interrupt is disabled. This bit is initializedto 0 at a reset. This bit can be read and written.

7 6 5 4 3 2 1 0

0000AAH WDCS SCE WTIE WTOF WTR WTC2 WTC1 WTC0 WTC

(R/W) (R) (R/W) (R/W) (R/W)(R) (R/W) (R/W)(1) (X) (0) (0) (0)(0) (0) (0)

Watch timer control register

Address:Bit No.


170

11.2 Watch Timer Control Register (WTC)

[Bit 4] WTOF

The WTOF bit is the watch timer interrupt request flag. When the WTIE bit is 1 and WTOF isset to 1, an interrupt request is generated. This bit is set to 1 at each interval set by theWTC1 and WTC0 bits. This bit is cleared by setting ot to 0 in a write operation, by transitionto stop mode, or a reset. Setting this bit to 1 has no effect on operation.

When this bit is read with a read/modify/write instruction, 1 is always returned.

[Bit 3] WTR

The WTR bit clears all bits of the counter of the watch time to 0. Setting this bit to 0 clearsthe watch counter. Setting this bit to 1 has no effect on operation. The return value for readoperations is always 1 for this bit.

[Bits 2, 1, and 0] WTC2, WTC1, and WTC0

These bits set the interval for the watch timer. Table 11.2-1 "Interval Settings for the WatchTimer" lists the interval settings. These bits are initialized to "000" at a reset. These bits canbe read and written.

When one of these bits is written, bit 4 (WTOF) should also be cleared at the same time.

Table 11.2-1 Interval Settings for the Watch Timer

WTC2 WTC1 WTC0 Interval for subclock at 32 kHz

0 0 0 62.5 ms

0 0 1 125.0 ms

0 1 0 62.5 ms

0 1 1 0.250 s

1 0 0 1.000 s

1 0 1 2.000 s

1 1 0 4.000 s

1 1 1 -

171


11.3 Operation of Watch Timer

The watch timer provides clocks to the watchdog timer, is used as the oscillation stabilization wait interval timer for subclocks, and provides the interval timer function that generates interrupts at given intervals.

Watch Counter

The watch timer consists of a 15-bit counter that counts pulses of the subclock used to generatea machine clock. It always continues with counting while the subclock is input. The watch timeris cleared by a power-on reset, transition to stop mode, or setting the WTR bit of the watch timercontrol register (WTC) to 0.

The watchdog counter and interval interrupt that use watch timer output are affected by clearingthe watch counter.

Interval Interrupt Function for the Watch Timer

The interval interrupt function uses the carry signal of the watch counter to generate interruptsat given intervals. The WTOF flag is set each time the interval set by the WTC1 and WTC0 bitsof the watch timer control register (WTC) has elapsed. This flag is set based on the last timethe watch timer was cleared.

On transition to stop mode, the watch timer is set up to be used as the oscillation stabilizationwait timer later on, and the WTOF flag is cleared at the time of mode transition.

172

CHAPTER 12 16-BIT I/O TIMER

This chapter explains the functions and operation of the 16-bit I/O timer.

12.1 "Overview of 16-Bit I/O Timer"

12.2 "Block Diagram of 16-Bit I/O Timer"

12.3 "16-Bit I/O Timer Registers"

12.4 "16-Bit Free-Run Timer"

12.5 "Output Compare"

12.6 "Input Capture"

12.7 "Operation of 16-Bit Free-Run Timer"

12.8 "Operation of 16-Bit Output Compare"

12.9 "Operation of 16-Bit Input Compare"

173


12.1 Overview of 16-Bit I/O Timer

The 16-bit I/O timer consists of one 16-bit free-run timer, four output compare modules, and two input capture modules.Using this function enables two independent waveforms to be output based on the 16-bit free-run timer, and also enables measuring input pulse width and external clock cycle.

16-bit Free-Run Timer (x 1)

The 16-bit free-run timer consists of a 16-bit up counter, control register, and prescaler. Theoutput of this timer counter is used for the basic timing (base timer) of input capture and outputcompare.

Counter operation clock (selectable from four types)

Four types of internal clocks: φ/4, φ/16, φ/64, φ/256

φ: Machine clock

Interrupt

An interrupt can be generated based on an overflow of a counter value or a compare match withcompare register 0. (The compare match operation requires to make mode settings.)

Initialization

A counter value can be initialized to 0000H by a reset, software clear, or compare match withcompare register 0.

Output Compare (x 4)

The output compare module consists of four 16-bit free-running compare registers, a compareoutput latch, and control register. When a 16-bit free-run timer value matches a compareregister value, the output level is reversed and an interrupt can be generated.

• Four compare registers can be operated independently.

• Output pin and interrupt flag corresponding to each compare register

• An output pin can be controlled by pairing four compare registers.

• The polarity of the output pin can be reversed by using four compare registers.

• The initial value of the output pin can be set.

• An interrupt can be generated by a compare match.

Input Capture (x 2)

The input capture module consists of the capture register and control register corresponding totwo independent external input pins. A 16-bit free-run timer value can be stored in the captureregister. Interrupts can be generated at the time an edge of the signal input from the externalpin is detected.

• The edge of the external input signal can be selected.

• Rising edge, falling edge, or both edges can be selected.

• Two input capture operations can be performed independently.

174

12.1 Overview of 16-Bit I/O Timer

• Interrupts can be generated at the time a valid edge of an external input signal is detected.

• The extended intelligent I/O service can be activated by an interrupt of the input captureoperation.

16-Bit I/O Timer Registers

Figure 12.1-1 16-Bit I/O Timer Registers

TCDT

15 0

TCCS

000066H

000068H

OCCP0 to 3

15 0

OCS1/3 OCS0/2

000050,52,54,56H

000058,5AH

IPCP0 to 1

15 0

ICS

000060,62H

000064H


Timer data register

Control status register

16-bit output compare

Compare register

16-bit input capture

Capture register



175


12.2 Block Diagram of 16-Bit I/O Timer

Figure 12.2-1 "Block Diagram of the 16-Bit I/O Timer" is a block diagram of the 16-bit I/O timer.

Block Diagram of the 16-Bit I/O Timer

Figure 12.2-1 Block Diagram of the 16-Bit I/O Timer

TQ OUT0

TQ OUT1

TQ OUT2

TQ OUT3

IN0

IN1

Bus

Control logic

Interrupt

To each block


16-bit timer

Clear

Output compare 0

Compare register 0

Output compare 1

Compare register 1

Output compare 2

Compare register 2

Compare register 3

Output compare 3

Input capture 0

Capture register 0 Edge selection

Edge selectionCapture register 1

176

12.3 16-Bit I/O Timer Registers

12.3 16-Bit I/O Timer Registers

The 16-bit I/O timer has the following six types of register:• Timer counter data register (TCDT) • Timer counter control status register (TCCS)• Output compare register (OCCP0 to OCCP3)• Output compare control status register (OCS0 to OCS3)• Input capture data register (IPCP0 and IPCP1)• Input capture control status register (ICS01)

16-Bit I/O Timer Registers

Figure 12.3-1 16-Bit I/O Timer Registers

15 14 13 12 11 10 9 8

000066H

T15 T14 T13 T12 T11 T10 T09 T08 TCDT(High)

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)(0) (0) (0) (0) (0) (0) (0) (0)

7 6 5 4 3 2 1 0

T07 T06 T05 T04 T03 T02 T01 T00 TCDT(Low)


000067H

High-order byte of timer counter data register

Bit No.

Bit No.

Address:

Address:

Read/write

Read/write

Initial value

Initial value

Low-order byte of timer counter data register

7 6 5 4 3 2 1 0

IVF IVFE STOP MODE CLR CLK1 CLK0 TCCS


000068H

Bit No.

Address:


Timer counter control status register

Reserved

15 14 13 12 11 10 9 8ch0 000051H

ch1 000053H OCCP0 to 3(High)C15 C14 C13 C12 C11 C10 C09 C08

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)(X) (X) (X) (X) (X) (X) (X) (X)

7 6 5 4 3 2 1 0ch0 000050H

ch1 000052HC07 C06 C05 C04 C03 C02 C01 C00


OCCP0 to 3(Low)

ch2 000055H

000057Hch3

000054H

000056Hch2ch3

High-order byte of output compare register

Bit No.

Address:


Bit No.

Address:


Low-order byte of output compare register

15 14 13 12 11 10 9 8

CMOD OTE1 OTE0 OTD1 OTD0 OCS0,2

(-) (-) (-) (R/W) (R/W) (R/W) (R/W) (R/W)(-) (-) (-) (0) (0) (0) (0) (0)

7 6 5 4 3 2 1 0

ICP1 ICP0 ICE1 ICE0 CST1 CST0 OCS1,3

(R/W) (R/W) (R/W) (R/W) (-) (-) (R/W) (R/W)(0) (0) (0) (0) (-) (-) (0) (0)

ch1ch0 000059H

00005BH

ch1ch0 000058H

00005AH

Bit No.

Address:



Address:

Bit No.

High-order byte of output compare control status register

Low-order byte of output compare control status register

177


15 14 13 12 11 10 9 8

IPCP0,1CP15 CP14 CP13 CP12 CP11 CP10 CP09 CP08

(R) (R) (R) (R) (R) (R) (R) (R)(X) (X) (X) (X) (X) (X) (X) (X)

7 6 5 4 3 2 1 0



ch1ch0 000063H

000061H

ch1ch0 000060H

000062H

Bit No.

Bit No.

Address:

Address:

Read/write

Read/write

Initial value

Initial value

High-order byte of input capture data register

Low-order byte of input capture data register

ICP1 ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00 ICS01


7 6 5 4 3 2 1 0

000064H

Bit No.

Address:


Input capture control status register

178

12.4 16-Bit Free-Run Timer


The 16-bit free-run timer has the following two types of register:• Timer counter data register (TCDT)• Timer counter control status register (TCCS)

16-Bit Free-Run Timer

The 16-bit free-run timer consists of a 16-bit up counter and a control status register. Countvalues of this timer are used for the basic timing (base timer) of the output compare and inputcapture.

• A count clock can be selected from four types.

• Counter overflow interrupts can be generated

• The counter can be initialized via a match with the value of compare register 0 of the outputcompare in accordance with the mode setting.

16-Bit Free-Run Timer Registers

The register configuration of the 16-bit free-run timer is shown below.

Figure 12.4-1 16-Bit Free-Run Timer Registers

Block Diagram of 16-Bit Free-Run Timer

A block diagram of the 16-bit free-run timer is shown below.

Figure 12.4-2 Block Diagram of 16-Bit Free-Run Timer

TCDT

15 0

TCCS

000066H

000068H

Timer counter data register


IVF IVFE STOP MODE CLR CLK1 CLK0

(TCCS)

Bus

Interrupt request

Divider

Comparator 0

16-bit up counter Clock

Count value outputT15 to T00

179


12.4.1 Timer Counter Data Register (TCDT)

The timer counter data register (TCDT) can be used to read count values of the 16-bit free-run timer.

Timer Counter Data Register (TCDT)

The counter value is cleared to "0000" at reset. A timer value can be set by writing to thisregister; this write operation must be performed in stop (STOP = 1) status.

The 16-bit free-run timer is initialized by the following causes:

• Reset

• Initialization based on the clear bit (CLR) of the control status register

• Initialization because of match between the compare register 0 of the output compare and atimer counter value. (This requires to make mode settings.)

Figure 12.4-3 Timer Counter Data Register (TCDT)

Note:

The TCDT register requires word accesses.

15 14 13 12 11 10 9 8

000066H

T15 T14 T13 T12 T11 T10 T09 T08 TCDT(High)


7 6 5 4 3 2 1 0

T07 T06 T05 T04 T03 T02 T01 T00 TCDT(Low)


000067H

High-order byte of timer counter data register

Bit No.

Bit No.

Address:

Address:

Read/write

Read/write

Initial value

Initial value

Low-order byte of timer counter data register

180


12.4.2 Timer Counter Control Status Register (TCCS)

The timer counter control status register (TCCS) controls the timer counter of the 16-bit free-run timer.

Timer Counter Control Status Register (TCCS)

Figure 12.4-4 Timer Counter Control Status Register (TCCS)


Bit 7 is reserved. Always set this bit to 0.

[Bit 6] IVF

IVF is the interrupt request flag for the 16-bit free-run timer.

If the 16-bit free-run timer suffers an overflow or if the counter is cleared via a comparematch with compare register 0 because of mode settings, this bit is set to 1. An interruptoccurs if the IVFE bit (bit 5) is set.

Writing 0 clears this bit. Writing 1 has no effect. read-modify-write instructions return a readvalue of 1 for this bit.

[Bit 5] IVFE

IVFE is the interrupt enable bit of the 16-bit free-run timer.

If this bit is 1 and the IVF bit (bit 6) is set to 1, an interrupt occurs.

7 6 5 4 3 2 1 0

IVF IVFE STOP MODE CLR CLK1 CLK0 TCCS


000068H

Bit No.

Address:



Reserved

Table 12.4-1 Function of the Interrupt Request Flag (IVF)

IVF Function

0 No interrupt request [initial value]

1 Interrupt request

Table 12.4-2 Function of Interrupt Enable Bit (IVFE)

IVFE Function

0 Interrupt disabled [initial value]

1 Interrupt enabled

181


[Bit 4] STOP

The STOP bit is used to stop the counting operation of the 16-bit free-run timer.

When 1 is written, the counting operation of the timer stops. When 0 is written, the countingoperation starts.

[Bit 3] MODE

The MODE bit is used to set the initialization condition of the 16-bit free-run timer. If this bitis 0, a counter value can be initialized by the reset and CLR bit (bit 2). If this bit is 1, thecounter value can be initialized by the reset, CLR bit (bit 2), and a match with the value ofcompare register 0 of the output compare.

[Bit 2] CLR

The CLR bit is used to initialize the active 16-bit free-run timer to "0000". When 1 is written,the counter value is initialized to "0000". Writing 0 has no effect. The value returned for readoperations is always 0. The counter is initialized at the time the counter value changes.

Table 12.4-3 Function of the Count Stop Bit (STOP)

STOP Function

0 Count enabled (operation) [initial value]

1 Count disabled (stop)

Note: If counting of the 16-bit free-run timer stops, the output compare operation also stops.

Table 12.4-4 Function of Initialization Condition Setting Bit (MODE)

MODE Function

0 Initialization by the reset or setting the clear bit [initial value]

1 Initialization by the reset, setting the clear bit, or having a compare register value of 0

Note: The counter value is initialized at the time the counter value changes.

Table 12.4-5 Function of the Initialization Bit (CLR)

CLR Function

0 Meaningless [initial value]

1 The counter value is initialized to "0000".

Note: To initialize a counter value while the timer is stopped, write "0000" to the data register.

182


[Bits 1 and 0] CLK1 and CLK0

The CLK1 and CLK0 bits are used to select a count clock of the 16-bit free-run timer. Theclock is updated immediately after these bits are set in a write operation. Be sure to stop theoperation of output compare and input capture before writing these bits.

Table 12.4-6 Count Clock Selection Bits (CLK1 and CLK0)

CLK1 CLK0 Count clock φφφφ=16MHz φφφφ=8MHz φφφφ=4MHz φφφφ=1MHz

0 0 φ/4 0.25 µS 0.5 µS 1µS 4µS

0 1 φ/16 1 µS 2µS 4µS 16 µS

1 0 φ/64 4µS 8µS 16µS 64µS

1 1 φ/256 16µS 32µS 64µS 256 µS

φ = machine clock frequency

183


12.5 Output Compare

The output compare has the following two types of register:• Output compare registers (OCCP0 to OCCP3)• Output compare control status registers (OCS0 to OCS3)

Output Compare

The output compare consists of 16-bit compare registers, compare output pin block, and controlregisters. When the value set in a compare register of this module matches that of the 16-bitfree-run timer, the output level of the respective pin is reversed and an interrupt can begenerated.

• The output compare has two compare registers that can be operated independently. Pinoutput can be controlled using the two compare registers, in accordance with the settings.

• The initial value of the output pin can be set.

• An interrupt can be generated via a compare match.

Output Compare Registers

The register configuration of the output compare is shown below.

Figure 12.5-1 Output Compare Registers

15 0

000050,52,54,56H

000058,59,5A,5BH

15 0

OCPx

CSx2 CSx1

Output compare register

Output compare control status register

x=0 to 3

x=0 to 3

184

12.5 Output Compare

Block Diagram of Output Compare

Figure 12.5-2 "Block Diagram of Output Compare" is a block diagram of the output compare.

Figure 12.5-2 Block Diagram of Output Compare

T Q OTE0 OUT0(OUT2)

CMOD

T Q OTE1 OUT1(OUT3)

ICP1 ICP0 ICE1 ICE0

Bus

16-bit timer counter value (T15 to T00)

Compare control

Compare register 0 (2)

Compare register 1 (3)

16-bit timer counter value (T15 to T00)

Compare control

Control section Compare 1 (3) interrupt

Compare 0 (2) interruptTo the variouscontrol blocks

185


12.5.1 Output Compare Registers (OCCP0 to OCCP3)

The output compare registers (OCCP0 to OCCP3) are 16-bit compare registers used to make a comparison with the value of the 16-bit free-run timer.

Output Compare Registers (OCCP0 to OCCP3)

The initial value of the registers is undefined. Therefore, set the initial value, then enable use ofthe register. When the values in this register match the value of the 16-bit free-run timer, acompare signal is generated to set the output compare interrupt flag. If output is enabled, theoutput level associated with the compare register is reversed.

Figure 12.5-3 Output Compare Registers (OCCP0 to OCCP3)

Note:

Registers OCCP0 to OCCP3 require word accesses.

15 14 13 12 11 10 9 8ch0 000051H

ch1 000053H OCCP0 to 3(High)C15 C14 C13 C12 C11 C10 C09 C08


7 6 5 4 3 2 1 0ch0 000050H

ch1 000052HC07 C06 C05 C04 C03 C02 C01 C00


OCCP0 to 3(Low)

ch2 000055H

000057Hch3

000054H

000056Hch2ch3

High-order byte of output compare register

Bit No.

Address:


Bit No.

Address:


Low-order byte of output compare register

186

12.5 Output Compare

12.5.2 Output Compare Control Status Registers (OCS0 to OCS3)

The output compare control status registers (OCS0 to OCS3) control the 16-bit free-run timer.

Output Compare Control Status Registers (OCS0 to OCS3)

Figure 12.5-4 Output Compare Control Status Registers (OCS0 to OCS3)

[Bits 15 to 13] Unused bits

[Bit 12] CMOD

CMOD switches the pin output level reverse operation mode for a compare match when pinoutput is enabled (OTE1 = 1 or OTE0 = 1).

For CMOD = 0 (initial value)

When CMOD = 0 (initial value), the output level of the pin associated with the compareregister is reversed.

• OUT0/2: Reverses the level via a match with compare register 0.


For CMOD = 1

When CMOD = 1, the output level of the pin associated with compare register 0 is reversedin the same way as when CMOD = 0. However, the output level of the pin (OUT1)associated with compare register 1 is reversed via a match with compare register 0 or amatch with compare register 1. If the values of compare registers 0 and 1 are equal, theoperation is the same as when one compare register is used.


15 14 13 12 11 10 9 8

CMOD OTE1 OTE0 OTD1 OTD0 OCS0,2

(-) (-) (-) (R/W) (R/W) (R/W) (R/W) (R/W)(-) (-) (-) (0) (0) (0) (0) (0)

7 6 5 4 3 2 1 0

ICP1 ICP0 ICE1 ICE0 CST1 CST0 OCS1,3

(R/W) (R/W) (R/W) (R/W) (-) (-) (R/W) (R/W)(0) (0) (0) (0) (-) (-) (0) (0)

ch1ch0 000059H

00005BH

ch1ch0 000058H

00005AH

Bit No.

Address:



Address:

Bit No.

High-order byte of output compare control status register

Low-order byte of output compare control status register

187


• OUT1/3: Reverses the level via a match with compare register 0 or a match with compareregister 1.

[Bits 11 and 10] OTE1 and OTE0

The bits OTE1 and OTE0 are used to enable the pin output of the output compare. Theinitial value of these bits is 0.

[Bits 9 and 8] OTD1 and OTD0

Bits OTD1 and OTD0 are used to change the pin output level when pin output of the outputcompare is enabled. The initial value of compare pin output is 0. Before writing, stop thecompare operation. In read operations, the output compare pin output value can bereferenced.

[Bits 7 and 6] ICP1 and ICP0

ICP1 and ICP0 bits are output compare interrupt flags. These bits are set to 1 when thecompare register matches the value of the 16-bit free-run timer. When the interrupt requestbits (ICE1 and ICE0) are enabled and these bits are set, an output compare interrupt occurs.

These bits are cleared by writing 0. Writing 1 has no effect. Read-modify-write instructionsreturn a read value of 1.

Table 12.5-1 Function of Pin Output Enable Bits (OTE1 and OTE0)

OTE1, OTE0 Function

0 Operates as a general-purpose port [initial value].

1 Enables output compare pin output.

OTE1: Corresponds to output compare 1/3.OTE0: Corresponds to output compare 0/2.

Table 12.5-2 Function of Pin Output Level Change Bits (OTD1 and OTD0)

OTD1, OTD0 Function

0 Sets the compare pin output to 0 [initial value].

1 Sets the compare pin output to 1.

OTD1: Corresponds to output compare 1/3.OTD0: Corresponds to output compare 0/2.

Table 12.5-3 Function of Output Compare Interrupt Bits (ICP1 and ICP0)

ICP1, ICP0 Function

0 No compare match [initial value]

1 Compare match

ICP1: Corresponds to output compare 1/3.ICP0: Corresponds to output compare 0/2.

188

12.5 Output Compare

[Bits 5 and 4] ICE1 and ICE0

ICE1 and ICE0 are output compare interrupt enable bits. When these bits are 1 and theinterrupt flags (ICP0 and ICP1) are set, an output compare interrupt occurs.

[Bits 3 and 2] Unused bits

[Bits 1 and 0] CST1 and CST0

Bits CST1 and CST0 are used to enable matching with the 16-bit free-run timer. Beforeenabling the compare operation, set a compare register value.

Note:

The OCS0 to OCS3 registers are synchronized with clocks of the 16-bit free-run timer. Thecompare operation also stops when the 16-bit free-run timer stops.

Table 12.5-4 Function of Output Compare Interrupt Enable Bits (ICE1 and ICE0)

ICE1, ICE0 Function

0 Disables output compare interrupts [initial value].

1 Enables output compare interrupts.

ICE1: Corresponds to output compare 1/3.ICE0: Corresponds to output compare 0/2.

Table 12.5-5 Bits for Enabling the Match Operation with 16-bit Free-Run Timer (CST1 and CST0)

CST1, CST0 Setting

0 Disables compare operation [initial value].

1 Enables compare operation.

CST1: Corresponds to output compare 1/3.CST0: Corresponds to output compare 0/2.

189


12.6 Input Capture

The input capture has the following two types of register:• Input capture data registers (IPCP0 and IPCP1)• Input capture control status register (ICS01)

Input Capture

This module provides a function for detecting a rising edge, falling edge, or both edges of thesignal input from an external input pin, and retains the 16-bit free-run timer value in the register.Interrupts can be generated based on edge detection. The input capture consists of the inputcapture data register and control register.

Each input capture has a corresponding external input pin.

• The valid edge of an external input signal can be selected from three types:

Rising edge, falling edge, or both edges

• An interrupt can be generated based on detection of a valid edge for an external input.

Input Capture Registers

The register configuration of the input capture is shown below.

Figure 12.6-1 Input Capture Registers

15 0

000060,62H

000064H

7 0

IPCx

ICSx

Input capture data register


x=0 to 1

x=0 to 1

190

12.6 Input Capture

Block Diagram of the Input Capture

Figure 12.6-2 Block Diagram of the Input Capture

IN0

EG11 EG10 EG01 EG00

IN1

ICP1 ICP0 ICE1 ICE0

Bus

Capture data register 0Edge

detection

Edgedetection

16-bit timer counter value(T15 to T00)

Capture data register 1

Interrupt

Interrupt

191


12.6.1 Input Capture Data Registers (IPCP0 and IPCP1)

Input capture data registers (IPCP0 and IPCP1) are used to retain 16-bit free-run timer values when a valid edge of the associated external pin input waveform is detected.

Input Capture Data Registers (IPCP0 and IPCP1)

Figure 12.6-3 Input Capture Data Registers (IPCP0 and IPCP1)

Note:

Registers IPCP0 and IPCP1 require word accesses. Data cannot be written to theseregisters.

15 14 13 12 11 10 9 8



7 6 5 4 3 2 1 0



ch1ch0 000061H

000063H

ch1ch0 000060H

000062H

Bit No.

Bit No.

Address:

Address:

Read/write

Read/write

Initial value

Initial value

High-order byte of input capture data register

Low-order byte of input capture data register

192

12.6 Input Capture

12.6.2 Input Capture Control Status Register (ICS01)

Th input capture control status register (ICS01) controls the 16-bit free-run timer.

Input Capture Control Status Register (ICS01)

Figure 12.6-4 Input Capture Control Status Register (ICS01)

Note:

The ICS01 register requires byte access.

[Bits 7 and 6] ICP1 and ICP0

ICP1 and ICP0 are input capture interrupt flags.

When a valid edge of an external input pin is detected, these bits are set to 1. When theinterrupt enable bits (ICE0 and ICE1) are set, an interrupt can be generated based ondetection of a valid edge.

These bits are cleared by writing 0. Writing 1 has no effect. Read-modify-write instructionscan return a read value of 1.

ICP1 ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00 ICS01


7 6 5 4 3 2 1 0

000064H

Bit No.

Address:



Table 12.6-1 Function of the Input Capture Interrupt Flags (ICP1 and ICP0)

ICP1, ICP0 Function

0 No valid edge detection [initial value]

1 Valid edge detection

ICP1: Corresponds to input capture 1.ICP0: Corresponds to input capture 0.

193


[Bits 5 and 4] ICE1 and ICE0

ICE1 and ICE0 are input capture interrupt enable bits. When these bits are 1 and theinterrupt flags (ICP0 and ICP1) are set, an input capture interrupt occurs.

[Bits 3, 2, 1, and 0] EG11, EG10, EG01, and EG00

EG11, EG10, EG01, and EG00 specify the valid edge polarity of the external input. Thesebits also enable input capture operation.

Table 12.6-2 Function of the Input Capture Interrupt Enable Bits (ICE1 and ICE0)

ICE1, ICE0 Function


1 Interrupt enabled

ICE1: Corresponds to input capture 1.ICE0: Corresponds to input capture 0.

Table 12.6-3 Function of Bits for Specifying a Valid Edge Polarity of the External Input (EGx1 and EGx0)

EG11EG01

EG10EG00

Edge detection polarity

0 0 No edge detection (stop status) [initial value]

0 1 Rising edge detection

1 0 Falling edge detection

1 1 Both-edge detection

EG01, EG00: Correspond to input capture 0.EG11, EG10: Correspond to input capture 1.

194

12.7 Operation of 16-Bit Free-Run Timer

12.7 Operation of 16-Bit Free-Run Timer

The 16-bit free-run timer starts counting from count value "0000" after the reset is released. This count value is used as the reference time of the 16-bit output compare and 16-bit input capture.

Operation of 16-Bit Free-Run Timer

A counter value is cleared under the following conditions:

• An overflow occurs.

• A compare match with output compare register 0 occurs (this requires making modesettings).

• The CLR bit of the TCCS register is set to 1 during operation.

• The TCDC register is set to "0000" during a stop of operation.

• At reset

An interrupt can be generated when an overflow occurs or when the counter is cleared by acompare match with the value in compare register 0. (The compare match interrupt requires tomake mode settings.)

Figure 12.7-1 Counter Clear Because of an Overflow

FFFFH

BFFFH

7FFFH

3FFFH

0000H

Counter valueOverflow

Time

Reset

Interrupt

195


Figure 12.7-2 Counter Clear Because of a Compare Match with the Value in Output Compare Register 0

16-Bit Free-Run Timer Count Timing

The 16-bit free-run timer counts up in accordance with an input clock (internal or external clock).When an external clock is selected, the timer counts up at the rising edge.

Figure 12.7-3 Count Timing of the Free-Run Timer

The counter can be cleared by a reset, software clear, or a match with the value in compareregister 0. The counter is cleared by a reset or software clear. Counter clear via a match withcompare register 0 is executed synchronously with the count timing.

Figure 12.7-4 Clear Timing of Free-Run Timer (Match with Compare Register 0)

FFFFH

BFFFH

7FFFH

3FFFH

0000H

BFFFH

Counter value

Time

Reset

Interrupt

Match Match

Compare registervalue

N N+1

External clock input

Count clock

Counter value

N 0000

N

Counter value

Compare register value

Compare match

196

12.8 Operation of 16-Bit Output Compare


The 16-bit output compare compares the specified compare register value with the value of the 16-bit free-run timer. When a match occurs, the output compare can set the interrupt request flag and reverse the output level.

Operation of 16-Bit Output Compare

Figure 12.8-1 Example of an Output Waveform When Compare Registers 0 and 1 are Used (Initial Value of Output is 0)

As shown in Figure 12.8-2 "Example of an Output Waveform When Two Compare Registers areUsed (The Initial Value of Output is 0.)", two compare registers can be used to change theoutput level (when CMOD = 1).

FFFFH

BFFFH

7FFFH

3FFFH

0000H

OUT0

OUT1

BFFFH

7FFFH

Counter value

Time

Reset

Value of compare register 0


Compare 0 interruptCompare 1 interrupt

197


Figure 12.8-2 Example of an Output Waveform When Two Compare Registers are Used (The Initial Value of Output is 0.)

16-Bit Output Compare Timing

When a free-running timer value matches the specified compare register value, the outputcompare can reverse the output value by generating a compare match signal, and can thengenerate an interrupt.

When a compare match occurs, the output transition is executed in synch with the count timingof the counter.

When the compare register is rewritten, a comparison with the counter value is not made.

Figure 12.8-3 Compare Operation When Rewriting the Compare Register

BFFFH

7FFFH

FFFFH

BFFFH

7FFFH

3FFFH

0000H

OUT0

OUT1

Counter value

Time

Reset



Compare 0 interrupt

Compare 1 interrupt

Associated with compare 0.Associated with compare 0 and 1.

N N+1 N+3N+2

N+1

N+3

M

M

Counter valueNo match signal is generated.


Compare register 0 write


Compare register 1 writeCompare 0 stop Compare 1 stop

198


Figure 12.8-4 Output Compare Interrupt Timing

Figure 12.8-5 Output Pin Change Timing for Output Compare

N N+1

N

Counter value


Compare match

Interrupt

N N+1 N+1N

N

Counter value


Compare match signal

Pin output

199


12.9 Operation of 16-Bit Input Compare

When the specified valid edge is detected, the 16-bit input capture can fetch a 16-bit free-run timer value into the capture register to generate an interrupt.

Operation of 16-Bit Input Capture

Figure 12.9-1 Example of Input Capture Fetch Timing

FFFFH

BFFFH

7FFFH

3FFFH

0000H

IN0

3FFFH

BFFFH

7FFFHBFFFH

IN1

Counter value

Time

Reset

Capture 0 Undefined

Undefined

Undefined

Capture 1

Capture example

Capture 0 interrupt

Capture 1 interrupt

Capture interrupt

Capture 0: rising edgeCapture 1: falling edgeCapture example: both edges (as example)

IN example

200

12.9 Operation of 16-Bit Input Compare

Input Capture Input Timing

Figure 12.9-2 Capture Timing for Input Signals

N N+1

N+1

Counter value

Input capture inputValid edge

Capture signal

Capture register

Interrupt

201


202

CHAPTER 13 8/16-BIT PPG

This chapter explains the functions and operation of the 8/16-bit PPG.

13.1 "Overview of 8/16-Bit PPG"

13.2 "Block Diagram of 8/16-Bit PPG"

13.3 "8/16-Bit PPG Registers"

13.4 "Operation of 8/16-Bit PPG"

203


13.1 Overview of 8/16-Bit PPG

The 8/16-bit PPG is a 8/16-bit reload timer module that performs pulse output control based on timer operation to allow PPG output.

Overview of 8/16-Bit PPG

The 8/16-bit PPG consists of the following hardware components: two 8-bit down counters, four8-bit reload registers, one 16-bit control register, two external pulse output pins, and twointerrupt outputs. The PPG provides the following functions:

8-bit PPG output in 2-channel independent operation mode

Allows 2-channel independent PPG output operation.

16-bit PPG output operation mode

Allows 1-channel 16-bit PPG output operation.

8+8-bit PPG output operation mode

Allows 8-bit PPG output operation with an arbitrary cycle by applying ch0 output to the ch1 clockinput.

PPG output operation

Outputs a pulse waveform with an arbitrary cycle and duty cycle. The PPG can also be used asa D/A converter when a circuit is connected externally.

204

13.2 Block Diagram of 8/16-Bit PPG

13.2 Block Diagram of 8/16-Bit PPG

Figure 13.2-1 "Block Diagram of 8/16-Bit PPG (ch0)" is a block diagram of the 8/16-bit PPG (ch0); Figure 13.2-2 "Block Diagram of 8/16-Bit PPG (ch1)" is a block diagram of the 8/16-bit PPG (ch1).

Block Diagram of 8/16-Bit PPG

Figure 13.2-1 Block Diagram of 8/16-Bit PPG (ch0)

PPG00

PPG01

PEN0

SRQ IRQ

PRLL0 PRLBH0

PIE0

PRLH0PUF0

PPGC0

PPG00 output enabled

PPG01 output enabledPeripheral clock divided by 16Peripheral clock divided by 8Peripheral clock divided by 4Peripheral clock divided by 2Peripheral clock

Inversion

PPG0 output latch

Clear

Count clockselection

PCNT (down counter)

Reloadch1: BorrowTimebase timer output

Main clock divided by 512

Selection L/H selector

Data bus for the low-level sideData bus for the high-level side

(Operation mode control)

205


Figure 13.2-2 Block Diagram of 8/16-Bit PPG (ch1)

PPG10

PPG11

PEN1

SR Q IRQ

PRLL1

PIE

PRLH1PUF

PPGC0

PRLBH1

PPG10 output enabled

PPG11 output enabledPeripheral clock divided by 16Peripheral clock divided by 8Peripheral clock divided by 4Peripheral clock divided by 2Peripheral clock

Inversion

PPG1 output latch

Clear

Count clockselection

PCNT (down counter)

ReloadTimebase counter outputMain clock divided by 512

L/H Selection L/H selector

Data bus for the low-level side

Data bus for the high-level side

(Operation mode control)

206

13.3 8/16-Bit PPG Registers


The 8/16-bit PPG has the following three types of registers:• PPG operation mode control register• PPG output control register• Reload register

8/16-Bit PPG Registers

Figure 13.3-1 8/16-Bit PPG Registers

7 6 5 4 3 2 1 0Address: ch0 000044H

PEN0 PE00 PIE0 PUF0 PPGC0

(R/W)(0) (1)

15 14 13 12 11 10 9 8Address: ch1 000045H

PEN1 PE10 PIE1 PUF1 MD1 MD0 PPGC1

7 6 5 4 3 2 1 0Address: ch0,1 0046H

PCS2 PCS1 PCS0 PCM2 PCM1 PCM0 PE11 PE01 PPGOE

15 14 13 12 11 10 9 8Address: ch1 000041H

ch1 000043H PRLH0,1

7 6 5 4 3 2 1 0Address: ch0 000040H

ch1 000042H PRLLO,1

(R/W) (R/W) (R/W)(-) (-) (-) (-)

(R/W) (R/W) (R/W) (R/W)

(R/W) (R/W) (R/W) (R/W)(R/W) (R/W) (R/W) (R/W)



(X) (X) (X) (X) (X) (X) (X) (X)

(X) (X) (X) (X) (X) (X) (X) (X)

(0) (0) (0)

(0) (0) (0) (0) (0) (0)

(X) (X) (X)

(X)

(-) (-)(R/W) (R/W)

(1)

(0) (0) (0) (0) (0) (0)(0) (0)

PPG0 operation mode control register

Bit No.

Bit No.

Bit No.

Bit No.

Bit No.

Reserved

Reserved

Read/write

Read/write

Read/write

Read/write

Read/write

Initial value

Initial value

Initial value

Initial value

Initial value


PPG0/1 output control register

Reload register H

Reload register L

207


13.3.1 PPG0 Operation Mode Control Register (PPGC0)

The PPG0 operation mode control register (PPGC0) is used for selection of the operation mode of the 8/16-bit PPG, pin output control, count clock selection, and trigger control.

PPG0 Operation Mode Control Register (PPGC0)

Figure 13.3-2 PPG0 Operation Mode Control Register (PPGC0)

[Bit 7] PEN0 (Ppg ENable)

The PEN0 bit selects the start of PPG operation and the operation mode as listed in Table13.3-1 "Function of Operation Enable Bit (PEN0)". Setting this bit to 1 causes the PPG tostart counting. This bit is initialized to 0 at a reset. This bit can be read and written.

[Bit 5] PE00 (Ppg output Enable 00)

The PE00 bit controls the pulse output external pin PG00 as listed in Table 13.3-2 "Functionof PPG0 Pin Output Enable Bit (PE00)". This bit is initialized to 0 at a reset. This bit can beread and written.

[Bit 4] PIE0 (Ppg Interrupt Enable)

The PIE0 bit enables or disables PPG interrupts as listed in Table 13.3-3 "Function of PPGInterrupt Enable Bit (PIE0)".

If this bit is 1, an interrupt request is issued when PUF0 is set to 1.

7 6 5 4 3 2 1 0Address: ch0 000044H

PEN0 PE00 PIE0 PUF0 PPGC0

(R/W)(0) (1)

(R/W) (R/W) (R/W)(-) (-) (-) (-)(0) (0) (0)(X) (X) (X)


Bit No.

Reserved


Table 13.3-1 Function of Operation Enable Bit (PEN0)

PEN0 Function

0 Operation stopped (low level output held) [initial value]

1 PPG operation enabled

Table 13.3-2 Function of PPG0 Pin Output Enable Bit (PE00)

PE00 Function

0 General-purpose port pin (pulse output disabled) [initial value]

1 PG00 = pulse output pin (pulse output enabled)

208


If this bit is 0, no interrupt request is issued. This bit is initialized to 0 at a reset. This bit canbe read and written.

Note:

The same interrupt vector number as that for 16-bit reload timer ch0 is assigned. To use

extended intelligent I/O service (EI2OS) when 16-bit reload timer ch0 is used, set the PIE0bit to 0.

[Bit 3] PUF0 (Ppg Underflow Flag)

The PUF0 bit controls a PPG counter underflow as listed in Table 13.3-4 "Function of PPGCounter Underflow Bit (PUF0)".

In the 8-bit PPG 2-ch mode and 8-bit prescaler + 8-bit PG mode, an underflow caused by thechange in the ch0 counter value from 00H to FFH sets the bit to 1. In the 16-bit PPG 1-chmode, an underflow caused by the change in the ch1/ch0 counter value from 0000H toFFFFH sets the bit to 1. This bit is set to 0 by writing 0.

Writing 1 has no effect.

At read with a read-modify-write instruction, a value of 1 is returned for this bit.

This bit is initialized to 0 at a reset. This bit can be read and written.


Bit 0 is reserved. Be sure to set this bit to 1.

Table 13.3-3 Function of PPG Interrupt Enable Bit (PIE0)

PIE0 Function


1 Interrupt enabled

Table 13.3-4 Function of PPG Counter Underflow Bit (PUF0)

PUF0 Function

0 PPG counter underflow not detected [initial value]

1 PPG counter underflow detected

209


13.3.2 PPG1 Operation Mode Control Register (PPGC1)

The PPG1 operation mode control register (PPGC1) is used for selection of the operation mode of the 8/16-bit PPG, pin output control, count clock selection, and trigger control.

PPG1 Operation Mode Control Register (PPGC1)

Figure 13.3-3 PPG1 Operation Mode Control Register (PPGC1)

[Bit 15] PEN1 (Ppg ENable)

The PEN1 bit selects the start of PPG operation and the operation mode as listed in Table13.3-5 "Function of Operation Enable Bit (PEN1)". Setting this bit to 1 causes the PWM tostart counting. This bit is initialized to 0 at a reset. This bit can be read and written.


The PE10 bit controls the pulse output external pin PG10 as listed in Table 13.3-6 "Functionof PG10 Pin Output Enable Bit (PE10)".

[Bit 12] PIE1 (Ppg Interrupt Enable)

The PIE1 bit enables or disables PPG interrupts as listed in Table 13.3-7 "Function of PPGInterrupt Enable Bit (PIE1)". If this bit is 1, an interrupt request is issued when PUF1 is set to1. If this bit is 0, no interrupt request is issued.

15 14 13 12 11 10 9 8Address: ch1 000045H

PEN1 PE10 PIE1 PUF1 MD1 MD0 PPGC1

(R/W) (R/W) (R/W) (R/W)

(0) (0) (0) (0) (0) (0)(X)

(-) (-)(R/W) (R/W)

(1)

Bit No.

Reserved



Table 13.3-5 Function of Operation Enable Bit (PEN1)

PEN1 Function

0 Operation stopped (low level output stored) [initial value]

1 PPG operation enabled

Table 13.3-6 Function of PG10 Pin Output Enable Bit (PE10)

PE10 Function



210



Note:

The same interrupt vector number as that for 16-bit reload timer ch0 is assigned. To use

extended intelligent I/O service (EI2OS) when 16-bit reload timer ch0 is used, set the PIE1bit to 0.

[Bit 11] PUF1 (Ppg Underflow Flag)

The PUF1 bit controls PPG counter underflows as listed in Table 13.3-8 "Function of PPGCounter Underflow Bit (PUF1)".

In the 8-bit PPG 2-ch mode and 8-bit prescaler + 8-bit PG mode, an underflow caused by thechange in the ch0 counter value from 00H to FFH sets the bit to 1. In the 16-bit PPG 1-chmode, an underflow caused by the change in the ch1/ch0 counter value from 0000H toFFFFH sets the bit to 1. This bit is set to 0 by writing 0. Writing 1 has no effect. At readoperations with a read-modify-write instruction, a value of 1 is returned for this bit.


[Bits 10 and 9] MD2 and MD1 (ppg count MoDe)

The MD2 and MD1 bits select the operation mode of the PPG timer as listed in Table 13.3-9"Function of Operation Mode Selection Bits (MD2 and MD1)". These bits are initialized to"00" at a reset.

These bits can be read and written.

Table 13.3-7 Function of PPG Interrupt Enable Bit (PIE1)

PIE1 Function


1 Interrupt enabled

Table 13.3-8 Function of PPG Counter Underflow Bit (PUF1)

PUF1 Function

0 PPG counter underflow not detected [initial value]

1 PPG counter underflow detected

Table 13.3-9 Function of Operation Mode Selection Bits (MD2 and MD1)

MD1 MD0 Operation mode

0 0 8-bit PPG 2-ch independent mode [initial value]

0 1 8-bit prescaler + 8-bit PPG 1-ch mode

1 0 Reserved (setting inhibited)

1 1 16-bit PPG 1-ch mode

211


Note:

• Do not set these bits to "10".

• When setting these bits to "01", do not set the PEN0 bit of the PPGC0 register and the PEN1bit of the PPGC1 register to "01". Setting the PEN0 bit and PEN1 bit to "11" or "00" at thesame time is recommended.

• When setting these bits to "11", rewrite PPGC0/PPGC1 by a word transfer to set the PEN0bit and PEN1 bit to "11" or "00" at the same time.


Bit 8 is reserved. Be sure to set this bit to 1.

212


13.3.3 PPG0/PPG1 Output Pin Control Register (PPGOE)

The PPG0/1 output pin control register (PPGOE) controls 8/16-bit PPG pin output.

PPG0/PPG1 Output Pin Control Register (PPGOE)

Figure 13.3-4 PPG0/PPG1 Output Pin Control Register (PPGOE)

[Bits 7 to 5] PCS2 to PCS0 (Ppg Count Select)

Bits PCS2 to PCS0 select the operation clock for the ch1 down counter as listed in Table13.3-10 "Function of Count Clock Selection Bits (PCS2 to PCS0)". These bits are initializedto "000" at a reset. These bits can be read and written.

Note:

In the 8-bit prescaler + 8-bit PPG mode and 16-bit PPG mode, the PPG for ch1 operateswith the count clock signal received from ch0. The specification of the PCS1 bit is invalid.

[Bits 4 to 2] PCM2 to PCM0 (Ppg Count Mode)

PCM2 to PCM0 bits select the operation clock for the ch0 down counter as listed in Table13.3-11 "Function of the Count Clock Selection Bits (PCM2 to PCM0)". These bits areinitialized to "000" at a reset. These bits can be read and written.

7 6 5 4 3 2 1 0Address: ch0,1 0046H

PCS2 PCS1 PCS0 PCM2 PCM1 PCM0 PE11 PE01 PPGOE

(R/W) (R/W) (R/W) (R/W)(R/W) (R/W) (R/W) (R/W)(0) (0) (0) (0) (0) (0)(0) (0)

Bit No.


PPG0/1 output control register

Table 13.3-10 Function of Count Clock Selection Bits (PCS2 to PCS0)

PCS2 PCS1 PCS0 Operation mode

0 0 0 Peripheral clock (62.5 ns/machine clock frequency of 16 MHz)

0 0 1 Peripheral clock/2 (125 ns/machine clock frequency of 16 MHz)


0 1 1 Peripheral clock/8 (500 µs/machine clock frequency of 16 MHz)


1 1 1 Clock input from timebase timer (128 µs/oscillation clock frequency of 4 MHz)

213



The PE11 bit controls the pulse output external pin PG11 as listed in Table 13.3-12"Function of PG11 Pin Output Enable Bit (PE11)". This bit is initialized to 0 at a reset. Thisbit can be read and written.


The PE01 bit controls the pulse output external pin PG01 as listed in Table 13.3-13"Function of the PG01 Pin Output Enable Bit (PE01)".


Table 13.3-11 Function of the Count Clock Selection Bits (PCM2 to PCM0)

PCM2 PCM1 PCM0 Operation mode

0 0 0 Peripheral clock (62.5 ns/machine clock frequency of 16 MHz)





1 1 1 Clock input from timebase timer (128 µs/oscillation clock frequency of 4 MHz)

Table 13.3-12 Function of PG11 Pin Output Enable Bit (PE11)

PE11 Function

0 General-purpose port pin (pulse output disabled)


Table 13.3-13 Function of the PG01 Pin Output Enable Bit (PE01)

PE01 Function



214


13.3.4 Reload Registers (PRLL and PRLH)

The reload registers (PRLL and PRLH) store values to be reloaded into the down counter PCNT.These registers have the following function:• PRLH: Stores the reload value for the high-level side.• PRLL: Stores the reload value for the low-level side.

Reload Registers (PRLL and PRLH)

Figure 13.3-5 Reload Registers (PRLL and PRLH)

The reload registers, each consisting of 8 bits, store values to be reloaded to the down counterPCNT. These registers have the following functions:

Each register can be read and written.

Note:

In the 8-bit prescaler + 8-bit PPG mode, setting different values in PRLL and PRLH for ch0may vary the PPG waveform on ch1 from cycle to cycle. We recommend setting the PRLLand PRLH for ch0 to the same value.

15 14 13 12 11 10 9 8Address: ch1 000041H

ch1 000043H PRLH0,1

7 6 5 4 3 2 1 0Address: ch0 000040H

ch1 000042H PRLL0,1



(X) (X) (X) (X) (X) (X) (X) (X)

(X) (X) (X) (X) (X) (X) (X) (X)

Bit No.

Bit No.

Read/write

Read/write

Initial value

Initial value

Reload register H

Reload register L

Register name Function

PRLL Stores the reload value for the low-level side.

PRLH Stores the reload value for the high-level side.

215


13.4 Operation of 8/16-Bit PPG

The 8/16-bit PPG contains two 8-bit PPG units and can operate in the 2-channel independent mode and in the 8-bit prescaler + 8-bit PPG mode and the 16-bit PPG 1-channel mode.

Operation of 8/16-Bit PPG

Each of the 8-bit PPG units has two 8-bit reload registers for the low-level and high-level sides(PRLL and PRLH). The value for the low level and the value for the high level written in theseregisters are alternately reloaded into the 8-bit down counter (PCNT), which counts down oneach pulse of the count clock. At a reload operation performed when a borrow is generated inthe counter, the pin output (PPG) value is inverted. This operation allows the pin output (PPG)to output a pulse signal with low-level and high-level widths corresponding to the reload registervalues.

Operation is started and restarted by writing the appropriate register bit.

Table 13.4-1 "Relationship between Reload Operation and Pulse Output" lists the relationshipbetween reload operation and pulse output.

When bit 4 (PIE0) of the PPG0 operation mode control register (PPGC0) is 1 and when bit 12(PIE1) of the PPG1 operation mode control register (PPGC1) is 1, a borrow from 00H to FFH ineach counter (a borrow from 0000H to FFFFH in the 16-bit PPG mode) causes an interruptrequest to be output.

Table 13.4-1 Relationship between Reload Operation and Pulse Output

Reload operation Status transition of output pins PPG0 and PPG1

PRLH --> PCNT PPG0x/1x [0 --> 1] rising edge

PRLL --> PCNT PPG0x/1x [1 --> 0] falling edge

216


13.4.1 8/16-Bit PPG Operation Modes

The following three types of operation mode are available for the 8/16-bit PPG:• 2-channel independent mode• 8-bit prescaler + 8-bit PPG mode• 16-bit PPG 1-channel mode

8/16-Bit PPG Operation Modes

2-channel independent mode

The 2-channel independent mode is the operation mode in which two 8-bit PPG units areoperated independently of each other. The PPG00 and PPG01 pins are connected to the PPGoutput of ch0 and the PPG10 and PPG11 pins are connected to the PPG output of ch1.

8-bit prescaler + 8-bit PPG mode

The 8-bit prescaler + 8-bit PPG mode is the operation mode in which an 8-bit PPG waveformwith an arbitrary cycle can be output by operating ch0 as an 8-bit prescaler and counting ch1with ch0 borrow output.

The PPG00 and PPG01 pins are connected to the prescaler output of ch0 and the PPG10 andPPG11 pins are connected to the PPG output of ch1.

16-bit PPG 1-channel mode

The 16-bit PPG 1-channel mode is the operation mode in which ch0 and ch1 interact andoperate as the 16-bit PPG. The PPG00 and PPG01 pins and PPG10 and PPG11 pins are bothconnected to the 16-bit PPG output.

217


13.4.2 8/16-Bit PPG Output Operation

In the 8/16-bit PPG, the PPG unit on ch0 is activated and starts counting when bit 7 (PEN0) of the PPG0 operation mode control register (PPGC0) is set to 1. The PPG unit on ch1 is activated and starts counting when bit 15 (PEN1) of the PPG1 operation mode control register (PPGC1) is set to 1. After the operation is started, the counting operation is stopped by setting the PEN0 bit of the PPGC0 register or the PEN1 bit of the PPGC1 register to 0. After the counting operation stops, pulse output is retained at the low level.

8/16-Bit PPG Output Operation

For 8/16-bit PPG operation, note the following two points:

• In the 8-bit prescaler + 8-bit PPG mode, do not enable ch1 operation while ch0 is in stoppedstate.

• In 16-bit PPG mode, use the PEN0 bit of the PPGC0 register and the PEN1 bit of thePPGC1 register to perform start and stop control at the same time.

During PPG operation, a pulse waveform is output successively with an arbitrary frequency andan arbitrary duty ratio (the ratio of the time the pulse wave is at the high level and the time thepulse wave is at the low level). Once the PPG starts outputting a pulse waveform, it does notstop until the setting for operation stop is made.

Figure 13.4-1 "Output Waveform during PPG Output Operation" shows the output waveformduring PPG output operation.

Figure 13.4-1 Output Waveform during PPG Output Operation

PEN

T x (L+1) T x (H+1)

Start of operation by PEN (starting with the low level)

Output pin PPG

(Start)

L: PRLL valueH: PRLH valueT: Peripheral clock ( , /4, /16) or input from timebase counter (by PPGC clock select)

218


Relationship between the Reloaded Value and Pulse Width

The pulse width of the output pulse signal is obtained by multiplying the value in reload register+ 1 by the count clock cycle. Note that when the reload register value is 00H during 8-bit PPGoperation and when the reload register value is 0000H during 16-bit PPG operation, the pulsewidth becomes one count clock cycle. When the reload register value is FFH during 8-bit PPGoperation, the pulse width is 256 count clock cycles. When the reload register value is FFFFHduring 16-bit PPG operation, the pulse width is 65536 count clock cycles.

The expressions for calculating a pulse width are as follows:

Pl = T x (L + 1)

Ph = T x (H + 1)

L: PRLL value

H: PRLH value

T: Input clock cycle

Ph: High-level pulse width

Pl: Low-level pulse width

219


13.4.3 Selecting 8/16-Bit PPG Count Clock

As the count clock used for 8/16-bit PPG operation, peripheral clock and timebase counter inputs are used. Four types of count clock input can be selected. (Two types of count clock can only be selected for the PPG unit on ch1.)

Selecting 8/16-Bit PPG Count Clock

Six types of count clock are available:

• If the value of bits 2 and 1 (PCM1 and PCM0) of the PPGC0 register is "00", one count clockis counted for each peripheral clock.

• If the value of bits 2 and 1 (PCM1 and PCM0) of the PPGC0 register is "01", one count clockis counted for each peripheral clock with 4 cycles.

• If the value of bits 2 and 1 (PCM1 and PCM0) of the PPGC0 register is "10", one count clockis counted for each peripheral clock with 16 cycles.

• If the value of bits 2 and 1 (PCM1 and PCM0) of the PPGC0 register is "11", one count clockis counted for each input from the timebase counter.

• If the value of bit 14 (PCS1) of the PPGC1 register is 0, one count clock is counted for eachperipheral clock.

• If the value of bit 14 (PCS1) of the PPGC1 register is 1, one count clock is counted for eachinput from the timebase counter.

In the 8-bit prescaler + 8-bit PPG mode and the 16-bit PPG mode, however, the PPG unit onch1 operates with the count clock signal from ch0. Therefore, the value of bit 14 (PCS1) of thePPGC1 register is invalid.

When the timebase counter input is used, the first count cycle when PPG operation is triggeredand the first count cycle when PPG operation is stopped may be shifted. When the timebasecounter is cleared during operation of this module, a cycle shift may also occur.

In 8-bit prescaler + 8-bit PPG mode, when ch0 is operating and ch1 is in the stopped state,activating ch1 may shift the first count cycle.

220


13.4.4 Controlling 8/16-Bit PPG Pulse Output on Pins

The pulse output generated by operating the 8/16-bit PPG can be output on external pins PPG00, PPG01, PPG10, and PPG11.

Controlling 8/16-Bit PPG Pulse Output on Pins

The pulse output generated by operating the 8/16-bit PPG can be output on external pinsPPG00, PPG01, PPG10, and PPG11.

Output on the external pin PPG00 is enabled via bit 5 (PE00) of the PPGC0 register and outputon the external PPG01 is enabled via bit 0 (PE01) of the PPGOE register. Output on theexternal pin PPG10 is enabled via bit 13 (PE10) of the PPGC1 register and output on theexternal pin PPG11 is enabled via bit 1 (PE11) of the PPGOE register. When these bits are 0(initial value), the pulse is output is not output on the external pins; these pins function as ageneral-purpose port. When these bits are set to 1, the pulse output is output on the externalpins.

In 16-bit PPG mode, the same waveform is output on PPG00, PPG01, PPG10, and PPG11, sothe same output can be obtained by enabling the output via either external pin.

In 8-bit prescaler + 8-bit PPG mode, a toggle waveform from the 8-bit prescaler is output onPPG00 and PPG01, and a waveform from the 8-bit PPG is output on PPG10 and PPG11.Figure 13.4-2 "Output Waveforms in 8-bit Prescaler + 8-bit PPG Mode" shows an example ofoutput waveforms in this mode.

Figure 13.4-2 Output Waveforms in 8-bit Prescaler + 8-bit PPG Mode

Ph0 Pl0

PPG0

PPG1

Ph1 Pl1

Pl0 = T (L0+1)Ph0 = T (L0+1)Pl1 = T (L0+1) (L1+1)Ph1 = T (L0+1) (H1+1)

L0: ch0 PRLL value and ch0 PRLH valueL1: ch1 PRLL valueH1: ch1 PRLH valueT: Input clock cyclePh0: High-level pulse width on PPG00 and PPG01Pl0: Low-level pulse width on PPG00 and PPG01Ph1: High-level pulse width on PPG10 and PPG11Pl1: Low-level pulse width on PPG10 and PPG11

Note: We recommend setting the same value in PRLL for ch0 and PRLH for ch0.

221


13.4.5 Write Timing for 8/16-Bit PPG Reload Registers

In all modes other than 16-bit PPG mode, using a word transfer instruction to write to the reload registers (PRLL and PRLH) is recommended. Using two byte transfer instructions to write data to these registers may result in an output with an unpredictable pulse width, depending on the write timing.

Writing Time Chart for 8/16-Bit PPG Reload Registers

Figure 13.4-3 Write Timing Chart

In the timing chart shown in Figure 13.4-3 "Write Timing Chart", suppose that the PRLL registervalue is rewritten from A to C before (1) and the PRLH register value is rewritten from B to Dafter (1). In this case, a pulse with count C for the low-level side and a pulse with count B forthe high-level side are output once because the values of the reload register (PRL) include C inPPLL and B in PRLH at the timing in (1).

Similarly, in 16-bit PPG mode, perform long-word transfer to write data to the PRL register forch0 and ch1 or perform word transfer to write data in PRL register in order from ch0 to ch1. Inthis mode, a write operation to the PRLL register for ch0 is performed temporarily. After a writeoperation to the PRL register for ch1 has been performed, writing to the PRL register for ch0 isperformed.

As shown in Figure 13.4-4 "Block Diagram Portion for PRL Writing", in modes other than 16-bitPPG mode, writing to the PPL registers for ch0 and ch1 can be performed independently.

Figure 13.4-4 Block Diagram Portion for PRL Writing

PPG0B B C B C C

A A D D(1)

Data to be written to PRL for ch0 Data to be written to PRL for ch1

Write for ch0 in other than 16-bit PPG mode Temporary latch

In 16-bit PPG mode, data is transferred in synchronization with writing for ch1.

PRL for ch0

Write for ch1

PRL for ch1

222


13.4.6 8/16-Bit PPG Interrupts

An 8/16-bit PPG interrupt becomes active when the reloaded value is counted out to cause a borrow.

8/16-Bit PPG Interrupts

In 8-bit PPG 2-channel mode and 8-bit prescaler + 8-bit PPG mode, each interrupt request isgenerated via a borrow in each counter. In 16-bit PPG mode, however, the PUF0 and PUF1bits are set at the same time by a borrow in the 16-bit counter. We recommend enabling onlyPIE0 or PIE1 bit to unify the interrupt cause. Moreover, we recommend manipulating the PUF0and PUF1 bits at the same time to clear the interrupt cause.

223


13.4.7 Initial Value for Each Hardware

This section explains the initial value at reset for each piece of 8/16-bit PPG hardware.

Initial Value of Each 8/16-Bit Hardware

Each piece of 8/16-bit hardware is initialized at reset as follows:

Registers

• PPGC0 --> 0X000001B

• PPGC1 --> 00000001B

• PPG0E --> XXXXXX00B

Pulse output

• PPG00, PPG01 --> L

• PPG10, PPG11 --> L

• PE00 --> PPG00 and PPG01 output disabled

• PE10 --> PPG10 and PPG11 output disabled

Interrupt request

• IRQ0 --> L

• IRQ1 --> L

Hardware other than the above is not initialized.

224

CHAPTER 14 8/16-BIT UP/DOWN COUNTER/TIMER

This chapter explains the functions and operation of the 8/16-bit up/down counter/timer.

14.1 "Outline of the 8/16-Bit Up/Down Counter/Timer"

14.2 "Block Diagrams of the 8/16-Bit Up/Down Counter/Timer"

14.3 "Registers of the 8/16-Bit Up/Down Counter/Timer"

14.4 "Selecting Count Modes of the 8/16-Bit Up/Down Counter/Timer"

14.5 "Reload and Compare Functions of the 8/16-Bit Up/Down Counter/Timer"

14.6 "Simultaneous Activation of the Reload and Compare Functions of the 8/16-Bit Up/Down Counter/Timer"

14.7 "Writing Data to the UDCR Register of the 8/16-Bit Up/Down Counter/Timer"

225


14.1 Outline of the 8/16-Bit Up/Down Counter/Timer

The 8/16-bit up/down counter/timer consists of six event input pins, two 8-bit up/down counters, two 8-bit reload/compare registers, and their control circuits.

Functions of the 8/16-Bit Up/Down Counter/Timer

The main functions of the 8/16-bit up/down counter/timer are as follows:

Countable range

The 8-bit count register can count in the range from 0 to 255. (For 16-bit x 1 operation mode,the register can count in the range from 0 to 65534.)

Count modes

Four count modes can be selected by selecting the count clock.

• Timer mode

• Up/down counter mode

• Phase difference count mode (multiplied by 2)

• Phase difference count mode (multiplied by 8)

Count clocks (in 16 MHz operation)

In timer mode, two types of internal clock can be selected.

• 125 ns (8 MHz: Divided by 2)

• 0.5 µs (1 MHz: Divided by 8)

Detection edge selection

In up/down count mode, four types of detection edge can be selected using an external pin inputsignal.

• Edge detection prohibited

• Falling edge detection

• Rising edge detection

• Falling and rising edge detection

Phase difference count mode

The term phase difference count mode applies to the counts of encoders such as motors. Byinputting the A-, B-, or Z-phase outputs of an encoder, the rotation angle and number ofrotations can be easily counted with high precision.

ZIN pin

Two types of ZIN pin function can be selected.

• Counter clear function

• Gate function

226

14.1 Outline of the 8/16-Bit Up/Down Counter/Timer

Compare/reload function

The 8/16-bit up/down counter/timer has compare and reload functions. Each function can beused individually or in combination. Activating both functions enables up/down counting usingan arbitrary width.

• Compare function (interrupt output during comparison)

• Compare function (interrupt output and counter clear during comparison)

• Reload function (interrupt output and reload during underflow)

• Compare/reload function (interrupt output and counter clear during comparison and interruptoutput and reload at underflow)

• Compare/reload prohibited

Interrupt control

The interrupts generated at comparison, reload (underflow), and overflow can be controlledindividually.

Count direction identification

The count direction flag can be used to identify the immediately preceding count direction.

Count direction and interrupt

An interrupt is generated when the count direction changes.

227


14.2 Block Diagrams of the 8/16-Bit Up/Down Counter/Timer

This section shows block diagrams of the 8/16-bit up/down counter/timer.

Block Diagrams of the 8/16-Bit Up/Down Counter/Timer

Figure 14.2-1 "Block Diagram of the 8/16-Bit Up/Down Counter/Timer (ch0)" shows a blockdiagram of the 8/16-bit up/down counter/timer (channel 0).

Figure 14.2-1 Block Diagram of the 8/16-Bit Up/Down Counter/Timer (ch0)

CGE1 CGE0 C/GS

CTUTZIN0

UCRE RLDE

UDCC

CarryCMPF

UDFF OVFFCES1 CES0

CMS1 CMS0 CITE UDIE

UDF1 UDF0 CDCF CFIE

CSTR

CLKS

AIN0

BIN0

8bit

8bit

Internal data bus

RCR0 (reload/compare register 0)

Edge/level detectionReload control

Counter clear

UDCR0 (up/down count register 0)

Up/down count

clock selection

Count clock

PrescalerInterrupt output

228

14.2 Block Diagrams of the 8/16-Bit Up/Down Counter/Timer

Figure 14.2-2 "Block Diagram of the 8/16-Bit Up/Down Counter/Timer (ch1)" shows a blockdiagram of the 8/16-bit up/down counter/timer (channel 1).

Figure 14.2-2 Block Diagram of the 8/16-Bit Up/Down Counter/Timer (ch1)

CGE1 CGE0 C/GS

CTUTZIN1

UCRE RLDE

UDCC

CMPF

UDFF OVFF

CMS1 CMS0 CES1 CES0 EN16 CITE UDIE

Carry

AIN1

BIN1 UDF1 UDF0 CDCF CFIE

CSTR

CLKS

8bit

8bit

Internal data bus

RCR1 (reload/compare register 1)

Edge/level detectionReload control

Counter clear

UDCR1 (up/down count register 1)

Up/down count

clock selection

Count clock

Prescaler Interrupt output

229


14.3 Registers of the 8/16-Bit Up/Down Counter/Timer

The 8/16-bit up/down counter/timer has the registers shown in Figure 14.3-1 "Register Configuration of the 8/16-Bit Up/Down Counter/Timer".

Registers of the 8/16-Bit Up/Down Counter/Timer

Figure 14.3-1 Register Configuration of the 8/16-Bit Up/Down Counter/Timer

15 14 13 12 11 10 9 8

UDCR1Address:000071H D17 D16 D15 D14 D13 D12 D11 D10

7 6 5 4 3 2 1 0


Bit No.

(R) (R) (R) (R)(0) (0) (0) (0) (0)

(R)(0)

(R) (R)(0)

(R)(0)

(R) (R) (R) (R)(0) (0) (0) (0) (0)

(R)(0)

(R) (R)(0)

(R)(0)

Bit No.

15 14 13 12 11 10 9 8

RCR1Address:000073H D17 D16 D15 D14 D13 D12 D11 D10

7 6 5 4 3 2 1 0


(W) (W) (W) (W)(0) (0) (0) (0) (0)

(W)(0)

(W) (W)(0)

(W)(0)

(W) (W) (W) (W)(0) (0) (0) (0) (0)

(W)(0)

(W) (W)(0)

(W)(0)

Bit No.

Bit No.

7 6 5 4 3 2 1 0

CSR0,1Address:000074H CSTR CITE UDIE CMPF OVFF UDFF UDF1 UDF0Address:000078H

Bit No.

(R/W) (R/W) (R) (R)(0) (0) (0) (0) (0)

(R/W)(0)

(R/W) (R/W)(0)

(R/W)(0)

15 14 13 12 11 10 9 8

CCRH0Address:000077H M16E CDCF CFIE CLKS CMS1 CMS0 CES1 CES0

Bit No.

(R/W) (R/W) (R/W) (R/W)(0) (0) (0) (0) (0)

(R/W)(0)

(R/W) (R/W)(0)

(R/W)(0)

15 14 13 12 11 10 9 8

CCRH1Address:00007BH CDCF CFIE CLKS CMS1 CMS0 CES1 CES0

Bit No.

(R/W) (R/W) (R/W) (R/W)(-) (0) (0) (0) (0)

(R/W)(0)

(-) (R/W)(0)

(R/W)(0)

7 6 5 4 3 2 1 0

CCRL0,1Address:000076HCTUT UCRE RLDE UDCC CGSC CGE1 CGE0Address:00007AH

Bit No.

(R/W) (R/W) (R/W) (R/W)(-) (0) (0) (0) (0)

(R/W)(0)

(-) (R/W)(0)

(R/W)(0)

Up/down count register 1

Read/write

Read/write

Read/write

Read/write

Read/write

Initial value

Initial value

Initial value

Initial value

Initial value


Reload/compare register 1


Counter status register 0/1

Counter control register 0high- order bits

Counter control register 1 high- order bits

Read/write

Read/write

Read/write

Initial value

Initial value

Initial value

Counter control register 0/1low-order bits

15 8 7 0

8bit 8bit

UDCR1

RCR1

Reserved area

CCRH0

Reserved area

CCRH1

UDCR0

RCR0

CSR0

CCRL0

CSR1

CCRL1

230


14.3.1 Up/Down Count Registers 0 and 1 (UDCR0 and UDCR1)

The up/down count registers 0 and 1 (UDCR0 and UDCR1) are 8-bit count registers. The internal prescaler or input of the AIN or BIN pins is used to execute the up/down count operation.

Up/Down Count Registers 0 and 1 (UDCR0 and UDCR1)

Figure 14.3-2 Up/Down Count Registers ch0 and ch1 (UDCR0 and UDCR1)

The up/down count registers (UDCR) are 8-bit count registers. The internal prescaler or input ofthe AIN or BIN pins is used to execute the up/down count operation. In addition, in 16-bit countmode, the up/down count registers can operate as 16-bit count registers. In this case, thesetting values of the eight high-order bits of the control register become ineffective for operation.

Direct write operations cannot be executed for the UDCR registers. Writing to an UDCRregister must be done through a reload/compare register (RCR). Write the value to be written tothe UDCR register to the RCR register first. Then, set the CTUT bit in the count control registerlower (CCRL) to 1 to transfer the value in the RCR register to the UDCR register.

When activated in 16-bit mode, use word access to read the UDCR registers.

15 14 13 12 11 10 9 8


7 6 5 4 3 2 1 0


Bit No.

(R) (R) (R) (R)(0) (0) (0) (0) (0)

(R)(0)

(R) (R)(0)

(R)(0)

(R) (R) (R) (R)(0) (0) (0) (0) (0)

(R)(0)

(R) (R)(0)

(R)(0)

Bit No.





231


14.3.2 Reload/Compare Registers 0 and 1 (RCR0 and RCR1)

The reload/compare registers 0 and 1 (RCR0 and RCR1) are 8-bit reload/compare registers. These registers are used to set the reload and compare values.

Reload/Compare Registers 0 and 1 (RCR0 and RCR1)

Figure 14.3-3 Reload/Compare Registers 0 and 1 (RCR0 and RCR1)

The reload/compare registers are 8-bit reload/compare registers. These registers are used toset the reload and compare values. The reload value is the same as the compare value. Whenthe reload and compare functions are activated, up/down counting is enabled between 00H andthe RCR register value (In 16-bit operation mode: 0000H and the RCR register value).

Only write operations are allowed for these registers. The registers cannot be read. Whilecounting is stopped, the CTUT bit in the CCR0/CCR1 register can be set to 1 to transfer (reloadby the software) the value in the RCR register to the up/down count register (UDCR).

Use word access to write to the reload/compare registers.

15 14 13 12 11 10 9 8


7 6 5 4 3 2 1 0


(W) (W) (W) (W)(0) (0) (0) (0) (0)

(W)(0)

(W) (W)(0)

(W)(0)

(W) (W) (W) (W)(0) (0) (0) (0) (0)

(W)(0)

(W) (W)(0)

(W)(0)

Bit No.

Bit No.Reload/compare register 1




232


14.3.3 Counter Status Registers 0 and 1 (CSR0 and CSR1)

The counter status registers 0 and 1 (CSR0 and CSR1) are used for the settings of the event flag and interrupt operation control of channels 0 and 1 in 8-bit mode.

Counter Status Registers 0 and 1 (CSR0 and CSR1)

Figure 14.3-4 "Counter Status Registers 0 and 1 (CSR0 and CSR1)" shows the bit configurationof the counter status registers 0 and 1 (CSR0 and CSR1).

Figure 14.3-4 Counter Status Registers 0 and 1 (CSR0 and CSR1)

[Bit 7] CSTR

The CSTR bit controls starting and stopping of the count operation for the up/down countregister (UDCR).

[Bit 6] CITE

When the CMPF bit has been set (compare occurred), the CITE bit controls whether to allowor prohibit interrupt output to the CPU.

7 6 5 4 3 2 1 0

CSR0,1Address:000074H CSTR CITE UDIE CMPF OVFF UDFF UDF1 UDF0Address:000078H

Bit No.

(R/W) (R/W) (R) (R)(0) (0) (0) (0) (0)

(R/W)(0)

(R/W) (R/W)(0)

(R/W)(0)

Counter status registers 0 and 1


Table 14.3-1 CSTR (Count Start Bit)

CSTR Function

0 Stops the count operation [initial value].

1 Starts the count operation.

Table 14.3-2 CITE (Compare Interrupt Output Control Bit)

CITE Function

0 Compare interrupt output prohibited [initial value].

1 Compare interrupt output allowed

233


[Bit 5] UDIE

When the OVFF and UDFF bits have been set (overflow/underflow occurred), the UDIE bitcontrols whether to allow or prohibit interrupt output to the CPU.

[Bit 4] CMPF (Compare Detection Flag)

When comparing the UDCR register and reload/compare register (RCR) values, the CMPFflag indicates whether the values match. If the UDCR and RCR register values match whencounting is started, this flag is set as soon as counting starts. In write operations, the flagcan only be set to 0, not 1.

[Bit 3] OVFF (Overflow Detection Flag)

The OVFF flag indicates whether an overflow occurred. In write operations, this flag canonly be set to 0, not to 1.

[Bit 2] UDFF

The UDFF flag indicates whether an underflow occurred. In write operations, this flag canonly be set to 0, not to 1.

Table 14.3-3 UDIE (Overflow/Underflow Interrupt Output Control Bit)

UDIE Function

0 Overflow/underflow interrupt output prohibited [initial value]

1 Overflow/underflow interrupt output allowed

Table 14.3-4 CMPF (Compare Detection Flag)

CMPF Function

0 The result of comparison is that the values did not match [initial value].

1 The result of comparison is that the values match.

Table 14.3-5 OVFF (Overflow Detection Flag)

OVFF Function

0 Overflow did not occur [initial value].

1 Overflow occurred.

Table 14.3-6 UDFF (Underflow Detection Flag)

UDFF Function

0 Underflow did not occur [initial value].

1 Underflow occurred.

234


[Bits 1 and 0] UDF1 and UDF0

The UDF1 and UDF0 bits indicate the immediately preceding count operation (up/down).These bits can only be read. They cannot be written.

Table 14.3-7 UDF1 and UDF0 (Up/Down Flag)

UDF1 UDF0 Function

0 0 No input [initial value].

0 1 Down count

1 0 Up count

1 1 Up/down counting occurred simultaneously.

235


14.3.4 Counter Control Register 0 Higher (CCRH0)

The counter control register 0 higher (CCRH0) is used to set operation control of channel 0 in 8-bit mode and set switching to 16-bit mode. This register is used to set up operation in combination with the counter control register 0 lower (CCRL0).

Counter Control Register 0 Higher (CCRH0)

Figure 14.3-5 "Counter Control Register 0 Higher (CCRH0)" shows the bit configuration of thecounter control register 0 higher (CCRH0).

Figure 14.3-5 Counter Control Register 0 Higher (CCRH0)

[Bit 15] M16E

The M16E bit selects (switches between) 8-bit x 2-channel or 16-bit x 1-channel operationmode.

[Bit 14] CDCF

The CDCF flag is set when the count direction changes. This flag is set if the count directionchanges from up to down or from down to up while counting is being started. In writingoperations, this flag can only be set to 0, not to 1.

15 14 13 12 11 10 9 8

CCRH0Address:000077H M16E CDCF CFIE CLKS CMS1 CMS0 CES1 CES0

Bit No.

(R/W) (R/W) (R/W) (R/W)(0) (0) (0) (0) (0)

(R/W)(0)

(R/W) (R/W)(0)

(R/W)(0)

Counter control register 0 higher


Table 14.3-8 M16E (16-Bit Mode Allowed Bit)

M16E 16-bit mode allowed setting

0 8-bit x 2-channel operation mode [initial value]

1 16-bit x 1-channel operation mode

Table 14.3-9 CDCF (Count Direction Change Flag)

CDCF Direction change detection

0 No direction change [initial value]

1 Direction change (at least once)

236


[Bit 13] CFIE

When the CDCF bit has been set, the CFIE bit controls interrupt output for the CPU. Aninterrupt is generated if the count direction changes at least once while counting is beingstarted.

[Bit 12] CLKS

When timer mode is selected, the CLKS bit selects the frequency of the built-in prescaler.

The CLKS bit is valid only in timer mode. In this case, only counting down is enabled.

[Bits 11 and 10] CMS1 and CMS0

The CMS1 and CMS0 bits select the count mode.

[Bits 9 and 8] CES1 and CES0

When up/down count mode is selected, the CES1 and CES0 bits select the detection edgeof the external pins AIN and BIN. In other than up/down count mode, this setting is invalid.

Table 14.3-10 CFIE (Count Direction Change Interrupt Enable Bit)

CFIE Direction change interrupt output

0 Direction change interrupt output prohibited [initial value]

1 Direction change interrupt output allowed.

Table 14.3-11 CLKS (Built-In Prescaler Selection Bit)

CLKS Selection internal clock

0 2 machine cycles [initial value]

1 8 machine cycles

Table 14.3-12 CMS1 and CMS0 (Count Mode Selection Bits)

CMS1 CMS0 Count mode

0 0 Timer mode (down count) [initial value].

0 1 Up/down count mode

1 0 Phase difference count mode (multiplied by 2)


Table 14.3-13 CES1 and CES0 (Count Clock Edge Selection Bits)

CES1 CES0 Selection edge

0 0 Edge detection prohibited [initial value].



1 1 Rising and falling edge detection

237


14.3.5 Counter Control Register 1 Higher (CCRH1)

The counter control register 1 higher (CCRH1) is used to set operation control of channel 1 in 8-bit mode. This register is used to set up operation in combination with the counter control register 1 lower (CCRL1).

Counter Control Register 1 Higher (CCRH1)

Figure 14.3-6 "Counter Control Register 1 Higher (CCRH1)" shows the bit configuration of thecounter control register 1 higher (CCRH1).

Figure 14.3-6 Counter Control Register 1 Higher (CCRH1)

[Bit 15] Unused bit

[Bit 14] CDCF

The CDCF flag is set when the count direction changes. This flag is set if the count directionchanges from up to down or from down to up while counting is being started. In writingoperations, this flag can only be set to 0, not to 1.

[Bit 13] CFIE

When the CDCF bit has been set, the CFIE bit controls interrupt output for the CPU. Aninterrupt is generated if the count direction changes at least once while counting is beingstarted.

15 14 13 12 11 10 9 8

CCRH1Address:00007BH CDCF CFIE CLKS CMS1 CMS0 CES1 CES0

Bit No.

(R/W) (R/W) (R/W) (R/W)(-) (0) (0) (0) (0)

(R/W)(0)

(-) (R/W)(0)

(R/W)(0)

Counter control register 1 higher


Table 14.3-14 CDCF (Count Direction Change Flag)

CDCF Direction change detection

0 The direction did not change [initial value].

1 The direction changed at least once.

Table 14.3-15 CFIE (Count Direction Change Interrupt Enable Bit)

CFIE Direction change interrupt output

0 Direction change interrupt output prohibited [initial value].

1 Direction change interrupt output allowed

238


[Bit 12] CLKS

When timer mode is selected, the CLKS bit selects the frequency of the built-in prescaler.The CLKS bit is valid only in timer mode. In this case, only down count is enabled.

[Bits 11 and 10] CMS1 and CMS0

The CMS1 and CMS0 bits select the count mode.

[Bits 9 and 8] CES1 and CES0

When up/down count mode is selected, the CES1 and CES0 bits select the detection edgeof the external pins AIN and BIN. In other than up/down count mode, this setting is invalid.

Table 14.3-16 CLKS (Built-In Prescaler Selection Bit)

CLKS Selection internal clock

0 2 machine cycles [initial value].

1 8 machine cycles

Table 14.3-17 CMS1 and CMS0 (Count Mode Selection Bits)its)

CMS1 CMS0 Count mode

0 0 Timer mode (down count) [initial value].

0 1 Up/down count mode



Table 14.3-18 CES1 and CES0 (Count Clock Edge Selection Bits)

CES1 CES0 Selection edge




1 1 Rising and falling edge detection

239


14.3.6 Counter Control Registers 0 and 1 Lower (CCRL0 and CCRL1)

The counter control registers 0 and 1 lower (CCRL0 and CCRL1) are used to set operation control of channels 0 and 1 in 8-bit mode. These registers are used to set up operation in combination with the counter control registers 0 and 1 higher (CCRH0 and CCRH1).

Counter Control Registers 0 and 1 Lower (CCRL0 and CCRL1)

Figure 14.3-7 "Counter Control Registers Lower Channels 0 and 1 (CCRL0 and CCRL1)" showsthe bit configuration of the counter control registers 0 and 1 lower (CCRL0 and CCRL1).

Figure 14.3-7 Counter Control Registers Lower Channels 0 and 1 (CCRL0 and CCRL1)

[Bit 7] Unused bit

[Bit 6] CTUT (Counter Write Bit)

The CTUT bit is used to transfer data from the RCR to the UDCR. When this bit is set to 1,data is transferred from the reload/compare register (RCR) to the up/down count register(UDCR). Writing 0 has no effect. The read value for this bit is always 0. Do not set this bitto 1 while counting is being started (when the CSTR bit in the counter status register (CSR0)is 1).

[Bit 5] UCRE

The UCRE bit controls clearing of the UDCR register due to comparison. This bit affectsonly clearing due to a comparison and has no affect on the UDCR register clear functions(such as via the ZIN pin)

7 6 5 4 3 2 1 0

CCRL0,1Address:000076H CTUT UCRE RLDE UDCC CGSC CGE1 CGE0Address:00007AH

Bit No.

(R/W) (R/W) (R/W) (R/W)(-) (0) (0) (0) (0)

(R/W)(0)

(-) (R/W)(0)

(R/W)(0)

Counter control registers 0 and 1 lower


Table 14.3-19 UCRE (UDCR Clear Enable Bit)

UCRE Counter clear using compare

0 Counter clear prohibited [initial value].

1 Counter clear allowed

240


[Bit 4] RLDE (Reload Enable Bit)

The RLDE bit controls activation of the reload function. If the UDCR register underflowswhen the reload function is activated, the RCR register value is transferred to the UDCRregister.

[Bit 3] UDCC (UDCR Clear Bit)

The UDCC bit clears the UDCR register. Setting this bit to 0 clears the UDCR register to0000H. Writing 1 is invalid. The read value for this bit is always 1.

[Bit 2] CGSC

The CGSC bit selects the function of the external pin ZIN.

[Bits 1 and 0] CGE1 and CGE0

The CGE1 and CGE0 bits select the detection edge/level of the external pin ZIN.

Table 14.3-20 RLDE (Reload Enable Bit)

RLDE Reload function

0 Reload function prohibited [initial value].

1 Reload function allowed

Table 14.3-21 CGSC (Counter Clear/Gate Selection Bit)

CGSC ZIN function

0 Counter clear function [initial value].

1 Gate function

Table 14.3-22 CGE1 and CGE0 (Counter Clear/Gate Edge Selection Bits)

CGE1 CGE0 Counter clear function selected

Gate function selected


Level detection prohibited (count disable)

0 1 Falling edge detection LOW level

1 0 Rising edge detection HIGH level

1 1 Setting prohibited Setting prohibited

241


14.4 Selecting Count Modes of the 8/16-Bit Up/Down Counter/Timer

Four types of count mode can be selected for the 8/16-bit up/down counter/timer. The CMS1 and CMS0 bits in the counter control register (CCRH) are used to control selection of these count modes.

Selecting Count Modes of the 8/16-Bit Up/Down Counter/Timer

Table 14.4-1 "Selecting Count Modes of the 8/16-Bit Up/Down Counter/Timer" lists the fourcount modes of the 8/16-bit up/down counter/timer.

Timer mode (down count)

In timer mode, the output of the built-in prescaler is counted down. The CLKS bit in the CCRHregister can select 2 or 8 machine cycles for the built-in prescaler.

Up/down count mode

In up/down count mode, up/down counting is performed each time the input of external pin AINor BIN is counted. The AIN pin input controls up counting. The BIN pin input controls downcounting.

The input of the AIN and BIN pins is detected at the edges. The CES1 and CES0 bits in theCCRH register can select the detection edge. Table 14.4-2 "Selecting the Detection Edges ofthe 8/16-Bit Up/Down Counter/Timer" lists the edges that can be used for detection.

Table 14.4-1 Selecting Count Modes of the 8/16-Bit Up/Down Counter/Timer

CMS1, CMS0 Count mode

00B Timer mode (down count)

01B Up/down count mode

10B Phase difference count mode (multiplied by 2)

11B Phase difference count mode (multiplied by 4)

Table 14.4-2 Selecting the Detection Edges of the 8/16-Bit Up/Down Counter/Timer

CES1, CES0 Edge for selection

00B Edge detection prohibited

01B Falling edge detection

10B Rising edge detection

11B Rising and falling edge detection

242

14.4 Selecting Count Modes of the 8/16-Bit Up/Down Counter/Timer

Phase difference count mode (multiplied by 2/ multiplied by 4)

In phase difference count mode, the phase difference between the A and B phases of the outputsignal of the encoder is counted. This is done by detecting and counting the input level of theBIN pin at detection of an input edge of the AIN pin and by detecting and counting the inputlevel of the AIN pin at detection of an input edge of the BIN pin.

In multiplied by 2 or multiplied by 4 mode, the phase difference of the AIN and BIN pin inputs iscounted as follows: Up counting is performed when the AIN pin input occurs earlier than the BINpin input. Down counting is performed when the BIN pin input is earlier than the AIN bin input.

In multiplied by 2 mode, the following counting operations are performed by detecting the AINpin value at the rising and falling edges of the BIN pin signal:

• If the AIN pin value detected at the rising edge of the BIN pin signal is high, up counting isperformed.

• If the AIN pin value detected at the rising edge of the BIN pin signal is low, down counting isperformed.

• If the AIN pin value detected at the falling edge of the BIN pin signal is high, down countingis performed.

• If the AIN pin value detected at the falling edge of the BIN pin signal is low, up counting isperformed.

Figure 14.4-1 "Outline of Operation in Phase Difference Count Mode (Multiplied by 2)" illustratesoperation in phase difference count mode (multiplied by 2).

Figure 14.4-1 Outline of Operation in Phase Difference Count Mode (Multiplied by 2)

In multiplied by 4 mode, the following counting operations are performed by detecting the AINpin value at the rising and falling edges of the BIN pin signal and by detecting the BIN pin valueat the rising and falling edges of the AIN pin signal:

• If the AIN pin value detected at the rising edge of the BIN pin signal is high, up counting isperformed.

• If the AIN pin value detected at the rising edge of the BIN pin signal is low, down counting isperformed.

• If the AIN pin value detected at the falling edge of the BIN pin signal is high, down countingis performed.

• If the AIN pin value detected at the falling edge of the BIN pin signal is low, up counting isperformed.

• If the BIN pin value detected at the rising edge of the AIN pin signal is high, down counting isperformed.

• If the BIN pin value detected at the rising edge of the AIN pin signal is low, up counting isperformed.

• If the BIN pin value detected at the falling edge of the AIN pin signal is high, up counting isperformed.

+1 +1 +1 +1 +1 -1 +1 -1 -1 -1 -10 1 2 3 4 5 4 5 4 3 2 1

AIN pin signal

BIN pin signal

Count value

243


• If the BIN pin value detected at the falling edge of the AIN pin signal is low, down counting isperformed.

Figure 14.4-2 "Outline of Operation in Phase Difference Count Mode (Multiplied by 4)" illustratesoperation in phase difference count mode (multiplied by 4).

Figure 14.4-2 Outline of Operation in Phase Difference Count Mode (Multiplied by 4)

When the encoder output is counted, inputting the A phase to the AIN pin, B phase to the BINpin, and Z phase to the ZIN pin enables the rotation angle and number of rotations to becounted and the rotation direction to be detected with high precision.

Note:

When this count mode is selected, selection of the detection edge using the CES1 andCES0 bits in the counter control register (CCRH) and the CGE1 and CGE0 bits in thecounter control register lower (CCRL) will be disabled.

+1 +1 +1 +1 +1 +1 +1 +1 +1 +1 -1 +1 -1 -1 -1 -1 -1 -1 -1 -10 1 2 3 4 5 6 7 8 9 10 9 10 9 8 7 6 5 4 3 2

-11

AIN pin signal

BIN pin signal

Count value

244

14.5 Reload and Compare Functions of the 8/16-Bit Up/Down Counter/Timer

14.5 Reload and Compare Functions of the 8/16-Bit Up/Down Counter/Timer

The 8/16-bit up/down counter/timer has reload and compare functions. These two types of functions can be combined to execute processing.

Reload and Compare Functions of the 8/16-Bit Up/Down Counter/Timer

Table 14.5-1 "Reload and Compare Functions of the 8/16-Bit Up/Down Counter/Timer" lists theavailable settings when selecting the reload and compare functions of the 8/16-bit up/downcounter/timer.

Reload function

When the reload function is activated, the value of the reload/compare register (RCR) istransferred to the up/down count register (UDCR) at the next down count clock signal afterunderflow occurs. In this case, the UDFF bit in the counter status register (CSR) is set and aninterrupt request generated.

Note:

In modes where down counting is not performed, activation of the reload function is disabled.

Table 14.5-1 Reload and Compare Functions of the 8/16-Bit Up/Down Counter/Timer

RLDE, UCRE Reload and compare functions

00B Compare/reload prohibited [initial value].

01B Compare allowed

10B Reload allowed

11B Compare/reload allowed

245


Figure 14.5-1 "Outline of Operation of the Reload Function" illustrates operation of the reloadfunction.

Figure 14.5-1 Outline of Operation of the Reload Function

Compare function

The compare function can be used in all modes other than timer mode. When the comparefunction is activated, the CMPF bit in the counter status register (CSR) is set and an interruptrequest generated if the values in the RCR and UDCR registers match. In addition, when thecompare clear function is activated, the UDCR register is cleared at the next up count clocksignal.

Note:

In modes where up counting is not performed, activation of the compare function is disabled.

Figure 14.5-2 "Outline of Operation of the Compare Function" illustrates operation of thecompare function.

Figure 14.5-2 Outline of Operation of the Compare Function

(0FFFFH )0FFH

RCR

00H

Reload, interrupt occurrence Reload, interrupt occurrence

Underflow Underflow

(0FFFFH)0FFH

RCR

0000H

Compare match Compare match

Counter clear, interrupt occurrence

Counter clear, interrupt occurrence

246

14.6 Simultaneous Activation of the Reload and Compare Functions of the 8/16-Bit Up/Down Counter/Tim-

14.6 Simultaneous Activation of the Reload and Compare Functions of the 8/16-Bit Up/Down Counter/Timer

At simultaneous activation of the reload and compare functions, up or down counting within an arbitrary width is enabled.

Simultaneous Activation of the Reload and Compare Functions of the 8/16-Bit Up/Down Counter/Timer

When the reload function is activated at an underflow, the reload function transfers the value ofthe reload/compare register (RCR) to the up/down count register (UDCR). In addition, if thevalues in the RCR and UDCR registers match when the compare function is activated, thecompare function clears the UDCR register. The reload and compare functions performs up/down counting operations between 00H and the value of the RCR.

Figure 14.6-1 "Outline of Operation When the Reload and Compare Functions are ActivatedSimultaneously" illustrates operation when the reload and compare functions are activatedsimultaneously.

Figure 14.6-1 Outline of Operation When the Reload and Compare Functions are Activated Simultaneously

CPU interrupts can be generated at compare match or reload (underflow). In addition, enablingthese interrupt outputs can be controlled individually.

The timing when reload or clearing is performed for the UDCR register depends on whethercounting has started or stopped.

FFFFH

RCR

0000H

Compare match Compare match Reload Reload Reload

Counter clear Counter clear

Compare match

Counter clearUnderflow Underflow Underflow

247


Reload/clear timing during counting

When a reload or clear event occurs during counting, all operations are performed insynchronization with the count clock. (Figure 14.6-2 "Reload/Clear Timing during Counting"shows the case where 80h is reloaded.)

Figure 14.6-2 Reload/Clear Timing during Counting

Count value at count disable after reload/clear

If a reload and clear event occurs during counting and counting while waiting for synchronizationwith the count clock (waiting for count input to execute synchronization), reload and clear areexecuted when counting is stopped. (Figure 14.6-3 "Count Value at Count Disable after Reload/Clear" shows the case where 80h is reloaded.)

Figure 14.6-3 Count Value at Count Disable after Reload/Clear

Reload/clear timing when counting has stopped

When a reload and clear event occurs when counting has stopped, reload and clear areexecuted when the event occurs. (Figure 14.6-4 "Reload/Clear Timing When Counting hasStopped" shows the case where 80h is reloaded.)

Figure 14.6-4 Reload/Clear Timing When Counting has Stopped

For clearing due to comparison, clear is executed when the UDCR and RCR register valuesmatch and up counting is performed. Even if the UDCR and RCR register values match, clearis not executed if down counting is subsequently performed or counting has stopped. The clear/reload timings are as explained above. For clearing, the timing applies to all events other thanreset input. For reload, the timing applies to all events.

If the clear and reload events occur at the same time, the clear event has priority.

UDCR 065h 066h 080h 081h

Reload/clear event Synchronized to this clock

Count clock

UDCR 065h 066h 080h

Reload/clear event

Count clock

Count enableEnable (count allowed) Disable (count prohibited)

UDCR 065h 080h

Reload/clear event

248

14.7 Writing Data to the UDCR Register of the 8/16-Bit Up/Down Counter/Timer


Data cannot be directly written from the data bus to the up/down count register (UDCR). Use the following procedure to write arbitrary data to the UDCR register:1. Write the data to be written to the UDCR register to the reload/compare register

(RCR) first. (Note that the current RCR register data will be lost.)2. Set the CTUT bit in the counter control register lower (CCRL) to 1 to transfer the

data from the RCR register to the UDCR register.Perform the above procedure when the CSTR bit in the counter status register (CST) is 0 when counting has stopped.

Writing Data to the UDCR Register

For clearing the counter, the following methods are available in addition to the above procedure:

• Clearing using reset input (initialization)

• Clearing using edge input from the ZIN pin

• Clearing by setting the UDCC bit of the CCRL register to 0

• Clearing using the compare function

These write operations can be executed regardless of whether counting is being started orstopped.

Count Clear/Gate Functions

As listed in Table 14.7-1 "Selecting ZIN Pin Functions", the CGSC bit in the CCRL register canbe used to select whether to use the ZIN pin for a count clear function or gate function.

While the count clear function is activated, the edge input from the ZIN pin is used to clear thecounter. Which edge of the ZIN pin input signal is used to clear the counter can be selectedusing the CGE1 and CGE0 bits in the counter control register higher (CCRH). Using thisfunction to input the Z phase output of the encoder to the ZIN pin enables the UDCR register tobe cleared when counting of the encoder starts.

While the gate function is activated, the level input from the ZIN pin is used to enable or disablecounting. Which level of the ZIN pin input signal is used to enable counting can be selectedusing the CGE1 and CGE0 bits in the CCRH register.

This function can be used in all count modes.

Table 14.7-1 Selecting ZIN Pin Functions

CGSC ZIN pin function

0B Counter clear function

1B Gate function

249


Table 14.7-2 "Selecting the Detection Edge Using the ZIN Pin Input Signal" lists the detectionedge selections using the ZIN pin input signal.

Count Direction Flag and Count Direction Change Flag

At up/down counting, the count direction flag (UDF1 and UDF0 bits in the counter status register(CSR)) indicates whether the immediately preceding count was an up count or down count. Thecount clock generated from the inputs of the AIN and BIN pins is used to determine whether torewrite the flag at each count.

For example, for motor control, this flag can be read to determine the current rotation direction.

This function can be used in all count modes.

Table 14.7-3 "Count Direction Flag" lists the count direction flag.

The count direction change flag (CDCF bit in the counter control register higher (CCRH)) is setwhen the count direction changes from up to down or from down to up. When this flag is set, aninterrupt for the CPU is generated. This interrupt and the count direction flag (UDF1 and UDF0bits in the CER register) can be used to find out how the count direction has changed.However, note that if the interval of the direction change is short, i.e., changes occurcontinuously, the direction indicated by the flag can already have returned to the originaldirection.

Table 14.7-4 "Count Direction Change Flag" lists the meaning of the count direction changeflag.

Table 14.7-2 Selecting the Detection Edge Using the ZIN Pin Input Signal

CGE1, CGE0 Counter clear function Gate function

00B Detection prohibited Detection prohibited

01B Rising edge LOW level

10B Falling edge HIGH level

Table 14.7-3 Count Direction Flag

UDF1, UDF0 Count direction

00B Down count

01B Up count

10B Up/down occurring simultaneously (The counting operation is not performed.)

Table 14.7-4 Count Direction Change Flag

CDCF Count direction change detection

0B No direction change

1B Direction change (at least once)

250


Compare Detection Flag

The compare detection flag (CMPF bit in the counter status register (CSR)) is set when the up/down count register (UDCR) value and reload/compare register (RCR) value become equalduring counting. In addition to a match occurring during up counting, the compare detection flagis also set when the register values match due to the occurrence of a reload event or if thevalues already matched when counting started.

Matching is not detected, however, if the match of register values occurred during downcounting (except for compare at reload using underflow). In this case, the flag is not set.

8-Bit x 2-Channel Operation and 16-Bit x 1-Channel Operation

This module can be used as an 8-bit up/down counter x two channels or as a 16-bit up/downcounter x one channel. Setting the M16E bit in the counter control register 0 higher (CCRH0) to0 sets 8-bit x 2-channel mode. Writing 1 sets 16-bit x 1-channel mode.

The CSR0, CCRL0, and CCRH0 registers can be used when operating in 16-bit x 1-channelmode. The CSR1, CCRL1, and CCRH1 registers cannot be used in this mode. In addition, theAIN0, BIN0, and ZIN0 pins can be used as input pins in this mode, while the AIN1, BIN1, andZIN1 pins cannot be used.

251


252

CHAPTER 15 DTP/EXTERNAL INTERRUPT UNIT

This chapter explains the functions and operation of the DTP/external interrupt unit.

15.1 "Outline of DTP/External Interrupt Unit"

15.2 "DTP/External Interrupt Registers"

15.3 "Operation of DTP/External Interrupt Unit"

15.4 "Precautions on Using DTP/External Interrupt Units"

253


15.1 Outline of DTP/External Interrupt Unit

The DTP (Data Transfer Peripheral)/external interrupt unit is a peripheral unit for

activating the extended intelligent I/O service (EI 2OS) or external interrupt processing.

DTP/External Interrupt Functions

The DTP/external interrupt circuit is located between an external peripheral *1 outside of the

device and the F2MC-16L CPU. This peripheral circuit receives DMA or interrupt requests

generated by the peripheral unit, passes the interrupts to the F2MC-16L CPU, and then starts

the extended intelligent I/O service (EI2OS) or interrupt processing. Two types of request level

can be selected for the extended intelligent I/O service (EI2OS): High and low. Four types ofrequest level can be selected for external interrupt requests: High, low, rising edge, and fallingedge.

*1: The term external peripheral means a device with peripheral function that is connected externally to an MB90650A series device.

Block Diagram of DTP/External Interrupt Unit

Figure 15.1-1 Block Diagram of DTP/External Interrupt Unit

4

4

4

4

4

Inte

rnal

dat

a bu

s

DTP/interrupt enable register

Gate Source FF Edge detection circuit Request input

DTP/interrupt cause register

Request level setting register

254

15.2 DTP/External Interrupt Registers


This device has the following three types of DTP/external interrupt registers:• DTP/interrupt enable register (ENIR)• DTP/interrupt cause register (EIRR)• Request level setting register (ELVR)

DTP/External Interrupt Registers

Figure 15.2-1 DTP/External Interrupt Registers

7 6 5 4 3 2 1 0 Bit No.

Address:000030H EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 ENIR


15 14 13 12 11 10 9 8 Bit No.

Address:000031H ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 EIRR


15 14 13 12 11 10 9 8 Bit No.

Address:000033H LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)(0) (0) (0) (0) (0) (0) (0) (0)7 6 5 4 3 2 1 0 Bit No.

Address:000032H LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0 ELVR









255


15.2.1 DTP/Interrupt Enable Register (ENIR)

The DTP/interrupt enable register (ENIR) uses device pins as DTP/external interrupt request input and determines whether to operate the function that generates requests for the interrupt controller.

DTP/Interrupt Enable Register (ENIR)

Figure 15.2-2 DTP/Interrupt Enable Register (ENIR)

The pins corresponding to the bits in this register that have been set to 1 are used for DTP/external interrupt request input. The function that generates requests for the interrupt controlleris active. The pins corresponding to the bits that have been set to 0 retain the DTP/externalinterrupt request input source. However, from these pins, no request for the interrupt controlleris generated.

7 6 5 4 3 2 1 0 Bit No.

Address:000030H EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 ENIR




256


15.2.2 DTP/Interrupt Cause Register (EIRR)

At reading, the DTP/interrupt cause register (EIRR) indicates whether a corresponding DTP/external interrupt request exists. At writing, this register clears the contents of the flip-flop that indicates the request.

DTP/Interrupt Cause Register (EIRR)

Figure 15.2-3 DTP/Interrupt Cause Register (EIRR)

A read value of 1 for a bit in this register indicates that there is a DTP/external interrupt requestfor the pin corresponding to the bit.

Writing 0 to a bit of this register clears the request flip-flop of the corresponding bit. Writing 1has no effect. In read-modify-write read operations, 1 is returned for the corresponding bit.

15 14 13 12 11 10 9 8 Bit No.

Address:000031H ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 EIRR




257


15.2.3 Request Level Setting Register (ELVR)

The request level setting register (ELVR) is used to select the type of request detected.

Request Level Setting Register (ELVR)

Figure 15.2-4 Request Level Setting Register (ELVR)

Two bits are assigned per pin. Table 15.2-1 "Request Level Setting Register (ELVR) Operation"lists the correspondence between the bits and pins. When a level has been selected for therequest input, the bit will be set again as long as the input is active even if the bit is cleared inbetween.

15 14 13 12 11 10 9 8 Bit No.

Address:000033H LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)(0) (0) (0) (0) (0) (0) (0) (0)7 6 5 4 3 2 1 0 Bit No.

Address:000032H LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0 ELVR





Table 15.2-1 Request Level Setting Register (ELVR) Operation

LBx LAx Operation

0 0 Low level request

0 1 High level request

1 0 Request at rising edge

1 1 Request at falling edge

258

15.3 Operation of DTP/External Interrupt Unit


The DTP/external interrupt unit provides external interrupt and DTP functions. This section describes the operation of these functions.

Operation of DTP/External Interrupt Unit

After an external interrupt request has been specified, this resource generates an interruptrequest signal for the interrupt controller. The resource generates the interrupt request signalwhen the request setting of the request level setting register (ELVR) is input for thecorresponding pin. For simultaneous interrupt requests, the interrupt controller determines the

interrupt request with the highest priority and generates an interrupt request for the F2MC-16LCPU.

The F2MC-16L CPU compares the interrupt request with the interrupt level mask register (ILM)in the processor status register (PS). If the request level is higher than that in the ILM register,the hardware interrupt processing microprogram is activated when processing of the instructioncurrently being executed is completed.

Figure 15.3-1 External Interrupt Operation

The CPU reads the information of the ISE bit in the interrupt control register (ICR), uses thisinformation to determine whether the relevant request involves interrupt processing, and thenbranches to the hardware interrupt processing microprogram. The interrupt processingmicroprogram reads the interrupt vector area, generates an interrupt acknowledge for theinterrupt controller, and transfers to the program counter the jump destination address of themacroinstruction generated from the vector. The microprogram then executes the user’sinterrupt processing program.

DTP Operation

To activate the intelligent I/O service, the user program initially specifies the address of theregister allocated between 000000H to 0000FFH in the I/O address pointer of the intelligent I/Oservice descriptor. It specifies the leading address of the memory buffer in the buffer addresspointer.

The DTP operation sequence is nearly identical to that for an external interrupt. The sequenceis exactly the same up to when the CPU activates the hardware interrupt processingmicroprogram. For a DTP, the ISE bit in the interrupt control register (ICR) that the CPU readsaccording to the hardware interrupt processing microprogram indicates DTP. Control is

therefore passed to the intelligent I/O service (EI2OS). When the intelligent I/O service (EI2OS)is activated, a read or write signal is sent to the addressed external peripheral and transfer

ELVR

EIRR

ENIR

F2MC-16L CPU

ICRyy IL

CMP CMP

ICRxx ILM

INTA

DTP/external interrupt unit Interrupt controller

Other request

Source

259


using this chip is executed. Have the external peripheral cancel the interrupt request for thischip within three machine cycles after transfer has been executed. The descriptor is updatedwhen transfer ends. The interrupt controller then generates a signal to clear the transfer source.Upon receiving the signal to clear the transfer source, this resource clears the flip-flop thatretains the source information and prepares to receive the next request from the pin.

Figure 15.3-2 Timing for Canceling an External Interrupt When DTP Operation Ends

Figure 15.3-3 Simple Example of an External Peripheral Interface

Interrupt cause

Internal operationSelect and readdescriptor

Edge request or high-level request

When the intelligent I/O service transfersfrom the I/O register to memory

Address bus pin Read address Write address

Data bus pin Read data Write data

Read signal

Write signal

Cancel within 3 machine cycles.

INTIRQ

DTP CORE MEMORY

MB90650A

Ext

erna

l per

iphe

ral

Reg

iste

r

Data, address, bus Internal data bus

Cancel within 3 machine cycles after transfer ends.

260


Switching Between External Interrupt Requests and DTP Requests

External interrupt requests and DTP requests are switched based on the setting of the ISE bit inthe interrupt control register (ICR) corresponding to this resource in the interrupt controller.

ICRs are assigned individually to each pin. As a result, a pin for which the the ISE bit of thecorresponding ICR register has been set to 1 operates as DTP request input. In addition, a pinwhose corresponding bit has been set to 0 operates as an external interrupt request.

Figure 15.3-4 Switching Between External Interrupt Requests and DTP Requests

ICRxx 0

ICRyy 1

F2MC-16L CPU

DTP

Pin DTP/external

interrupt unit


External interrupt

261


15.4 Precautions on Using DTP/External Interrupt Units

Note the four points below regarding use of DTP/external interrupt units:• Conditions of peripherals connected externally when a DTP is used• Return from standby status• Operation procedure for DTP/external interrupt units• External interrupt request levels

Conditions of Peripherals Connected Externally When a DTP is Used

To support a DTP, external peripherals must be able to automatically clear requests whentransfer is executed. In addition, if the transfer request is not cancelled within three machinecycles (tentative value) after the transfer operation starts, this resource handles this as if thenext transfer request has been generated.

Return From Standby Status

If an external interrupt is used to return from standby status in clock stop mode, use the inputrequest as a high-level request. A low-level request can cause incorrect operation. For anedge request, return from standby status in clock stop mode is not performed.

Operation Procedure for DTP/External Interrupt Units

Use the following procedure to set the registers in the DTP/external interrupt unit:

1. Disable the corresponding bit of the DTP/external interrupt enable register (ENIR)..

2. Set the corresponding bit of the request level setting register (ELVR).

3. Clear the corresponding bit of the DTP/external interrupt cause register (EIRR).

Enable the corresponding bit of the DTP/external interrupt allowed register.

(For steps 3) and 4), simultaneous writing using word specification is allowed.)

Always disable the ENIR register before making the register settings in this resource. Inaddition, always clear the ENIR register before enabling the ENIR register. This is done toprevent an interrupt cause from being activated by mistake when register settings are made orwhen interrupts become allowed.

External Interrupt Request Levels

• When the request level is an edge request, the pulse width must be at least three machinecycles so that input of the edge can be detected.

• When the request input level is detected as a level, the request to the interrupt controllerremains active even if the request input is entered externally and then cancelled. Therequest remains active because of the internal source retention circuit shown in Figure 15.4-1 "Clearing the Source Retention Circuit When Making Level Settings". To cancel therequest to the interrupt controller, clear the external interrupt request flag bit and then clearthe source retention circuit as shown in Figure 15.4-2 "Interrupt Cause and Interrupt Requestto the Interrupt Controller When Interrupts are Allowed".

262

15.4 Precautions on Using DTP/External Interrupt Units

Figure 15.4-1 Clearing the Source Retention Circuit When Making Level Settings

Figure 15.4-2 Interrupt Cause and Interrupt Request to the Interrupt Controller When Interrupts are Allowed

Note:

Edge detection cannot be used to return from clock mode.

Interrupt cause Level detection Source FF(source retention circuit)

The source is retained until cleared.

Enable gate To interrupt controller

Interrupt causeHigh level

Interrupt request tointerrupt controller Becomes inactive due to clearing of the source FF.

263


264

CHAPTER 16 DELAYED INTERRUPT GENERATION MODULE

This chapter explains the functions and operation of the delayed interrupt generation module.

16.1 "Outline of the Delayed Interrupt Generation Module"

16.2 "Operation of the Delayed Interrupt Generation Module"

265


16.1 Outline of the Delayed Interrupt Generation Module

The delayed interrupt generation module generates interrupts for switching tasks. When this module is used, the software can generate and cancel interrupt requests for

the F2C-16L CPU.

Block Diagram of the Delayed Interrupt Generation Module

Figure 16.1-1 "Block Diagram of the Delayed Interrupt Generation Module" shows a blockdiagram of the delayed interrupt generation module.

Figure 16.1-1 Block Diagram of the Delayed Interrupt Generation Module

Registers of the Delayed Interrupt Generation Module

Figure 16.1-2 "Delayed Interrupt Cause Generation/Cancellation Register (DIRR)" shows theregister configuration of the delayed interrupt generation module (delayed interrupt causegeneration/cancellation register (DIRR: Delayed interrupt request register)).

The delayed interrupt cause generation/cancellation register (DIRR) controls generation andcancellation of delayed interrupt requests. Writing 1 to this register generates a delayedinterrupt request. Writing 0 to this register cancels the delayed interrupt request.

At a reset, source cancelled status is set.

Either 0 or 1 can be written to the unused bit area. Taking future extension into consideration,however, we recommend using the set bit and clear bit instructions when accessing thisregister.

Figure 16.1-2 Delayed Interrupt Cause Generation/Cancellation Register (DIRR)

Inte

rnal

dat

a bu

s

Delayed interrupt cause generation/cancellation decoder

Source latch

15 14 13 12 11 10 9 8 Bit No.

Address:00009FH R0 DIRR

(-) (-) (-) (-) (-) (-) (-) (R/W)(-) (-) (-) (-) (-) (-) (-) (0)

Delayed interrupt cause generation/cancellation register


266

16.2 Operation of the Delayed Interrupt Generation Module

16.2 Operation of the Delayed Interrupt Generation Module

When the CPU sets the relevant bit of the DIRR register to 1 via software, the request latch in the delayed interrupt generation module is set and an interrupt request is generated for the interrupt controller.If another interrupt request has a lower priority than this interrupt or if there is no other interrupt request, the interrupt controller generates an interrupt request for the

F2MC-16L CPU.

Operation of the Delayed Interrupt Generation Module

The F2MC-16L CPU compares the interrupt request with the interrupt level mask register (ILM)in the processor status register (PS). If the request level (IL) is higher than that in the ILMregister, the hardware interrupt processing microprogram is activated when the instructioncurrently being executed ends, and the interrupt processing routine for this interrupt is executed.

Setting the relevant bit of the DIRR register to 0 via the interrupt processing routine clears thisinterrupt cause and switches the task.

Figure 16.2-1 "Operation of the Delayed Interrupt Generation Module" shows the operation ofthe delayed interrupt generation module.

Figure 16.2-1 Operation of the Delayed Interrupt Generation Module

Precautions on Using the Delayed Interrupt Generation Module

Delayed interrupt request latch

Setting the relevant bit in the DIRR register to 1 sets the delayed interrupt request latch. Settingthis bit to 0 clears the latch. Therefore, a software portion for clearing the interrupt cause mustbe created in the interrupt processing routine. Otherwise, interrupt processing may restart againafter returning from interrupt processing.

MB90650A series CPU

ICRyy IL

CMP CMP

DIRR ICRxx ILM

NTA

WRITE

Delayed interrupt generation module Interrupt controller

Other request

267


268

CHAPTER 17 A/D CONVERTER

This chapter explains the functions and operation of the A/D converter.

17.1 "Outline of the A/D Converter"

17.2 "A/D Converter Registers"

17.3 "A/D Converter Operation"

17.4 "Notes on Using the A/D Converter"

17.5 "Conversion Data Protection Function"

269


17.1 Outline of the A/D Converter

The A/D converter converts analog input voltage to a digital value.

Outline of the A/D Converter

The A/D converter has the following features:

Conversion time: Minimum of 6.13 µµµµs per channel

(98 machine cycles, machine clock frequency 16 MHz, sampling time included)

Sampling time: Minimum of 3.75 µµµµs per channel

(60 machine cycles and machine clock frequency of 16 MHz)

Use of RC type successive approximation conversion method with a Sample and Hold circuit

10-bit resolution

Program-based selection of analog input from eight channels

• Single conversion mode: Selection and conversion for one channel

• Scan conversion mode: Continuous conversion for multiple channels. Up to eight channelscan be programmed.

• Continuous conversion mode: Specified channels can be repeatedly converted.

• Stop conversion mode: Temporary stop when one channel is converted and the device isentering standby mode until the next activation. (The start of conversion can besynchronized.)

At the end of A/D conversion, an A/D conversion end interrupt request can be generated for the CPU. This interrupt can activate the I 2OS and cause a transfer of the A/D conversion result data to memory. Therefore, this interrupt is suitable for continuous processing.

The software, external trigger (falling edge), or timer (rising edge) can be selected as the activation source.

270

17.1 Outline of the A/D Converter

Block Diagram of the A/D Converter

Figure 17.1-1 Block Diagram of the A/D Converter

AVCCAVRH,L

AVSS

MPX

AN0AN1AN2AN3AN4AN5AN6AN7

ADCR1,2

ADCS1,2

D/A converter

Inpu

t circ

uit

Sample and Hold circuit

Comparator

Successiveapproximation register

Dec

oder

Data register

Inte

rnal

dat

a bu

s

A/D control register 1

A/D control register 2

ADTG pinActivate trigger

Timer(PPG1 output)

Activate timerOperating clock

Prescaler

271


17.2 A/D Converter Registers

Figure 17.2-1 "A/D Converter Registers" shows the A/D converter registers.

A/D Converter Registers

Figure 17.2-1 A/D Converter Registers

15 14 13 12 11 10 9 8 Bit No.

Address: ch1 000037H BUSY INT

D9 D8

D6D7 D5 D4 D3 D2 D1 D0

INTE PAUS STS1 STS0 STRT DA ADCS2

7 6 5 4 3 2 1 0 Bit No.

Address: ch0,1 0036H MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0 ADCS1

15 14 13 12 11 10 9 8 Bit No.

Address: ch1 000039H ADCR2

7 6 5 4 3 2 1 0 Bit No.

Address: ch0 000038H ADCR1

Control status register higher

Control status register lower

Data register higher

Data register lower







(R)(-)

(R)(-)

(R)(-)

(R)(-)

(R)(-)

(R)(-)

(R)(-)

(R)(-)

(R)(-)

(R)(-)

(R)(-)

(R)(-)

(R)(-)

(R)(-)

(R)(-)

(R)(-)

15 8 7 0

ADCS2

ADCR2

8bit

ADCS1

ADCR1

8bit

272


17.2.1 Control Status Registers (ADCS1 and ADCS2)

The control status registers (ADCS1 and ADCS2) are used to control the A/D converter and display the status.

Control Status Registers (ADCS1 and ADCS2)

Figure 17.2-2 Control Status Registers (ADCS1 and ADCS2)

Note:

Do not rewrite the ADCS1 during A/D conversion.

[Bit 15] BUSY (Busy flag and stop)

The BUSY bit is used to indicate A/D converter operation. This bit is set when A/Dconversion is started and cleared when A/D conversion stops.

At reading

A value of 0 for this bit indicates that A/D conversion has stopped. When this bit is 1, A/Dconversion is in progress.

At writing

Setting this bit to 0 by a write during A/D conversion forcibly stops operation. This techniquecan be used to forcibly stop operation in continuous mode and stop mode.

Bit 15 cannot be set to 1.

Reading with RMW instructions always returns 1. In single mode, this bit is cleared at theend of A/D conversion. In continuous mode and stop mode, this bit is not cleared until 0 iswritten to stop A/D conversion.

Note:

Do not perform forced stop and software activation (BUSY = 0 and STRT = 1) at the sametime.

15 14 13 12 11 10 9 8 Bit No.

Address : ch1 000037H BUSY INT INTE PAUS STS1 STS0 STRT DA ADCS2

7 6 5 4 3 2 1 0 Bit No.

Address : ch0,1 0036H MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0 ADCS1

Control status register higher

Control status register lower

Read/write

Read/write

Initial value

Initial value

(R/W)(0)

(R/W)(0)

(R/W)(0)

(R/W)(0)

(R/W)(0)

(R/W)(0)

(R/W)(0)

(R/W)(0)

(R/W)(0)

(R/W)(0)

(R/W)(0)

(R/W)(0)

(R/W)(0)

(R/W)(0)

(R/W)(0)

(R/W)(0)

273


[Bit 14] INT (Interrupt)

When conversion data is written to the data register (ADCR), the INT bit is set to 1.

If the INTE bit is 1, setting the INT bit to 1 generates an interrupt request. In addition, if I2OS

activation has been enabled, the I2OS is activated. Writing 1 has no effect.

Writing 0 clears the INT bit via the clear signal of the I2OS.

Note:

Stop the A/D converter before writing 0 to clear the INT bit.

[Bit 13] INTE (INTerrupt Enable)

The INTE bit is used to prohibit or allow interrupts when conversion terminates.

If the I2OS is being used, set the INTE bit to 1. Generation of an interrupt request activates

the I2OS.

[Bit 12] PAUS (a/d converter PAUSe)

When A/D conversion is stopped temporarily, the PAUS bit is set to 1.

Only one register is available for storing the result of A/D conversion. Therefore, atcontinuous conversion, the previous data will be lost unless the conversion result is

transferred in advance by the I2OS.

To protect the data, A/D conversion is stopped without the next conversion data being stored

if the data register contents are not transferred by the I2OS. When transfer by the I2OS iscompleted, A/D conversion is restarted.

Note:

The PAUS bit is valid only when the I2OS is being used. See Section 17.5 "Conversion DataProtection Function."

[Bits 11 and 10] STS1 and STS0 (Start Source select)

The STS1 and STS0 bits are used to select the A/D activation source.

Table 17.2-1 INTE (Interrupt Allowed/Prohibited Specification Bit) Functions

INTE Function

0 Interrupt prohibited [initial value].

1 Interrupt allowed

274


For modes where two activation sources are involved, the A/D unit is started from the sourcethat arrives first. The activation source changes as soon as the bits are rewritten.Therefore, to rewrite the bits during A/D operation, switch when the conversion activationsource to be used has not been set.

For the external pin trigger, the falling edge is detected.

If the external trigger input level is low, setting these bits to external pin trigger activation cancause A/D conversion to start.

When a timer is selected, the output of 16-bit reload timer 1 is selected.

[Bit 9] STRT (StaRT)

Setting the STRT bit to 1 starts A/D the unit. To restart the A/D unit, set the STRT bit againto 1.

In stop mode, the A/D unit cannot be restarted with the operation functions.

Note:

Do not execute forced stop and software activation (BUSY = 0 and STRT = 1) at the sametime.


Bit 8 is a reserved bit. Always set this bit to 0.

[Bits 7 and 6] MD1 and MD0 (a/d converter MoDe set)

The MD1 and MD0 bits are used to set the operation mode.

Table 17.2-2 STS1 and STS0 (A/D Activation Source Selection Bits) Functions

STS1 STS0 Function

0 0 Software activation [initial value].

0 1 External pin trigger activation and software activation

1 0 Timer activation and software activation

1 1 External pin trigger activation, timer activation, and software activation

Table 17.2-3 MD1 and MD0 Operation Modes

MD1 MD0 Operation mode

0 0 Single mode. All restarts during operation are allowed [initial value]..

0 1 Single mode. Restart during operation is not allowed.

1 0 Continuous mode. Restart during operation is not allowed.

1 1 Stop mode. Restart during operation is not allowed.

275


Single mode

A/D conversion is executed from the channels set by the ANS2 to ANS0 bits up to thechannels set by the ANE2 to ANE0 bits. Conversion stops when one conversion operation iscomplete.

Continuous mode

A/D conversion is performed repeatedly from the channels set by the ANS2 to ANS0 bits upto the channels set by the ANE2 to ANE0 bits.

Stop mode

A/D conversion is executed and stopped temporarily for each channel from the channels setby the ANS2 to ANS0 bits up to the channels set by the ANE2 to ANE0 bits. Generation ofan activation source restarts a conversion operation that has been stopped temporarily.

Note:

• When A/D conversion is started in continuous or stop mode, conversion continues until it isstopped by the BUSY bit.

• Setting the BUSY bit to 0 stops conversion.

• Restart not allowed in single, continuous, and stop modes applies to all activation operationsusing a timer, external trigger, and software.

[Bits 5, 4, and 3] ANS2, ANS1, and ANS0 (ANalog Start channel set)

The ANS2, ANS1, and ANS0 bits are used to specify the channel where A/D conversion is tobe started.

When the A/D converter is activated, A/D conversion is started from the channel selectedusing these bits. The converted channel can be read during A/D conversion. In stop mode,the channel used for conversion before stopping can be read.

Table 17.2-4 ANS2, ANS1, and ANS0 Bit Start Channels

ANS2 ANS1 ANS0 Start channel

0 0 0 AN0 [initial value].

0 0 1 AN1

0 1 0 AN2

0 1 1 AN3

1 0 0 AN4

1 0 1 AN5

1 1 0 AN6

1 1 1 AN7

276


[Bits 2, 1, and 0] ANE2, ANE1, and ANE0 (ANalog End channel set)

The ANE2, ANE1, and ANE0 bits are used to specify the end channel of A/D conversion.

If the same channel as that set using the ANS2 to ANS0 bits is specified, one-channelconversion is performed (single conversion).

If continuous or stop mode has been set, the start channel specified using the ANS2 toANS0 bits is restored when conversion of the channel set using the ANE2, ANE1, and ANE0bits completes.

If ANS is less than ANE for the set channels, conversion starts from ANS. When conversionof up to channel 7 is completed, conversion returns to channel 0 and continues up to ANE.

Example: Channel setting ANS = channel 6 and ANE = channel 3 in single mode

Operation: Channel 6 --> channel 7 --> channel 0 --> channel 1 --> channel 2 --> channel 3

Table 17.2-5 ANE2, ANE1, and ANE0 Bit End Channels

ANE2 ANE1 ANE0 End channel

0 0 0 AN0 [initial value].

0 0 1 AN1

0 1 0 AN2

0 1 1 AN3

1 0 0 AN4

1 0 1 AN5

1 1 0 AN6

1 1 1 AN7

277


17.2.2 Data Registers (ADCR1 and ADCR2)

The data registers (ADCR1 and ADCR2) are used to store the result of A/D conversion. The registers specify the selected A/D conversion resolution and the machine cycle.

Data Registers (ADCR1 and ADCR2)

Figure 17.2-3 Data Registers (ADCR1 and ADCR2)

[Bits 9 and 8] D9 and D8

When 10-bit resolution has been selected, the two high-order bits of the digital valueexpressing the conversion result are stored in these bits.

[Bits 7 to 0] D7 to D0

These bits comprise the A/D conversion storage register. The digital value expressing theconversion result is stored in these bits.

The value in this register is updated each time conversion is completed. The finalconversion value is always stored. See Section 17.5 "Conversion Data Protection Function."

At a reset, this register is undefined.

Note:

Do not write data to this register during A/D operation.

D9 D8

D6D7 D5 D4 D3 D2 D1 D0

15 14 13 12 11 10 9 8 Bit No.

Address : ch1 000039H ADCR2

7 6 5 4 3 2 1 0 Bit No.

Address : ch0 000038H ADCR1

Data register higher

Data register lower



(R) (-)(R) (R) (R) (R) (R) (R)(-) (-) (-) (-) (-) (-) (-) (-)

(R) (R) (R) (R) (R) (R) (R)(-) (-) (-) (-) (-) (-) (-) (-)

(R)

278

17.3 A/D Converter Operation


The A/D converter has three types of operation mode, as follows:• Single mode• Continuous mode• Stop mode

Single Mode

In single mode, the analog inputs set using the ANS and ANE bits are converted in sequence.Then, when conversion completes at the end channel set using the ANE bit, the A/D converterstops operating.

If the start and end channels are the same (ANS = ANE), conversion is performed only for thechannel set using ANS.

Example:

ANS = 000, ANE = 011

Start --> AN0 --> AN1 --> AN2 --> AN3 --> End

ANS = 010, ANE = 010

Start --> AN2 --> End

Continuous Mode

In continuous mode, the analog inputs set using the ANS and ANE bits are converted insequence. Then, when conversion completes at the end channel set using the ANE bit,processing returns to analog input of ANS, and A/D conversion continues.


Example:

ANS = 000, ANE = 011

Start --> AN0 --> AN1 --> AN2 --> AN3 --> AN0 --> Repeat

ANS = 010, ANE = 010

Start --> AN2 --> AN2 --> AN2 --> Repeat

For conversion in continuous mode, conversion is continued repeatedly until the BUSY bit in thecontrol status register (ADCS) is set to 0. (Setting the BUSY bit to 0 forcibly stops operation.)

When operation is forcibly stopped, conversion of the item being converted will be stopped.(When operation is forcibly stopped, data for which conversion has not been completed yet willbe stored in the data register (ADCR).

279


Stop Mode

In stop mode, the analog inputs set using the ANS and ANE bits are converted in sequence.However, conversion is stopped temporarily each time one channel is converted. Restartingreleases temporary stop.

When conversion terminates at the end channel set using the ANE bit, processing returns toanalog input of ANS, and A/D conversion continues.


Example:

ANS = 000, ANE = 011

Start --> AN0 --> Stop --> Activate --> AN1 --> Stop --> Activate --> AN2 --> Stop --> Activate--> AN3 --> Stop --> Activate --> AN0 --> Repeat

ANS = 010, ANE = 010

Start --> AN2 --> Stop --> Activate --> AN2 --> Stop --> Activate --> AN2 --> Repeat

In this example, only the sources set using the STS1 and STS0 bits in the ADCS register areused as activation sources.

Using stop mode enables start of conversion to be synchronized.

280


17.3.1 Conversion Using I 2OS

The A/D converter can use the intelligent I/O service (I 2OS) to transfer A/D conversion results to memory.

Conversion Using the I 2OS

When the I2OS is being used, the conversion data protection function ensures that multiple dataitems will be accurately transferred to memory without any data loss even at continuousconversion.

Figure 17.3-1 Example of Operation Flow from Activation of A/D Conversion to Transfer of Conversion Data (Continuous Mode)

Activate A/D conversion

Sample & Hold

Convert

Activate I2OS

Transfer data

Interrupt processingTerminate conversion

Generate interrupt Clear interrupt

: Depends on the I2OS setting.

281


17.3.2 Example of Activation of I 2OS in Single Mode

The following procedure is used to activate the I 2OS in single mode:• The analog inputs (AN1 to AN3) are converted and conversion stops.• The conversion data is stored in sequence at the addresses 200 H to 206H.

• The software activates the I 2OS.• Highest interrupt level

Example of I 2OS Activation in Single Mode

Table 17.3-1 Example of I 2OS Activation in Single Mode

Setting item Program example Explanation of operation

I2OS setting MOV ICR3, #08H Sets the strongest interrupt, activates I2OS at an interrupt, and sets the descriptor address.

MOV BAPL, #00H Transfer destination address for the conversion data

MOV BAPM, #02H -

MOV BAPH, # 00H -

MOV ISCS, #08H Transfers the word data and increments the transfer destination address after transfer. Transfers the data from the I/O area to memory. Terminates upon a request from the resource.

MOV IOA, #38H -

MOV DCT, #03H Executes three I2OS transfer operations. Sets the same transfer count.

A/D converter setting MOV ADCS1, #0BH Single mode, start channel AN1, and end channel AN3

MOV ADCS2, #A2H Activates the A/D converter using the software and starts A/D conversion.

I2OS termination interrupt sequence

RET Returns from the interrupt.

ICR3: Interrupt control registerBAPL: Buffer address pointer lowerBAPM: Buffer address pointer middleBAPH: Buffer address pointer higherISCS: I2OS status registerIOA: I/O address registerDCT: Data counter

282


Figure 17.3-2 Example of I 2OS Activation in Single Mode

AN1

AN2

AN3

Begin of start operation Interrupt

Interrupt

Interrupt

Termination Interrupt sequence

Parallel processing

I2OS transfer

I2OS transfer

I2OS transfer

283


17.3.3 Example of I 2OS Activation in Continuous Mode

The following procedure is used to activate the I 2OS in continuous mode:• The analog inputs (AN3 to AN5) are converted and two conversion data items for

each channel obtained.• The conversion data is stored in sequence at the addresses 600 H to 60CH.

• External edge input activates the I 2OS.• Highest interrupt level

Example of I 2OS Activation in Continuous Mode

Table 17.3-2 Example of I 2OS Activation in Continuous Mode




MOV BAPM, #06H

MOV BAPH, # 00H


MOV IOA, #38H Transfer source address

MOV DCT, #06H Executes six I2OS transfer operations. Transfers the data of three channels x 2.

A/D converter setting MOV ADCS1, #9DH Single mode, start channel AN3, and end channel AN5

MOV ADCS2, #A4H Activates the A/D converter using an external edge and starts A/D conversion.


MOV ADCS2, #00H -



284


Figure 17.3-3 Example of I 2OS Activation in Continuous Mode

AN3

AN4

AN5

Begin of start operation Interrupt

After all 6 transfer operations

Interrupt sequence

Termination

I2OS transfer

Interrupt I2OS transfer

Interrupt I2OS transfer

285


17.3.4 Example of I 2OS Activation in Stop Mode

The following procedure is used to activate the I 2OS in stop mode:• The analog input (AN3) is converted 12 times at specific intervals.• The conversion data is stored in sequence at the addresses 600 H to 618H.

• External edge input activates the I 2OS.• Highest interrupt level

Activation Example of I 2OS in Stop Mode

Table 17.3-3 Example of I 2OS Activation in Stop Mode




MOV BAPM, #06H

MOV BAPH, # 00H


MOV IOA, #38H Transfer source address

MOV DCT, #0CH Executes 12 I2OS transfer operations. Transfers the data of three channels x 2.

A/D converter setting MOV ADCS1, #DBH Continuous mode, start channel AN3, and end channel AN3 (1 channel conversion)

MOV ADCS2, #A4H Activates the A/D converter using an external edge and starts A/D conversion.


MOV ADCS2, #00H -



286


Figure 17.3-4 Example of I 2OS Activation in Stop Mode

AN3Begin of start operation Interrupt I2OS transfer

Stop

External edge activation

After 12 transfer operations

Interrupt sequence

Termination

287


17.4 Notes on Using the A/D Converter

This section provides notes on using the A/D converter.

Notes on Using the A/D Converter

The A/D activation source bits STS1 and STS0 of the ADCS2 register are used to activate theA/D converter via an external trigger or internal timer. However, the input value of the externaltrigger or internal timer must be set in the inactive state. Operation can start if the bits are set tothe active state.

When setting STS1 and STS0, set ADTG = 1 for input and internal timer (16-bit reload timer) =0 for output.

For the pins used for analog input, always set the bit of the corresponding ADER register to 1.

Each pin of port 5 is controlled as follows:

0: Port input mode

1: Analog input mode

At a reset, the bit is set to 1.

Bit 15 14 13 12 11 10 9 8

Address : 00001FH ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE011111111B

R/W R/W R/W R/W R/W R/W R/W R/W

Initial value

288

17.5 Conversion Data Protection Function

17.5 Conversion Data Protection Function

The A/D converter has a function for protecting the conversion data. This protection function enables continuous conversion and ensures the correctness of multiple data

items via the I 2OS.

Conversion Data Protection Function

Only one conversion data register is provided in this device. Therefore, when A/D conversion isexecuted continuously, and conversion data is stored each time a conversion operation ends,the previous data will be lost. To protect the previous data, the following applies if the previous

data has not been transferred to memory by the I2OS: A/D conversion is stopped temporarilywithout the next item of conversion data being stored in the register even if the A/D converterhas terminated conversion.

Temporary stop is released after the I2OS has transferred the previous conversion data tomemory.

When the previously converted data has been transferred, the A/D converter continuesconversion without temporary stop.

Figure 17.5-1 Operational Flow of the Data Protection Function (Using the I 2OS)

NO

YESYES NO

Activate I2OS

Activate A/D continuous conversion

Completion of firstconversion operation

Store to data register

Completion of secondconversion operation Activate I2OS

Terminate I2OS? Stop A/D conversiontemporarily

Store to data register Activate I2OS

Completion of thirdconversion operation Activate I2OS

Continue

Completion of allconversion operations Activate I2OS

End

Interrupt routine

Stop A/D conversion

289


Note:

• The conversion data protection function is related to the INT and INTE bits of the ADCS2register.

• The conversion data protection function operates only when interrupts are allowed (INTE =1). When interrupts are prohibited (INTE = 0), the conversion data will be continuouslystored to the register, resulting in the old data being lost if continuous A/D conversion is

executed. In addition, if the I2OS is not used when interrupts are allowed (INTE = 1), the INTbit will not be cleared. As a result, the conversion data protection function will operate andA/D conversion will be stopped temporarily. In this case, the temporary stop will be releasedwhen the INT bit is cleared via the interrupt routine.

• If interrupts are prohibited when A/D conversion is stopped temporarily during operation of

the I2OS, A/D conversion can be executed, causing new data to be written before the olddata is transferred. Moreover, the standby data will be lost if A/D conversion is restartedduring temporary stop.

290

CHAPTER 18 D/A CONVERTER

This chapter explains the functions and operation of the D/A converter.

18.1 "Outline of the D/A Converter"

18.2 "D/A Converter Registers"

18.3 "D/A Converter Operation"

291


18.1 Outline of the D/A Converter

This block is a R-2R-method D/A converter that provides 8-bit resolution. The D/A converter has two built-in channels. The D/A control registers are independent and can control output.

D/A Converter Registers

Figure 18.1-1 D/A Converter Registers

DA17Address : 00003BH DA16 DA15 DA14 DA13 DA12 DA11 DA10 DADR1

DA0700003AH DA06 DA05 DA04 DA03 DA02 DA01 DA00 DADR0

15 14 13 12 11 10 9 8

7 6 5 4 3 2 1 0

Bit No.

Bit No.

(R/W) (R/W) (R/W)(R/W)(X) (X) (X) (X) (X) (X)

(R/W)(X)(X)

(R/W)(R/W) (R/W)

(R/W) (R/W) (R/W)(R/W)(X) (X) (X) (X) (X) (X)

(R/W)(X)(X)

(R/W)(R/W) (R/W)

00003DH DAE1 DACR1

00003CH DAE0 DACR0

15 14 13 12 11 10 9 8

7 6 5 4 3 2 1 0

Bit No.

Bit No.

(-) (-) (-) (R/W)(-) (-) (-) (-) (-) (0)

(-)(-)(-)

(-) (-) (-)

(-) (-) (-) (R/W)(-) (-) (-) (-) (-) (0)

(-)(-)(-)

(-) (-) (-)

D/A converter data register 1


D/A control register 1






Address :

Address :

Address :

292

18.1 Outline of the D/A Converter

Block Diagram of the D/A Converter

Figure 18.1-2 "Block Diagram of the D/A Converter" shows a block diagram of the D/Aconverter.

Figure 18.1-2 Block Diagram of the D/A Converter

DA DA DA DA DA DA DA DA DA DA DA DA DA DA DA DA17 16 15 14 13 12 11 10 07 06 05 04 03 02 01 00

DVR DVR

DA17 DA07

2R 2RR R

DA16 DA06

2R 2RR R

DA15 DA05

DA11 DA01

2R 2RR R

DA10 DA00

2R 2R2R 2R

DAE1 DAE0

Internal data bus

Standby control Standby control

DA output channel 1 DA output channel 0

293


18.2 D/A Converter Registers

There are two types of D/A converter register, as follows:• D/A converter data registers (DADR0 and DADR1)• D/A control registers (DACR0 and DACR1)

D/A Converter Data Registers (DADR0 and DADR1)

Figure 18.2-1 "D/A Converter Data Registers (DADR0 and DADR1)" shows the configuration ofthe D/A converter data registers (DADR0 and DADR1).

Figure 18.2-1 D/A Converter Data Registers (DADR0 and DADR1)

[Bits 15 to 8] DA17 to DA10

These bits are used to specify the output voltage of channel 1 of the D/A converter. At areset, these bits are not initialized. These bits can be read and written.

[Bits 7 to 0] DA07 to DA00

These bits are used to set the output voltage of channel 0 of the D/A converter. At a reset,these bits are not initialized. These bits can be read and written.

DA1700003BH

DA16 DA15 DA14 DA13 DA12 DA11 DA10 DADR1

DA0700003AH DA06 DA05 DA04 DA03 DA02 DA01 DA00 DADR0

15 14 13 12 11 10 9 8

7 6 5 4 3 2 1 0

Bit No.

Bit No.

(R/W) (R/W) (R/W)(R/W)(X) (X) (X) (X) (X) (X)

(R/W)(X)(X)

(R/W)(R/W) (R/W)

(R/W) (R/W) (R/W)(R/W)(X) (X) (X) (X) (X) (X)

(R/W)(X)(X)

(R/W)(R/W) (R/W)





Address:

Address:

294

18.2 D/A Converter Registers

D/A Control Registers (DACR0 and DACR1)

Figure 18.2-2 "D/A Control Registers (DACR0 and DACR1)" shows the configuration of the D/Aconverter control registers (DACR0 and DACR1).

Figure 18.2-2 D/A Control Registers (DACR0 and DACR1)

[Bits 8 and 0] DAE1 and DAE0

The DAE1 and DAE0 bits are used to allow or prohibit D/A converter output. The DAE1 bit isused to control channel 1. The DAE0 bit is used to control channel 0.

Setting these bits to 1 allows D/A converter output. Writing 0 prohibits D/A converter output.

At a reset, these bits are initialized to 0. These bits can be read and written.

00003DHDAE1 DACR1

00003CH DAE0 DACR0

15 14 13 12 11 10 9 8

7 6 5 4 3 2 1 0

Bit No.

Bit No.

(-) (-) (-) (R/W)(-) (-) (-) (-) (-) (0)

(-)(-)(-)

(-) (-) (-)

(-) (-) (-) (R/W)(-) (-) (-) (-) (-) (0)

(-)(-)(-)

(-) (-) (-)




Address:

Address:


295


18.3 D/A Converter Operation

To start D/A converter output, set the allow bit for the corresponding D/A converter output channel of the D/A control register (DACR) to 1.

D/A Converter Operation

When D/A output is prohibited, the analog switch inserted in series to the output of eachchannel is turned off. In addition, the D/A converter is cleared to 0 internally and the path of thedirect current disconnected. The above operations are performed even in stop mode.

The output voltage of the D/A output is in the range of 0 V to 255/256 x DVR. To change theoutput voltage range, adjust the DVR voltage externally.

No built-in buffer amplifier is provided for the D/A converter output. In addition, because ananalog switch (almost equal to 100 Ω) is inserted in series to the output, allow sufficient time foradjustment when a load is externally applied to the output.

Table 18.3-1 "Theoretical Values of D/A Converter Output Voltage" lists the theoretical values ofthe D/A converter output voltage.

Table 18.3-1 Theoretical Values of D/A Converter Output Voltage

Setting value of DA07 to DA00

andDA17 to DA10

Theoretical value of output voltage

00H 0/256 x DVR (=0V)

01H 1/256 x DVR

02H 2/256 x DVR

: :

FDH 253/256 x DVR

FEH 254/256 x DVR

FFH 255/256 x DVR

296

CHAPTER 19 UART

This chapter explains the functions and operation of the UART.

19.1 "Outline of the UART"

19.2 "Block Diagram of the UART"

19.3 "UART Registers"

19.4 "UART Baud Rates"

19.5 "UART Operation"

19.6 "UART Flags and Interrupt Generation Sources"

19.7 "UART Application Example and Notes on Use"

297

CHAPTER 19 UART

19.1 Outline of the UART

The UART is a serial I/O port used for asynchronous communication or CLK synchronous communication.

UART Features

The UART has the following features:

• Full-duplex double buffer

• Asynchronous communication and CLK synchronous communication are supported

• Multiprocessor mode is supported

• Built-in dedicated baud rate generator

• An arbitrary baud rate can be set using an external clock.

• Error detection function (parity, framing, and overrun)

• The transfer signals have NRZ codes.

• Intelligent I/O service (I2OS) supported

Table 19.1-1 Baud Rates

Operation Baud rate (*1)

Asynchronous 31250/9615/4808/2404/1202 bps

CLK synchronous 1M/500K/250K/125K/115.2K/62.5K bps

*1: Value when the internal machine clock has a frequency of 6, 8, 10, 12, or 16 MHz.

298

19.2 Block Diagram of the UART

19.2 Block Diagram of the UART

Figure 19.2-1 "Block Diagram of the UART" shows a block diagram of the UART.

Block Diagram of the UART

Figure 19.2-1 Block Diagram of the UART

SCK0

SIN0

SOT0

SIDR SODR

MD1 PEN PEMD0 P ORECS2 SBL FRECS1 CL RDRFCS0 A/D TDRE

RECSCKE RXE RIESOE TXE TIE

Control signalReceive interrupt(to the CPU)

Dedicated baud rategenerator

PPG1(internal connection)

External clock

Clock selectioncircuit Receive clock

Send clock Send interrupt(to the CPU)

Receive control circuit

Start bit detectioncircuit

Receive bit counter

Receive paritycounter

Send control circuit

Send start circuit

Send bit counter

Send parity counter

Receive statusdecision circuit

Receive shifter Send shifter

Receive end Send start

Receive error generationsignal for I2OS (to the CPU)

F2MC-16L bus

SMR register

SCR register

SSR register

Control signal

299

CHAPTER 19 UART

19.3 UART Registers

There are five types of UART register, as follows:• Serial mode register (SMR)• Serial control register (SCR)• Serial input data register (SIDR)/serial output data register (SODR)• Serial status register (SSR)• Communication prescaler control register (CDCR)

UART Registers

Figure 19.3-1 UART Registers

7 6 5 4 3 2 1 0 Bit No.

Address : 000020H MD1 MD0 CS2 CS1 CS0 SCKE SOE SMR

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)(0) (0) (0) (0) (0) (0) (0) (0)

(R/W)

Bit No.

Address : 000021H PEN P SBL CL A/D REC RXE TXE SCR

(R/W) (R/W) (R/W) (R/W) (R/W) (W) (R/W) (R/W)(0) (0) (0) (0) (0) (1) (0) (0)

15 14 13 12 11 10 9 8

7 6 5 4 3 2 1 0 Bit No.

Address : 000022H D7 D6 D5 D4 D3 D2 D1 D0 SIDR(read)SODR(write)


15 14 13 12 11 10 9 8 Bit No.

Address : 000023H PE ORE FRE RDRF TDRE RIE TIE SSR

(R) (R) (R) (R) (R) (-) (R/W) (R/W)(0) (0) (0) (0) (1) (-) (0) (0)

15 14 13 12 11 10 9 8 Bit No.

Address : 000027H MD DIV3 CDCR

(R/W) (R/W) (R/W) (R/W)(0) (-) (-) (-) (1) (1) (1) (1)

DIV2 DIV1 DIV0

(R/W)(-) (-) (-)

Serial mode register

Serial control register

Serial input data registerSerial output data register

Serial status register

Communication prescaler control register

Reserved






15 8 7 0

SMR

SSR

CDCR

SMR

SIDR/SODR

000021H,000020H

000023H,000022H

000027H

300

19.3 UART Registers

19.3.1 Serial Mode Register (SMR)

The serial mode register (SMR) specifies the operation mode of the UART.Specify the operation mode while operation is stopped. Do not write to this register during operation.

Serial Mode Register (SMR)

Figure 19.3-2 Configuration of the Serial Mode Register (SMR)

[Bits 7 and 6] MD1 and MD0 (MoDe select)

The MD1 and MD0 bits are used to select the operation mode of the UART.

Note:

CLK asynchronous mode (multiprocessor) of mode 1 means that multiple slave CPUs areconnected to one host CPU.

This resource cannot identify the data format of the receive data. Accordingly, only themaster in multiprocessor mode is supported.

Moreover, the parity check function cannot be used. Therefore, set the PEN bit in the serialcontrol register (SCR) to 0.

7 6 5 4 3 2 1 0 Bit No.

Address : 000020H MD1 MD0 CS2 CS1 CS0 SCKE SOE SMR

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)(0) (0) (0) (0) (0) (0) (0) (0)

(R/W)

Serial mode register


Reserved

Table 19.3-1 MD0 and MD1 (Operation Mode Selection Bits)

Mode MD1 MD0 Operation mode

0 0 0 Asynchronous normal mode [initial value].

1 0 1 Asynchronous multiprocessor mode

2 1 0 CLK synchronous mode

- 1 1 Setting prohibited

301

CHAPTER 19 UART

[Bits 5 to 3] CS2, CS1, and CS0 (Clock Select)

These bits are used to select the baud rate clock source.

When the dedicated baud rate generator is selected, the baud rate is determined at thesame time.

Note:

When the internal timer is selected, PPG1 is selected for the MB90650A series.


Always set this bit to 0.

[Bit 1] SCKE (SCIK Enable)

For communication in CLK synchronous mode (mode 2), the SCKE bit specifies whether touse the SCK0 pin as a clock input pin or as a clock output pin.

In CLK asynchronous mode or external clock mode, always set the SCKE bit to 0.

Note:

To use the SCK0 pin as a clock input pin, the external clock source must be selected.

[Bit 0] SOE (Serial Output Enable)

The SOE bit specifies whether to use the external pin (SOT0) in combination with a general-purpose I/O port pin as a serial output pin or as an I/O port pin.

Table 19.3-2 CS0 to CS2 (Baud Rate Selection Bits)

CS2 CS1 CS0 Clock input

000B to 100B Dedicate baud rate generator

1 0 1 Reserved

1 1 0 Internal timer

1 1 1 External clock

Table 19.3-3 SCKE (SCIK Enable) Bit Functions

SCKE Function

0 Functions as a clock input pin [initial value].

1 Functions as a clock output pin.

Table 19.3-4 SOE (Serial Output Enable) Bit Functions

SOE Function

0 External pin functions as a general-purpose I/O port pin [initial value].

1 External pin functions as a serial data output pin (SOT0).

302

19.3 UART Registers

19.3.2 Serial Control Register (SCR)

The serial control register (SCR) controls the transfer protocol for serial communication.

Serial Control Register (SCR)

Figure 19.3-3 Configuration of the Serial Control Register (SCR

[Bit 15] PEN (Parity ENable)

For serial communication, the PEN bit specifies whether to perform data communication withparity added.

Note:

Parity can be added only in normal mode (mode 0) of the asynchronous communicationmodes. Parity cannot be added in multiprocessor mode (mode 1) or CLK synchronouscommunication mode (mode 2).

[Bit 14] P (Parity)

The P bit is used to specify even or odd parity when data communication is performed withparity added.

Bit No.

Address : 000021H PEN P SBL CL A/D REC RXE TXE SCR

(R/W) (R/W) (R/W) (R/W) (R/W) (W) (R/W) (R/W)(0) (0) (0) (0) (0) (1) (0) (0)

15 14 13 12 11 10 9 8

Serial control register


Table 19.3-5 PEN (Parity ENable) Bit Functions

PEN Function

0 No parity [initial value].

1 Parity

Table 19.3-6 P (Even/Odd Parity Specification Bit)

P Function

0 Even parity [initial value].

1 Odd parity

303

CHAPTER 19 UART

[Bit 13] SBL (Stop Bit Length)

The SBL bit is used to specify the bit length of the stop bit, which is the frame end mark,when asynchronous communication is performed.

[Bit 12] CL (Character Length)

The CL bit is used to specify the data length of one frame to be sent or received.

Note:

Seven-bit data can be handled only in normal mode (mode 0) of the asynchronouscommunication modes. Use eight-bit data for multiprocessor mode (mode 1) or CLKsynchronous communication mode (mode 2).

[Bit 11] A/D (Address/Data)

In normal mode (mode 1) of the asynchronous communication modes, the A/D bit specifiesthe data format of the frame to be sent and received.

[Bit 10] REC (Receiver Error Clear)

The REC bit is used to clear the error flags (PE, ORE, and FRE) of the SSR register. Settingthis bit to 1 is invalid. The read value returned for this bit is always 1.

[Bit 9] RXE (Receiver Enable)

The RXE bit is used to control receive operations of the UART.

Table 19.3-7 SBL (Stop Bit Length Specification Bit)

SBL Function

0 1 stop bit [initial value].

1 2 stop bits

Table 19.3-8 CL (Send/Receive Data Length Specification Bit)

CL Function

0 7-bit data [initial value].

1 8-bit data

Table 19.3-9 A/D (Address/Data) Bit Functions

A/D Function

0 Data frame [initial value].

1 Address frame

Table 19.3-10 RXE (Receiver Enable) Bit Functions

RXE Function

0 Receive operations prohibited [initial value].

1 Receive operations allowed

304

19.3 UART Registers

Note:

If receive operations are prohibited while data is being received (when data has been inputto the receive shift register), receive operations are stopped when reception of the frame iscompleted and the receive data has been stored in the receive data buffer (SIDR).

[Bit 8] TXE (Transmitter Enable)

The TXE bit is used to control send operations of the UART.

Note:

If send operations are prohibited while data is being sent (when data has been output fromthe send register), send operations are stopped when there is no more data in the send databuffer (SODR).

When setting the TXE bit to 0, wait for the following specific interval after data has beenwritten to the SODR:

The specific interval is 1/16 of the baud rate in clock asynchronous transfer mode. In clocksynchronous transfer mode, the specific interval is the baud rate.

Table 19.3-11 TXE (Transmitter Enable) Bit Functions

TXE Function

0 Send operations prohibited [initial value].

1 Send operations allowed

305

CHAPTER 19 UART

19.3.3 Serial Input Data Register (SIDR)/Serial Output Data Register (SODR)

The serial input data register (SIDR) is a serial data receive register. The serial output data register (SODR) is a serial data send register.The SIDR and SODR are allocated at the same address.

Serial Input Data Register (SIDR)/Serial Output Data Register (SODR)

Figure 19.3-4 Configuration of the Serial Input Data Register (SIDR)/Serial Output Data Register (SODR)

If the data length is seven bits, the remaining high-order bit (D7) becomes invalid. Write theSODR bit when the TDRE bit in the serial status register (SSR) is 1.

Note:

Writing to this address means writing to the SODR register; reading from this address meansreading the SIDR register.

7 6 5 4 3 2 1 0 Bit No.

Address : 000022H D7 D6 D5 D4 D3 D2 D1 D0 SIDR(read)SODR(write)


Serial input data registerSerial output data register


306

19.3 UART Registers

19.3.4 Serial Status Register (SSR)

The serial status register (SSR) consists of flags that indicate the operating status of the UART.

Serial Status Register (SSR)

Figure 19.3-5 Configuration of the Serial Status Register (SSR)

[Bit 15] PE (Parity Error)

The PE bit is an interrupt request flag that is set if a parity error occurs while data is beingreceived. To clear the flag once it is set, set the REC bit (bit 10) in the serial control register(SCR) to 0.

When the PE bit is set, the data in the serial input data register (SIDR) will become invalid.

[Bit 14] ORE (Overrun Error)

The ORE bit is an interrupt request flag that is set if an overrun error occurs while data isbeing received. To clear the flag once it is set, set the REC bit (bit 10) in the serial controlregister (SCR) to 0.

When the ORE bit is set, the data in the serial input data register (SIDR) will become invalid.

15 14 13 12 11 10 9 8 Bit No.

Address : 000023H PE ORE FRE RDRF TDRE RIE TIE SSR

(R) (R) (R) (R) (R) (-) (R/W) (R/W)(0) (0) (0) (0) (1) (-) (0) (0)

Serial status register


Table 19.3-12 PE (Parity Error) Bit Functions

PE Function

0 No parity error [initial value].

1 A parity error occurred.

Table 19.3-13 ORE (Over Run Error) Bit Functions

ORE Function

0 No overrun error [initial value].

1 An overrun error occurred.

307

CHAPTER 19 UART

[Bit 13] FRE (FRaming Error)

The FRE bit is an interrupt request flag that is set if a framing error occurs while data is beingreceived. To clear the flag once it is set, set the REC bit (bit 10) in the serial control register(SCR) to 0. When the FRE bit is set, the data in the serial input data register (SIDR) willbecome invalid.

[Bit 12] RDRF (Receiver Data Register Full)

The RDRF bit is an interrupt request flag that indicates that there is data in the serial inputdata register (SIDR). The RDRF bit is set when receive data is loaded into the SIDRregister. The RDRF bit is automatically cleared when the SIDR register is read.

[Bit 11] TDRE (Transmitter Data Register Empty)

The TDRE bit is an interrupt request flag that indicates that the send data can be written tothe serial output data register (SODR). The TDRE bit is cleared when the data is written tothe SODR. When the written data is loaded into the send register and transfer started, theTDRE bit is set again to indicate that the next item of send data can be written.

[Bit 9] RIE (Receiver Interrupt Enable)

The RIE bit is used to control receive interrupts.

Note:

Receive interrupt causes include indication of normal reception using the RDRF bit inaddition to indication of errors using the error flag bits (PE, ORE, and FRE).

Table 19.3-14 FRE (FRaming Error) Bit Functions

FRE Function

0 No framing error [initial value].

1 A framing error occurred.

Table 19.3-15 RDRF (Receiver Data Register Full) Bit Functions

RDRF Function

0 No receive data [initial value].

1 Receive data

Table 19.3-16 TDRE (Transmitter Data Register Empty) Bit Functions

TDRE Function

0 Send data write prohibited

1 Send data write allowed [initial value].

Table 19.3-17 RIE (Receiver Interrupt Enable) Bit Functions

RIE Function


1 Interrupt allowed

308

19.3 UART Registers

[Bit 8] TIE (Transmitter Interrupt Enable)

The TIE bit is used to control send interrupts.

Note:

The send interrupt causes include send requests using the TDRE bit.

Table 19.3-18 TIE (Transmitter Interrupt Enable) Bit Functions

TIE Function


1 Interrupt allowed

309

CHAPTER 19 UART

19.3.5 Communication Prescaler Control Register (CDCR)

The communication prescaler control register (CDCR) controls the division of the machine clock.

Communication Prescaler Control Register (CDCR)

The operating clock of the UART is obtained by dividing the output of the machine clock. Thisregister is designed to control the communication prescaler so that a specific baud rate can beobtained for a variety of machine clocks.

Figure 19.3-6 Configuration of the Communication Prescaler Control Register (CDCR)

[Bit 15] MD (Machine clock divide moDe select)

The MD bit enables operation of the communication prescaler.

[Bits 11, 10, 9, and 8] DIV3 to DIV0 (Divide 3 to Divide 0)

These bits are used to determine the division factor.

15 14 13 12 11 10 9 8 Bit No.

Address : 000027H MD DIV3 CDCR

(R/W) (R/W) (R/W) (R/W)(0) (-) (-) (-) (1) (1) (1) (1)

DIV2 DIV1 DIV0

(R/W)(-) (-) (-)

Communication prescaler control register


Table 19.3-19 MD (Machine clock divide moDe select) Bit Functions

CDCR Function

0 The communication prescaler is stopped [initial value].

1 The communication prescaler operates.

Table 19.3-20 DIV3 to DIV0 (Divide 3 to Divide 0) Bit Functions

DIV3 DIV2 DIV1 DIV0 Division factor (div)

1 1 0 1 Divide by 3

1 1 0 0 Divide by 4

1 0 1 1 Divide by 5

1 0 1 0 Divide by 6

1 0 0 0 Divide by 8

Note• If the division factor is changed, allow a time of two cycles for clock stabilization time

before performing communication.

310

19.3 UART Registers

Settings of the Communication Prescaler Control Register

Make the settings in the communication prescaler control register as listed in the table belowbased on the machine clock frequency φ to be used.

Table 19.3-21 Settings of the Communication Prescaler Control Register

Machine clock frequency φφφφ

div DIV3 DIV2 DIV1 DIV0 φφφφ/div

4 MHz 4 1 1 0 0 1 MHz

6 MHz 6 1 0 1 0

8 MHz 8 1 0 0 0

6 MHz 3 1 1 0 1 2 MHz

8 MHz 4 1 1 0 0

10 MHz 5 1 0 1 1

12 MHz 6 1 0 1 0

14 MHz 7 1 0 0 1

16 MHz 8 1 0 0 0

8 MHz 2 1 1 1 0 4 MHz

12 MHz 3 1 1 0 1

16 MHz 4 1 1 0 0

If a machine clock and div setting other than those listed in the table above is used, make the settings in such a way that φ/div does not exceed a maximum of 4.25 MHz.

311

CHAPTER 19 UART

19.4 UART Baud Rates

Three types of UART clock can be selected, as follows:• Dedicated baud rate generator• Internal timer• External clock

Dedicated Baud Rate Generator

Table 19.4-1 "Baud Rates (At Asynchronous Communication)" and Table 19.4-2 "Baud Rates(At CLK Synchronous Communication)" list the baud rates when the dedicated baud rategenerator is selected. The baud rates are calculated using ( (machine clock frequency) = 16MHz and div (machine clock division factor) = 8. In addition, Table 19.4-3 "CommunicationPrescaler Settings" lists the setting values of the communication prescaler.

Table 19.4-1 Baud Rates (At Asynchronous Communication)

CS2 CS1 CS0 Asynchronous communication

Expression for calculation

0 0 0 9615 bps (φ/div)/(8x13x2)

0 0 1 4808 bps (φ/div)/(8x13x22)

0 1 0 2404 bps (φ/div)/(8x13x23)

0 1 1 1202 bps (φ/div)/(8x13x24)

1 0 0 31250 bps (φ/div)/26

Table 19.4-2 Baud Rates (At CLK Synchronous Communication)

CS2 CS1 CS0 CLK synchronous communication

Expression for calculation

0 0 0 1M bps (φ/div)/2

0 0 1 500K bps (φ/div)/22

0 1 0 250K bps (φ/div)/23

0 1 1 125K bps (φ/div)/24

1 0 0 62.5K bps (φ/div)/25

312

19.4 UART Baud Rates

Table 19.4-3 Communication Prescaler Settings

MD DIV3 DIV2 DIV1 DIV0 div Recommended machine clock frequency

1 1 1 0 1 3 6 MHz

1 1 1 0 0 4 8 MHz

1 1 0 1 1 5 10 MHz

1 1 0 1 0 6 12 MHz

1 1 0 0 0 8 16 MHz

313

CHAPTER 19 UART

Internal Timer

When the bits CS2 to CS0 in the serial mode register (SMR) have been set to "110" and aninternal timer is selected, the PPG1 operates in reload mode. The expression for calculating thebaud rate in this case is as follows:

Asynchronous: ( φ φ φ φ / N) / (16 x 2 x (n + 1))

CLK synchronous: ( φφφφ / N) / (2 x (n + 1))

φ: Machine clock frequency

N: Timer count clock source

n: Timer reload value

Table 19.4-4 "Baud Rates and Reload Values (Asynchronous)" lists the relationship betweenthe baud rates and reload values (decimal values) when the machine clock is set to a frequencyof 7.3728 MHz.

When the internal timer (PPG1) is selected as the baud rate clock source, the output PPG1x ofthe PPG1 has already been connected internally in this controller. Therefore, externalconnection from the external pin PPG1x of the PPG1 to the external clock input pin SCK0 of theUART is not required. In addition, if the output pin of the PPG1 has not been used for any otherpurposes, it can be used as an I/O port pin.

External Clock

When the bits CS2 to CS0 of the SMR register have been set to "111" and an external timerselected, the baud rate is as follows, where f is the frequency of the external clock:

Asynchronous: f/16

CLK synchronous: f

However, the value f must not exceed 2 MHz.

Table 19.4-4 Baud Rates and Reload Values (Asynchronous)

Baud rate Reload value

N=21

(Machine clock frequency divided by 2)

N=23

(Machine clock frequency divided by 8)

38400 2 -

19200 5 -

9600 11 2

4800 23 5

2400 47 11

1200 95 23

600 191 47

300 383 95

314

19.5 UART Operation

19.5 UART Operation

The UART has two types of operation mode: Asynchronous mode and CLK synchronous mode. Setting values in the serial mode register (SMR) and serial control register (SCR) allows switching between these operation modes.

UART Operation

Note:

The stop bit length in asynchronous mode can be specified only for send operations. Forreceive operations, the stop bit length is always 1 bit. For modes other than the above, donot set the stop bit length because the UART does not operate in those modes.

Table 19.5-1 UART Operation Modes

Mode Parity Data length Operation mode Stop bit length

0 Yes/no 7 Asynchronous normal mode 1 bit or 2 bits

Yes/no 8

1 No 8+1 Asynchronous multiprocessor mode

2 No 8 CLK synchronous mode No

315

CHAPTER 19 UART

19.5.1 Asynchronous Mode

When the UART is used in operation mode 0 (normal mode) or operation mode 1 (multiprocessor mode), the transfer method is asynchronous. Moreover, the UART handles only data in non-return-to-zero format (NRZ format).

Transfer Data Format

Figure 19.5-1 Transfer Data Format (Modes 0 and 1)

As shown in Figure 19.5-1 "Transfer Data Format (Modes 0 and 1)", the transfer data mustbegin with a start bit (low level data). When the specified data bit length is transferred in thesequence of LSB first, the data transfer terminates with a stop bit (high level data). If anexternal clock has been selected, be sure to enter the clock pulse.

In normal mode (mode 0), the data length can be set to seven or eight bits. In multiprocessormode (mode 1), however, the data length must be eight bits. In addition, a parity bit cannot beadded in multiprocessor mode. The A/D bit must be added at the end.

Receive Operations

Receive operations are always performed if the RXE bit in the serial control register (SCR) is 1.When the start bit is detected, one frame of data is received based on the data formatdetermined by the value in the SCR register. The error flag is set if an error is detected afterone frame of data has been received. The RDRF flag in the serial status register (SSR) is set inthis case. Moreover, if the RIE bit in the same SSR register has been set to 1 as well, a receiveinterrupt for the CPU is generated. Each flag of the SSR register is checked. If the receiveoperation is performed normally, the serial input data register (SIDR) is read. If an error hasoccurred, perform the required error processing. The RDRF flag is cleared when the SIDRregister is read.

Send Operations

When the TDRE flag in the serial status register (SSR) is 1, the send data is written to the serialoutput data register (SODR). In this case, the data is sent if the TXE bit in the serial controlregister (SCR) is 1.

When the data in the SODR register is loaded into the send shift register and sending hasstarted, the TDRE flag in the SSR register is set again. This enables the next item of send datato be read. In this case, if the TIE bit in the same SSR register has been set to 1, a sendinterrupt is generated for the CPU to request that send data be read into the SODR register.

The TDRE flag in the SSR register is cleared when data is read into the SODR register.

SIN0,SOT0

0 1 0 1 1 0 0 1 0 1 1Start LSB MSB Stop

A/D Stop(Mode 0)(Mode 1)

The transferred data is 01001101B.

316

19.5 UART Operation

19.5.2 CLK Synchronous Mode

When the UART is used in operation mode 2 (normal mode), the transfer is clock synchronous. Moreover, the UART handles only data in non-return-to-zero format (NRZ format).

Transfer Data Format in CLK Synchronous Mode

Figure 19.5-2 Transfer Data Format (Mode 2)

If an internal clock (dedicated baud rate generator or internal timer) has been selected, output ofthe data receive synchronous clock is automatically generated when data is sent.

Only eight-bit data can be handled by the3 device. A parity bit cannot be added. Because thereare no start and stop bits, errors other than overrun errors cannot be detected.

If an external clock has been selected, a clock pulse of exactly one byte must be supplied afterconfirming that there is data in the send data buffer SODR register of the sending side UART.(The TDRE flag in the SSR register is 0.) Always set the mark level to high before sendingstarts and after sending ends.

SCLK

RXE,TXE

SIN0,SOT0

1 0 1 1 0 0 1 0LSB MSB

SODR write

Mark

(Mode 2)

The transferred data is 01001101B.

317

CHAPTER 19 UART

Setting Values of Each Control Register When CLK Synchronous Mode is Used

Table 19.5-2 "Setting Values of Each Control Register When CLK Synchronous Mode is Used"lists the setting values of each control register when CLK synchronous mode is used.

Start of Communication in CLK Synchronous Mode

Writing to the serial output data register (SODR) starts communication. Even in the case thatonly receiving is to be performed, dummy send data must be written to the SODR register.

Termination of Communication in CLK Synchronous Mode

Checking for a change of the RDRF flag in the serial status register (SSR) to 1 can be used toconfirm that communication has terminated.

Use the ORE bit of the SSR register to determine that communication has been performednormally.

Table 19.5-2 Setting Values of Each Control Register When CLK Synchronous Mode is Used

Register name Bit name Setting

SMR register MD1, MD0 "10"

CS2, CS1, CS0 Specifies clock input.

SCKE Set 1 for the communication prescaler or an internal timer. Set 0 for an external clock.

SOE Set 1 for sending. Set 0 for receiving only.

SCR register PEN 0

P, SBL, A/D These bits have no effect.

CL 1

REC 0 (for initialization)

RXE, TXE Set at least one of these bits to 1.

SSR register RIE Set to 1 to use interrupts. Set to 0 to not use interrupts.

TIE 0

318

19.6 UART Flags and Interrupt Generation Sources


The UART has five flags (PE, ORE, FRE, RDRF, and TDRE) and two types of interrupt generation sources (for receiving and for sending).

UART Flags (PE, ORE, FRE, RDRF, and TDRE)

PE (parity error), ORE (overrun error), and FRE (framing error)

These flags are set if an error occurs while data is being received. Setting the REC bit in theserial control register (SCR) to 0 clears these flags.

RDRF

The RDRF flag is set when receive data is loaded into the serial input data register (SIDR) andcleared when the SIDR register is read. In mode 1, however, no parity detection function isavailable. In mode 2, neither parity detection function nor framing error detection function areavailable.

TDRE

The TDRE flag is set when the serial output data register (SODR) becomes empty and writing isenabled. Writing to the SODR register clears this flag.

UART Interrupt Generation Sources

There are two types of UART interrupt generation sources: One type for receiving and one forsending. At receiving, the PE, ORE, FRE, and RDRF flags in the serial status register (SSR)are used to request interrupts. At sending, the TDRE flag in the SSR register is used to requestinterrupts.

319

CHAPTER 19 UART

19.6.1 Set Timings of UART Interrupts and Flags

This section shows the timings of setting the interrupts and flags in each operation mode.

Set Timings of the UART Interrupts and Flags

During receive operations in mode 0

The PE, ORE, FRE, and RDRF flags in the serial status register (SSR) are set when receivetransfer completes and the final stop bit is detected. An interrupt request to the CPU is thengenerated. When the PE, ORE, and FRE flags are set to "active," the data in the serial inputdata register (SIDR) becomes invalid.

Figure 19.6-1 "Set Timings (Mode 0) of the PE, ORE, FRE, and RDRF Flags" shows the settimings (in mode 0) of the PE, ORE, FRE, and RDRF flags.

Figure 19.6-1 Set Timings (Mode 0) of the PE, ORE, FRE, and RDRF Flags


The ORE, FRE, and RDRF flags in the serial status register (SSR) are set when receive transferterminates and the final stop bit is detected. An interrupt request to the CPU is then generated.Because the data length of receivable data is eight bits, the data indicating the address/data inthe final bit 9 becomes invalid. When the ORE and FRE flags are active, the data in the serialinput data register (SIDR) becomes invalid.

Figure 19.6-2 "Set Timings (in Mode 1) of the ORE, FRE, and RDRF Flags" shows the settimings (in mode 1) of the ORE, FRE, and RDRF flags.

D6 D7 Stop

PE,ORE,FRE

RDRF

Data

Receive interrupt

320


Figure 19.6-2 Set Timings (in Mode 1) of the ORE, FRE, and RDRF Flags


The ORE and RDRF flags in the serial status register (SSR) are set when receive transfer endsand the final item of data (D7) is detected. An interrupt request to the CPU is then generated.When the ORE flag is set to "active," the data in the serial input data register (SIDR) becomesinvalid.

Figure 19.6-3 "Set Timings (in Mode 2) of the ORE and RDRF Flags" shows the set timings(mode 2) of the ORE and RDRF flags.

Figure 19.6-3 Set Timings (in Mode 2) of the ORE and RDRF Flags

During send operations in modes 0, 1, and 2

The TDRE flag in the serial status register (SSR) is cleared when the send data is written to theserial output data register (SODR). In addition, when the SODR register value is transferred tothe internal shift register, the SODR register is set to the write-enabled state, and the TDRE flagis set. When the TDRE flag is set, an interrupt request to the CPU is generated. When the TXEbit (also including the RXE bit in mode 2) in the serial control register (SCR) is set to 0 whiledata is being sent, the TDRE flag in the SSR register is set to 1. After the shifter for sendingstops, send operations of the UART are prohibited. After the TXE bit (also including the RXE bitin mode 2) in the SCR register was set to 0 while data is being sent, the data written to theSODR register is sent before sending is stopped.

Figure 19.6-4 "Set Timings (Modes 0 and 1) of the TDRE Flag" shows the set timings (modes 0and 1) of the TDRE flag.

Figure 19.6-5 "Set Timings (Mode 2) of the TDRE Flag" shows the set timings (mode 2) of theTDRE flag.

D7 Stop

ORE,FRE

RDRF

Data Address/data

Receive interrupt

D5 D6 D7

ORE

RDRF

Data

Receive interrupt

321

CHAPTER 19 UART

Figure 19.6-4 Set Timings (Modes 0 and 1) of the TDRE Flag

Figure 19.6-5 Set Timings (Mode 2) of the TDRE Flag

TDRE

ST D0 D1 D2 D3 D4 D5 D6 D7 SP SP ST D0 D1 D2 D3A/D

SODR write

SOT0 interrupt

SOT0 output

ST: Start bit

D0 to D7: Data bitsSP: Stop bitA/D: Address/data multiplexer

Request interrupt to the CPU.

TDRE

D1 D2 D3 D4 D5 D6 D7 D0 D2 D3 D4 D5 D6 D7D1D0

SODR write

SOT0 interrupt

SOT0 output

Request interrupt to the CPU.

D0 to D7: Data bits

322

19.7 UART Application Example and Notes on Use


This section provides a sample system configuration when mode 1 is used as an example for UART application, and a communication flowchart.

UART Application Example (Sample System Configuration When Mode 1 is Used)

Mode 1 is used in cases where several slave CPUs are to be connected to one host CPU. Thisresource supports only the communication interface of the host side. Figure 19.7-1 "SampleSystem Configuration When Mode 1 is Used" shows a system construction example whenmode 1 is used.

Figure 19.7-1 Sample System Configuration When Mode 1 is Used

SO

SI

SO SI SO SIHost CPU

Slave CPU#0 Slave CPU#1

323

CHAPTER 19 UART

UART Communication Flowchart

As shown in Figure 19.7-2 "Communication Flowchart When Mode 1 is Used", communicationstarts when the host CPU transfers address data. The data is address data when the A/D bit inthe serial control register (SCR) is 1. This address data is used to select the slave CPU usedfor communication and enable communication with the host CPU. The data is regular datawhen the A/D bit in the SCR register is 0.

Because the parity check function cannot be used in mode 1, set the PEN bit in the SCRregister to 0.

Figure 19.7-2 Communication Flowchart When Mode 1 is Used

START

No

Yes

No

Yes

END

(Host CPU)

Set transfer mode to 1

Set data for selecting theslave CPU in D0 to D7,set A/D bit to 1,and transfer 1 byte.

Set A/D bit to 0

Enable receive

Communicate with slave CPU

Communication ended?

Communicatewith other slave CPU?

Prohibit receive

324


Intelligent I/O Service (I 2OS)

See Section 3.6 "Extended Intelligent I/O Service (EI2OS)" for details about the I2OS.

Notes on Using the UART

Set the communication mode while operation is stopped. The send and receive data isunpredictable at the instance when the mode is set.

When synchronous transfer mode (mode 2) is being used, the communication control circuit canstop if the timing of writing to the send data register (SODR) matches the timing of the receiveinterrupt request (RDRF = 1). Therefore, write to the SODR register when data transfer hasbeen completely finished or write to the SODR register immediately after sending has started.

325

CHAPTER 19 UART

326

CHAPTER 20 I/O EXTENDED SERIAL INTERFACE

This chapter explains the functions and operation of the I/O extended serial interface.

20.1 "Outline of the I/O Extended Serial Interface"

20.2 "I/O Extended Serial Interface Registers"

20.3 "Operation of the I/O Extended Serial Interface"

327


20.1 Outline of the I/O Extended Serial Interface

The I/O extended serial interface enables data transfer using a clock synchronous method in an 8-bit x 1-channel configuration. LSB first or MSB first can be selected for data transfer.

Outline of the I/O Extended Serial Interface

The I/O extended serial interface has two types of operation mode, as follows:

Internal shift clock mode

In this mode, the data is transferred synchronized with the internal clock (communicationprescaler).

External shift clock mode

In this mode, the data is transferred synchronized with the clock input from an external pin(SCK). By using the general-purpose ports that share the external pin (SCK), CPU instructionscan also be used to transfer data.

Block Diagram of the I/O Extended Serial Interface

Figure 20.1-1 Block Diagram of the I/O Extended Serial Interface

SIN1,2

SOT1,2

SCK1,2

2 1 0

SMD2 SMD1 SMD0 SIE SIR BUSY STOP STRT MODE BDS SOE SCOE

F2MC-16L bus

(MSB first) D0 to D7 D7 to D0 (LSB first)

Select transfer direction

SDR (serial data register)ReadWrite

Control circuit Shift clock counter

Internal clock (communication prescaler)

Interrupt request

F2MC-16L bus

328

20.2 I/O Extended Serial Interface Registers


The I/O extended serial interface has three types of register, as follows:• Serial mode control status register higher• Serial mode control status register lower• Serial data register

I/O Extended Serial Interface Registers

Figure 20.2-1 I/O Extended Serial Interface Registers

15 14 13 12 11 10 9 8

000025H SMCS000029H SMD2 SMD1 SMD0 SIE SIR BUSY STOP STRT

(R/W) (R/W) (R/W) (R/W) (R/W) (R) (R/W) (R/W)(0) (0) (0) (0) (0) (0) (1) (0)

7 6 5 4 3 2 1 0

000024H

000028H MODE BDS SOE SCOE SMCS

(-) (-) (-) (-) (R/W) (R/W) (R/W) (R/W)(-) (-) (-) (-) (0) (0) (0) (0)

7 6 5 4 3 2 1 0

000026H

00002AH D7 D6 D5 D4 D3 D2 D1 D0 SDR


Serial mode control status register higherBit No.

Bit No.

Bit No.

Address:

Address:

Address:




Serial mode control status register lower

Serial data register

329


20.2.1 Serial Mode Control Status Register (SMCS)

The serial mode control status register (SMCS) controls the transfer operation mode of serial I/O.

Serial Mode Control Status Register (SMCS)

Figure 20.2-2 Serial Mode Control Status Register (SMCS)

[Bit 3] MODE

The MODE bit is used to select the condition for activation from stopped status. However,writing this bit during operation is prohibited. At a reset, the MODE bit is initialized to 0.

The MODE bit can be read and written.

When activating the extended intelligent I/O service, set this bit to 1.

15 14 13 12 11 10 9 8000025H

SMCSSMD2 SMD1 SMD0 SIE SIR BUSY STOP STRT

(R/W) (R/W) (R/W) (R/W) (R/W) (R) (R/W) (R/W)(0) (0) (0) (0) (0) (0) (1) (0)

7 6 5 4 3 2 1 0

MODE BDS SOE SCOE SMCS

(-) (-) (-) (-) (R/W) (R/W) (R/W) (R/W)(-) (-) (-) (-) (0) (0) (0) (0)

000029H

000024H000028H

Bit No.

Bit No.

Address:

Address:



Serial mode control status register higher

Serial mode control status register lower

Note: Only 0 is allowed for SIR (bit 11) write operations. Only 1 is allowed for STRT (bit 8) write operations. Read operations always return 0.

Table 20.2-1 MODE (Activation Condition Select) Bit Functions

MODE Function

0 Activated when STRT = 1 is set [initial value].

1 Activated at reading/writing of the serial data register.

330


[Bit 2] BDS (Bit Direction Select)

At serial data input/output, the BDS bit is used to select whether to transfer data starting fromthe least significant bit (LSB first) or from the most significant bit (MSB first). Table 20.2-2"BDS (Bit Direction Select) Bit Functions" lists the selections. At a reset, the BDS bit isinitialized to 0.

The BDS bit can be read and written.

Note:

Set the transfer direction bit before writing data to the SDR register.

[Bit 1] SOE (Serial Output Enable)

As listed in Table 20.2-3 "SOE (Serial Out Enable) Bit Functions", the SOE bit is used tocontrol output of the output external pins (SOT1 and SOT2) for serial I/O. At a reset, theSOE bit is initialized to 0.

The SOE bit can be read and written.

[Bit 0] SCOE (SCLK Output Enable)

As listed in Table 20.2-4 "SCOE (SCLK Output Enable) Bit Functions", the SCOE bit is usedto control output of the I/O external pins (SCK1 and SCK2) for the shift clock.

To transfer data for each instruction in external shift clock mode, set the SCOE bit to 0. At areset, the SCOE bit is initialized to 0. The SCOE bit can be read and written.

Table 20.2-2 BDS (Bit Direction Select) Bit Functions

BDS Function

0 LSB first [initial value].

1 MSB first

Table 20.2-3 SOE (Serial Out Enable) Bit Functions

SOE Function

0 General-purpose port pin [initial value].

1 Serial data output

Table 20.2-4 SCOE (SCLK Output Enable) Bit Functions

SCOE Function

0 At transfer for each general-purpose port pin instruction [initial value].

1 Shift clock output pin

331


[Bits 15, 14, and 13] SMD2, SMD1, and SMD0 (Serial Shift Clock Mode)

As listed in Table 20.2-5 "SMD0 to SMD2 (Serial Shift Clock Mode Select) Bit Functions", theSMD2, SMD1, and SMD0 bits are used to select the serial shift clock mode.

At a reset, the SMD2, SMD1, and SMD0 bits are initialized to "000." Rewriting these bitsduring transfer is prohibited.

For the shift clock, five types of internal shift clock and one external shift clock can beselected.

Do not set SMD2, SMD1, and SMD0 to "110" or "111," because these values are reserved.

When SCOE = 0 has been set for the clock selection, the ports that share the SCK1 andSCK2 pins can be operated so that shifting can also be performed for each instruction.

Table 20.2-5 SMD0 to SMD2 (Serial Shift Clock Mode Select) Bit Functions

SMD2 SMD1 SMD0 Division factor A

φφφφ=16MHzdiv=8

φφφφ=8MHzDiv=4

φφφφ=4MHzdiv=4

0 0 0 2 1 MHz 1 MHz 500 KHz

0 0 1 4 500 KMHz 500 KMHz 250 KMHz

0 1 0 16 125 KMHz 125 KMHz 62.5 KMHz

0 1 1 32 62.5 KMHz 62.5 KMHz 31.2 KMHz

1 0 0 64 31.2 MHz 31.2 MHz 15.6 MHz

1 0 1 - External shift clock mode

1 1 0 - Reserved

1 1 1 - Reserved

Table 20.2-6 Recommended Machine Cycles Using Communication Prescaler (CDCR) Settings

Div* Machine clock Recommended machine cycle

MD D3 D2 D1 D0

3 1 1 1 0 1 6 MHz

4 1 1 1 0 0 8 MHz

5 1 1 0 1 1 10 MHz

6 1 1 0 1 0 12 MHz

7 1 1 0 0 1 14 MHz

8 1 1 0 0 0 16 MHz

Note: See the explanation of the communication prescaler control register (CDCR). D3 to D0 are abbreviations of DIV0 to DIV3.

332


[Bit 12] SIE (Serial I/O Interrupt Enable)

As listed in Table 20.2-7 "SIE (Serial I/O Interrupt Enable) Bit Functions", the SIE bit is usedto control serial I/O interrupt requests.

At a reset, the SIE bit is initialized to 0. The SIE bit can be read and written.

[Bit 11] SIR (Serial i/o Interrupt Request)

The SIR bit is set to 1 when serial data transfer ends. When the SIR bit is set to 1 wheninterrupts are allowed (SIE = 1), an interrupt request to the CPU is generated. Clearing ofthe SIR bit depends on the MODE bit. If the MODE bit is 0, setting the SIR bit to 0 in writingoperations clears the bit. If the MODE bit is 1, reading or writing the SDR register clears theSIR bit.

Regardless of the MODE bit setting, a reset or setting the STOP bit to 1 clears the SIR bit.

Setting the SIR bit to 1 has no effect. Reading using a read-modify-write instruction alwaysreturns 1.

[Bit 10] BUSY

The BUSY bit indicates whether serial transfer is being executed. At a reset, the BUSY bit isinitialized to 0. The BUSY bit can only be read.

[Bit 9] STOP

The STOP bit is used to forcibly stop serial transfer.

Setting this bit to 1 sets stop when STOP = 1.

At a reset, the STOP bit is initialized to 1. The STOP bit can be read and written.

[Bit 8] STRT

The STRT bit is used to start serial transfer. Setting the STRT bit to 1 in stopped statusstarts transfer. Writing 1 during serial transfer or during serial shift register R/W standby isignored. Writing 0 has no effect.

Reading always returns 0.

Table 20.2-7 SIE (Serial I/O Interrupt Enable) Bit Functions

SIE Function

0 Serial I/O interrupt prohibited [initial value].

1 Serial I/O interrupt allowed

Table 20.2-8 BUSY Bit Functions

BUSY Function

0 Stop or serial data register R/W standby status [initial value].

1 Serial transfer status

Table 20.2-9 STOP Bit Functions

STOP Function

0 Regular operation

1 Stop transfer when STOP = 1 [initial value].

333


20.2.2 Serial Shift Data Register (SDR)

The serial shift data register (SDR) retains the transfer data of serial I/O. Reading and writing to the SDR register during transfer is prohibited.

Serial Shift Data Register (SDR)

Figure 20.2-3 Serial Shift Data Register (SDR)

7 6 5 4 3 2 1 0

D7 D6 D5 D4 D3 D2 D1 D0 SDR


000026H

00002AH

Bit No.Address:


Serial shift data register

334

20.3 Operation of the I/O Extended Serial Interface


The I/O extended serial interface is configured from the SMCS and SDR registers and used for input/output of 8-bit serial data.

Operation of the I/O Extended Serial Interface

At input/output of serial data, the contents of the shift register are output to the serial output pin(SOT1 pin) as a bit series. The contents are output synchronized with the falling edge of theserial shift clock (external clock, internal clock). The contents are then input to the SDR registeras a bit series from the serial input pin (SIN1 pin). The contents are input synchronized with therising edge of the serial shift clock. The BDS bit of the SMCS register can be used to specifythe shift direction (transfer from MSB or transfer from LSB).

When transfer terminates, stopped status or data register R/W standby status is set dependingon the MODE bit of the SMCS register. Transiting from each of these states to transfer status isdone as follows:

• On return from stopped status, set the STOP bit to 0 and the STRT bit to 1. (The STOP andSTRT bits can be set at the same time.)

• On return from SDR register R/W standby status, read or write the data register.

335


20.3.1 Shift Clocks

There are two modes for the shift clock: Internal shift clock mode and external shift clock mode. The SMCS register is used to specify the shift clock mode. Stop serial input/output before switching the shift clock modes. The BUSY bit can be read to determine whether stopped status applies.

Internal Shift Clock Mode

The internal shift clock operates using the output of the communication prescaler. A shift clockwith a duty ratio of 50% can be output from the SCK pin as the synchronous timing output. Onebit is transferred for each clock pulse.

The transfer rate can be represented using the following expression:

Where A is the division ratio indicated by the SMD bit of the SMCS register of 2, 22, 24, 25, or

26.

External Shift Clock Mode

In external shift clock mode, one bit is transferred for each clock pulse synchronized with theexternal shift clock input from the SCK pin. A transfer rate up to 1/(8 machine cycles) from theDC is enabled. For example, if one machine cycle is 62.5 ns, then a transfer rate up to 2 MHz isenabled.

Transfer is also enabled for each instruction. This is enabled using the following settings:

1. Select external shift clock mode and set the SCOE bit of the SMCS register to 0.

2. Write 1 to the direction register of the port that shares the SCK pin and set the port to outputmode.

After the above settings have been made, writing 1 and 0 to the port data register (PDR)enables the value of the port output to the SCK pin to be fetched as the external clock andtransfer executed. Start the shift clock from high.

Note:

Writing to the SMCS and SDR registers during serial I/O is prohibited.

Transfer rate (s)Internal clock machine cycle (Hz)

=A

336


20.3.2 Operation States of the I/O Extended Serial Interface

The I/O extended serial interface has four operating states, as follows:• STOP status• Stopped status• SDR register R/W standby status• Transfer status

STOP Status

STOP status is set at a reset or when the STOP bit of the SMCS register is set to 1. In STOPstatus, the shift counter is initialized and the SIR register is set to 0. To return from STOPstatus, set the STOP bit to 0 and the STRT bit to 1 (both can be set at the same time). Becausethe STOP bit has priority over the STRT bit, transfer operations will not be executed even if theSTRT bit is 1 when the STOP bit is 1.

Stopped Status

If the MODE bit is 0, the SMCS register BUSY bit is set to 0 and the SIR bit is set to 1 whentransfer terminates, the counter is initialized, and stopped status is set. To return from stoppedstatus, set the STRT bit to 1 to restart the transfer operation.

Serial Data Register (SDR) R/W Standby Status

If the SMCS register MODE bit is 1, the BUSY bit is set to 0 and the SIR bit is set to 1 whenserial transfer ends and SDR R/W standby status is set. If the interrupt allowed register hasbeen set to interrupts allowed, an interrupt signal is output from this block.

To return from R/W standby status, read or write the SDR register to set the BUSY bit to 1 so asto restart the transfer operation.

Transfer Status

Transfer status is set when the BUSY bit is set to 1 and transfer is being executed. The MODEbit can be used to transit to stopped status and R/W standby status.

Figure 20.3-1 "Transition Diagram of I/O Extended Serial Interface Operation" shows atransition diagram of I/O extended serial interface operation. Figure 20.3-2 "ConceptualDiagram of Reading and Writing the Serial Data Registers" shows a conceptual diagram ofreading and writing the serial data registers.

337


Figure 20.3-1 Transition Diagram of I/O Extended Serial Interface Operation

Figure 20.3-2 Conceptual Diagram of Reading and Writing the Serial Data Registers

STOP=0 & STRT=0STOP

STRT=0, BUSY=0 STOP=1 STRT=0, BUSY=0MODE=0

MODE=0STOP=0 &

& STOP=0 STOP=1 STOP=0 STOP=1STRT=1 & &

STRT=1

MODE=1& & STOP=0STRT=1, BUSY=1 STRT=1, BUSY=0

MODE=1SDR R/W & MODE=1

Terminate transfer

Reset

Terminate

TerminateTransfer Serial data register R/W standby

SOT CPU

SIN

Ser

ial d

ata

Data busReadWrite

Output interrupt

I/O extended serial interface

Data bus

ReadWrite

Input interruptData bus Interrupt controller

Explanation of items and in Figure 20.3-2

If the MODE bit is 1, transfer is terminated using the shift clock counter, the SIR bit is set to 1, and R/W standby status is set. If the SIE bit is 1, an interrupt signal is generated. An interrupt signal is not generated, however, if the SIE bit is "inactive" or the STOP bit has been set to 1 to stop transfer.

When the SDR register is read or written, the interrupt request is cleared and serial transfer is started.

338


20.3.3 Start/Stop Timing of Shift Operations

Use the following settings to start and stop shift operations:Start: Set the SMCS register STOP bit to 0 and the STRT bit to 1.Stop: The shift operation is stopped when transfer ends or when the STOP bit is set to 1. When stopping when the STOP bit is set to 1, the shift operation stops with the SIR bit set to 0 regardless of the MODE bit setting. When stopping when transfer terminates, the SIR bit is set to 1 and the shift operation stops regardless of the MODE bit setting.

Start/Stop Timing of Shift Operations

The BUSY bit is set to 1 in serial transfer status regardless of the MODE bit. The BUSY bit isset to 0 in stopped status or R/W standby status. Read the BUSY bit to confirm the transferstatus.

339


Internal shift clock mode (LSB first)

Figure 20.3-3 Shift Operation Timing (Internal Clock)

External shift clock mode (LSB first)

Figure 20.3-4 Shift Operation Timing (External Clock)

Executing instruction shift in external shift clock mode (LSB first)

Figure 20.3-5 Shift Operation Timing (Shifting for Each Instruction in External Shift Clock Mode)

SCK1,2

STRT

BUSY

SOT1,2 D00

(Start transfer) (End of transfer)

Output 1

When MODE = 0

(Retain data)D07

Note: D07 to D00 represent output data.

SCK1,2

STRT

BUSY

SOT1,2 D00

(Start transfer) (End of transfer)

When MODE = 0

(Retain data)D07


SCK1,2

STRT

BUSY

SOT1,2 D06

PDR SCK bit 0 PDR SCK bit 0

PDR SCK bit 1 (end of transfer)

When MODE = 0

D07 (Retain data)

Note: D07 to D00 represent output data. For instruction shift, high is output when the bit corresponding to the PDR SCK bit is set to 1. Low is output when this bit is set to 0. (This applies, however, only when the SCOE bit has been set to 0 when external shift clock mode is selected.)

340


Stopping by setting the STOP bit to 1 (LSB first and using an internal clock)

Figure 20.3-6 Stop Timing When the STOP Bit is Set to 1

SCK1,2

STRT

BUSY

STOP

SOT1,2 D03 D04

(Start transfer) (End transfer)

Output 1

When MODE = 0

(Retain data)D05


341


20.3.4 Serial Data I/O Timing

During serial data transfer, data is output from the serial output pin (SOT2) at the falling edge of the shift clock. Data is input to the serial input pin (SIN0) at the rising edge of the shift clock.

Serial Data I/O Timing

Figure 20.3-7 "Serial Data I/O Shift Timing" shows the serial data I/O shift timing.

Figure 20.3-7 Serial Data I/O Shift Timing

SCK1,2

SIN1,2 DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7

SOT1,2 DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7

SCK1,2

SIN1,2

SOT1,2

DI0DI1DI2DI3DI4DI5DI6DI7

DO0DO1DO2DO3DO4DO5DO6DO7

LSB first (When the BDS bit is 0)

MSB first (When the BDS bit is 1)

SIN input

SIN input

SOT output

SOT output

342


20.3.5 I/O Extended Serial Interface Interrupt Functions

The I/O extended serial interface can generate interrupt requests for the CPU. When data transfer ends, the SIR bit (interrupt flag) is set. If the SMCS register SIE bit (interrupt allowed bit) is 1, an interrupt request is output to the CPU.

I/O Extended Serial Interface Interrupt Functions

Figure 20.3-8 "Interrupt Signal Output Timing of the I/O Extended Serial Interface" shows theinterrupt signal output timing of the I/O extended serial interface.

Figure 20.3-8 Interrupt Signal Output Timing of the I/O Extended Serial Interface

SCK1,2

BUSYSIE="1"

SIR

SOT1,2 D06

(End of transfer)

SDR RD/WR

When MODE = 2

(Retain data)D07

343


344

CHAPTER 21 I2C INTERFACE

This chapter explains the functions and operation of the I 2C interface.

21.1 "Outline of the I2C Interface"

21.2 "I2C Block Diagram"

21.3 "I2C Interface Registers"

21.4 "I2C Interface Operation"

345


21.1 Outline of the I 2C Interface

The I2C interface is a serial I/O port that supports the Inter IC BUS. The I 2C interface

operates as a master/slave device on the I 2C bus.

I2C Interface Features

In the MB90650A series, the I2C interface is built in as one channel.

The I2C has the following features:

• Master/slave sending and receiving

• Arbitration function

• Clock synchronization function

• Slave address/general call address detection function

• Transfer direction detection function

• Start condition repeat generation and detection function

• Bus error detection function

346

21.2 I2C Block Diagram

21.2 I2C Block Diagram

Figure 21.2-1 "Block Diagram of the I 2C Interface" shows a block diagram of the I 2C interface.

Block Diagram of the I 2C Interface

Figure 21.2-1 Block Diagram of the I 2C Interface

ICCR

EN

ICCR 5 6 7 8

CS4

CS3

CS22 4 8 16 32 64 128 256 Sync

CS1

CS0

IBSR

BB

RSCLast Bit

LRB

TRX

FBT First Byte

AL

IBCR

BERSCL

BEIEIRQ SDA

INTE

INT

IBCR

SCC

MSS

ACK

GCAA

IDARIBSR

AAS

GCA

IADR

F2

MC

-16

L b

us

Enable I2C

Clock division 1 Machine clock

Clock selection 1

Clock division 2

Generate shift clock

Clock selection 2Shift clock

edge change timing

Bus busy

Repeated start

Send/receive

Detect start/stop condition

Error

Detect arbitration loss

Request interrupt

StartTerminate

Master

Allow ACK

Allow GC-ACK

Detect start/stop condition

Slave

Global call Compare slave address

347


21.3 I2C Interface Registers

The I2C interface has the following five types of registers:• Bus status register• Bus control register• Clock control register• Address register• Data register

I2C Interface Registers

Figure 21.3-1 I 2C Interface Registers

7 6 5 4 3 2 1 0

000080H BB RSC AL LRB TRX AAS GCA FBTIBSR

(R) (R) (R) (R) (R) (R) (R) (R)( 0) ( 0) ( 0) ( 0) ( 0) ( 0) ( 0) ( 0)

15 14 13 12 11 10 9 8

BER BEIE SCC MSS ACK GCAA INTE INT IBCR

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)( 0) ( 0) ( 0) ( 0) ( 0) ( 0) ( 0) ( 0)

000081H

7 6 5 4 3 2 1 0

EN CS4 CS3 CS2 CS1 CS0 ICCR

(-) (-) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)(-) (-) ( 0) (X) (X) (X) (X) (X)

000082H

15 14 13 12 11 10 9 8

A6 A5 A4 A3 A2 A1 A0 IADR

(-) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)(-) (X) (X) (X) (X) (X) (X) (X)

000083H

7 6 5 4 3 2 1 0

D7 D6 D5 D4 D3 D2 D1 D0 IDAR


000084H

Bus status registerBit No.

Bit No.

Bit No.

Bit No.

Bit No.

Address:

Address:

Address:

Address:

Address:






Bus control register

Clock control register

Address register

Data register

348


21.3.1 Bus Status Register (IBSR)

The bus status register (IBSR) has the following functions:• Repeated start condition detection• Arbitration lost detection• Acknowledge storage• First byte detection• Addressing detection• General call address detection• Data transfer

Bus Status Register (IBSR)

Figure 21.3-2 Bus Status Register (IBSR)

[Bit 7] BB (Bus Busy)

The BB bit indicates the status of the I2C bus.

[Bit 6] RSC (Repeated Start Condition)

The RSC bit is used to detect the repeated start condition. Setting the INT bit to 0 clears theRSC bit. Unless addressing is performed in slave mode, detecting the start or stop conditionwhen the bus is stopped also clears the RSC bit.

7 6 5 4 3 2 1 0

000080H BB RSC AL LRB TRX AAS GCA FBTIBSR

(R) (R) (R) (R) (R) (R) (R) (R)( 0) ( 0) ( 0) ( 0) ( 0) ( 0) ( 0) ( 0)

Bit No.

Address:


Bus status register

Table 21.3-1 BB (Bus Busy) Bit Functions

BB I2C bus status

0 The stop condition was detected [initial value].

1 The start condition was detected.

349


[Bit 5] AL (Arbitration Lost)

The AL bit is used to detect arbitration loss.

Setting the INT bit to 0 clears the AL bit.

[Bit 4] LRB (Last Received Bit)

The LRB bit is an acknowledge storage bit. The LRB bit is used to store anacknowledgement sent from the receiving side. Detecting a start or stop condition clears theLRB bit.

[Bit 3] TRX (Transfer/Receive)

The TRX bit indicates sending/receiving during data transfer.

[Bit 2] AAS (Addressed As Slave)

The AAS bit is used to detect addressing.

Detecting the start or stop condition clears the AAS bit.

Table 21.3-2 RSC (Repeated Start Condition) Bit Functions

RSC IStart condition detection status

0 The repeated start condition has not been detected [initial value].

1 The start condition was detected again during use of the bus.

Table 21.3-3 AL (Arbitration Lost) Bit Functions

AL Arbitration lost detection status

0 Arbitration loss has not been detected [initial value].

1 Arbitration loss occurred during master send. Alternatively, the MSS bit was set to 1 while another system was using the bus.

Table 21.3-4 TRX (Transfer/Receive) Bit Functions

TRX IData transfer send/receive status

0 Receive status [initial value].

1 Send status

Table 21.3-5 AAS (Addressed As Slave) Bit Functions

AAS Function

0 Not addressed as slave [initial value].

1 Addressed as slave

350


[Bit 1] GCA (General Call Address)

The GCA bit is used to detect general call addresses (00H). Detecting the start or stopcondition clears the GCA bit.

[Bit 0] FBT (First Byte Transfer)

The FBT bit is used to detect the first byte. Setting the INT bit to 0 or addressing in otherthan slave mode clears the FBT bit even if detection of the start condition has set the FBT bitto 1.

Table 21.3-6 GCA (General Call Address) Bit Functions

GCA Function

0 A general call address was not received in slave mode [initial value].

1 A general call address was received.

Table 21.3-7 FBT (First Byte Transfer) Bit Functions

FBT Function

0 The receive data was other than the first byte [initial value].

1 The receive data was the first byte (address data).

351


21.3.2 Bus Control Register (IBCR)

The bus control register (IBCR) has the following functions:• Interrupt request/interrupt allowed• Start condition generation• Master/slave selection• Acknowledge generation allowed

Bus Control Register (IBCR)

Figure 21.3-3 Bus Control Register (IBCR)

[Bit 15] BER (Bus ERror)

The BER bit is a bus error interrupt request flag. When this bit is set, the CCR register ENbit is cleared, the I2C interface is set to stopped status, and data transfer is terminated.

[Bit 14] BEIE (Bus Error Interrupt Enable)

The BEIE bit is used to allow bus error interrupts. When the BEIE bit is 1, an interrupt isgenerated if the BER bit is 1.

15 14 13 12 11 10 9 8

BER BEIE SCC MSS ACK GCAA INTE INT IBCR

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)( 0) ( 0) ( 0) ( 0) ( 0) ( 0) ( 0) ( 0)

000081H

Bit No.

Address:


Bus control register

Table 21.3-8 BER (Bus ERror) Bit Functions

BER Function

At writing 0 The bus error interrupt request flag is cleared [initial value].

1 No relationship

At reading 0 A bus error has not been detected [initial value].

1 An invalid start or stop condition was detected during data transfer.

Table 21.3-9 BEIE (Bus Error Interrupt Enable) Bit Functions

BEIE Function

0 Bus error interrupt prohibited [initial value].

1 Bus error interrupt allowed

352


[Bit 13] SCC (Start Condition Continue)

The SCC bit is used to generate the start condition. Reading the SCC bit always returns 0.

[Bit 12] MSS (Master Slave Select)

The MSS bit is used to select the master/slave. The MSS bit is cleared when arbitration lossoccurs during master transfer. Slave mode is then set.

[Bit 11] ACK (ACKnowledge)

The ACK bit is used to allow acknowledge to be generated when data is received. The ACKbit is invalid when address data is received in slave mode.

[Bit 10] GCAA (General Call Address Acknowledge)

The GCAA bit is used to allow acknowledge to be generated when a general call address isreceived.

Table 21.3-10 SCC (Start Condition Continue) Bit Functions at Writing

SCC Function

0 No relationship [initial value].

1 At master transfer, the start condition is generated again and address data transfer is started.

Table 21.3-11 MSS (Master Slave Select) Bit Functions

MSS Function

0 The stop condition is generated and slave mode is set after transfer terminates [initial value].

1 Master mode is set, the start condition is generated, and address data transfer is started.

Table 21.3-12 ACK (ACKnowledge) Bit Functions

ACK Function

0 Acknowledge is not generated [initial value].

1 Acknowledge is generated.

Table 21.3-13 GCAA (General Call Address Acknowledge) Bit Functions

GCAA Function

0 Acknowledge is not generated [initial value].

1 Acknowledge is generated.

353



The INTE bit is used to allow interrupts. When the INTE bit is 1, an interrupt is generated ifthe INT bit is 1.

[Bit 8] INT (INTerrupt)

The INT bit is a flag used to request an interrupt after transfer terminates. When the INT bitis 1, the SCL line is maintained low. Writing 0 clears this bit, releases the SCL line, andtransfers the next byte. In addition, detecting the start or stop condition in master moderesets the INT bit to 0.

Notes on SCC, MSS, and INT Bit Conflicts

Writing the SCC, MSS, and INT bits at the same time can cause conflicts between transferringthe next bye, generating the start condition, and generating the stop condition. The order ofpriority at this time is as follows:

• Making the next byte transfer and generating the stop condition

When setting either the INT or the MSS bit to 0, setting the MSS bit to 0 has priority. Thiswill generate a stop condition.

• Making the next byte transfer and generating the start condition

When setting the INT to 0 and the SCC bit to 1, setting the SCC bit to 1 has priority. A startcondition will be generated.

• Generating the start condition and generating the stop condition

Setting the SCC bit to 1 and the MSS bit to 0 at the same time is prohibited.

Table 21.3-14 INTE (INTerrupt Enable) Bit Functions

INTE Function


1 Interrupt allowed

Table 21.3-15 INT (INTerrupt) Bit Functionsns

INT Function

At writing 0 The flag requesting an interrupt after transfer terminates is cleared [initial value].

1 No relationship

At reading 0 Transfer has not ended [initial value].

1 This is set if the following conditions apply when transfer of one byte including the acknowledge bit has ended:• Bus master• Addressed as slave• A general call address was received.• Arbitration loss occurred.• An attempt was made to generate a start condition when another

system was using the bus.

354


21.3.3 Clock Control Register (ICCR)

The clock control register (ICCR) has the following functions:

• I2C interface operation enable• Serial clock frequency setting

Clock Control Register (ICCR)

Figure 21.3-4 Clock Control Register (ICCR)

[Bits 7 and 6] Unused bits

[Bit 5] EN (ENable)

The EN bit enables I2C interface operation. When the EN bit is 0, each bit of the BSRregister and BCR register (except for the BER and BEIE bits) is cleared. The EN bit iscleared when the BER bit is set.

[Bits 4 to 0] CS4 to CS0 (Clock Period Select 4 to 0)

These bits are used to set the frequency of the serial clock.

The frequency fsck of the shift clock is set based on the following expression:

7 6 5 4 3 2 1 0

EN CS4 CS3 CS2 CS1 CS0 ICCR

(-) (-) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)(-) (-) ( 0) (X) (X) (X) (X) (X)

000082H

Bit No.

Address:


Clock control register

Table 21.3-16 EN (ENable) Bit Functions

EN Operating status

0 Operation prohibited [initial value].

1 Operation allowed

fsck =m x n + 4

: Machine clock frequency

355


For example, selecting m = 5 and n = 32 when φ = 16 MHz sets a serial clock frequency of97.561 KHz.

Note:

+4 cycles is the minimum overhead for checking a change in the output level of the SCL pin.If the delay in the rising of the SCL pin is large or the slave device has prolonged the clock,the overhead will be greater than this value.

Table 21.3-17 Serial Clock Frequency Setting (CS4 and CS3)

m CS4 CS3

5 0 0

6 0 1

7 1 0

8 1 1

Table 21.3-18 Serial Clock Frequency Setting (CS2 to CS0)

n CS2 CS1 CS0

4 0 0 0

8 0 0 1

16 0 1 0

32 0 1 1

64 1 0 0

128 1 0 1

256 1 1 0

512 1 1 1

356


21.3.4 Address Register (IADR)

The address register (IADR) is used to specify the slave address.

Address Register (IADR)

Figure 21.3-5 Address Register (IADR)

[Bits 14 to 8] A6 to A0 (Slave Address Bits)

The bits A6 to A0 form a register used to specify the slave address. In slave mode, thisregister is compared with the DAR register after address data is received. If the registercontents match, acknowledge is sent to the master.

15 14 13 12 11 10 9 8

A6 A5 A4 A3 A2 A1 A0 IADR

(-) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)(-) (X) (X) (X) (X) (X) (X) (X)

000083H

Bit No.

Address:


Address register

357


21.3.5 Data Register (IDAR)

The data register (IDAR) is used for serial transfer.

Data Register (IDAR)

Figure 21.3-6 Data register (IDAR)

[Bits 7 to 0] D7 to D0 (data bits)

The bits D7 to D0 (data bits) form a data register used for serial transfer. Data is transferredstarting from the MSB. When data is received (TRX = 0), the data output value is set to 1.

At writing, this register acts as a double buffer. If the bus is being used (BB = 1), the writedata is loaded into the serial transfer register when each byte is transferred. At reading, theserial transfer register is read directly. Therefore, the receive data is valid only when the INTbit has been set.

7 6 5 4 3 2 1 0

D7 D6 D5 D4 D3 D2 D1 D0 IDAR


000084H

Bit No.

Address:


Data register

358

21.4 I2C Interface Operation


The I2C bus executes communication using two two-way bus lines consisting of one

serial data line (SDA) and one serial clock line (SCL). For these bus lines, the I 2C interface has two open-drain I/O pins (SDA and SCL) that enable using wired logic.

Start Condition

Setting the MSS bit to 1 while the bus is open (BB = 0 and MSS = 0) sets the I2C interface tomaster mode and generates at the same time the start condition. In master mode, the SCC bitcan be set to 1 to generate the start condition again even if the bus is busy (BB = 1).

There are two conditions for generating the start condition, as follows:

1. The MSS bit can only be set to 1 while the bus is not busy (MSS = 0, BB = 0, INT = 0, andAL = 0).

2. The SCC bit can only be set to 1 in bus master interrupt status (MSS = 1, BB = 1, INT = 1,and AL = 0).

Setting the MSS bit to 1 while another system (in idle status) is using the bus sets the AL bit to1. Setting the MSS and SCC bits to 1 under conditions other than conditions 1) and 2) above isignored.

Stop Condition

Setting the MSS bit to 0 in master mode (MSS = 1) generates the stop condition and sets slavemode.

The condition for generating the stop condition is as follows:

• The MSS bit can only be set to 0 in bus master interrupt status (MSS = 1, BB = 1, INT = 1,and AL = 0).

Setting the MSS bit to 0 under conditions other than the above is ignored.

Addressing

In master mode, the BB and TRX bits are set to 1 and the IDAR register contents are outputstarting from the MSB after the start condition is generated. Upon receiving acknowledge fromthe slave after the address data is sent, bit 0 of the send data (bit 0 of the IDAR register aftersending) is inverted and the result of the inversion stored in the TRX bit.

In slave mode, the BB bit is set to 1, the TRX bit is set to 0, and the send data from the masteris received in the IDAR register after the start condition is generated. After the address data isreceived, the IDAR and IADR registers are compared. If the contents of the registers match, theAAS bit is set to 1 and acknowledge is sent to the master. Finally, the value of bit 0 of thereceive data (bit 0 of the IDAR register after receiving) is stored in the TRX bit.

Arbitration

Arbitration occurs if at least two masters are sending data at the same time. If one’s own senddata is 1 and the data on the SDA line is low, loss of arbitration is detected and the AL bit is setto 1. Moreover, if the bus is busy as previously described, the AL bit will be set to 1 if anattempt is made to generate the start condition.

When the AL bit is set to 1, the MSS and TRX bits are set to 0 and slave receive mode is set.

359


Acknowledge

The receiving side sends an acknowledge signal to the sending side. The ACK bit can be usedto select whether to acknowledge when data is received. When data is sent, acknowledgementfrom the receiving side is stored in the LRB bit.

If no acknowledge signal is received from the master receiving side when a slave sends data,the TRX bit is set to 0 and slave receive mode is set. As a result, the master can generate thestop condition when the slave releases the SCL line.

Bus Error

A bus error is assumed and the I2C is set to stopped status if the following conditions occur:

• A basic rule violation is detected on the I2C bus during data transfer.

• The stop condition is detected in master mode.

• A basic rule violation is detected on the I2C bus during bus idle status.

360


21.4.1 I2C Interface Transfer Flow

Figure 21.4-1 "Operational Flow of Transfer of One Byte from the Master to the Slave" shows the operational flow of transferring one byte from the master to the slave. Figure 21.4-2 "Operational Flow of Transfer of One Byte from the Slave to the Master" shows the operational flow of transferring one byte from the slave to the master.

I2C Interface Transfer Flow

Figure 21.4-1 Operational Flow of Transfer of One Byte from the Master to the Slave

Start

BB set, TRX set BB set, TRX set

AAS set

LBR reset

INT set, TRX set INT set, TRX set

LBR reset

INT set INT set

INT resetBB reset, TRX reset BB reset, TRX reset

AAS reset

end

Master Slave

DAR: WriteMSS: 1 write

Start condition

Transfer address data

Acknowledge

DAR: WriteINT: 0 write

Interrupt ACK: 1 writeINT: 0 write

Transfer data

Acknowledge

Interrupt DAR: ReadINT: 0 write

MSS: 0 write

Stop condition

361


Figure 21.4-2 Operational Flow of Transfer of One Byte from the Slave to the Master

Start

LBR set, TRX set

INT set INT set

INT resetBB reset, TRX reset BB reset, TRX reset

AAS reset

end

BB set, TRX set

LBR reset

INT set, TRX set

BB set, TRX set

AAS set

INT set, TRX set

Master Slave

DAR: WriteMSS: 1 write

Start condition

Transfer address data

Acknowledge

INT: 0 write Interrupt DAR: WriteINT: 0 write

Transfer data

Negative acknowledge

DAR: Read InterruptINT: 0 write

MSS: 0 write

Stop condition

362


21.4.2 I2C Interface Mode Transitions

Figure 21.4-3 "I 2C Interface Mode Transitions" shows the mode transitions of the I 2C interface.

I2C Interface Mode Transitions

Figure 21.4-3 I 2C Interface Mode Transitions

STCNO

YES

TRX,AAS,LRB:resetFBT:set

YESSTC&BB=1 RSC:set

NO

BB:set

RSC,FBT:reset

AAS:set

INT:set

NOTRX=1

YES YESSPC AAS,LRB,BB,RSC

:resetNO

INT: 0 write

FBT:reset

YES

NO

TRX:reset

Slave receive mode

Receive 8 bits

Compare addresses?

Match

Output confirmation response

Save to SCLline low

Slave receive mode

Slave send mode

Open SCL line

Send/receive

Confirmation response?

363


364

CHAPTER 22 DTMF GENERATOR

This chapter explains the functions and operation of the DTMF generator.

22.1 "Outline of the DTMF Generator"

22.2 "DTMF Generator Registers"

22.3 "DTMF Generator Operation"

365


22.1 Outline of the DTMF Generator

For the DTMF generator, the frequencies of the COL (high group) and ROW (low group) are selected based on the value set in the dial data. The combined frequency of the ROW and COL is then output from the DTMF pin.

DTMF Generator Features

The DTMF generator has the following features:

• DTMF continuous sending enabled (single tone also enabled)

• CCITT total tone output enabled for dial numbers 0 to 9, *, #, and A to D

Block Diagram of the DTMF Generator

Figure 22.1-1 Block Diagram of the DTMF Generator

DTMF

Division circuit

Clock

Select frequency

COL step wave generation circuit

ROW step wave generation circuit

Voltage dataadder

ROW/COL decoder Select

frequency

Presetcounter

Count clock

Terminate

Internal clock

Control signal generation section

Divisioncircuit

Select frequency

Dial data

DTMF data register DTMD

DTMF control registerDTMC

Internal bus

366

22.2 DTMF Generator Registers


Figure 22.2-1 "DTMF Generator Registers" shows the DTMF generator registers.

DTMF Generator Registers

Figure 22.2-1 DTMF Generator Registers

000088HDTMC

000089n DTMD

TEST0 CSL2 CSL1 CSL0 CDIS RDIS OUTE TEST1

7 6 5 4 3 2 1 0

(R/W) (R/W) (R/W) (R/W)(0) (0) (0) (0) (0) (0)

(R/W)(0)(0)

(R/W) (R/W) (R/W)

TEST2 TEST1 TEST0 DDAT3 DDAT2 DDAT1DDAT0

7 6 5 4 3 2 1 0

(-) (R/W) (R/W) (R/W)(0) (0) (X) (0) (0) (0)

(R/W)(0)(0)

(R/W) (R/W) (R/W)

DTMF control register (DTMC)

DTMF data register (DTMD)

Bit No.

Bit No.

Address:

Address:



367


22.2.1 DTMF Control Register (DTMC)

The DTMF control register (DTMC) selects the machine clock, allows or prohibits high-group/low-group tone generation, and controls output of the DTMF signal.

DTMF Control Register (DTMC)

Figure 22.2-2 DTMF Control Register (DTMC)

[Bit 7] TEST0

The TEST0 bit is used for testing. During write operations, write 0.

[Bits 6, 5, and 4] CSL2, CSL1, and CSL0

These bits are used to select the machine clock. Set these bits based on the frequency tobe used. When selecting bits for other than this clock, an accurate DTMF signal cannot beoutput. In addition, do not switch the machine clock during operation.

000088HTEST0 CSL2 CSL1 CSL0 CDIS RDIS OUTE TEST1

7 6 5 4 3 2 1 0

(R/W) (R/W) (R/W) (R/W)(0) (0) (0) (0) (0) (0)

(R/W)(0)(0)

(R/W) (R/W) (R/W)

Address:


DTMF control register (DTMC)

Table 22.2-1 Machine Clock Selection Bits

Machine clock CSL2 CSL1 CSL0

2 MHz 0 0 0

4 MHz 0 0 1

6 MHz 0 1 0

8 MHz 0 1 1

10 MHz 1 0 0

12 MHz 1 0 1

14 MHz 1 1 0

16 MHz 1 1 1

368


[Bit 3] CDIS

The CDIS bit is used to prohibit high-group tone generation.

[Bit 2] RDIS

The RDIS bit is used to prohibit low-group tone generation.

[Bit 1] OUTE

The OUTE bit is used to control output of the DTMF signal.

[Bit 0] TEST1

The TEST1 bit is used for testing. During write operations, write 0.

Table 22.2-2 CDIS Bit Functions

CDIS Function

0 High-group tone generation is allowed.

1 High-group tone generation is prohibited.

Table 22.2-3 RDIS Bit Functions

RDIS Function

0 Low-group tone generation is allowed.

1 Low-group tone generation is prohibited.

Table 22.2-4 OUTE Bit Functions

OUTE Function

0 DTMF signal output is allowed.

1 DTMF signal output is prohibited.

369


22.2.2 DTMF Data Register (DTMD)

The DTMF data register (DTMD) sets the dial data.

DTMF Data Register (DTMD)

Figure 22.2-3 DTMF Data Register (DTMD)

[Bits 5, 6, and 7] TEST0, TEST1, and TEST2

These bits are used for testing. During writing operations, write 0.

[Bits 2, 1, and 0] DDAT3 to DDAT0

These bits are used to set the dial data.

000089H000X 0000BTEST2 TEST1 TEST0 DDAT3 DDAT2 DDAT1 DDAT0

7 6 5 4 3 2 1 0

(R/W)(0)

(R/W)(0)

(R/W)(0)

(R/W)(0)

(-)(X)

(R/W)(0)

(R/W)(0)

(R/W)(0)

DTMF data register (DTMD)Initial value

Initial value

Address:

Read/write

370

22.3 DTMF Generator Operation

22.3 DTMF Generator Operation

The frequencies of the COL (high group) and ROW (low group) are selected based on the value set in the dial data. The combined frequency of the ROW and COL is then output from the DTMF pin. The software uses the OUTE bit to control the output timing of the DTMF signal.

DTMF Generator Operation

DTMF signal output

When the OUTE bit of the DTMF register is 1, the DTMF signal is output. When the OUTE bit is0, the DTMF signal is not output. Table 22.3-1 "Relationship between the Setting Values of theDial Data (DDA3 to DDA0) and Output Signals" lists the relationship between the ROW, COL,and values set for the dial data. Table 22.3-2 "DTMF Output Frequencies" lists the DTMFoutput frequencies.

Single tone output

When the RDIS bit of the DTMF control register is 1, only the single tone of the low group isoutput. The high group is prohibited. When the CDIS bit is 1, only the single tone of the highgroup is output. The low group is prohibited. When both bits are 1, the DTMF signal is notoutput.

Table 22.3-1 Relationship between the Setting Values of the Dial Data (DDA3 to DDA0) and Output Signals

Dial number Register value

DTMF

ROW COL

Frequency Frequency

1 1 1 697.35 1 1207.3

2 2 1 697.35 2 1336.90

3 3 1 697.35 3 1474.93

4 4 2 769.82 1 1207.3

5 5 2 769.82 2 1336.90

6 6 2 769.82 3 1474.93

7 7 3 851.79 1 1207.3

8 8 3 851.79 2 1336.90

9 9 3 851.79 3 1474.93

0 A 4 940.73 2 1336.90

* B 4 940.73 1 1207.3

# C 4 940.73 3 1474.93

371


A D 1 697.35 4 1633.99

B E 2 769.82 4 1633.99

C F 3 851.79 4 1633.99

D 0 4 940.73 4 1633.99

Table 22.3-2 DTMF Output Frequencies

Reference frequency

(CCITT recommended)

DTMF output

Output frequency

Frequency deviation

ROW1 697 Hz 69.35 Hz 0.050%

ROW2 770 Hz 77.17 Hz -0.022%

ROW3 852 Hz 85.79 Hz -0.024%

ROW4 941 Hz 94.73 Hz -0.028%

COL1 1209 Hz 120.73 Hz -0.105%

COL2 1336 Hz 133.90 Hz 0.067%

COL3 1477 Hz 147.93 Hz -0.140%

COL4 1633 Hz 163.99 Hz 0.060%

Table 22.3-1 Relationship between the Setting Values of the Dial Data (DDA3 to DDA0) and Output Signals

Dial number Register value

DTMF

ROW COL

Frequency Frequency

372

CHAPTER 23 CLOCK MONITOR FUNCTION

This chapter explains the functions and operation of the clock monitor.

23.1 "Outline of the Clock Monitor Function"

23.2 "Clock Output Allowed Register (CLKR)"

373


23.1 Outline of the Clock Monitor Function

The clock monitor function outputs the division clock (clock for the monitor) of the machine clock from the CKOT pin.

Block Diagram of the Clock Monitor Function

Figure 23.1-1 Block Diagram of the Clock Monitor Function

CKEN

FRQ2

FRQ1

FRQ0 P65/CKOT

Inte

rnal

dat

a bu

s

Divisioncircuit

Machine clock ( )

374

23.2 Clock Output Allowed Register (CLKR)

23.2 Clock Output Allowed Register (CLKR)

The clock output allowed register (CLKR) is used to enable CKOT output and select the clock output frequency.

Clock Output Allowed Register (CLKR)

Figure 23.2-1 Clock Output Allowed Register (CLKR)

[Bits 7, 6, and 5] Unused bits

[Bit 3] CKEN

The CKEN bit is used to enable CKOT output.

[Bits 2, 1, and 0] FRQ2, FRQ1, and FRQ0

These bits are used to select the clock output frequency.

7 6 5 4 3 2 1 0

0003EH CKEN FRQ2 FRQ1 FRQ0 CLKR

(-) (-) (-) (-) (R/W) (R/W) (R/W) (R/W)(-) (-) (-) (-) (0) (0) (0) (0)Initial value

Address:

Read/write

Clock output allowed registerBit No.

Table 23.2-1 CKEN Bit Functions

CKEN Function

0 Regular port

1 CKOT output

Table 23.2-2 FRQ2, FRQ1, and FRQ0 (Clock Output Frequency Select) Bit Functions

FRQ2 FRQ1 FRQ0 Output clock φφφφ=16MHz φφφφ=8MHz φφφφ=4MHz

0 0 0 21/φ 125 ns 250 ns 500 ns

0 0 1 21/φ 250 ns 500 ns 1 µ

0 1 0 23/φ 500 ns 1 µ 2 µ

0 1 1 24/φ 1 µs 2µ 4 µ

1 0 0 25/φ 2µs 4 µ 8 µ

1 0 1 26/φ 4 µs 8 µ 16 µ

1 1 0 27/φ 8 µs 16 µ 32 µ

1 1 1 28/φ 16 µs 32 µ 64 µ

375


376

CHAPTER 24 2M-BIT FLASH MEMORY

This chapter explains the functions and operation of the 2M-bit flash memory.The following three methods are available for writing data to, and erasing data from the flash memory:1. Executing a program to write and erase data2. Using a serial dedicated programmer (AF200, manufactured by Yokogawa Digital

Computer)3. Using a parallel programmer (MODEL 1890A, manufactured by Minato Electronics)This chapter explains method 1, "Executing a program to write and erase data."

24.1 "Outline of the 2M-Bit Flash Memory"

24.2 "Sector Configuration of the 2M-Bit Flash Memory"

24.3 "Flash Memory Control Status Register (FMCS)"

24.4 "Activating the Flash Memory Automatic Algorithm"

24.5 "Confirming the Automatic Algorithm Execution Status"

24.6 "Detailed Explanation of Flash Memory Write/Erase"

24.7 "Flash Memory Program Example"

377


24.1 Outline of the 2M-Bit Flash Memory

The 2M-bit flash memory is mapped to banks FC to FF on the CPU memory map. The function of the flash memory interface circuit enables read and program access from the CPU in the same way as with the mask ROM. Data can be written to and erased from the flash memory by using instructions from the CPU, and by access through the flash memory interface circuit. Accordingly, the flash memory can be rewritten while it is mounted using internal CPU control. Data and programs can thus be used more efficiently.However, such operations as "enable sector protect" cannot be used for the 2M-bit flash memory.

Features of the 2M-Bit Flash Memory

• 256K words x 8/128K words x 16 bit (16K + 8K + 8K + 32K + 64K + 64K + 64K) sectorconfiguration

• Automatic program algorithm (similar to Embedded Algorithm: MBM29F400TA)

• Erase temporary stop and erase restart functions

• Complete detection of writing and erasure using data polling and toggle bits

• Complete detection of writing and erasure using CPU interrupts

• Compatibility with JEDEC standard commands

• Erasure of individual sectors enabled (Sectors can be combined freely.)

• Write/erase count (minimum) 10,000 times

Embedded Algorithm is a trademark of Advanced Micro Device.

Flash Memory Writing and Erasure Methods

The flash memory cannot be written to and read at the same time. That is, when writing data to,or erasing data from the flash memory, copy the program in the flash memory to RAM andexecute it in RAM. This enables writing without accessing the program in the flash memory.

Flash Memory Register

Flash memory control status register (FMCS)

0000AEHFMCSINTE RDYINT WE RDY LPM1 LPM0

7 6 5 4 3 2 1 0

(R/W)(0)

(W)(0)

(R/W)(0)

(W)(0)

(R/W)(X)

(R/W)(0)

(R/W)(0)

(R/W)(0)

Flash memory control status register (FMCS)

Bit No.Address:


Reserved Reserved

378

24.2 Sector Configuration of the 2M-Bit Flash Memory

24.2 Sector Configuration of the 2M-Bit Flash Memory

Figure 24.2-1 "Sector Configuration of the 2M-Bit Flash Memory" shows the sector configuration of the 2M-bit flash memory. The addresses in the figure indicate the high-order and low-order addresses of each sector.

Sector Configuration

At access from the CPU, SA0 is mapped in the FC bank register, SA1 in the FD bank register,SA2 in the FE bank register, and SA3 to SA6 in the FF bank register.

Figure 24.2-1 Sector Configuration of the 2M-Bit Flash Memory

FFFFFFh 7FFFFh

FFC000h 7C000hFFBFFFh 7BFFFh

FFA000h 7A000hFF9FFFh

FF8000h77FFFh

FF0000h 70000hFEFFFFh 6FFFFh

FE0000h 60000hFDFFFFh 5FFFFh

FD0000h 50000hFCFFFFh 4FFFFh

FC0000h 40000h

Flash memory CPU address Writer address *1

SA6 (16 KB)

SA5 (8 KB)

SA4 (8 KB)

SA3 (32 KB)

SA2 (64 KB)

SA1 (64 KB)

SA0 (64 KB)

*1: The writer address means the address corresponding to the CPU address when a parallel writer is used to write data to the flash memory. When a general-purpose writer is used to write and erase data, this address is used for writing and erasing.

379


24.3 Flash Memory Control Status Register (FMCS)

The flash memory control status register (FMCS) is a register of the flash memory interface circuit. This register is used to write data to, and erase data from the flash memory.

Flash Memory Control Status Register (FMCS)


The INTE bit is used to generate an interrupt to the CPU when flash memory write or eraseis completed.

An interrupt to the CPU is generated when the INTE and RDYINT bits are 1. An interrupt isnot generated if the INTE bit is 0.

[Bit 6] RDYINT (ReaDY INTerrupt)

The RDYINT bit indicates the operating status of the flash memory.

When flash memory write or erase completes, the RDYINT bit is set to 1. Data cannot bewritten to or erased from the flash memory while this bit is 0 after flash memory write orerase. Data can be written to or erased from the flash memory after flash memory write orerase completes and this bit is set to 1.

Writing 0 clears the RDYINT bit to 0. Writing 1 is ignored. The RDYINT bit is set to 1 at theend of the flash memory automatic algorithm (see Section 24.4 "Activating the Flash MemoryAutomatic Algorithm"). Reading with a read-modify-write (RMW) instruction always returns1.

[Bit 5] WE (Write Enable)

The WE bit is used to enable writing to the flash memory area.

When the WE bit is 1, a write operation after a command sequence (see Section 24.4

0000AEHFMCSINTE DRYINT WE RDY LPM1 LPM0

7 6 5 4 3 2 1 0

(R/W)(0)

(W)(0)

(R/W)(0)

(W)(0)

(R/W)(X)

(R/W)(0)

(R/W)(0)

(R/W)(0)

Flash memory control status register (FMCS)Bit No.

Address:


Reserved Reserved

0 Interrupt at completion of write/erase is allowed.

1 Interrupt at completion of write/erase is prohibited.

0 Write/erase is being executed.

1 Write/erase is completed (an interrupt request is generated).

380

24.3 Flash Memory Control Status Register (FMCS)

"Activating the Flash Memory Automatic Algorithm") is issued to the FC to FF banksbecomes a write operation to the flash memory area. When the WE bit is 0, write/erasesignals are not generated. The WE bit is used when activating the flash memory write/erasecommands.

If writing or erasure is not executed, we recommend setting the WE bit to 0 to prevent datafrom being written to the flash memory by mistake.

[Bit 4] RDY (ReaDY)

The RDY bit is used to enable flash memory write/erase.

Data cannot be written to or erased from the flash memory while the RDY bit is 0. However,read and reset commands or suspend commands such as the sector erase temporary stopcommand can be accepted even while the RDY bit is 0.


Always set this bit to 0 at normal usage.

[Bit 1] Empty bit

Always set this bit to 0 at normal usage.

[Bits 2 and 0] LPM1 and LPM0 (Low Power Mode)

The LPM1 and LPM0 bits are used to suppress the power consumption of the flash memory.When these bits are "00", the flash memory operates normally. When these bits are "01","10", or "11", the select signal to the flash memory at flash memory access is used tosuppress the overall power consumption of the flash memory. However, because accesstime becomes significantly larger compared to when the LPM bits are "00", memory accessat high-speed operation of the CPU will be disabled. When using low power mode, run theCPU using the corresponding frequency of 4 MHz, 8 MHz, or 10 MHz.

Always use normal power mode when operating at a frequency greater than 10 MHz.

Note:

The RDYINT and RDY bits do not change at the same time. Ensure at program creation thatonly one of the bits is used for determining the operating status.

0 Flash memory write/erase is prohibited.

1 Flash memory write/erase is allowed.

0 Write/erase is being executed.

1 Write/erase has completed (next data write/erase operation is enabled).

00 Normal power mode

01 Low power mode (operating at internal operation frequency of 4 MHz or less)



381


Timing for end of automatic algorithmRDYINT bitRDY bit

1 machine cycle

382

24.4 Activating the Flash Memory Automatic Algorithm

24.4 Activating the Flash Memory Automatic Algorithm

Four types of command are available for activating the flash memory automatic algorithm: Read/reset (two types), write, and chip erase. For sector erase, temporary stop and restart can be controlled.

Command Sequence Table

Table 24.4-1 "Command Sequence Table" lists the commands that can be used for writing datato, and erasing data from the flash memory. Data is always written to the command register inmultiples of bytes. However, use word access in write operations; the data of the high-orderbyte will be ignored.

Table 24.4-1 Command Sequence Table

Command sequence

Bus write cycle

1st bus write cycle 2nd bus write cycle 3rd bus write cycle 4th bus write cycle 5th bus write cycle

6th bus write cycle

Address Data Add-ress

Data Add-ress

Data Add-ress

Data Add-ress

Data Add-ress

Data

Read/reset *1 1 FxXXXX XXF0 - - - - - - - - - -

Read/reset *1 4 FxAAAA XXAA Fx5554 XX55 FxAAAA XXF0 RA RD - - - -

Interrupt program

4 FxAAAA XXAA Fx5554 XX55 FxAAAA XXA0 PA(even)

PD(word)

- - - -

Chip erase 6 FxAAAA XXAA Fx5554 XX55 FxAAAA XX80 FxAAAA XXAA Fx5554 XX55 FxAAAA XX10

Sector erase 6 FxAAAA XXAA Fx5554 XX55 FxAAAA XX80 FxAAAA XXAA Fx5554 XX55 SA(even)

XX30

Sector erase temporary stop Stop erase temporarily during sector erase at input of Address FxXXXX Data (xxB0H).

Sector erase and restart Restart erase after sector erase temporary stop at input of Address FxXXXX Data (xx30H).

Note: The addresses Fx in the table refer to addresses FF, FE, FD, and FC. Set the value of the access target bank for each operation.The addresses in the table refer to values in the CPU memory map. All addresses and data are represented using hexadecimal notation. The letter X stands for an arbitrary value.RA: Read addressPA: Write address. Only an even-numbered address can be specified.SA: Sector address. See Section 24.2, "Sector Configuration of the 2M-Bit Flash Memory."RD: Read dataPD: Write data. Only word data can be specified.*1: Both types of read/reset command can reset the flash memory to read mode.

383


24.5 Confirming the Automatic Algorithm Execution Status

Because the sequence of write/erase operations is implemented using the automatic algorithm, the flash memory has hardware to indicate the operating status in the flash memory and whether operation has been completed. The automatic algorithm can confirm the operating status of the built-in flash memory using the hardware sequence described below.

Hardware Sequence Flags

The hardware sequence flags consist of the four bits DQ7, DQ6, DQ5, and DQ3. Each bit has adedicated function. The DQ7 bit is a data polling flag. The DQ6 bit is a toggle bit flag. TheDQ5 bit is a timing limit exceeded flag. The DQ3 bit is a sector erase timer flag. These bits canbe used to determine whether write, chip/sector erase and termination, and erase code write areenabled.

To access the hardware sequence flag, enter the command sequence (see Table 24.4-1"Command Sequence Table" in Section 24.4 "Activating the Flash Memory AutomaticAlgorithm") and then read the address of the target sector in the flash memory.

Table 24.5-1 "Bit Assignments of the Hardware Sequence Flags" lists the bit assignments of thehardware sequence flags.

To determine whether automatic write or chip/sector erase is being executed, check thehardware sequence flags or check the RDY bit of the flash memory control register (FMCS).This allows to check whether writing has completed. After write/erase has completed, the statusreturns to read/reset status. When creating a program, use one of the flags to determinewhether automatic write/erase has completed and then execute the next operation, such asdata reading. In addition, the hardware sequence flags can also be used to determine whethersubsequent sector erase code write operations are enabled. Table 24.5-2 "Hardware SequenceFlag Functions" lists the hardware sequence flag functions.

Table 24.5-1 Bit Assignments of the Hardware Sequence Flags

Bit No. 7 6 5 4 3 2 1 0

Hardware sequence flag DQ7 DQ6 DQ5 - DQ3 - - -

384


The next subsections explain the individual hardware sequence flags.

Table 24.5-2 Hardware Sequence Flag Functions

Status DQ7 DQ6 DQ5 DQ3

Status transition in normal operation

Write --> Write completion (write address specified)

DQ7 --> DATA:7

Toggle --> DATA:6

0 --> DATA:5

0 --> DATA:3

Chip/sector erase --> Erase completion

0 --> 1 Toggle --> Stop

0 --> 1 1

Sector erase wait --> Erase start 0 Toggle 0 0 --> 1

Erase --> Sector erase temporary stop (sector being erased)

0 --> 1 Toggle --> 1

0 1 --> 0

Sector erase temporary stop --> Erase restart (sector being erased)

1 --> 0 1 --> Toggle

0 0 --> 1

Sector erase temporary stop (sector not being erased)

DATA:7 DATA:6 DATA:5 DATA:3

Abnormal operation

Write DQ7 Toggle 1 0

Chip/sector erase 0 Toggle 1 1

385


24.5.1 Data Polling Flag (DQ7)

The data polling flag is used by a data polling function to determine whether the automatic algorithm is being executed or has ended.

Write Operations

When a read access is made while the automatic algorithm is being executed, the flash memoryoutputs the inverse of bit 7 for the data item written last regardless of the specified address.When a read access is made after the automatic algorithm has ended, the flash memoryoutputs bit 7 of the value at the specified address.

Chip/Sector Erase Operations

When a read access is made while the chip erase/sector erase algorithm is being executed, theflash memory outputs 0 for the sector currently being erased when sector erase has beenexecuted. When chip erase has been executed, the flash memory outputs 0 regardless of thespecified address. When the erase algorithm has ended, the flash memory outputs 1 in thesame way as above.

Sector Erase Temporary Stop Operations

When a read access is made while sector erase is stopped temporarily, the flash memoryoutputs 1 if the specified address refers to the sector being erased. If the specified addressdoes not refer to the sector being erased, the flash memory outputs bit 7 (DATA:7) of the valueat the specified address. The toggle bit flag (DQ6) can also be accessed at the same time todetermine whether erasing the current sector has stopped temporarily or which sector is beingerased.

Data Polling Flag Status Transitions

Table 24.5-3 "Data Polling Flag Status Transitions in Normal Operation" and Table 24.5-4 "DataPolling Flag status Transitions in Abnormal Operation" list the status transitions of the datapolling flag.

Table 24.5-3 Data Polling Flag Status Transitions in Normal Operation

Operating status

Write --> Completion

Chip/sector erase -->

Completion

Sector erase wait --> Start

Sector erase -->

Erase temporary

stop (sector being

erased)

Sector erase

temporary stop --> Restart (sector being

erased)

Sector erase

temporary stop (sector

not being erased)

DQ7 DQ7 --> DATA:7 0 --> 1 0 0 --> 1 1 --> 0 DATA:7

Table 24.5-4 Data Polling Flag status Transitions in Abnormal Operation

Operating status

Write Chip/sector erase

DQ7 DQ7 0

386


Note:

When the automatic algorithm is activated, attempts of read access to the specified addressare ignored. During data reading, end of operations as indicated by the data polling flag(DQ7) enables the other bits to be output. Therefore, to read data after the automaticalgorithm has ended, execute a read operation to determine whether data polling has ended,and then read the data.

387


24.5.2 Toggle Bit Flag (DQ6)

In the same way as the data polling flag, the toggle bit flag is used by a toggle bit function to indicate whether the automatic algorithm is being executed or has ended.

Write and Chip/Sector Erase Operations

When consecutive read access operations are executed during execution of the automatic writealgorithm or chip/sector erase algorithm, the flash memory outputs the toggle status, i.e.,outputs 1 and 0 alternately at each read operation regardless of the specified address. Whenconsecutive read access operations are executed after the automatic write algorithm or chip/sector erase algorithm has terminated, the flash memory stops the toggle operation of bit 6 andoutputs bit 6 (DATA:6) of the value read at the specified address.

Sector Erase Temporary Stop Operations

When a read access operation is executed while sector erase is stopped temporarily, the flashmemory outputs 1 if the specified address belongs to the sector being erased. If the specifiedaddress does not belong to the sector being erased, the flash memory outputs bit 6 (DATA:6) ofthe value read at the specified address.

Remark

If an attempt is made to write to a sector that is write-protected, the toggle operation willcontinue for approximately 2 µs and then end without the data being rewritten.

If all of the selected sectors are write-protected at erase, the toggle operation will continuefor approximately 100 µs. The toggle bit will then be set to read/reset status without the databeing rewritten.

Toggle Bit Flag Status Transition

Table 24.5-5 "Toggle Bit Flag Status Transitions in Normal Operation" and Table 24.5-6 "ToggleBit Flag Status Transitions in Abnormal Operation" list the status transitions of the toggle bit flag.

Table 24.5-5 Toggle Bit Flag Status Transitions in Normal Operation

Operating status



Completion


Sector erase -->

Erase temporary

stop (sector being

erased)

Sector erase


erased)

Sector erase


not being erased)

DQ6 Toggle --> DATA:6

Toggle --> Stop

Toggle Toggle --> 1 1 --> Toggle DATA:6

Table 24.5-6 Toggle Bit Flag Status Transitions in Abnormal Operation

Operating status


DQ6 Toggle Toggle

388


24.5.3 Timing Limit Exceeded Flag (DQ5)

The timing limit exceeded flag indicates whether execution of the automatic algorithm has exceeded the time (internal pulse count) prescribed in flash memory.

Write and Chip/Sector Erase Operations

When a read access operation is executed after the write or chip/sector erase automaticalgorithm has been activated, 0 is returned if execution was within the prescribed time (timerequired for write/erase). If execution exceeded the prescribed time, 1 is returned. Becausethis is not related to whether the automatic algorithm is being executed or has ended, this flagcan be used to determine whether write/erase succeeded or failed: When this flag is 1, thisindicates that writing has failed if the data polling function or toggle bit function has not yetexecuted the automatic algorithm.

For example, a failure will occur if an attempt is made to write 1 to a flash memory address forwhich 0 has been written. In this case, the flash memory is locked and the automatic algorithmdoes not end. As a result, the data polling flag (DQ7) does not return a valid result. In addition,the toggle operation of the toggle bit flag (DQ6) does not stop, the timing limit will be exceeded,and the timing limit exceeded flag (DQ5) becomes 1. This status indicates that the flashmemory was not used correctly. It does not mean that the flash memory is faulty. When thisstatus occurs, execute the reset command.

Timing Limit Exceeded Flag Status Transition

Table 24.5-7 "Timing Limit Exceeded Flag Status Transitions in Normal Operation" and Table24.5-8 "Timing Limit Exceeded Flag Status Transitions in Abnormal Operation" list the statustransitions of the timing limit exceeded flag.

Table 24.5-7 Timing Limit Exceeded Flag Status Transitions in Normal Operation

Operating status



Completion


Sector erase -->

Erase temporary

stop (sector being

erased)

Sector erase


erased)

Sector erase


not being erased)

DQ5 0 --> DATA:5 0 --> 1 0 0 0 DATA:5

Table 24.5-8 Timing Limit Exceeded Flag Status Transitions in Abnormal Operation

Operating status


DQ5 1 1

389


24.5.4 Sector Erase Timer Flag (DQ3)

The sector erase timer flag indicates whether the system is waiting for sector erase after the sector erase command has been activated.

Sector Erase Operations

When a read access operation is executed after the sector erase command has been activated,the flash memory outputs 0 if the system is waiting for sector erase regardless of the addressindicated by the address signal of the sector that issued the command. The flash memoryoutputs 1 if the time for waiting for sector erase has been exceeded.

If this flag is 1 when the data polling function or toggle bit function indicates that the erasealgorithm is being executed, erasing has been started under internal control. Writing of thesubsequent sector erase code or a command other than erase temporary stop will be ignoreduntil erase has been completed.

If this flag is 0, the flash memory will accept writing of the added sector erase code. To confirmthis, we recommend checking this flag prior to writing the subsequent sector erase code. If thisflag is 1 at the second status check, the added sector erase code may have not been accepted.

Sector Erase Operations

When a read access operation is executed during sector erase temporary stop, the flashmemory outputs 1 if the specified address belongs to the sector being erased. If the specifiedaddress does not belong to the sector being erased, the flash memory outputs bit 3 (DATA:3) ofthe value read at the specified address.

Sector Erase Timer Flag Status Transitions

Table 24.5-8 "Timing Limit Exceeded Flag Status Transitions in Abnormal Operation" and Table24.5-9 "Sector Erase Timer Flag Status Transitions in Normal Operation" list the statustransitions of the sector erase timer flag.

Table 24.5-9 Sector Erase Timer Flag Status Transitions in Normal Operation

Operating status



Completion


Sector erase -->

Erase temporary

stop (sector being

erased)

Sector erase


erased)

Sector erase


not being erased)

DQ3 0 --> DATA:3 1 0 --> 1 1 --> 0 0 --> 1 DATA:3

Table 24.5-10 Sector Erase Timer Flag Status Transitions in Abnormal Operation

Operating status


DQ3 0 1

390

24.6 Detailed Explanation of Flash Memory Write/Erase


This section describes the procedure for issuing a command for activating the automatic algorithm and executing each operation of flash memory read/reset, write, chip erase, sector erase, sector erase temporary stop, and sector erase restart.

Detailed Explanation of Flash Memory Write/Erase

For the flash memory read/reset, write, chip erase, sector erase, sector erase temporary stop,or sector erase restart operation, the automatic algorithm can be executed by executing thewrite cycle of the command sequence for the bus (see Table 24.4-1 "Command SequenceTable" in Section 24.4 "Activating the Flash Memory Automatic Algorithm"). The write cycle forthe bus must be executed continuously. Completion of the automatic algorithm can be checkedusing such means as the data polling function. After normal completion, the status returns toread/reset status.

Each operation is explained in the following order:

1. Flash memory read/reset status (See Section 24.6.1 "Flash Memory Read/Reset Status".)

2. Flash memory data write (See Section 24.6.2 "Flash Memory Data Write".)

3. Flash memory total data erase (chip erase) (See Section 24.6.3 "Flash Memory Total DataErase (Chip Erase)".)

4. Flash memory arbitrary data erase (sector erase) (See Section 24.6.4 "Flash MemoryArbitrary Data Erase (Sector Erase)".)

5. Flash memory sector erase temporary stop (See Section 24.6.5 "Flash Memory SectorErase Temporary Stop".)

6. Flash memory sector erase restart (See Section 24.6.6 "Flash Memory Sector EraseRestart".)

391


24.6.1 Flash Memory Read/Reset Status

This section describes the procedure for issuing a read/reset command to set the flash memory to read/reset status.

Flash Memory Read/Reset Status

To set the flash memory to read/reset status, send the read/reset commands listed in thecommand sequence table (see Table 24.4-1 "Command Sequence Table" in Section 24.4"Activating the Flash Memory Automatic Algorithm") continuously to the target sectors in theflash memory.

For the read/reset command, there are two command sequences. One consists of one busoperation and the other consists of three bus operations. However, there is no other essentialdifference between the two.

The read/reset status is the initial status of the flash memory. The read/reset status is alwaysset when the power supply is turned on or a command completes normally. The read/resetstatus is the status to wait for command input.

In read/reset status, data can be read with normal read access operations. In the same way aswith the mask ROM, programs can be accessed from the CPU. The read/reset command is notrequired to read data with normal read operations. The read/reset command is mainly used toinitialize the automatic algorithm in cases such as when a command does not end normally forsome reason.

392


24.6.2 Flash Memory Data Write

This section describes the procedure for issuing a write command to write data to the flash memory.

Flash Memory Data Write

To activate the data write automatic algorithm of the flash memory, send the write commandslisted in the command sequence table (see Table 24.4-1 "Command Sequence Table" inSection 24.4 "Activating the Flash Memory Automatic Algorithm") continuously to the targetsectors in the flash memory. The automatic algorithm is activated and automatic write startedwhen data write to the target address completes in the fourth cycle.

Addressing Method

Only even-numbered addresses can be specified as write addresses in the write data cycle.The result of writing will become unpredictable if an odd-numbered address is specified. Thatis, writing of data must be performed in units of words and to even-numbered addresses.

Writing can be performed using any order of addresses. Writing operations that exceed thesector boundary are also allowed. A single write command writes only one word of data.

Notes on Writing Data

Writing cannot change a data item 0 to a data item 1. When overwriting data item 0 with dataitem 1, the data polling algorithm (DQ7) or toggle operation (DQ6) will not end and the flashmemory elements will be determined as being faulty. The prescribed write time will beexceeded and the timing limit exceeded flag (DQ5) will indicate an error. Apart from that, it willappear as if data item 1 had been written. However, when data is read in read/reset status,data item 0 is returned. Only erase operations can set a data item 0 to a data item 1.

All other commands are ignored while the automatic write algorithm is being executed. If ahardware reset occurs during writing, the data at the address being written to will becomeunpredictable.

Flash Memory Write Procedure

Figure 24.6-1 "Example of Flash Memory Write Procedure" shows an example procedure forwriting to the flash memory. The hardware sequence flag (see Section 24.5 "Confirming theAutomatic Algorithm Execution Status") can be used to determine the status of the automaticalgorithm in the flash memory. In this example, the data polling flag (DQ7) is used to confirmthat writing has ended.

The data read to check the flag is read from the address at which the last write operation wasexecuted.

The data polling flag (DQ7) changes at the same time that the timing limit exceeded flag (DQ5)changes. Therefore, even if the timing limit exceeded flag (DQ5) is for example 1, the datapolling flag bit (DQ7) must be checked again.

Something similar applies to the toggle bit flag (DQ6): The toggle operation stops at the sametime that the timing limit exceeded flag (DQ5) changes to 1. Therefore, the toggle bit flag (DQ6)must be checked again in this case.

393


Figure 24.6-1 Example of Flash Memory Write Procedure

FMCS :WE(bit5)

FMCS :WE(bit5)

Data

Data

Data

0

1

Data

Start of writing

Enable flash memory write

Write command sequence

Write address <-- Write data

FxAAAA <-- XXAAFx5554 <-- XX55FxAAAA <-- XXA0

Read internal address Next address

Data polling (DQ7)?

Timing limit (DQ5)?

Read internal address

Data polling (DQ7)?

Read error Final address?

Prohibit flash memory write

End writing

: Confirmation using the hardware sequence flag.

394


24.6.3 Flash Memory Total Data Erase (Chip Erase)

This section describes the procedure for issuing a chip erase command to erase all data from the flash memory.

Flash Memory Total Data Erase (Chip Erase)

To erase all data from the flash memory, send the chip erase commands listed in the commandsequence table (see Table 24.4-1 "Command Sequence Table" in Section 24.4 "Activating theFlash Memory Automatic Algorithm") continuously to the target sectors in the flash memory.

The chip erase command is executed in six bus operations. Chip erase starts when writingcompletes in the sixth cycle. At chip erase, the user need not write to the flash memory beforeerasing. During execution of the automatic erase algorithm, 0 is written to all cells of the flashmemory before automatically erasing to ensure that the cells are 0.

395


24.6.4 Flash Memory Arbitrary Data Erase (Sector Erase)

This section describes the procedure for issuing a sector erase command to erase arbitrary sectors from the flash memory. Erasure can be performed for each sector. Multiple sectors can also be specified at the same time.

Flash Memory Arbitrary Data Erase (Sector Erase)

To erase arbitrary sectors from the flash memory, send the sector erase commands listed in thecommand sequence table (see Table 24.4-1 "Command Sequence Table" in Section 24.4"Activating the Flash Memory Automatic Algorithm") continuously to the target sectors in theflash memory.

Sector Specification Method

The sector erase command is executed using six bus operations. At the sixth cycle, the sectorerase code (30H) is written to an accessible even-numbered address in the target sector to startthe 50 µs sector erase wait operation. When multiple sectors are erased, the erase code (30H)is written to the address in the target sector to be erased following the above processing.

Notes on Specifying Multiple Sectors

Erase is started when the 50 µs interval for waiting for sector erase has elapsed after the finalsector erase code was written. That means, to erase multiple sectors at the same time, theaddress of the sector to be erased next and the erase code (sixth cycle of the commandsequence) must be entered within 50 µs. The address and erase code may not be acceptedafter this time. The sector erase timer (hardware sequence flag DQ3) can be used to determinewhether subsequent writing of the sector erase code is effective. At this time, have the addressused to read the sector erase timer indicate the sector to be erased.

Sector Erase Procedure

The hardware sequence flag (see Section 24.5 "Confirming the Automatic Algorithm ExecutionStatus") can be used to determine the status of the automatic algorithm in the flash memory.Figure 24.6-2 "Example of Flash Memory Erase Procedure" shows an example procedure forerasing a flash memory sector. In this example, the toggle bit flag (DQ6) is used to confirm thaterasure has ended.

Note that the data used to check the flag is read from the sector to be erased.

The toggle bit flag (DQ6) stops the toggle operation at the same time that the timing limitexceeded flag (DQ5) changes to 1. Therefore, even if the timing limit exceeded flag (DQ5) is forexample 1, the toggle bit flag (DQ6) must be checked again.

Something similar applies to the data polling flag (DQ7): The data polling flag changes at thesame time that the timing limit exceeded flag (DQ5) changes. Therefore, the data polling flag(DQ7) must be checked again in this case.

396


Figure 24.6-2 Example of Flash Memory Erase Procedure

FMCS :WE(bit5)

FMCS :WE(bit5)

N

Y

Y

0

1

N

Y

N

Y

N

0

1

Start erase

Enable flash memory erase

Erase command sequenceFxAAAA <-- XXAAFx5554 <-- XX55FxAAAA <-- XX80FxAAAA <-- XXAAFx5544 <-- XX55

Sector erase timer(DQ3)? Enter code to the sector to

be erased

Read internal address Other sector to beerased?

Internal address read 1

Internal address read 2 Next sector

Toggle bit (DQ6) data 1 (DQ6) = data 2 (DQ6)?

Toggle bit (DQ6) data 1 (DQ6) = data 2 (DQ6)?

Timing limit (DQ5)?



Erase error Final sector?

Prohibit flash memory erase

End erase: Confirm use of hardware sequence flag.

397


24.6.5 Flash Memory Sector Erase Temporary Stop

This section describes the procedure for issuing a sector erase temporary stop command to temporarily stop a flash memory sector erase operation. Data can be read from sectors that are not being erased.

Flash Memory Sector Erase Temporary Stop

To temporarily stop erasure of a flash memory sector, send the sector erase temporary stopcommands listed in the command sequence table (see Table 24.4-1 "Command SequenceTable" in Section 24.4 "Activating the Flash Memory Automatic Algorithm") to the flash memory.

The sector erase temporary stop command can stop erasure of a sector currently being erased,enabling reading data from a sector not being erased. In temporary stopped state, only readingis enabled. Writing is disabled. The sector erase temporary stop command is valid only duringsector erase for which an erase wait time applies. The command is ignored during chip eraseor write.

Writing the erase temporary stop code (B0H) executes the sector erase temporary stopcommand. At this time, have the address indicate an arbitrary address in the flash memory.The erase temporary stop command is ignored if it is entered again when erasure has beenstopped temporarily.

If the sector erase temporary stop command is entered during the interval for waiting for sectorerase, the sector erase wait state is terminated immediately, erasure is canceled, and the erasestopped state is set. If the sector erase temporary stop command is entered during sectorerase after the sector erase waiting interval, erase stopped state is set after a maximum time of15 µs.

398


24.6.6 Flash Memory Sector Erase Restart

This section describes the procedure for issuing a sector erase restart command to restart a flash memory sector erase operation that has been stopped temporarily.

Flash Memory Sector Erase Restart

To restart sector erase that has been stopped temporarily, send continuously to the flashmemory, the sector erase restart commands listed in the command sequence table (see Table24.4-1 "Command Sequence Table" in Section 24.4 "Activating the Flash Memory AutomaticAlgorithm").

The sector erase restart command is used to restart sector erase from the sector erasetemporary stopped state that has been set using the sector erase temporary stop command.Writing the erase restart code (30H) executes the sector erase restart command. At this time,have the address indicate an arbitrary address in the flash memory area.

The sector erase restart command is ignored if it is entered during a sector erase operation.

399


24.7 Flash Memory Program Example

This section provides a flash memory program example.

Flash Memory Program Example

NAME FLASHWE TITLE FLASHWE ;-------------------------------------------------------------------;MB90F574/A-FLASH test program; ;1: Transfer the program (address FFBC00H in sector SA6) in FLASH ; to RAM .(address 001500H);2: Execute the program in RAM.;3: Write the PDR1 value to FLASH (address FD0000H in sector SA1).;4: Read the written value (address FD0000H in sector SA1) and ; output it to PDR2.;5: Erase the written sector (SA1).;6: Output an erase data confirmation.;Conditions; - RAM transfer byte count: 100H (256B); - Determining the end of write and erase; Determination of the end of the operation using DQ5 ; (the timing limit exceeded flag).; Determination of the end of operation using DQ6 ; (the toggle bit flag).; Determination of the end of operation using RDY ; (FMCS).; - Handling errors; Output high to P00 to P07.; Issue the reset command. ;-------------------------------------------------------------------; RESOUS IOSEG ABS=00 ;"RESOUS" I/O segment definition ORG 0000H PDR0 RB 1 PDR1 RB 1 PDR2 RB 1 PDR3 RB 1 ORG 0010H DDR0 RB 1 DDR1 RB 1 DDR2 RB 1 DDR3 RB 1 ORG 00A1H CKSCR RB 1 ORG 00AEH FMCS RB 1 ORG 006FH ROMM RB 1 RESOUS ENDS

400


; SSTA SSEG RW 0127H STA_T RW 1 SSTA ENDS; DATA DSEG ABS=0FFH ;FLASH command address ORG 5554H COMADR2 RW 1 ORG 0AAAAHCOMADR1 RW 1 DATA ENDS;/////////////////////////////////////////////////////////////;Main program (SA3) ;/////////////////////////////////////////////////////////////CODE CSEG START: ; /////////////////////////////////////////////////////; Initialization; ///////////////////////////////////////////////////// MOV CKSCR,#0BAH ;Set to triple. MOV RP,#0 MOV A,#!STA_T MOV SSB,A MOVW A,#STA_T MOVW SP,A MOV ROMM,#00H ;Mirror off MOV PDR0,#00H ;For error confirmation MOV DDR0,#0FFH MOV PDR1,#00H ;Data input port MOV DDR1,#00H MOV PDR2,#00H ;Data output port MOV DDR2,#0FFH; ////////////////////////////////////////////////////////////; Transfer the FLASH write erase program (FFBC00H) to RAM ; (address 1500H); //////////////////////////////////////////////////////////// MOVW A,#1500H ;Transfer destination RAM area MOVW A,#0BC00H ;Transfer destination address (location in the program) MOVW RW0,#100H ;Number of transfer bytes MOVS ADB,PCB ;Transfer from FFBC00H to 001500H. CALLP 001500H ;Jump to an address of the transferred program; /////////////////////////////////////////////////////; Data output; /////////////////////////////////////////////////////OUT MOV A,#0FDH MOV ADB,A MOVW RW2,#0000H MOVW A,@RW2+00 MOV PDR2,A END JMP * CODE ENDS

401


;////////////////////////////////////////////////////////////;FLASH write erase program (SA6) ;//////////////////////////////////////////////////////////// RAMPRG CSEG ABS=0FFH ORG 0BC00H ; ////////////////////////////////////////////; Initialization; //////////////////////////////////////////// MOVW RW0,#0500H ;RW0: RAM space for confirming input data, 00:0500 and later MOVW RW2,#0000H ;RW2: Flash memory write address, FD:0000 and later MOV A,#00H ;DTB modification MOV DTB,A ;Bank specification for @RW0 MOV A,#0FDH ;ADB modification 1 MOV ADB,A ;Bank specification for write mode specification address MOV PDR3,#00H ;Switch initialization MOV DDR3,#00H ; WAIT1 BBC PDR3:0,WAIT1 ;Start writing with PDR3:0 Hi; ;//////////////////////////////////////////////// ; Write (SA1) ;//////////////////////////////////////////////// MOV A,PDR1 MOVW @RW0+00,A ;Confirm PDR1 data in RAM MOV FMCS,#20H ;Set write mode MOVW ADB:COMADR1,#00AAH ;Flash memory write command (1) MOVW ADB:COMADR2,#0055H ;Flash memory write command (2) MOVW ADB:COMADR1,#00A0H ;Flash memory write command (3); MOVW A,@RW0+00 ;Write the input data (RW0) to ; flash memory (RW2) MOVW @RW2+00,A WRITE ;Check waiting time; ////////////////////////////////////////////////////////////; ERROR if the time limit exceeded check flag is set during ; toggle operation; //////////////////////////////////////////////////////////// MOVW A,@RW2+00 AND A,#20H ;DQ5 time limit check BZ NTOW ;Time limit exceeded MOVW A,@RW2+00 ;AH MOVW A,@RW2+00 ;AL XORW A ;XOR of AL (If the value is incorrect, 1.) AND A,#40H ;Is the DQ6 toggle bit incorrect? BNZ ERROR ;If correct, to ERROR

402


; /////////////////////////////////////// ; ; Write termination check (FMCS-RDY); /////////////////////////////////////// NTOW MOVW A,FMCS AND A,#10H ;Extract FMCS RDY bits (4 bits) BZ WRITE ; Writing ended? MOV FMCS,#00H ;Release write mode; /////////////////////////////////////////////////////; Write data output MOVW RW2,#0000H ;Output write data; ///////////////////////////////////////////////////// MOVW A,@RW2+00 MOV PDR2,A; WAIT2 BBC PDR3:1,WAIT2 ;Start sector erase with PDR3:1 Hi;/////////////////////////////////////////////;Sector erase (SA1);///////////////////////////////////////////// MOV @RW2+00,#0000H ;Initialize address MOV FMCS,#20H ;Set erase mode MOVW ADB:COMADR1,#00AAH ;Flash memory erase command (1) MOVW ADB:COMADR2,#0055H ;Flash memory erase command (2) MOVW ADB:COMADR1,#0080H ;Flash memory erase command (3) MOVW ADB:COMADR1,#00AAH ;Flash memory erase command (4) MOVW ADB:COMADR2,#0055H ;Flash memory erase command (5) MOV @RW2+00,#0030H ;Issue erase command to sector to be erased (6)ELS ; Check waiting time; //////////////////////////////////////////////////////////// ; ERROR if the time limit exceeded check flag is set during ; toggle operation ; //////////////////////////////////////////////////////////// MOVW A,@RW2+00 AND A,#20H ;DQ5 time limit check BZ NTOE ;Time limit exceeded MOVW A,@RW2+00 ;AH From DQ6 during writing MOVW A,@RW2+00 ;AL High and low are output alternately for each read XORW A ;XOR of AH and AL (If the DQ6 ; value is incorrect, 1. Writing in progress.) AND A,#40H ;Is the DQ6 toggle bit high? BNZ ERROR ;If high, to ERROR; /////////////////////////////////////// ; Erase termination check (FMCS-RDY); /////////////////////////////////////// NTOE MOVW A,FMCS ; AND A,#10H ;Extract FMCS RDY bits (4 bits) BZ ELS ;Sector erase ended? MOV FMCS,#00H ;Release FLASH erase mode RETP ;Return to main program

403


;////////////////////////////////////////////// ;Error;////////////////////////////////////////////// ERROR MOV FMCS,#00H ;Release FLASH mode MOV PDR0,#0FFH ;Confirm error handling MOV ADB:COMADR1,#0F0H ;Reset command (reading enabled) RETP ;Return to main programRAMPRG ENDS;/////////////////////////////////////////////VECT CSEG ABS=0FFH ORG 0FFDCH DSL START DB 00H VECT ENDS;

404

CHAPTER 25 MB90F654A SERIAL PROGRAMMING CONNECTION EXAMPLES

This chapter provides serial programming connection examples for the case when the AF200 Flash Microcomputer Programmer manufactured by Yokogawa Digital Computer is used.

25.1 "Basic Configuration of MB90F654A Serial Programming Connections"

25.2 "Serial Programming Connection Example (When the User’s Power Supply Is Used)"

25.3 "Serial Programming Connection Example (When Power Is Supplied From the Programmer Power Supply)"

25.4 "Example of the Minimum Connection Configuration of the Flash Microcomputer Programmer (When the User’s Power Supply Is Used)"

25.5 "Example of the Minimum Connection Configuration of the Flash Microcomputer Programmer (When Power Is Supplied From the Programmer Power Supply)"

405


25.1 Basic Configuration of MB90F654A Serial Programming Connections

The MB90F654A supports flash ROM serial onboard write operations (a Fujitsu standard). This section describes these specifications.

Basic Configuration of MB90F654A Serial Programming Connections

The AF200 Flash Microcomputer Programmer manufactured by Yokogawa Digital Computer isused for Fujitsu standard serial onboard write operations.

Figure 25.1-1 "Basic Configuration of MB90F654A Serial Programming Connections" shows thebasic configuration of MB90F654A serial programming connections.

Figure 25.1-1 Basic Configuration of MB90F654A Serial Programming Connections

Note:

Contact Yokogawa Digital Computer for details about the functions and operation method ofthe AF200 Flash Microcomputer Programmer, general-purpose communication cable(AZ210) for connection, and connectors.

Host interface cable (AZ201)

AF200 Flash Microcomputer Programmer + memory card

General-purpose communication cable (AZ210)

CLK synchronous serial connection MB90F654A

user system

Stand-alone operation enabled

RS232C

Table 25.1-1 Pins Used for Fujitsu Standard Serial Onboard Programming Operations

Pin Function Additional explanation

MD2, MD1, MD0

Mode pins These pins are controlled by the Flash Microcomputer Programmer in programming mode.

X0, X1 Oscillation pins In programming mode, the CPU internal operating clock has the same frequency as the PLL clock. Therefore, because the oscillation clock frequency is the same as that of the internal operating clock, the oscillation pins used at serial rewriting are set to 1 MHz to 16 MHz.

PO0, PO1 Programming program activation pins

-

RSTX Reset pin -

406

25.1 Basic Configuration of MB90F654A Serial Programming Connections

The control circuit shown in Figure 25.1-2 "Control Circuit" is required if the user’s system alsouses the P00, SIN0, SOT0, and SCK0 pins. (The /TICS signal of the Flash MicrocomputerProgrammer can be used to disconnect the user’s circuit during serial programming operations.See the connection example.)

Figure 25.1-2 Control Circuit

SIN0 Serial data input pin These pins are used to set the UART to CLK synchronous mode.

SOT0 Serial data output pin

SCK0 Serial clock input pin

VCC Power supply voltage supply pin

Connection to the Flash Microcomputer Programmer is not required if the programming voltage (3 V plus or minus 10%) is supplied from the user’s system.At connection, be careful not to cause a short circuit with the user’s power supply.

VSS GND pin This GND pin shall be shared with the GND pin of the Flash Microcomputer Programmer.

Table 25.1-1 Pins Used for Fujitsu Standard Serial Onboard Programming Operations

Pin Function Additional explanation

AF200 write control pin MB90F654A

write control pin

AF200 /TICS pin

User

Table 25.1-2 AF200 Flash Microcomputer Programmer System Configuration (Manufactured by Yokogawa Digital Computer Co. Ltd.)

Type Function

AF200 /ACP Flash Microcomputer Programmer main unit and 100 V power supply adapter

/AC2P Flash Microcomputer Programmer mainframe and overseas power supply adapter

AZ201 PC/AT RS232C cable

AZ210 Standard target probe (a). Length: 1 m

FF001A Fujitsu F2MC-16L Flash Microcomputer control module

/P2 2MB PC Card (Option)

/P4 4MB PC Card (Option)

Inquiries: Yokogawa Digital Computer Co. Ltd., Equipment Division Sales DepartmentTelephone: (81)-42-333-6224

407


25.2 Serial Programming Connection Example (When the User’s Power Supply Is Used)

Figure 25.2-1 "Example of Serial Programming Connection in MB90F654A Internal Vector Mode (When the User’s Power Supply is Used)" shows an example of a serial programming connection when the power supply voltage of the microcomputer is supplied from the user’s power supply.For the MD2 and MD0 mode pins, MD2 = 1 and MD0 = 0 are input using TAUX3 and TMODE of the Flash Microcomputer Programmer (AF200).Serial reprogramming mode: MD2, MD1, and MD0 = 110

Serial Programming Connection Example (When the User’s Power Supply Is Used)

Figure 25.2-1 Example of Serial Programming Connection in MB90F654A Internal Vector Mode (When the User’s Power Supply is Used)

10k

10k

10k

DX10-28S

AF200

MB90F654A

10K

(19)

(12)

(23)

(10)

(13)

(27)

(6)

(7,8,

14,15,

21,22,

1,28)

1

28 15

14

( )

DX10-28S

10k(5)

10k

(2)

1MHz 16MHz

3,4,9,11,16,17,18,20,24,25,26

OPEN

DX10-28S

P00

MD0

MD1

Vss

Vcc

SCK0

SOT0

SIN0

MD2

RSTX

P01

X0

X1

GND

TRXD

TTXD

TCK

TMODE

TAUX3

/TICS

TAUX

/TRES

TVcc

AF200 Flash Microcomputer Programmer

User system

Connector DX10-28S

User

User

User's power supply

- The pins 3, 4, 9, 11, 16, 17, 18, 20, 24, 25, and 26 are open.

- DX10-28S: Right angle type

Pin 14 Pin 1

Pin 28 Pin 15

Connector (Hirose Electric) pin arrangement

TAUX3

TMODE

TAUX

/TICS

/TRES

TTXD

TRXD

TCK

TVcc

GND

(19)

(12)

(23)

(10)

(5)

(13)

(27)

(6)

(2)

(7,8,14,15,21,22,1,28)

MD2

MD1

MD0

X0

X1

P00

RSTX

P01

SIN0

SOT0

SCK0

Vcc

Vss

1MHz 16MHz

DX10-28S

MB90F654A

408

25.2 Serial Programming Connection Example (When the User’s Power Supply Is Used)

• Similar to P00, the control circuit shown in the figure below is required if the user’s systemalso uses the SIN0, SOT0, and SCK0 pins. (The /TICS signal of the Flash MicrocomputerProgrammer can be used to disconnect the user’s circuit during serial programmingoperations.)

• Turn off the user’s power supply before connecting the AF200.

AF200 write control pin MB90F654A

write control pin

User

AF200 /TICS pin

409


25.3 Serial Programming Connection Example (When Power Is Supplied From the Programmer Power Supply)

Figure 25.3-1 "Example of Serial Programming Connection in MB90F654A Internal Vector Mode (When Power is Supplied from the Programmer Power Supply)" shows an example for a serial programming connection when the power supply voltage of the microcomputer is supplied from the writer’s power supply. For the MD2 and MD0 mode pins, MD2 = 1 and MD0 = 0 are input using TAUX3 and TMODE of the Flash Microcomputer Programmer (AF200).Serial reprogramming mode: MD2, MD1, and MD0 = 110

Serial Programming Connection Example (When Power Is Supplied From the programmer Power Supply)

Figure 25.3-1 Example of Serial Programming Connection in MB90F654A Internal Vector Mode (When Power is Supplied from the Programmer Power Supply)

10k

10k

10k

DX10-28S

AF200

MB90F654A

10K

(19)

(12)

(23)

(10)

(13)

(27)

(6)

(3)

(7,8,

14,15,

21,22,

1,28)

1

28 15

14

DX10-28S

10k

(5)

10k

1MHz 16MHz

AZ264

2,4,9,11,16,17,18,20,24,25,26

OPEN

DX10-28S

GND

TRXD

TTXD

TCK

TMODE

TAUX3

/TICS

TAUX

/TRES

Vcc

P00

MD0

MD1

Vss

Vcc

SCK0

SOT0

SIN0

MD2

RSTX

P01

X0

X1

Power supply regulator AZ264

- The 2, 4, 9, 11, 16, 17, 18, 20, 24, 25, and 26 pins are open.

- DX10-28S: Right angle type


User's system

Connector DX10-28S MB90F654A

TAUX3

TMODE

TAUX

/TICS

/TRES

TTXD

TRXD

TCK

Vcc

GND

(19)

(12)

(23)

(10)

(5)

(13)

(27)

(6)

(3)

(7,8,14,15,21,22,1,28)

MD2

MDI

MD0X0

X1

P00

RSTX

P01

SIN0

SOT0

SCK0

Vcc

Vss

User

User

User's power supply

Pin 14 Pin 1

Pin 28 Pin 15

DX10-28S


to

410

25.3 Serial Programming Connection Example (When Power Is Supplied From the Programmer Power

• Similar to P00, the control circuit shown in the figure below is required if the user’s systemalso uses the SIN0, SOT0, and SCK0 pins. (The /TICS signal of the Flash MicrocomputerProgrammer can be used to disconnect the user’s circuit during serial programmingoperations.)


• When the programming power supply is supplied from the AF200, be careful not to cause ashort circuit with the user’s power supply.

AF200 write control pin

AF200 /TICS pin

User

MB90F654A write control pin

411


25.4 Example of the Minimum Connection Configuration of the Flash Microcomputer Programmer (When the User’s Power Supply Is Used)

Figure 25.4-1 "Example of the Minimum Connection Configuration of the Flash Microcomputer Programmer (When the User’s Power Supply Is Used)" shows an example of the minimum connection configuration of the Flash Microcomputer Programmer (AF200) when the power supply voltage of the microcomputer is supplied from the user’s power supply. For flash memory write operations, the MD2, MD1, MD0, P00 pins and the Flash Microcomputer Programmer need not be connected if the pins are set as shown in Figure 25.4-1 "Example of the Minimum Connection Configuration of the Flash Microcomputer Programmer (When the User’s Power Supply Is Used)".Serial reprogramming mode: MD2, MD1, and MD0 = "110"

Example of the Minimum Connection Configuration of the Flash Microcomputer Programmer (When the User’s Power Supply Is Used)

Figure 25.4-1 Example of the Minimum Connection Configuration of the Flash Microcomputer Programmer (When the User’s Power Supply Is Used)

10k

DX10-28S

AF200

MB90F654A

(7,8,

14,15,

21,22,

1,28)

1

28 15

14

( )

DX10-28S

(13)

(27)

(6)

(2)

10k(5)

10k10k

10k

10k

10k

1

0

1

10k10k

0

1

1MHz 16MHz

GND

TTXD

TRXD

TCK

TVcc

/TRES

MD1

Vss

MD2

SIN0

SOT0

SCK0

Vcc

MD0

RSTX

P00

P01

X0

X1

3,4,9,10,11,12,16,17,18,19,20,

23,24,25,26 OPEN

DX10-28S


User's system

MB90F654A

1 during serial rewrite




User circuit


User circuit

1MHz to 16MHz

Connector DX10-28S

MD2

MD1

MD0

X0

X1

P00

P01

RSTX

SIN0SOT0

SCK0

Vcc

Vss

/TRESTTXD

TRXD

TCKTVcc

GND

User's power supply

- DX10-28S: Right angle typePin 28 Pin 15


DX10-28S- The 3, 4, 9, 10, 11, 12, 16, 17, 18, 19, 20, 23, 24, 25, and 26 pins are open.

Pin 14 Pin 1

(5)

(13)

(27)

(6)

(2)

(7,8,14,15,21,22,1,28)

412

25.4 Example of the Minimum Connection Configuration of the Flash Microcomputer Programmer (When

• The control circuit shown in the figure below is required if the user’s system also uses theSIN0, SOT0, and SCK0 pins. (The /TICS signal of the Flash Microcomputer Programmercan be used to disconnect the user’s circuit during serial programming operations.)




AF200 /TICS pin

User

10K

413


25.5 Example of the Minimum Connection Configuration of the Flash Microcomputer Programmer (When Power Is Supplied From the Programmer Power Supply)

Figure 25.5-1 "Example of the Minimum Connection Configuration of the Flash Microcomputer Programmer (When Power Is Supplied From the Programmer Power Supply)" shows an example of the minimum connection configuration of the Flash Microcomputer Programmer (AF200) when the power supply voltage of the microcomputer is supplied from the writer’s power supply.The MD2, MD1, MD0, P00 pins and the Flash Microcomputer Programmer need not be connected.Serial reprogramming mode: MD2, MD1, and MD0 = "110"

Example of the Minimum Connection Configuration of the Flash Microcomputer Programmer (When Power Is Supplied From the Programmer Power Supply)

Figure 25.5-1 Example of the Minimum Connection Configuration of the Flash Microcomputer Programmer (When Power Is Supplied From the Programmer Power Supply)

10k

DX10-28S

AF200

MB90F654A

(7,8,

14,15,

21,22,

1,28)

1

28 15

4

( )

DX10-28S

(13)

(27)(6)

10k(5)

10k10k

10k

10k

10k

1

0

1

10k

10k0

1

(3)

1MHz 16MHz

AZ264

GND

TTXD

TRXD

TCK

/TRES

Vcc

MD1

Vss

MD2

SIN0

SOT0

SCK0

MD0

RSTX

P00

P01

Vcc

X

X1

3,4,9,10,11,12,16,17,18,19,20,

23,24,25,26 OPEN

DX10-28S

X


User's system




MB90F654A

1MHz to 16MHz

10k0 during serial rewrite User circuit


User circuit

Connector DX10-28S

User's power supply

Pin 4 Pin 1Power supply regulatorAZ264

- The 3, 4, 9, 10, 11, 12, 16, 17, 18, 19, 20, 23, 24, 25, and 26 pins are open.

- DX10-28S: Right angle typePin 28 Pin 15


DX10-28S

/TRESTTXD

TCK

Vcc

GND

MD2

MD1

MD0

X1

P00

P01

RSTXSIN0SOT0SCK0

Vcc

Vss

(5)(13)(27)(6)

(3)

(7,8,l14,15,21,22,1,28)

414

25.5 Example of the Minimum Connection Configuration of the Flash Microcomputer Programmer (When

• The control circuit shown in the figure below is required if the user’s system also uses theSIN0, SOT0, and SCK0 pins. (The /TICS signal of the Flash Microcomputer Programmercan be used to disconnect the user’s circuit during serial programming operations.)


• When the programming power supply is supplied from the AF200, be careful not to cause ashort circuit with the user’s power supply.


AF200 /TICS pin


User

10K

415


416

APPENDIX

The appendixes provide I/O maps, instructions, and other information.

APPENDIX A "I/O MAP"

APPENDIX B "INTERRUPT VECTORS"

APPENDIX C "PIN STATES FOR EACH CPU STATE"

APPENDIX D "OUTLINE OF INSTRUCTIONS"

417

APPENDIX A I/O MAP

APPENDIX A I/O MAP

Table A-1 "I/O Map" lists the address assignment of each register of the peripheral functions built into the MB90650A.

I/O Map

Table A-1 I/O Map

Address Register Abbreviation Access Resource Initial value

00H Port 0 data register PDR0 R/W Port 0 XXXXXXXX




04H Port 4 data register PDR4 R/W Port 4 1XXXXXXX



07H Port 7 data register PDR7 R/W Port 7 ---XX111

08H Port 8 data register PDR8 R/W Port 8 -XXXXXXX


0AH Port A data register PDRA R/W Port A -----XXX

0B to 0FH Reserved area

10H Port 0 direction register DDR0 R/W Port 0 00000000




14H Port 4 direction register DDR4 R/W Port 4 -0000000



17H Port 7 direction register DDR7 R/W Port 7 ---00---

18H Port 8 direction register DDR8 R/W Port 8 -0000000


1AH Port A direction register DDRA R/W Port A -----000

1BH Port 4 direction register ODR4 R/W Port 4 -0000000

418

APPENDIX A I/O MAP

1CH Port 0 direction register RDR0 R/W Port 0 00000000

1DH Port 1 direction register RDR1 R/W Port 1 00000000

1EH Port 6 direction register RDR6 R/W Port 6 00000000

1FH Analog input enable register ADER R/W Port 5, A/D 11111111

20H Serial mode register 0 SMR0 R/W UART0 00000000

21H Serial control register 0 SCR0 R/W 00000100

22H Serial input register/serial output register 0

SIDR/SODR R/W XXXXXXXX

23H Serial status register 0 SSR0 R/W 00001-00

24H Serial mode control status register 0

SMCS0 R/W I/O extended serial interface

0

----0000


SMCS0 R/W 00000010

26H Serial data register 0 SDR0 R/W XXXXXXXX

27H Clock division control register CDCR R/W Communication prescaler

0---1111


SMCS1 R/W I/O extended serial interface

1

----0000


SMCS1 R/W 00000010

2AH Serial data register 1 SDR1 R/W XXXXXXXX

2B to 2FH Reserved area

30H Interrupt/DTP enable register ENIR R/W DTP/external interrupt unit

00000000

31H Interrupt/DTP source register EIRR R/W XXXXXXXX

32H Request level setting register ELVR R/W 00000000

33H 00000000

34 to 35H Reserved area

36H Control status register ADCS1ADCS2

R/W A/D converter 00000000

37H 00000000

38H Data register ADCR1ADCR2

R XXXXXXXX

39H XXXXXXXX

Table A-1 I/O Map


419

APPENDIX A I/O MAP

3AH D/A converter data register 0 DAT0 R/W D/A converter XXXXXXXX

3BH D/A control status register 1 DAT1 R/W XXXXXXXX

3CH D/A control register ch. 0 DACR0 R/W -------0

3DH D/A control register ch. 1 DACR1 R/W -------0

3EH Clock control register CLKR R/W CKOT output ----0000

3FH Reserved area

40H Reload register L (ch. 0) PRLL0 R/W 8/16-bit PPG XXXXXXXX

41H Reload register H (ch. 0) PRLH0 R/W XXXXXXXX

42H Reload register L (ch. 1) PRLL1 R/W XXXXXXXX

43H Reload register H (ch. 1) PRLH1 R/W XXXXXXXX

44H PPG0 operation mode control register

PPGC0 R/W 0X000XX1

45H PPG1 operation mode control register

PPGC1 R/W 0X000001

46H PPG0 and PPG1 output control register

PPGOE R/W 00000000

47 to 4FH Reserved area

50H Compare register ch. 0 lower OCCP0 R/W 16-bit I/O timer output compare (channels 0 to

3)

XXXXXXXX

51H Compare register ch. 0 higher XXXXXXXX

52H Compare register ch. 1 lower OCCP1 R/W XXXXXXXX






58H Compare control status register ch. 0

OCS0 R/W 0000--00

59H Compare control status register ch. 1

OCS1 R/W ---00000

5AH Compare control status register ch. 2

OCS2 R/W 0000--00

5BH Compare control status register ch. 3

OCS3 R/W ---00000

5C to 5FH Reserved area

Table A-1 I/O Map


420

APPENDIX A I/O MAP

60H Input capture register ch. 0 lower

IPCP0 RR

16-bit I/O timer input capture

(channels 0 and 1)

XXXXXXXX

61H Input capture register ch. 0 higher

XXXXXXXX

62H Input capture register ch. 1 lower

IPCP1 R XXXXXXXX

63H Input capture register ch. 1 higher

R XXXXXXXX

64H Input capture control status register

ICS01 R/W 00000000

65H Reserved area - - --------

66H Timer data register lower TCDTL R/W 16-bit I/O timer free run timer

(channels 0 and 1)

00000000

67H Timer data register higher TCDTH R/W 00000000

68H Timer control status register TCCS R/W 00000000

69 to 6FH Reserved area

70H Up/down count register ch. 0 UDCR0 R 8/16-bit up/down timer

counter

00000000

71H Up/down count register ch. 1 UDCR1 00000000

72H Reload compare register ch. 0 RCR0 W 00000000

73H Reload compare register ch. 1 RCR1 00000000

74H Counter status register ch. 0 CSR0 R/W 00000000


76H Counter control register ch. 0 CCRL0 R/W -0000000

77H CCRH0 00000000

78H Counter status register ch. 1 CSR1 R/W 00000000


7AH Counter control register ch. CCRL1 R/W -0000000

7BH CCRH1 -0000000

7C to 7FH Reserved area

80H I2C bus status register IBSR R I2C bus I/F 00000000

81H I2C bus control register IBCR R/W 00000000

82H I2C bus clock selection register

ICCR R/W --0XXXXX

83H I2C bus address register IADR R/W -XXXXXXX

84H I2C bus data register IDAR R/W XXXXXXXX

Table A-1 I/O Map


421

APPENDIX A I/O MAP

85H to 87H Reserved area

88H DTMF control register DTMC 00000000

89H DTMF data register DTMD 000X0000

8A to 9EH Reserved area (Accessing 90 to 9EH is prohibited.)

9FH Delayed interrupt cause generation/release register

DIRR R/W Delayed interrupt

generation module

-------0

A0H Low power mode register LPMCR R/W Low power 00011000

A1H Clock selection register CKSCR R/W Low power 11111100

A2 to A4H Reserved area

A5H Automatic ready function selection register

ARSR W External pin 0011--00

A6H External address output control register

HACR W External pin 00000000

A7H Bus control signal selection register

EPCR W External pin 0000*00-

A8H Watchdog control register WDTC R/W Watchdog timer XXXXX111

A9H Time base timer control register

TBTC R/W Time base timer 1--00100

AAH Clock timer control register WTC R/W Clock timer 1X000000

AB to ADH Reserved area

AEH Flash memory control status register

FMCS R/W Flash memory 000X0000

AFH Reserved area

B0H Interrupt control register 00 ICR00 R/W Interrupt controller

00000111

B1H Interrupt control register 01 ICR01 R/W 00000111









Table A-1 I/O Map


422

APPENDIX A I/O MAP

Note:

Addresses of 00FFH or less refer to reserved areas. External bus access signals are not output.

For the write enable bit, the value for initialization at a reset is noted as the initial value. This isnot the value read at a read operation.

LPMCR, CKSCR, and WDTC may or may not be initialized, depending on the type of reset.The initial value when they are initialized is noted here.

• Explanation of read/write operations

R/W: Read/write enabled

R: Read only

W: Write only

• Explanation of initial values

0: The initial value of this bit is 0.

1: The initial value of this bit is 1.

X: The initial value of this bit is undefined.

*: This bit is not used. The initial value is undefined.

BAH Interrupt control register 10 ICR10 R/W Interrupt controller

00000111

BBH Interrupt control register 11 ICR11 R/W 00000111

BCH Interrupt control register 12 ICR12 R/W 00000111

BDH Interrupt control register 13 ICR13 R/W 00000111

BAH Interrupt control register 10 ICR10 R/W 00000111

BBH Interrupt control register 11 ICR11 R/W 00000111

BCH Interrupt control register 12 ICR12 R/W 00000111

BDH Interrupt control register 13 ICR13 R/W 00000111

BEH Interrupt control register 14 ICR14 R/W 00000111

BFH Interrupt control register 15 ICR15 R/W 00000111

C0H to FFH

External area - - - -

Table A-1 I/O Map


423

APPENDIX B INTERRUPT VECTORS


Appendix B indicates the relationship between interrupt causes and the interrupt vectors and interrupt registers for the MB90650A.

Interrupt Vectors

Table B-1 Interrupt Causes, Interrupt Vectors, and Interrupt Registers




Reset X # 08 FFFFDCH - -

INT9 instruction X # 09 FFFFD8H - -

Exception X # 10 FFFFD4H - -

A/D converter O # 11 FFFFD0H ICR00 0000B0H

Time base timer interval timer interrupt

X # 12 FFFFCCH

DTP0 (external interrupt 0) O # 13 FFFFC8H ICR01 0000B1H

16-bit free run timer (I/O timer) overflow

O # 14 FFFFC4H

Extended I/O serial 1 O # 15 FFFFC0H ICR02 0000B2H

DTP1 (external interrupt 1) O # 16 FFFFBCH

Extended I/O serial 2 O # 17 FFFFB8H ICR03 0000B3H

DTP2 (external interrupt 2) O # 18 FFFFB4H

DTP3 (external interrupt 3) O # 19 FFFFB0H ICR04 0000B4H

8/16-bit PPG0 counter borrow O # 20 FFFFACH

8/16-bit U/D counter 0 compare O # 21 FFFFA8H ICR05 0000B5H


O # 22 FFFFA4H

8/16-bit PPG1 counter borrow O # 23 FFFFA0H ICR06 0000B6H

DTP4/5 (external interrupt 4/5) O # 24 FFFF9CH


O # 25 FFFF98H ICR07 0000B7H


O # 26 FFFF94H

424


Note:

For resources that have two interrupt causes for the same interrupt number, the IIOSinterrupt clear signal clears both interrupt request flags.

Clock prescaler X # 27 FFFF90H ICR08 0000B8H


8/16-bit U/D counter 1 compare O # 29 FFFF88H ICR09 0000B9H


O # 30 FFFF84H


O # 31 FFFF80H ICR10 0000BAH


O # 32 FFFF7CH


O # 33 FFFF78H ICR11 0000BBH


O # 34 FFFF74H

Flash memory write/erase completion

X # 35 FFFF70H ICR12 0000BCH


UART0 reception completion * # 37 FFFF68H ICR13 0000BDH

UART0 send completion * # 39 FFFF60H ICR14 0000BEH

I2C interface X # 41 FFFF58H ICR15 0000BFH

Delayed interrupt X # 42 FFFF54H

O: The IIOS interrupt clear signal clears the interrupt request flag.*: The IIOS interrupt clear signal clears the interrupt request flag. There is a stop request.X: The IIOS interrupt clear signal does not clear the interrupt request flag.

Table B-1 Interrupt Causes, Interrupt Vectors, and Interrupt Registers




425

APPENDIX C PIN STATES FOR EACH CPU STATE


Table C-1 "Pin States in Single Chip Mode" to Table C-3 "Pin States in External Bus 16-Bit Data Bus Mode" list the pin states at stop, hold, and reset for each bus mode.

Pin States in Single Chip Mode

Table C-1 Pin States in Single Chip Mode

Pin name Sleep Stop Hold Reset

SPL=0 SPL=1

P07 to P00P17 to P10P27 to P20P37 to P30P47 to P40P57 to P50P67 to P60P74 to P70P86P92 to P91P97 to P94PA2 to PA0

The immediately preceding status is retained. *2


Input cut offOutput Hi-Z *3

(No status) Input disabledOutput Hi-Z

P85 to P80P93, P90

Input enabled *1 Input enabled *1

*1: The same as other ports when used as an output port function. Input enabled means that the input function can be used. Pull-up, pull-down, or external input is required.

*2: The status output immediately preceding this mode is output as is or output is disabled.The output status is output as is means that if an output built-in peripheral is operating, output is executed based on the built-in peripheral. In case of port output, output is retained. Input disabled means that operation of the input gate directly from the pin is enabled, but because the internal circuit is not operating, the pin signal has not been received internally.

*3: Input cut off indicates that operation of the input gate immediately from the pin is prohibited. Output Hi-Z means that the pin drive transistor has been set to drive prohibited state and that the pin has been set to high impedance.

426


Table C-2 Pin States in External Bus 16-Bit Data Bus Mode


SPL=0 SPL=1

P07 to P00P17 to P10

Input disabledOutput Hi-ZOutput status *4

Input disabledOutput Hi-Z

Input shutdownOutput H-Z *3



P27 to P20 Output status *4 General purpose *2 Output status *4

A23 to A16*8

P37(COK) General purpose *2 General purpose *2 General purpose *2 Input disabledOutput Hi-Z

CLK *5 CLK *6 CLK *5

P36(RDY) The immediately preceding status is retained. *2


Input disabled

P35(HAKX) Low output

P34(HRQ) 1 output

P33(WRHX) General purpose *2 General purpose *2 General purpose *2

WRHX*7 WRHX*7 WRHX*8

P32(WRLX) General purpose *2 General purpose *2 General purpose *2


P31(RDX) High output High output Input disabledOutput Hi-Z

High output

P30(ALE) Low output Low output Low output

P47 to P40P57 to P50P67 to P60P74 to P70P86P92 to P91P97 to P94PA2 to PA0





P85 to P80P93, P90


*1 to *3: See Table C-1 "Pin States in Single Chip Mode".

*4: Output status means that driving of the pin drive transistor is enabled, but because operation of the internal circuit is set to the stopped state, output is fixed to low, not high.The output fluctuates if the output circuit is used while the internal peripheral circuit is operating.

*5: CLK output

*6: Output status

*7: High output

*8: Input disabled, Output Hi-Z

427


Table C-3 Pin States in External Bus 16-Bit Data Bus Mode


SPL=0 SPL=1

P07 to P00 Input disabledOutput Hi-Z


Input shutdownOutput H-Z *3



P17 to P10 Output status *4 Output status *4 General purpose *2 Output status *4

P27 to P20 A23 to A16*8

P37(CLK) General purpose *2 General purpose *2 General purpose *2 Input disabledOutput Hi-Z

CLK *5 CLK *6 CLK *5

P36(RDY) The immediately preceding status is retained. *2



P35(HAKX) Low output

P34(HRQ) 1 output

P33(WRHX) The immediately preceding status is retained.

P32(WRLX) General purpose *2 General purpose *2 General purpose *2


P31(RDX) High output High output Input disabledOutput Hi-Z

High output

P30(ALE) Low output Low output Low output

P47 to P40P57 to P50P67 to P60P74 to P70P86P92 to P91P97 to P94PA2 to PA0





P85 to P80P93, P90


*1 to *3: See Table C-1 "Pin States in Single Chip Mode".

*4: See Table C-2 "Pin States in External Bus 16-Bit Data Bus Mode".

*5: CLK output

*6: Output status

*7: High output

*8: Input disabled, Output Hi-Z

428

APPENDIX D OUTLINE OF INSTRUCTIONS


Appendix D describes the instructions used by the F 2MC-16L.

D.1 "Types of Instructions"

D.2 "Addressing"

D.3 "Direct Addressing"

D.4 "Indirect Addressing"

D.5 "Execution Cycle Count"

D.6 "Effective Address Fields"

D.7 "How to Use the Instruction Tables"

D.8 "F2MC-16L Instruction Tables"

D.9 "Instruction Maps"

429


D.1 Types of Instructions

The F2MC-16L has 340 types of instruction. Addressing is performed using the effective address fields of the instructions or the instruction codes.

Types of Instruction

The F2MC-16L has the 340 types of instruction shown below:

• Transfer instructions (byte): 41

• Transfer instructions (word and long word): 38

• Addition and subtraction instructions (byte, word, and long word): 42

• Increase and decrease instructions (byte, word, and long word): 12

• Comparison instructions (byte, word, and long word): 11

• - Unsigned multiplication and division instructions (word and long word): 11

• Logic instructions (byte and word): 39

• Logic instructions (long word): 6

• Sign inversion instructions (byte and word): 6

• Normalize instruction (long word): 1

• Shift instructions (byte, word, and long word): 18

• Branch instructions: 50

• Other control instructions (byte, word, and long word): 28

• Bit manipulation instructions: 21

• Accumulator operation instructions (byte and word): 6

• String instructions: 10

430


D.2 Addressing

For the F 2MC-16L, the effective address field of the instruction or the instruction code (implied) determines the address format. When the instruction code is used to determine the address format, specify the address based on the instruction code used. Several types of addressing methods can be selected based on the instruction.

Addressing

The F2MC-16L has the 23 types of addressing methods shown below:

• Immediate (#imm)

• Register direct

• Direct branch address (addr16)

• Physical direct branch address (addr24)

• I/O direct (io)

• Abbreviated direct address (dir)

• Direct address (addr16)

• I/O direct bit address (io:bp)

• Abbreviated direct bit address (dir:bp)

• Direct bit address (addr16:bp)

• Vector address (#vct)

• Register indirect (@RWj j = 0 to 3)

• Register indirect with post increment (@RWj+ j = 0 to 3)

• Register indirect with displacement (@RWi+disp8 i = 0 to 7, @RWj+disp16 j = 0 to 3)

• Long register indirect with displacement (@RLi+disp8 i = 0 to 3)

• Program counter indirect with displacement (@PC+disp16)

• Register indirect with base index (@RW0+RW7, @RW1+RW7)

• Program counter relative branch address (rel)

• Register list (rlst)

• Accumulator indirect (@A)

• Accumulator indirect branch address (@A)

• Indirect specification branch address (@ear)

• Indirect specification branch address (@eam)

431


Effective Address Fields

Table D.2-1 "Effective Address Field" lists the address formats specified for the effectiveaddress fields.

Table D.2-1 Effective Address Field

Code Notation Address format Default bank

0001020304050607

R0R1R2R3R4R5R6R7

RW0RW1RW2RW3RW4RW5RW6RW7

RL0(RL0)RL1(RL1)RL2(RL2)RL3(RL3)

Register directThe ea corresponds to byte, word, or long word type, in that order, from the left.

None

08090A0B

@RW0@RW1@RW2@RW3

Register indirect

DTBDTBADBSPB

0C0D0E0F

@RW0+@RW1+@RW2+@RW3+

Register indirect with post increment

DTBDTBADBSPB

10111213

@RW0+disp8@RW1+disp8@RW2+disp8@RW3+disp8

Register indirect with 8-bit displacement

DTBDTBADBSPB

14151617



DTBDTBADBSPB

18191A1B



DTBDTBADBSPB

1C1D1E1F

@RW0+RW7@RW1+RW7@PC+disp16addr16

Register indirect with indexRegister indirect with indexPC indirect with 16-bit displacementDirect address

DTBDTBPCBDTB

432


D.3 Direct Addressing

In direct addressing, the operand values, registers, and addresses are specified directly.

Direct Addressing

Immediate (#imm)

The operand values are specified directly (#imm4, #imm8, #imm16, and #imm32).

Figure D.3-1 Example of Immediate (#imm) Addressing

Register direct

The direct registers are specified as operands. Table D.3-1 "Register Direct Addressing" liststhe registers that can be specified and provides examples for register direct addressing.

MOVW A, #01212H

2 2 3 3A 4 4 5 5

4 4 5 5A 1 2 1 2

(This instruction stores the operand value in A.)

Before execution

After execution (The instruction transfers AL --> AH.)

Table D.3-1 Register Direct Addressing

General-purpose register

Byte R0, R1, R2, R3, R4, R5, R6, R7

Word RW0, RW1, RW2, RW3, RW4, R5W, RW6, RW7

Long word RL0, RL1, RL2, RL3

Dedicated register Accumulator A, AL

Pointer SP*1

Bank PCB, DTB, USB, SSB, ADB

Page DPR

Control PS, CCR, RP, ILM

*1: For SP, the user stack pointer (USP) or system stack pointer (STP) is selected and used based on the value of the S flag bit in the condition code register (CCR). For a branch instruction, the program counter (PC) is specified implicitly even if it is not specified in an instruction operand.

433


Figure D.3-2 Example of Register Direct Addressing

Direct branch address (addr16)

The branch destination addresses are specified directly using a displacement. The data lengthof the displacement is 16 bits, and the branch destination is indicated in logical space. Directbranch addresses are used for unconditional branch and subroutine call instructions. Theaddress bits 16 to 23 are specified in the program bank register (PCB).

Figure D.3-3 Example of Direct Branch Address (addr16) Addressing

MOV R0, A

0 7 1 6A 2 5 3 4

? ?

3 4

0 7 1 6A 2 5 6 4

R0

R0

Before execution

After execution

(This instruction transfers the eight low-order bits of A to the general-purpose register R0.)

Memory space

Memory space

JMP 3B20H

3 C 2 0PC

3 B2 0

4 FPCB

3 B 2 0PC 4 FPCB

4F3C22H

4F3C21H

6 24F3C20H JMP 3B20H

4F3B20H

Before execution

After execution

Memory space

(This instruction executes unconditional branching using direct specification of a branch address in a bank.)

Next instruction

434


Physical direct branch address (addr24)

The branch destination addresses are specified directly using a displacement. The data lengthof the displacement is 24 bits. Physical direct branch addresses are used for unconditionalbranch, subroutine call, and software interrupt instructions.

Figure D.3-4 Example of Physical Direct Branch Address (addr24) Addressing

I/O direct (io)

The operand memory addresses are specified directly using an 8-bit displacement. The I/Ospaces of physical addresses 000000H to 0000FFH are accessed regardless of the data bankregister (DTB) and direct page register (DPR) values. If a prefix for specifying the access spaceis coded before the instruction that uses this address specification, it will be invalid.

Figure D.3-5 Example of I/O Direct (io) Addressing

JMPP 333B20H

3 C 2 0PC

3 33 B

4 FPCB

3 B 2 0PC 3 3PCB

4F3C23H

4F3C22H

2 04F3C21H

6 34F3C20H JMPP 333B20H

333B20H

Before execution

After execution

Memory space

Next instruction

(This instruction executes unconditional branching using a direct branch address in 24-bit specification.)

MOVW A, i:0C0H

0 7 1 6A 2 5 3 4

F F

2 5 3 4A F F E EE E

0000C1H

0000C0H

Before execution

After execution

Memory space

(This instruction reads using I/O direct addressing and stores the value in A.)

435


Abbreviated direct address (dir)

The eight low-order bits of the memory address are specified directly in the operand. Theaddress bits 15 to 8 are specified in the direct page register (DPR). The address bits 23 to 16are specified in the data bank register (DTB).

Figure D.3-6 Example of Abbreviated Direct Address (dir) Addressing

Direct address (addr16)

The 16 low-order bits of the memory address are specified directly in the operand. The addressbits 23 to 16 are specified in the data bank register (DTB). Prefix instructions that specify theaccess spaces are invalid for this addressing method.

Figure D.3-7 Example of Direct Address (addr16) Addressing

MOV S:20H, A

4 4 5 5A 1 2 1 2

6 6DPR

6 6

? ?

1 2

4 4 5 5A 1 2 1 2

DPR

7 7DTB

7 7DTB

776620H

776620H

Before execution

After execution

Memory space

Memory space

(This instruction writes the contents of the eight low-order bits of A using abbreviated direct addressing.)

BRA 3B20H

3 C 2 0PC

F FF E

4 FPCB

3 B 2 0PC 4 FPCB

4F3C22H

4F3C21H

6 04F3C20H BRA 3B20H

4F3B20H

Before execution

After execution

Memory space

Next instruction

(This instruction executes unconditional relative branching.)

436


I/O direct bit address (io:bp)

The bits of physical addresses 000000H to 0000FFH are specified directly. The bit position isindicated by :bp. The larger value becomes the most significant bit (MSB). The smaller valuebecomes the least significant bit (LSB).

Figure D.3-8 Example of I/O Direct Bit Address (io:bp) Addressing

Abbreviated direct bit address (dir:bp)

The eight low-order bits of the memory address are specified directly in the operand. Theaddress bits 15 to 8 are specified in the direct page register (DPR). The address bits 23 to 16are specified in the data bank register (DTB). The bit position is indicated by :bp. The largervalue becomes the most significant bit (MSB). The smaller value becomes the least significantbit (LSB).

Figure D.3-9 Example of Abbreviated Direct Bit Address (dir:bp) Addressing

SETB i:0C1H:0

0 0

0 1

0000C1H

0000C1H

Before execution

After execution

Memory space

Memory space

(This instruction manipulates the set bits using I/O direct bit addressing.)

SETB S:10H:0

5 5DTB

5 5

0 0

0 1DTB

6 6DPR

6 6DPR

556610H

556610H

Before execution

After execution

Memory space

Memory space

(This instruction manipulates the set bits using abbreviated direct bit addressing.)

437


Direct bit address (addr16:bp)

The values are specified directly for arbitrary bits within the 64 KB. The address bits 23 to 16are specified in the data bank register (DTB). The bit position is indicated by :bp. The largervalue becomes the most significant bit (MSB). The smaller value becomes the least significantbit (LSB).

Figure D.3-10 Example of Direct Bit Address (addr16:bp) Addressing

Vector address (#vct)

The branch destination address becomes the contents of the specified vector. Vector numberscan have one of two data lengths: 4 bits or 8 bits. Vector addresses are used for subroutinecall and software interrupt instructions.

Figure D.3-11 Example of Vector Address (#vct) Addressing

SETB 2222H:0

5 5DTB

5 5

0 0

0 1DTB

552222H

552222H

Before execution

After execution

Memory space

Memory space

(This instruction manipulates the set bits using direct bit addressing.)

CALLV #15

0 0 0 0PC

F FPCB

F F

D 0

D 0 0 0PC

PCB

FFFFE1H

0 0FFFFE0H

E FFFC000H CALLV #15

Before execution

After execution

Memory space

(This instruction branches to the address indicated by the interrupt vector specified in the operand.)

438


Note:

When the program bank register (PCB) is FFH, the vector area shares the vector area of#vct8 (#0 to #7). Care must therefore be taken when vector addresses are used. (SeeTable D.3-2 "CALLV Vectors".)

Table D.3-2 CALLV Vectors

Instruction Vector address L Vector address H

CALLV #0 XXFFFEH XXFFFFH

CALLV #1 XXFFFCH XXFFFDH

CALLV #2 XXFFFAH XXFFFBH

CALLV #3 XXFFF8H XXFFF9H





CALLV #8 XXFFEEH XXFFEFH

CALLV #9 XXFFECH XXFFEDH

CALLV #10 XXFFEAH XXFFEBH

CALLV #11 XXFFE8H XXFFE9H





Note: The PCB register value is entered for XX.

439


D.4 Indirect Addressing

In indirect addressing, addresses are specified indirectly using the data of the addresses indicated by the specified operands.

Indirect Addressing

Register indirect (@RWj j = 0 to 3)

This addressing method accesses the memory at the address indicated by the contents of thegeneral-purpose register RWj. When RW0 and RW1 are used, the address bits 23 to 16 areindicated in the data bank register (DTB). When RW3 is used, the address bits 23 to 16 areindicated in the system stack bank register (SSB). When RW2 is used, the address bits 23 to16 are indicated in the additional data bank register (ADB).

Figure D.4-1 Example of Register Indirect (@RWj j= 0 to 3) Addressing

Register indirect with post increment (@RWj+ j = 0 to 3)

This addressing method accesses the memory at the address indicated by the contents of thegeneral-purpose register RWj. After the operand operation, RWj is incremented by the operanddata length (1 for byte, 2 for word, and 4 for long word). When RW0 and RW1 are used, theaddress bits 23 to 16 are indicated in the data bank register (DTB). When RW3 is used, theaddress bits 23 to 16 are indicated in the system stack bank register (SSB). When RW2 isused, the address bits 23 to 16 are indicated in the additional data bank register (ADB).

If the result of post increment indicates the address of the register itself for which post incrementhas been specified, the incremented value will be accessed the next time. In this case,however, if the relevant instruction was a write instruction, writing using the instruction haspriority. Therefore, the register that should have been incremented is used for writing.

MOVW A, @RW1

0 7 1 6A

D 3 0 F

2 5 3 4

RW1 F FE E

2 5 3 4A

D 3 0 F

F F E E

RW1

7 8DTB

7 8DTB

78D310H

78D30FH

Before execution

After execution

Memory space

(This instruction reads using register indirect addressing and stores the result in A.)

440


Figure D.4-2 Example for Register Indirect Addressing with Post Increment (@RWj+ j= 0 to 3)

Register indirect with displacement (@RWi+disp8 i = 0 to 7, @RWj+disp16 j = 0 to 3)

This addressing method accesses the memory at the address obtained by adding thedisplacement to the contents of the general-purpose register RWj. There are two types ofdisplacement: Byte and word. The displacement is added as a signed value. When RW0,RW1, RW4, and RW5 are used, the address bits 23 to 16 are indicated in the data bank register(DTB). When RW3 and RW7 are used, the address bits 23 to 16 are indicated in the systemstack bank register (SSB). When RW2 and RW6 are used, the address bits 23 to 16 areindicated in the additional data bank register (ADB).

Figure D.4-3 Example of Register Indirect Addressing with Displacement (@RWi+disp8 i = 0 to 7, @RWj+disp16 j= 0 to 3)

MOVW A, @RW1+

0 7 1 6A

D 3 0 F

2 5 3 4

RW1 F FE E

2 5 3 4A

D 3 1 1

F F E E

RW1

7 8DTB

7 8DTB

78D310H

78D30FH

Before execution

After execution

Memory space

(This instruction reads using register indirect addressing with post increment and stores the result in A.)

MOVW A, @RW1+10H

0 7 1 6A

D 3 0 F

2 5 3 4

RW1 F FE E

2 5 3 4A

D 3 0 F

F F E E

RW1

7 8DTB

7 8DTB

78D320H

78D31FH

+10H

Before execution

After execution

Memory space

(This instruction reads using register indirect addressing with displacement and stores the result in A.)

441


Long register indirect with displacement (@RLi+disp8 i = 0 to 3)

This addressing method accesses the memory at the address indicated by the 24 low-order bitsof the result obtained by adding the displacement to the contents of the general-purposeregister RLi. The displacement is eight bits. The displacement is added as a signed value.

Figure D.4-4 Example of Long Register Indirect Addressing with Displacement (@RLi+disp8 i = 0 to 3)

Program counter indirect addressing with displacement (@PC+disp16)

This addressing method accesses the memory at the address indicated by (instruction address+ 4 + disp16). The displacement has a length of words. The address bits 23 to 16 are specifiedusing the program bank register (PCB). Note that the operand address of each instructionshown below is not regarded as address of the instruction + disp16.

• DBNZ eam, rel

• DWBNZ eam, rel

• CBNE eam, #imm8, rel

• CWBNE eam, #imm16, rel

• MOV eam, #imm8

• MOVW eam, #imm16

Figure D.4-5 Example of Program Counter Indirect Addressing with Displacement (@PC+disp16)

MOVW A, @RL2+25H

0 7 1 6A 2 5 3 4

F 3 8 2 4 B 0 2RL2 F FE E

2 5 3 4A F F E E

F 3 8 2 4 B 0 2RL2

824B28H

824B27H

+25H

Before execution

After execution

Memory space

(This instruction reads using long register indirect addressing with displacement and stores the result in A.)

MOVW A, @PC+20H

0 7 1 6A 2 5 3 4

C 5PCB

C 5

F FE E

0 02 0 MOVW

A, @PC+20H

2 5 3 4A F F E E

PCB

C5457BH

C5457AH

C54559H

C54558H

9 E7 3

C54557H

C54556H

C5455AH+20H

+4

4 5 5 6PC

4 5 5 APC

Before execution

After execution

Memory space

(This instruction reads using PC indirect addressing with displacement and stores the result in A.)

442


Register indirect with base index (@RW0+RW7, @RW1+RW7)

This addressing method accesses the memory at the address indicated by the result of addingRW0 or RW1 to the contents of the general-purpose register RW7. The address bits 23 to 16are indicated in the data bank register (DTB).

Figure D.4-6 Example of Register Indirect Addressing with Base Index (@RW0+RW7, @RW1+RW7)

Program counter relative branch address (rel)

The branch destination address is the value obtained by adding the value of program counter(PC) and the 8-bit displacement. If the result exceeds 16 bits, the excess part is ignored withoutthe bank register being incremented or decremented. As a result, the address is restricted to a64 KB bank. This addressing method is used for unconditional and conditional branchinstructions. The address bits 23 to 16 are indicated in the program counter register (PCB).

Figure D.4-7 Example of Program Counter Relative Branch Address (rel)

MOVW A, @RW1+RW7

0 7 1 6A

D 3 0 F

2 5 3 4

RW1 F FE E

2 5 3 4A

D 3 0 F

F F E E

RW1

0 1 0 1RW7

7 8DTB

0 1 0 1RW7

7 8DTB

78D411H

78D410H+

Before execution

After execution

Memory space

(This instruction reads using register indirect addressing with base index and stores the result in A.)

BRA 3B20H

3 C 2 0PC

F FF E

4 FPCB

3 B 2 0PC 4 FPCB

4F3C22H

4F3C21H

6 04F3C20H BRA 3B20H

4F3B20H

Before execution

After execution

Memory space

Next instruction

(This instruction executes an unconditional relative branch.)

443


Register list (rlst)

The register list specifies the registers used as the target of push/pop operations on the stack.

Figure D.4-8 Register List Configuration

Figure D.4-9 Example of Register List (rlist) Addressing

RW7 RW6 RW5 RW4 RW3 RW2 RW1 RW0

MSB LSB

The register is selected if the corresponding bit is 1. The register is not selected if the corresponding bit is 0.

POPW RW0, RW4

3 4 F ASP

RW0RW1RW2RW3RW4RW5RW6RW7 XXXX

0 40 3

34FDH

34FCH

34FEH

0 20 1

34FBH

34FAHSP

3 4 F ESP

0 10 2RW0RW1RW2RW3RW4RW5RW6RW7

0 30 4

0 40 3

34FDH

34FCH

34FEH

0 20 1

34FBH

34FAH

SP

(This instruction transfers the data of the memory area indicated by SP to the word registers indicated in the register list.)

Before execution After execution

Memory space Memory space

XXXX

XXXXXXXXXXXX

XXXXXXXXXXXX

XXXX

XXXXXXXX

XXXX

XXXXXXXX

444


Accumulator indirect (@A)

This addressing method accesses the memory at the address indicated by the contents (16 bits)of the address expressed in the low-order byte (AL) of the accumulator. The address bits 23 to16 are specified by mnemonics in the data bank register (DTB).

Figure D.4-10 Example of Accumulator Indirect (@A) Addressing

Accumulator indirect branch address (@A)

The branch destination address becomes the contents (16 bits) of the address expressed in thelow-order byte (AL) of the accumulator. This address indicates the branch destination in thebank space. The address bits 23 to 16 are specified using the program bank register (PCB).For a JCTX (Jump Context) instruction, however, the address bits 23 to 16 are specified usingthe data bank register (DTB). This addressing method is used for unconditional branchinstructions.

Figure D.4-11 Example of Accumulator Indirect Branch Address (@A) Addressing

MOVW A, @A

0 7 1 6A 2 5 3 4

DTB F FE E

0 7 1 6A F F E E

DTB

B B

B B

BB2535H

BB2534H

Before execution

After execution

Memory space

(This instruction reads using accumulator indirect addressing and stores the result in A.)

JMP @A

6 6 7 7A 3 B 2 0 6 1

3 C 2 0PC 4 FPCB

6 6 7 7A 3 B 2 0

3 B 2 0PC 4 FPCB

4F3C20H JMP @A

4F3B20H

Before execution

After execution

Memory space

Next instruction

(This instruction executes an unconditional branch using an accumulator indirect branch address.)

445


Indirect specification branch address (@ear)

The word data of the address indicated by ear becomes the branch destination address.

Figure D.4-12 Example of Indirect Specification Branch Address (@ear) Addressing

Indirect specification branch address (@eam)

The word data at the address indicated by eam becomes the branch destination address.

Figure D.4-13 Example of Indirect Specification Branch Address (@eam) Addressing

JMP @@RW0

0 83 C 2 0PC

7 F 4 8PW0

4 FPCB

2 1DTB

3 B 2 0PC

7 F 4 8PW0

4 FPCB

2 1DTB

4F3C21H

7 34F3C20H

3 B217F49H

2 0217F48H

JMP @@RW0

4F3B20H

Before execution

After execution

Memory space

Next instruction

(This instruction executes an unconditional branch using the indirect address of register indirect addressing.)

JMP @RW0

0 0

3 C 2 0PC

3 B 2 0PW0

4 FPCB

3 B 2 0PC

3 B 2 0PW0

4 FPCB

4F3C21H

7 34F3C20H JMP @RW0

4F3B20H

Before execution

After execution

Memory space

Next instruction

(This instruction executes an unconditional branch using register indirect addressing.)

446


D.5 Execution Cycle Count

The actual number of cycles required to execute instructions (execution cycle count) is obtained by adding the number of cycles for each instruction itself, a correction value determined from the conditions, and the number of cycles for program fetch.

Execution Cycle Count

The actual number of cycles required to execute instructions (execution cycle count) is obtainedby adding the number of cycles for each instruction itself, a correction value determined fromthe conditions, and the number of cycles for program fetch. When fetching programs intomemory connected via a 16-bit bus, such as the built-in ROM, program fetching is performedeach time the instruction being executed exceeds the word boundary. As a result, the executioncycle count will increase if other operations such as data access interfere with program fetch.

When fetching programs into memory connected via an 8-bit external data bus, programfetching is performed for each byte of the instruction being executed. As a result, the executioncycle count will increase if other operations such as data access interfere with program fetch.At CPU intermittent operation, the clock supply to the CPU for the number of cycles specified bythe CG0 and CG1 bits of the low-power mode control register will stop temporarily when ageneral-purpose register, built-in ROM, built-in RAM, built-in I/O area, or the external data bus isaccessed. Therefore, for determining the number of cycles required to execute instructions atCPU intermittent operation, add the value of access counts x temporary stop cycle counts to thenormally required execution cycle count.

Calculating the Execution Cycle Count

Table D.5-1 "Execution Cycle Counts for Each Addressing Method of Execution Addresses" liststhe instruction execution cycle counts. Table D.5-2 "Correction Values of Number of Cycles forCalculating the Execution Cycle Count" and Table D.5-3 "Correction Values of Number ofCycles for Calculating the Number of Program Fetch Cycles" list the data of the correctionvalues.

447


Table D.5-1 Execution Cycle Counts for Each Addressing Method of Execution Addresses

Code

Operand(a)*1

Register access count for each addressing methodExecution cycle count for

each addressing method

00|

07

RiRwiRLi

Given in the instruction tables

Given in the instruction tables

08|

0B@RWj 2 1

0C|

0F@RWj+ 4 2

10|

17@RWi+disp8 2 1

18|

1B@RWi+disp16 2 1

1C1D1E1F


4421

2200

*1: (a) is used for ~ (number of cycles) and B (correction value) in Section D.8 "F2MC-16L Instruction Tables."

448


Table D.5-2 Correction Values of Number of Cycles for Calculating the Execution Cycle Count

Operand (b) byte* 1 (c) word* 1 (d) long* 1

Cycle count

Access count

Cycle count

Access count

Cycle count

Access count

Internal register +0 1 +0 1 +0 2

Internal memoryEven-numbered address

+0 1 +0 1 +0 2

Internal memoryOdd-numbered address

+0 1 +2 2 +4 4

External data bus16-bit even-numbered address

+1 1 +1 1 +2 2

External data bus16-bit odd-numbered address

+1 1 +4 2 +8 4

External data bus *2

8 bits+1 1 +4 2 +8 4

*1: (b), (c), and (d) are used for ~ (number of cycles), B (correction value), and instruction rules in Section D.8 "F2MC-16L Instruction Tables."

*2: When an external data bus is used, the number of wait cycles of ready input and automatic ready must also be added.

Table D.5-3 Correction Values of Number of Cycles for Calculating the Number of Program Fetch Cycles

Instruction Byte boundary Word boundary

Internal memory — +2

External data bus 16 bits — +3

External data bus 8 bits +3 —

Note 1 When an external data bus is used, the number of wait cycles of ready input and automatic ready must also be added.

Note 2 Because instruction execution is delayed by all program fetch operations, use this correction value for calculating the worst case.

449


D.6 Effective Address Fields

Table D.6-1 "Effective Address Field" lists the effective address fields.

Effective Address Fields

Table D.6-1 Effective Address Field

Code Notation Address format

Number of bytes of address

extension * 1

0001020304050607

R0R1R2R3R4R5R6R7

RW0RW1RW2RW3RW4RW5RW6RW7

RL0(RL0)RL1(RL1)RL2(RL2)RL3(RL3)

Register directThe ea corresponds to byte, word, or long word type, in that order, from the left.

—

08090A0B

@RW0@RW1@RW2@RW3

Register indirect 0

0C0D0E0F

@RW0+@RW1+@RW2+@RW3+

Register indirect with post increment 0

1011121314151617

@RW0+disp8 @RW1+disp8 @RW2+disp8 @RW3+disp8 @RW4+disp8 @RW5+disp8 @RW6+disp8 @RW7+disp8


1

18191A1B

@RW0+disp16 @RW1+disp16 @RW2+disp16 @RW3+disp16


2

1C1D1E1F


Register indirect with indexRegister indirect with indexPC indirect with 16-bit displacementDirect address

0022

*1: The number of bytes of address extension corresponds to "+" of "#" (number of bytes) in Section D.8 "F2MC-16L Instruction Tables."

450


D.7 How to Use the Instruction Tables

Table D.7-1 "Descriptions of Items in the Instruction Tables" lists items used in Section

D.8 "F2MC-16L Instruction Tables." Table D.7-2 "Explanation of Codes in the Instruction Tables" lists the used codes.

Descriptions of Items in the Instruction Tables

Table D.7-1 Descriptions of Items in the Instruction Tables

Item Explanation

MnemonicUpper letters and codes: Used as is even for assembler.Lower letters: Rewritten and described for assembler.Number after a lower case letter: Indicates the bit width in an instruction.

# Indicates the number of bytes.

Indicates the number of cycles.See Table D.5-1 "Execution Cycle Counts for Each Addressing Method of Execution Addresses" for the letters in an item.

RGIndicates the register access count when an instruction is executed.This count is used for calculating the correction value at CPU intermittent operation.

B

Indicates the correction value for calculating the actual number of cycles when an instruction is executed.The actual number of cycles when an instruction is executed can be calculated by adding the value in the "~" column.

Operation Indicates the operation executed by an instruction.

LH

Indicates specific operations for bits 15 to 8 of the accumulator.Z: Transfers 0.X: Extends the sign and transfers.-: Does not transfer.

AH

Indicates specific operations for the 16 high-order bits of the accumulator.*: Transfers from AL to AH.-: Does not transfer.Z: Transfers "00" to AH.X: Sign-extends AH and transfers 00H or FFH to AH.

451


I

Indicates the status of each flag I (interrupt enable), S (stack), T (sticky bit), N (negative), Z (zero), V (overflow), and C (carry).

*: Change when an instruction is executed.-: Do not change.Z: Set when an instruction is executed.X: Reset when an instruction is executed.

S

T

N

Z

V

C

RMW

Indicates whether the instruction is a read-modify-write instruction (a single instruction reads data from memory and writes the result to memory).

*: Read-modify-write instruction-: Not a read-modify-write instruction

Note: Read-modify-write instructions cannot be used for addresses that have different meanings for read and write.

Table D.7-2 Explanation of Codes in the Instruction Tables

Notation Explanation

A 32-bit accumulatorThe bit length used depends on the instruction.

Byte: 8 low-order bits of ALWord: 16 bits of ALLong: 32 bits of AL:AH

AHAL

16 high-order bits of A16 low-order bits of A

SP Stack pointer (USP or SSP)

PC Program counter

PCB Program bank register

DTB Data bank register

ADB Additional data bank register

SSB System stack bank register

USB User stack bank register

SPB Current stack bank register (SSB or USB)

DPR Direct page register

brg1 DTB, ADB, SSB, USB, DPR, PCB, SPB

brg2 DTB, ADB, SSB, USB, DPR, SPB

Ri R0, R1, R2, R3, R4, R5, R6, R7

Table D.7-1 Descriptions of Items in the Instruction Tables

Item Explanation

452


RWi RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7

RWj RW0, RW1, RW2, RW3

RLi RL0, RL1, RL2, RL3

diraddr16addr24

ad24 0-15ad24 16-23

Abbreviated direct addressingDirect addressingPhysical direct addressingBits 0 to 15 of addr24Bits 16 to 23 of addr24

io I/O area (000000H to 0000FFH)

#imm4#imm8#imm16#imm32

ext (imm8)

4-bit immediate data8-bit immediate data16-bit immediate data32-bit immediate data16-bit data with sign-extended 8-bit immediate data

disp8disp16

8-bit displacement16-bit displacement

bp Bit offset

vct4vct8

Vector number (0 to 15)Vector number (0 to 255)

( ) b Bit address

releaream

PC relative branch specificationEffective address specification (code 00 to 07)Effective address specification (code 08 to 1F)

rlst Register list

Table D.7-2 Explanation of Codes in the Instruction Tables

Notation Explanation

453


D.8 F2MC-16L Instruction Tables

Table D.8-1 "41Transfer Instructions (Byte) (41 Instructions)" to Table D.8-17 "String

Instructions (10 Instructions)" list the instructions used by the F 2MC-16L.

F2MC-16L Instruction Tables

Table D.8-1 41Transfer Instructions (Byte) (41 Instructions)

Mnemonic # RG B Operation LH

AH

I S T N Z V C RMW

MOVMOVMOVMOVMOVMOVMOVMOVMOVMOVN

A,dirA,addr16A,RiA,earA,eamA,ioA,#imm8A,@AA,@RLi+disp8A,#imm4

23122+22231

34223+(a)323101

0011000020

(b)(b)00(b)(b)0(b)(b)0

byte (A) <-- (dir)byte (A) <-- (addr16)byte (A) <-- (Ri)byte (A) <-- (ear)byte (A) <-- (eam)byte (A) <-- (io)byte (A) <-- imm8byte (A) <-- ((A))byte (A) <-- ((RLi)+disp8)byte (A) <-- imm4

ZZZZZZZZZZ

*******-**

----------

----------

----------

*********R

**********

----------

----------

----------

MOVXMOVXMOVXMOVXMOVXMOVXMOVXMOVXMOVXMOVX

A,dirA,addr16A,RiA,earA,eamA,ioA,#imm8A,@AA,@RWi+disp8A,@RLi+disp8

23222+22223

34223+(a)323510

0011000012

(b)(b)00(b)(b)0(b)(b)(b)

byte (A) <-- (dir)byte (A) <-- (addr16)byte (A) <-- (Ri)byte (A) <-- (ear)byte (A) <-- (eam)byte (A) <-- (io)byte (A) <-- imm8byte (A) <-- ((A))byte (A) <-- ((RWi)+disp8)byte (A) <-- ((RLi)+disp8

XXXXXXXXXX

*******-**

----------

----------

----------

**********

**********

----------

----------

----------

MOVMOVMOVMOVMOVMOVMOVMOVMOVMOVMOVMOVMOVMOVMOVMOVMOV

dir,Aaddr16,ARi,Aear,Aeam,Aio,A@RLi+disp8,ARi,earRi,eamear,Rieam,RiRi,#imm8io,#imm8dir,#imm8ear,#imm8eam,#imm8@AL,AH/ MOV

@A,T

23122+2322+22+23333+2

34223+(a)31034+(a)45+(a)25524+(a)3

00110022121100100

(b)(b)00(b)(b)(b)0(b)0(b)0(b)(b)0(b)(b)

byte (dir) <-- (A)byte (addr16) <-- (A)byte (Ri) <-- (A)byte (ear) <-- (A)byte (eam) <-- (A)byte (io) <-- (A)byte ((RLi)+disp8) <-- (A)byte (Ri) <-- (ear)byte (Ri) <-- (eam)byte (ear) <-- (Ri)byte (eam) <-- (Ri)byte (Ri) <-- imm8byte (io) <-- imm8byte (dir) <-- imm8byte (ear) <-- imm8byte (eam) <-- imm8byte ((A)) <-- (AH)

-----------------

-----------------

-----------------

-----------------

-----------------

************--*-*

************--*-*

-----------------

-----------------

-----------------

XCHXCHXCHXCH

A,earA,eamRi,earRi,eam

22+22+

45+(a)79+(a)

2042

02×(b)02×(b)

byte (A) <--> (ear)byte (A) <--> (eam)byte (Ri) <--> (ear)byte (Ri) <--> (eam)

ZZ--

----

----

----

----

----

----

----

----

----

Note: For (a) to (d) in the table, see Table D.5-1 "Execution Cycle Counts for Each Addressing Method of Execution Addresses" and Table D.5-2 "Correction Values of Number of Cycles for Calculating the Execution Cycle Count".

454


Table D.8-2 Transfer Instructions (Word and Long) (38 Instructions)


AH

I S T N Z V C RMW

MOVWMOVWMOVWMOVWMOVWMOVWMOVWMOVWMOVWMOVWMOVW

A,dirA,addr16A,SPA,RWiA,earA,eamA,ioA,@AA,#imm16A,@RWi+disp8A,@RLi+disp8

231122+22323

341223+(a)332510

00011000012

(c)(c)000(c)(c)(c)0(c)(c)

word (A) <-- (dir)word (A) <-- (addr16)word (A) <-- (SP)word (A) <-- (RWi)word (A) <-- (ear)word (A) <-- (eam)word (A) <-- (io)word (A) <-- ((A))word (A) <-- imm16word (A) <-- ((RWi)+disp8)word (A) <-- ((RLi)+disp8)

-----------

*******-***

-----------

-----------

-----------

***********

***********

-----------

-----------

-----------

MOVWMOVWMOVWMOVWMOVWMOVWMOVWMOVWMOVWMOVWMOVWMOVWMOVWMOVWMOVWMOVWMOVWMOVW

dir,Aaddr16,ASP,ARWi,Aear,Aeam,Aio,A@RWi+disp8,A@RLi+disp8,ARWi,ear RWi,eamear,Rwieam,RwiRWi,#imm16io,#imm16ear,#imm16eam,#imm16@AL,AH/MOVW@A,T

231122+22322+22+3444+2

341223+(a)351034+(a)45+(a)2524+(a)3

000110012212110100

(c)(c)000(c)(c)(c)(c)0(c)0(c)0(c)0(c)(c)

word (dir) <-- (A)word (addr16) <-- (A)word (SP) <-- (A)word (RWi) <-- (A)word (ear) <-- (A)word (eam) <-- (A)word (io) <-- (A)word ((RWi)+disp8) <-- (A)word ((RLi)+disp8) <-- (A)word (RWi) <-- (ear)word (RWi) <-- (eam)word (ear) <-- (RWi)word (eam) <-- (RWi)word (RWi) <-- imm16word (io) <-- imm16word (ear) <-- imm16word (eam) <-- imm16word ((A)) <-- (AH)

------------------

------------------

------------------

------------------

------------------

**************-*-*

**************-*-*

------------------

------------------

------------------

XCHWXCHWXCHWXCHW

A,earA,eamRWi, earRWi, eam

22+22+

45+(a)79+(a)

2042

02 x (c)02 x (c)

word (A) <--> (ear)word (A) <-- >(eam)word (RWi) <--> (ear)word (RWi) <--> (eam)

----

----

----

----

----

----

----

----

----

----

MOVLMOVLMOVL

A,earA,eamA,#imm32

22+5

45+(a)3

200

0(d) 0

long (A) <-- (ear)long (A) <-- (eam)long (A) <-- imm32

---

---

---

---

---

***

***

---

---

---

MOVLMOVL

ear,Aeam,A

22+

45+(a)

20

0(d)

long (ear1) <-- (A) long(eam1) <-- (A)

--

--

--

--

--

**

**

--

--

--


455


Table D.8-3 Addition and Subtraction Instructions (Byte, Word, and Long) (42 Instructions)


AH

I S T N Z V C RMW

ADDADDADDADDADDADDADDCADDCADDCADDDC

SUBSUBSUBSUBSUBSUBSUBCSUBCSUBCSUBDC

A,#imm8A,dirA,earA,eamear,Aeam,AAA,ear A,eam A

A,#imm8A,dirA,earA,eamear,Aeam,AAA,earA,eamA

2222+22+122+1

2222+22+122+1

2534+(a)35+(a)234+(a)3

2534+(a)35+(a)234+(a)3

0010200100

0010200100

0(b)0(b)02×(b)00(b)0

0(b)0(b)02×(b)00(b)0

byte (A) <-- (A) + imm8byte (A) <-- (A) + (dir)byte (A) <-- (A) + (ear)byte (A) <-- (A) + (eam)byte (ear) <-- (ear) + (A)byte (eam) <-- (eam) + (A)byte (A) <-- (AH) + (AL) + (C)byte (A) <-- (A) + (ear)+ (C)byte (A) <-- (A) + (eam)+ (C) byte (A) <-- (AH) + (AL) + (C) (decimal)byte (A) <-- (A) - imm8byte (A) <-- (A) - (dir)byte (A) <-- (A) - (ear)byte (A) <-- (A) - (eam)byte (ear) <-- (ear) - (A)byte (eam) <-- (eam) - (A)byte (A) <-- (AH) - (AL) - (C)byte (A) <-- (A) - (ear) - (C)byte (A) <-- (A) - (eam) - (C)byte (A) <-- (AH) - (AL) - (C) (decimal)

ZZZZ-ZZZZZ

ZZZZ--ZZZZ

----------

----------

----------

----------

----------

----------

----------

----------

**********

**********

**********

**********

**********

**********

**********

**********

-----*----

-----*----

ADDWADDWADDWADDWADDWADDWADDCWADDCWSUBWSUBWSUBWSUBWSUBWSUBWSUBCWSUBCW

AA,earA,eamA,#imm16ear,Aeam,AA,earA,eamAA,earA,eamA,#imm16ear,Aeam,AA,earA,eam

122+322+22+122+322+22+

234+(a)235+(a)34+(a)234+(a)235+(a)34+(a)

0100201001002010

00(c)002×(c)0(c)00(c)002×(c)0(c)

word (A) <-- (AH) + (AL)word (A) <-- (A) + (ear)word (A) <-- (A) + (eam)word (A) <-- (A) + imm16word (ear) <-- (ear) + (A)word (eam) <-- (eam) + (A)word (A) <-- (A) + (ear) + (C)word (A) <-- (A) + (eam) + (C)word (A) <-- (AH) - (AL)word (A) <-- (A) - (ear)word (A) <-- (A) - (eam)word (A) <-- (A) - imm16word (ear) <-- (ear) - (A)word (eam) <-- (eam) - (A)word (A) <-- (A) - (ear) - (C)word (A) <-- (A) - (eam) - (C)

----------------

----------------

----------------

----------------

----------------

****************

****************

****************

****************

-----*-------*--

ADDLADDLADDLSUBLSUBLSUBL

A,earA,eamA,#imm32A,earA,eamA,#imm32

22+522+5

67+(a)467+(a)4

200200

0(d)00(d)0

long (A) <-- (A) + (ear)long (A) <-- (A) + (eam)long (A) <-- (A) + imm32long (A) <-- (A) - (ear)long (A) <-- (A) - (eam)long (A) <-- (A) - imm32

------

------

------

------

------

******

******

******

******

------


456


Table D.8-4 Increment and Decrement Instructions (Byte, Word, and Long) (12 Instructions)


AH

I S T N Z V C RMW

INCINC

DECDEC

eaream

eaream

22+

22+

35+(a)

35+(a)

20

20

02×(b)02×(b)

byte (ear) <-- (ear) + 1byte (eam) <-- (eam) + 1

byte (ear) <-- (ear) - 1 byte (eam) <-- (eam) - 1

--

--

--

--

--

--

--

--

--

--

**

**

**

**

**

**

--

--

-*

-*

INCWINCW

DECWDECW

eaream

eaream

22+

22+

35+(a)

35+(a)

20

20

02×(c)

02×(c)

word (ear) <-- (ear) + 1word (eam) <-- (eam) + 1

word (ear) <-- (ear) - 1word (eam) <-- (eam) - 1

--

--

--

--

--

--

--

--

--

--

**

**

**

**

**

**

--

--

-*

-*

INCLINCL

DECLDECL

eaream

eaream

22+

22+

79+(a)

79+(a)

40

40

02×(d)

02×(d)

long (ear) <-- (ear) + 1long (eam) <-- (eam) + 1

long (ear) <-- (ear) - 1long (eam) <-- (eam) - 1

--

--

--

--

--

--

--

--

--

--

**

**

**

**

**

**

--

--

-*

-*


Table D.8-5 Comparison Instructions (Byte, Word, and Long) (11 Instructions)


AH

I S T N Z V C RMW

CMPCMPCMPCMP

AA,earA,eamA,#imm8

122+2

1 23+(a)2

0100

00(b)0

byte (AH) - (AL)byte (A) - (ear)byte (A) - (eam)byte (A) - imm8

----

----

----

----

----

****

****

****

****

----

CMPWCMPWCMPWCMPW

AA,earA,eamA,#imm16

122+3

1 23+(a)2

0100

00(c)0

word (AH) - (AL)word (A) - (ear)word (A) - (eam)word (A) - imm16

----

----

----

----

----

****

****

****

****

----

CMPLCMPLCMPL

A,earA,eamA,#imm32

22+5

67+(a)3

200

0(d)0

long (A) - (ear)long (A) - (eam)long (A) - imm32

---

---

---

---

---

***

***

***

***

---


457


Table D.8-6 Unsigned Multiplication and Division Instructions (Word and Long) (11 lnstructions)


AH

I S T N Z V C RMW

DIVU

DIVU

DIVU

DIVUW

DIVUW

A

A,ear

A,eam

A,ear

A,eam

1

2

2+

2

2+

**1

**2

**3

**4

**5

0

1

0

1

0

0

0

**6

0

**7

word (AH) / byte (AL)quotient --> byte (AL) remainder --> byte (AH)word (A) / byte (ear)quotient --> byte (A) remainder --> byte (ear)word (A) / byte (eam)quotient --> byte (A) remainder --> byte (eam)long (A) / word (ear)quotient --> word(A) remainder --> word(ear)long (A) / word (eam)quotient --> word(A) remainder --> word(eam)

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

*

*

*

*

*

*

*

*

*

*

-

-

-

-

-

MULUMULUMULUMULUWMULUWMULUW

AA,earA,eamAA,earA,eam

122+122+

**8**9**10**11**12**13

010010

00(b)00(c)

byte (AH) * byte (AL) --> word (A)byte (A) * byte (ear) --> word (A)byte (A) * byte (eam) --> word (A)word (AH) * word (AL) --> Long (A)word (A) * word (ear) --> Long (A)word (A) * word (eam) --> Long (A)

-----

-----

-----

-----

-----

-----

-----

-----

-----

-----

**1 3 for zero division, 7 for overflow, and 15 for normal operation


**3 6 + (a) for zero division, 9 + (a) for overflow, and 19 + (a) for normal operation


**5 6 + (a) for zero division, 8 + (a) for overflow, and 26 + (a) for normal operation

**6 (b) for zero division or overflow and 2 x (b) for normal operation

**7 (c) for zero division or overflow and 2 x (c) for normal operation

**8 3 for byte (AH) zero and 7 for byte (AH) not zero

**9 4 for byte (ear) zero and 8 for byte (ear) not zero

**10 5 + (a) for byte (eam) zero and 9 + (a) for byte (eam) not zero

**11 3 for word (AH) zero and 11 for word (AH) not zero

**12 4 for word (ear) zero and 12 for word (ear) not zero

**13 5 + (a) for word (eam) zero and 13 + (a) for word (eam) not zero


458


Table D.8-7 Logic Instructions 1 (Byte and Word) (39 Instructions)


AH

I S T N Z V C RMW

ANDANDANDANDAND

OROROROROR

XORXORXORXORXORNOTNOTNOT

A,#imm8A,earA,eamear,Aeam,A

A,#imm8A,earA,eamear,Aeam,A

A,#imm8A,earA,eamear,Aeam,AAeaream

222+22+

222+22+

222+22+122+

234+(a)35+(a)

234+(a)35+(a)

234+(a)35+(a)235+(a)

01020

01020

01020020

00(b)02×(b)

00(b)02×(b)

00(b)02×(b)002×(b)

byte (A) <-- (A) and imm8byte (A) <-- (A) and (ear)byte (A) <-- (A) and (eam)byte (ear) <-- (ear)and (A)byte (eam) <-- (eam)and (A)

byte (A) <-- (A) or imm8byte (A) <-- (A) or (ear)byte (A) <-- (A) or (eam)byte (ear) <-- (ear)or (A)byte (eam) <-- (eam)or (A)

byte (A) <-- (A) xor imm8 byte (A) <-- (A) xor (ear)byte (A) <-- (A) xor (eam)byte (ear) <-- (ear)xor (A)byte (eam) <-- (eam)xor (A)byte (A) <-- not (A)byte (ear) <-- not (ear)byte (eam) <-- not (eam)

-----

-----

--------

-----

-----

--------

-----

-----

--------

-----

-----

--------

-----

-----

--------

*****

*****

********

*****

*****

********

RRRRR

RRRRR

RRRRRRRR

-----

-----

--------

----*

----*

----*--*

ANDWANDWANDWANDWANDWANDW

ORWORWORWORWORWORW

XORWXORWXORWXORWXORWXORWNOTWNOTWNOTW

AA,#imm16A,earA,eamear,Aeam,A

AA,#imm16A,earA,eamear,Aeam,A

AA,#imm16A,earA,eam ear,Aeam,AAeaream

1322+22+

1322+22+

1322+22+122+

2234+(a)35+(a)

2234+(a)35+(a)

2234+(a)35+(a)235+(a)

001020

001020

001020020

000(c)02×(c)

000(c)02×(c)

000(c)02×(c)002×(c)

word (A) <-- (AH) and (A)word (A) <-- (A) and imm16word (A) <-- (A) and (ear)word (A) <-- (A) and (eam)word (ear) <-- (ear)and (A)word (eam) <-- (eam)and (A)

word (A) <-- (AH) or (A)word (A) <-- (A) or imm16word (A) <-- (A) or (ear)word (A) <-- (A) or (eam)word (ear) <-- (ear)or (A)word (eam) <-- (eam)or (A)

word (A) <-- (AH) xor (A)word (A) <-- (A) xor imm16word (A) <-- (A) xor (ear)word (A) <-- (A) xor (eam)word (ear) <-- (ear)xor (A)word (eam) <-- (eam)xor (A) word (A) <-- not (A)word (ear) <-- not (ear)word (eam) <-- not (eam)

------

------

--------

------

------

--------

------

------

--------

------

------

--------

------

------

--------

******

******

********

******

******

********

RRRRRR

RRRRR

RRRRRRRRR

------

------

--------

-----*

-----*

----*--*


459


Table D.8-8 Logic Instructions 2 (Long) (6 Instructions)


AH

I S T N Z V C RMW

ANDLANDL

ORLORL

XORLXORL

A,earA,eam

A,earA,eam

A,earA,eam

22+

22+

22+

67+(a)

67+(a)

67+(a)

20

20

20

0(d)

0(d)

0(d)

long (A) <-- (A) and (ear)long (A) <-- (A) and (eam)

long (A) <-- (A) or (ear)long (A) <-- (A) or (eam)

long (A) <-- (A) xor (ear)long (A) <-- (A) xor (eam)

--

--

--

--

--

--

--

--

--

--

--

--

--

--

--

**

**

**

**

**

**

RR

RR

RR

--

--

--

--

--

--


Table D.8-9 Sign Inversion Instructions (Byte and Word) (6 Instructions)


AH

I S T N Z V C RMW

NEG

NEGNEG

A

eaream

1

22+

2

35+(a)

0

20

0

02×(b)

byte (A) <-- 0 - (A)

byte (ear) <-- 0 - (ear)byte (eam) <-- 0 - (eam)

X

--

-

--

-

--

-

--

-

--

*

**

*

**

*

**

*

**

-

-*

NEGW

NEGWNEGW

A

eaream

1

22+

2

35+(a)

0

20

0

02×(c)

word (A) <-- 0 - (A)

word (ear) <-- 0 - (ear)word (eam) <-- 0 - (eam)

-

--

-

--

-

--

-

--

-

--

*

**

*

**

*

**

*

**

-

-*


Table D.8-10 Normalize Instruction (Long) (1 Instruction)


AH

I S T N Z V C RMW

NRML A,R0 2 **1 1 0 long (A) <-- Shift up to the location of the first 1.byte (RD) <-- Shift count at that time

- - - - - - * - - -

**1:Note:

If the accumulator is all zero, 4. Otherwise, 6 + (R0).For (a) to (d) in the table, see Table D.5-1 "Execution Cycle Counts for Each Addressing Method of Execution Addresses" and Table D.5-2 "Correction Values of Number of Cycles for Calculating the Execution Cycle Count".

460


Table D.8-11 Shift Instructions (Byte, Word, and Long) (18 Instructions)

Mnemonic # RG

B Operation LH

AH

I S T N Z V C RMW

RORCROLC

RORCRORCROLCROLC

ASRLSRLSL

AA

eareameaream

A,R0A,R0A,R0

22

22+22+

222

22

35+(a)35+(a)

**1**1**1

00

2020

111

00

02×(b)02×(b)

000

byte (A) <-- With right rotate carrybyte (A) <-- With left rotate carry

byte (ear) <-- With right rotate carrybyte (eam) <-- With right rotate carrybyte (ear) <-- With left rotate carrybyte (eam) <-- With left rotate carry

byte (A) <-- Arithmetic right barrel shift (A,1 bit)byte (A) <-- Logical right barrel shift (A,R0)byte (A) <-- Logical left barrel shift (A,R0)

--

----

---

--

----

---

--

----

---

--

----

---

--

----

**-

**

****

***

**

****

***

--

----

---

**

****

***

--

-*-*

---

ASRWLSRWLSLW

ASRW LSRWLSLW

AA/SHRW AA/SHLW A

A,R0A,R0A,R0

111

222

222

**1**1**1

000

111

000

000

word (A) <-- Arithmetic right shift (A, 1 bit)word (A) <-- Logical right shift (A, 1 bit)word (A) <-- Logical left shift (A, 1 bit)

word (A) <-- Arithmetic right barrel shift (A, R0)word (A) <-- Logical right barrel shift (A, R0)word (A) <-- Logical left barrel shift (A, R0)

---

---

---

---

---

---

---

---

**-

**-

*R*

***

***

***

---

---

***

***

---

---

ASRLLSRLLSLL

A,R0A,R0A,R0

2 22

**2**2**2

111

000

long (A) <-- Arithmetic right barrel shift (A, R0)long (A) <-- Logical right barrel shift (A, R0)long (A) <-- Logical left barrel shift (A, R0)

---

---

---

---

**-

***

***

---

***

---

**1 If R0 is 0, 6. Otherwise, 5 + (R0).

**2 If R0 is 0, 6. Otherwise, 6 + (R0).


461


Table D.8-12 Branch Instructions 1 (31 Instructions)


AH

I S T N Z V C RMW

BZ/BEQBNZ/BNEBC/BLOBNC/BHSBNBPBVBNVBT BNTBLTBGEBLEBGTBLSBHIBRA

rel relrel relrelrelrelrelrelrel relrelrelrelrelrelrel

22222222222222222

**1**1**1**1**1**1**1**1**1**1**1**1**1**1**1**1**1

00000000000000000

00000000000000000

Branch at (Z) = 1Branch at (Z) = 0Branch at (C) = 1Branch at (C) = 0Branch at (N) = 1Branch at (N) = 0Branch at (V) = 1Branch at (V) = 0Branch at (T) = 1Branch at (T) = 0Branch at (V) xor (N) = 1Branch at (V) xor (N) = 0((V) xor (N)) or (Z) = 1((V) xor (N)) or (Z) = 0Branch at (C) or (Z) = 1Branch at (C) or (Z) = 0Unconditional branch

-----------------

-----------------

-----------------

-----------------

-----------------

-----------------

-----------------

-----------------

-----------------

-----------------

JMPJMPJMPJMPJMPPJMPPJMPP

@Aaddr16@ear@eam@ear *1@eam *1addr24

1322+22+4

2334+(a)56+(a)4

0010200

000(c)0(d)0

word (PC) <-- (A)word (PC) <-- addr16word (PC) <-- (ear)word (PC) <-- (eam)word (PC) <-- (ear), (PCB) <-- (ear+2)word (PC) <-- (eam), (PCB) <-- (eam+2)word(PC) <-- ad24 0-15,(PCB) <-- ad24 16-23

-------

-------

-------

-------

-------

-------

-------

-------

-------

-------

CALLCALLCALLCALLVCALLP

CALLP

@ear *2@eam *2addr16 *3#vct4 *3@ear *4

@eam *4

22+312

2+

67+(a)6710

11+(a)

10002

0

(c)2×(c)(c)2×(c)2×(c)

**2

word (PC) <-- (ear)word (PC) <-- (eam)word (PC) <-- addr16Vector call instructionword(PC) <-- (ear)0-15,(PCB) <-- (ear)16-23word(PC) <-- (eam)0-15,(PCB) <-- (eam)16-23

-----

-

-----

-

-----

-

-----

-

-----

-

-----

-

-----

-

-----

-

-----

-

-----

-

CALLP addr24 *5 4 10 0 2×(c) word(PC) <-- addr0-15, (PCB) <-- addr16-23

- - - - - - - - - -

**1: If branching is performed, 4. If branching is not performed, 3.

**2: 3 x (c) + (b)

*1: Read (word) branch destination address

*2: W: Save (word) to stack, R: Read (word) branch destination address

*3: Save (word) to stack

*4: W: Save (long) to stack, R: Read (long) branch destination address

*5: W: Save (long) to stack


462


Table D.8-13 Branch Instructions 2 (19 Instructions)

Mnemonic # RG

B Operation LH

AH

I S T N Z V C RMW

CBNECWBNE

A,#imm8,relA,#imm16,rel

34

**1**1

00

00

Branch at byte (A) not equal to imm8Branch at word (A) not equal to imm16

--

--

--

--

--

**

**

**

**

--

CBNECBNECWBNECWBNE

ear,#imm8,releam,#imm8,rel *3ear,#imm16,releam,#imm16,rel*3

44+55+

**2**3**4**3

1010

0(b)0(c)

Branch at byte (ear) not equal to imm8Branch at byte (eam) not equal to imm8Branch at word (ear) not equal to imm16Branch at word (eam) not equal to imm16

----

----

----

----

----

****

****

****

****

----

DBNZ

DBNZ

ear,rel

eam,rel

3

3+

**5

**6

2

2

0

2×(b)

Branch at byte (ear) = (ear) - 1, (ear)not equal to 0Branch at byte (eam) = (eam) - 1, (eam) not equal to 0

-

-

-

-

-

-

-

-

-

-

*

*

*

***

-

-

-

*

DWBNZ

DWBNZ

ear,rel

eam,rel

3

3+

**5

**6

2

2

0

2×(c)

Branch at word (ear) = (ear) - 1, (ear) not equal to 0Branch at word (eam) = (eam) - 1, (eam) not equal to 0

-

-

-

-

-

-

-

-

-

-

*

*

*

*

*

*

-

-

-

*

INTINTINTPINT9RETI

#vct8addr16addr24

23411

2016172015

00000

8×(c)6×(c)6×(c)8×(c)6×(c)

Software interruptSoftware interruptSoftware interruptSoftware interruptReturn from interrupt

-----

-----

RRRR*

SSSS*

----*

----*

----*

----*

----*

-----

LINK #imm8 2 6 0 (c) At function entrance, the old frame pointer is saved to the stack, the new frame pointer is set, and the area of the local pointer is confirmed.

- - - - - - - - - -

UNLINK 1 5 0 (c) At function exit, the old frame pointer is returned from the stack.

- - - - - - - - - -

RET RETP

*1*2

11

46

00

(c)(d)

Return from subroutineReturn from subroutine

--

--

--

--

--

--

--

--

--

--



**3: If branching is performed, 7 + (a). If branching is not performed, 6 + (a).



**6: If branching is performed, 8 + (a). If branching is not performed, 7 + (a).

*1: Return (word) from stack

*2: Return (long) from stack

*3: For the CBNE and CWBNE instructions, do not use in RWj+ addressing mode.


463


Table D.8-14 Other Control Instructions (Byte, Word, and Long) (28 Instructions)


AH

I S T N Z V C RMW

PUSHWPUSHWPUSHWPUSHW

AAHPSrlst

1112

444**3

000

(c)(c)(c)**4

word (SP) <-- (SP) - 2 , ((SP)) <-- (A)word (SP) <-- (SP) - 2 , ((SP)) <-- (AH)word (SP) <-- (SP) - 2 , ((SP)) <-- (PS)(SP) <-- (SP) - 2n , ((SP)) <-- (rlst)

----

----

----

----

----

----

----

----

----

----

POPWPOPWPOPWPOPW

AAHPSrlst

1112

334**2

000

(c)(c)(c)**4

word (A) <-- ((SP)) , (SP) <-- (SP) + 2word (AH) <-- ((SP)) , (SP) <-- (SP) + 2word (PS) <-- ((SP)) , (SP) <-- (SP) + 2(rlst) <-- ((SP)) , (SP) <-- (SP)

----

*---

--*-

--*-

--*-

--*-

--*-

--*-

--*-

----

JCTX @A 1 14 0 6×(c) Context switch instruction - - * * * * * * * -

ANDOR

CCR,#imm8CCR,#imm8

22

33

00

00

byte (CCR) <-- (CCR) and imm8byte(CCR) <-- (CCR) or imm8

--

--

**

**

**

**

**

**

**

--

MOVMOV

RP,#imm8ILM,#imm8

22

22

00

00

byte (RP) <-- imm8byte (ILM) <-- imm8

--

--

--

--

--

--

--

--

--

--

MOVEAMOVEAMOVEAMOVEA

RWi,earRWi,eamA,earA,eam

22+22+

32+(a)11+(a)

1100

0000

word (RWi) <-- earword (RWi) <-- eamword (A) <-- earword (A) <-- eam

----

--**

----

----

----

----

----

----

----

----

ADDSPADDSP

#imm8#imm16

23

33

00

00

word (SP) <-- ext(imm8)word (SP) <-- imm16

--

--

--

--

--

--

--

--

--

--

MOVMOV

A,brg1brg2,A

22

**11

00

00

byte (A) <-- (brg1)byte (brg2) <-- (A)

Z-

*-

--

--

--

**

**

--

--

--

NOPADBDTBPCBSPBNCCCMR

1111111

1111111

0000000

0000000

No operationPrefix code for AD space accessPrefix code for DT space accessPrefix code for PC space accessPrefix code for SP space accessPrefix code for flag no-changePrefix code for common register bank

-------

-------

-------

-------

-------

-------

-------

-------

-------

-------

**1: PCB, ADB, SSB, USB: 1, DTB, DPR: 2

**2: 7 + 3 x (pop count) + 2 x (last register number for pop operations). If RLST = 0 (no transfer register, 7.

**3: 29 + 3 x (push count) - 3 x (last register number for push operations). If RLST = 0 (no transfer register), 8.

**4: (pop count) x (c) or (push count) x (c)


464


Table D.8-15 Bit Manipulation Instructions (21 Instructions)


AH

I S T N Z V C RMW

MOVBMOVBMOVB

A,dir:bpA,addr16:bpA,io:bp

343

554

000

(b)(b)(b)

byte (A) <-- ( dir:bp )bbyte (A) <-- ( addr16:bp )bbyte (A) <-- ( io:bp )b

ZZZ

***

---

---

---

***

***

---

---

---

MOVBMOVBMOVB

dir:bp,Aaddr16:bp,Aio:bp,A

343

776

000

2×(b)2×(b)2×(b)

bit ( dir:bp )b <-- (A)bit ( addr16:bp )b <-- (A)bit ( io:bp )b <-- (A)

---

---

---

---

---

***

***

---

---

***

SETBSETBSETB

dir:bpaddr16:bpio:bp

343

777

000

2×(b)2×(b)2×(b)

bit ( dir:bp )b <-- 1bit ( addr16:bp )b <-- 1bit ( io:bp )b <-- 1

---

---

---

---

---

---

---

---

---

***

CLRBCLRBCLRB

dir:bpaddr16:bpio:bp

343

777

000

2×(b)2×(b)2×(b)

bit ( dir:bp )b <-- 0bit ( addr16:bp )b <-- 0bit ( io:bp )b <-- 0

---

---

---

---

---

---

---

---

---

***

BBCBBCBBC

dir:bp,reladdr16:bp,relio:bp,rel

454

**1**1**2

000

(b)(b)(b)

Branch at (dir:bp) b = 0Branch at (addr16:bp) b = 0Branch at (io:bp) b = 0

---

---

---

---

---

---

***

---

---

---

BBSBBSBBS

dir:bp,reladdr16:bp,relio:bp,rel

454

**1**1**2

000

(b)(b)(b)

Branch at (dir:bp) b = 1Branch at (addr16:bp) b = 1Branch at (io:bp) b = 1

---

---

---

---

---

---

***

---

---

---

SBBS addr16:bp,rel 5 **3 0 2×(b) Branch at (addr16:bp) b = 1, bit = 1 - - - - - - * - - *

WBTS io:bp 3 **4 0 **5 Wait until (io:bp) b = 1 - - - - - - - - - -

WBTC io:bp 3 **4 0 **5 Wait until (io:bp) b = 0 - - - - - - - - - -



**3: If the condition is established, 10. If the condition is not established, 9.

**4: Undefined count

**5: Until the condition is established.


Table D.8-16 Accumulator Operation Instructions (Byte and Word) (6 Instructions)


AH

I S T N Z V C RMW

SWAPSWAPW/XCHW A,TEXTEXTWZEXTZEXTW

111111

321211

000000

000000

byte (A)0-7 <--> (A)8-15word (AH) <--> (AL)Byte sign-extensionWord sign-extensionByte zero extensionWord zero extensionbyte

--X-Z-

-*-X-Z

------

------

------

--**RR

--****

------

------

------

465


Table D.8-17 String Instructions (10 Instructions)


AH

I S T N Z V C RMW

MOVS / MOVSI MOVSD

SCEQ / SCEQISCEQD

FILS / FILSI

22

22

2

**2**2

**1**1

6m+6

**3**3

**4**4

**3

byte transfer @AH+ <-- @AL+, counter = RW0byte transfer @AH- <-- @AL-, counter = RW0

byte retrieval @AH+ <-- AL, counter RW0byte retrieval @AH- <-- AL, counter RW0

byte fill @AH+ <-- AL, counter RW0

--

--

-

--

--

-

--

--

-

--

--

-

--

--

-

--

**

*

--

**

*

--

**

-

--

**

-

--

--

-

MOVSW / MOVSWI

MOVSWD

SCWEQ / SCWEQI

SCWEQD

FILSW / FILSWI

2

2

2

2

2

**2

**2

**1

**1

6m+6

**6

**6

**7

**7

**6

word transfer @AH+ <-- @AL+, counter = RW0

word transfer @AH- <-- @AL-, counter = RW0

word retrieval @AH+ -| AL, counter = RW0

word retrieval @AH- -| AL, counter = RW0

word fill @AH+ <-- AL, counter = RW0

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

*

*

*

-

-

*

*

*

-

-

*

*

-

-

-

*

*

-

-

-

-

-

-

**1: If RW0 is 0, 5. At count out, 4 + 7 x (RW0). At matching, 7n + 5.

**2: If RW0 is 0, 5. Otherwise, 4 + 8 x (RW0).

**3: (b) x (RW0) If the source and destination access different areas, calculate item (b) separately for each.

**4: (b) × n

**5: 2 × (RW0)

**6: (c) x (RW0) + (c) x (RW0) If the source and destination access different areas, calculate item (c) separately for each.

**7: (c) × n

**8: 2 × (RW0)

Note: m: RW0 value (counter value)n: Looped count


466


D.9 Instruction Maps

The F2MC-16 L instruction codes consist of one or two bytes. The instruction maps consist of multiple pages. Table D.9-2 "Basic Page Map" to Table D.9-21 "XCHW RWi,

ea Instruction 4 (First Byte = 7F H)" list the instruction maps of the F 2MC-16 L.

Instruction Map Structure

Figure D.9-1 Instruction Map Structure

Instructions that consist of only one byte (such as the NOP instruction) are completed within thebasic page. For instructions requiring two bytes (such as the MOVS instruction), the presenceof the map for the second byte is detected when the first byte is accessed. The map for thesecond byte can then be accessed to check the second byte. Figure D.9-2 "Correspondencebetween Instruction Codes and Instruction Maps" shows the correspondence between theactual instruction codes and instruction maps.

Basic page map : First byte

Bit manipulationinstructions

String manipulation instructions

Two-byte instructions ea instructions x 9 : Second byte

467


Figure D.9-2 Correspondence between Instruction Codes and Instruction Maps

Table D.9-1 "Instruction Code Examples" provides examples of instruction codes.

Table D.9-1 Instruction Code Examples

Instruction First byte (from basic page map)

Second byte (from extended

page map)

NOP 00+0=00 -

AND A, #8 30+4=34 -

MOV A, ADB 60+F=6F 00+0=00

@RW2+d8, #8, rel 70+0=70 F0+2=F2

XY

+Z

UV

+W

Instructioncode First byte Second byte Operand Operand

May not be presentdepending on the instruction.

The length dependson the instruction.

[Basic page map]

[Extended page map *1]

*1: The extended page map is the generic name for the maps of bit manipulation, string manipulation, two-byte, and ea instructions. In actuality, there are multiple extended page maps depending on the instruction type.

468


Table D.9-2 Basic Page Map

0010

2030

4050

6070

8090

A0

B0

C0

D0

E0

F0

NO

P

INT

9

AD

DD

C

A

NE

G

A

PC

B

DT

B

AD

B

SP

B

LIN

K

#im

m8

UN

LIN

K

MO

V

RP

,#8

NE

GW

A

LSLW

A

AS

RW

A

LSR

W

A

CM

R

NC

C

SU

BD

C

A

JCT

X

@

A

EX

T

ZE

XT

SW

AP

AD

DS

P

#8

AD

DL

A,#

32

SU

BL

A,#

32

MO

V

ILM

,#8

CM

PL

A,#

32

EX

TW

ZE

XT

W

SW

AP

W

AD

DS

P

#

16

AD

D

A

,dir

SU

B

A

,dir

AD

DC

A

CM

P

A

AN

D

C

CR

,#8

OR

C

CR

,#8

DIV

U

A

MU

LU

A

AD

DW

A

SU

BW

A

CB

NE

A,

#8,

rel

CM

PW

A

AN

DW

A

OR

W

A

XO

RW

A

MU

LUW

A

AD

D

A

,#8

SU

B

A

,#8

SU

BC

A

CM

P

A

,#8

AN

D

A

,#8

OR

A

,#8

XO

R

A

,#8

NO

T

A

AD

DW

A,#

16

SU

BW

A,#

16

CW

BN

E A

,

#16

,rel

CM

PW

A,#

16

AN

DW

A,#

16

OR

W

A,#

16

XO

RW

A,#

16

NO

TW

A

MO

V

A

,dir

MO

V

d

ir,A

MO

V

A

,#8

MO

VX

A

,#8

MO

V

dir,

#8

MO

VX

A

,dir

MO

VW

A

,SP

MO

VW

S

P,A

MO

VW

A

,dir

MO

VW

di

r,A

MO

VW

A,#

16

MO

VL

A,#

32

PU

SH

W

A

PU

SH

W

AH

PU

SH

W

PS

PU

SH

W

rlst

MO

V

A

,io

MO

V

i

o,A

MO

V

A

,add

r16

MO

V

ad

dr16

,A

MO

V

io

,#8

MO

VX

A

,io

MO

VW

io,

#16

MO

VX

A

,add

r16

MO

VW

A

,io

MO

VW

i

o,A

MO

VW

A

,add

r16

MO

VW

ad

dr16

,A

PO

PW

A

PO

PW

AH

PO

PW

PS

PO

PW

rls

t

BR

A

rel

JMP

@A

JMP

add

r16

JMP

P

add

r24

CA

LL

add

r16

CA

LLP

add

r24

RE

TP

RE

T

INT

#

vct8

INT

add

r16

INT

P

add

r24

RE

TI

MO

VE

A

RW

i,ea

MO

V

R

i,ea

MO

VW

RW

i,ea

MO

V

ea

,Ri

MO

VW

ea,R

Wi

XC

H

R

i,ea

XC

HW

RW

i,ea

MO

V

A

,Ri

MO

VW

A,R

Wi

MO

V

R

i,A

MO

VW

RW

i,A

MO

V

R

i,#8

MO

VW

R

Wi,#

16

MO

VX

A

,Ri

MO

VW

A,

@

RW

i+d8

MO

VX

A,

@R

Wi+

d8

MO

VW @

R

Wi+

d8,A

MO

VN

A

,#4

CA

LLV

#4

BZ

/BE

Q

rel

BN

Z/B

NE

re

l

BC

/BLO

rel

BN

C /B

HS

re

l

BN

rel

BP

rel

BV

rel

BN

V

rel

BT

rel

BN

T

rel

BLT

rel

BG

E

rel

BLE

rel

BG

T

rel

BLS

rel

BH

I

rel

ea

inst

ruct

ion

1

ea

inst

ruct

ion

2

ea

inst

ruct

ion

3

ea

inst

ruct

ion

4

ea

inst

ruct

ion

5

ea

inst

ruct

ion

6

ea

inst

ruct

ion

7

ea

inst

ruct

ion

8

ea

inst

ruct

ion

9

Bit

man

ipu-

latio

n in

stru

ctio

n

Str

ing

man

ipu

latio

n in

s-tr

uctio

n

Tw

o-by

te

inst

ruct

ion

+0

+1

+2

+3

+4

+5

+6

+7

+8

+9

+A

+B

+C

+D +E +F

469


Table D.9-3 Bit Manipulation Instruction Map (First Byte = 6C H)

MO

VB

A,io

:bp

MO

VB

A,d

ir:bp

MO

VB

A,

ad

dr16

:bp

MO

VB

io:b

p,A

MO

VB

dir:

bp,A

MO

VB

addr

16:b

p,A

CLR

B

io

:bp

CLR

B

dir:

bp

CLR

B

add

r16:

bp

SE

TB

io

:bp

SE

TB

dir:

bp

SE

TB

ad

dr16

:bp

BB

C

io

:bp,

rel

BB

C

d

ir:bp

,rel

BB

C a

d16

:bp

,rel

BB

S

io

:bp,

rel

BB

S

d

ir:bp

,rel

BB

S a

d16

:bp

,rel

WB

TS

io

:bp

WB

TC

io

:bp

SB

BS

ad

dr16

:bp

0010

2030

4050

6070

8090

A0

B0

C0

D0

E0

F0

+0

+1

+2

+3

+4

+5

+6

+7

+8

+9

+A

+B

+C

+D +E +F

470


Table D.9-4 String Manipulation Instruction Map (First Byte = 6E H)

MO

VS

I M

OV

SD

MO

VS

WI

MO

VS

WD

PC

B,P

CB

PC

B,D

TB

PC

B,A

DB

PC

B,S

PB

DTB

,PC

B

DTB

,DTB

DTB

,AD

B

DTB

,SP

B

AD

B,P

CB

AD

B,D

TB

AD

B,A

DB

AD

B,S

PB

SP

B,P

CB

SP

B,D

TB

SP

B,A

DB

SP

B,S

PB

PC

B

DTB

AD

B

SP

B

SC

EQ

I P

CB

DTB

AD

B

SP

B

SC

EQ

D P

CB

DTB

AD

B

SP

B

SC

WE

QI

PC

B

DTB

AD

B

SP

B

SC

WE

QD

PC

B

DTB

AD

B

SP

B

FILS

I P

CB

DTB

AD

B

SP

B

FILS

WI

0010

2030

4050

6070

8090

A0

B0

C0

D0

E0

F0

+0

+1

+2

+3

+4

+5

+6

+7

+8

+9

+A

+B

+C

+D +E +F

471


Table D.9-5 Two-Byte Instruction Map (First Byte = 6F H)

0010

2030

4050

6070

8090

A0

B0

C0

D0

E0

F0

MO

V

A,

DTB

MO

V

A,

ADB

MO

V

A,

SSB

MO

V

A,

USB

MO

V

A,

DPR

MO

V

A

,@A

MO

V

A,

PCB

RO

LC

A

LSLW

A,R

0

MO

VW

A

,@A

ASR

W

A,R

0

LSR

W

A,R

0

MO

V

D

TB,A

MO

V

AD

B,A

MO

V

SS

B,A

MO

V

U

SB,A

MO

V

D

PR,A

MO

V

@AL

,AH

MO

VX

A

,@A

RO

RC

A

LSLL

A,R

0

MO

VW

@AL

,AH

ASR

L

A,R

0

LSR

L

A,R

0

MO

VX A

,

@

RL0

+d8

MO

VX A

,

@

RL1

+d8

MO

VX A

,

@

RL2

+d8

MO

VX A

,

@

RL3

+d8

LSL

A,R

0

NR

ML

A,R

0

ASR

A,R

0

LSR

A,R

0

MO

V @

RL0

+d8,

A

MO

V @

RL1

+d8,

A

MO

V @

RL2

+d8,

A

MO

V @

RL3

+d8,

A

MO

VW @

RL

0+d8

,A

MO

VW @

RL

1+d8

,A

MO

VW @

RL

2+d8

,A

MO

VW @

RL

3+d8

,A

MO

V

A

,

@

RL0

+d8

MO

V

A

,

@

RL1

+d8

MO

V

A

,

@

RL2

+d8

MO

V

A

,

@

RL3

+d8

MO

VW

A,

@

RL0

+d8

MO

VW

A,

@

RL1

+d8

MO

VW

A,

@

RL2

+d8

MO

VW

A,

@

RL3

+d8

+0

+1

+2

+3

+4

+5

+6

+7

+8

+9

+A

+B

+C

+D +E +F

472


Table D.9-6 ea Instruction 1 (First Byte = 70 H)

0010

2030

4050

6070

8090

A0

B0

C0

D0

E0

F0

+0

+1

+2

+3

+4

+5

+6

+7

+8

+9

+A

+B

+C

+D +E +F

ADD

L

A

,RL0

ADD

L

A

,RL0

ADD

L

A

,RL1

ADD

L

A

,RL1

ADD

L

A

,RL2

ADD

L

A

,RL2

ADD

L

A

,RL3

ADD

L

A

,RL3

ADD

L

A

,@R

W0

ADD

L

A

,@R

W1

ADD

L

A

,@R

W2

ADD

L

A

,@R

W3

ADD

L

A,

@R

W0+

ADD

L

A,

@R

W1+

ADD

L

A,

@R

W2+

ADD

L

A,

@R

W3+

ADD

L

A,

@R

W0+

d8

ADD

L

A,

@R

W1+

d8

ADD

L

A,

@R

W2+

d8

ADD

L

A,

@R

W3+

d8

ADD

L

A,

@R

W4+

d8

ADD

L

A,

@R

W5+

d8

ADD

L

A,

@R

W6+

d8

ADD

L

A,

@R

W7+

d8

ADD

L

A,

@R

W0+

d16

ADD

L

A,

@R

W1+

d16

ADD

L

A,

@R

W2+

d16

ADD

L

A,

@R

W3+

d16

ADD

L

A,

@R

W0+

RW

7

ADD

L

A,

@R

W1+

RW

7

ADD

L

A,

@PC

+d16

ADD

L

A,

a

ddr1

6

SUBL

A

,RL0

SUBL

A

,RL0

SUBL

A

,RL1

SUBL

A

,RL1

SUBL

A

,RL2

SUBL

A

,RL2

SUBL

A

,RL3

SUBL

A

,RL3

SUBL

A

,@R

W0

SUBL

A

,@R

W1

SUBL

A

,@R

W2

SUBL

A

,@R

W3

SUBL

A,

@R

W0+

SUBL

A,

@R

W1+

SUBL

A,

@R

W2+

SUBL

A,

@R

W3+

SUBL

A,

@R

W0+

d8

SUBL

A,

@R

W1+

d8

SUBL

A,

@R

W2+

d8

SUBL

A,

@R

W3+

d8

SUBL

A,

@R

W4+

d8

SUBL

A,

@R

W5+

d8

SUBL

A,

@R

W6+

d8

SUBL

A,

@R

W7+

d8

SUBL

A,

@R

W0+

d16

SUBL

A,

@R

W1+

d16

SUBL

A,

@R

W2+

d16

SUBL

A,

@R

W3+

d16

SUBL

A,

@R

W0+

RW

7

SUBL

A,

@R

W1+

RW

7

SUBL

A,

@PC

+d16

SUBL

A,

a

ddr1

6

CW

BNE

RW

0,

#16,

rel

RW

1,

#16,

rel

RW

2,

#16,

rel

RW

3,

#16,

rel

RW

4,

#16,

rel

RW

5,

#16,

rel

RW

6,

#16,

rel

RW

7,

#16,

rel

@

RW

0,

#16,

rel

@

RW

1,

#16,

rel

@

RW

2,

#16,

rel

@

RW

3,

#16,

rel

CW

BNE

@R

W0+

d8,

#16

,rel

@R

W1+

d8,

#16

,rel

@R

W2+

d8,

#16

,rel

@R

W3+

d8,

#16

,rel

@R

W4+

d8,

#16

,rel

@R

W5+

d8,

#16

,rel

@R

W6+

d8,

#16

,rel

@R

W7+

d8,

#

16,re

l

@R

W0+

d16

,

#

16,re

l

@R

W1+

d16

,

#

16,re

l

@R

W2+

d16

,

#

16,re

l

@R

W3+

d16

,

#

16,re

l

@R

W0+

RW

7

,

#

16,re

l

@R

W1+

RW

7

,

#

16,re

l

@PC

+d16

,

#

16,re

l

addr

16,

#

16,re

l

CM

PL

A,

RL0

CM

PL

A,

RL0

CM

PL

A,

RL1

CM

PL

A,

RL1

CM

PL

A,

RL2

CM

PL

A,

RL2

CM

PL

A,

RL3

CM

PL

A,

RL3

CM

PL

A

,@R

W0

CM

PL

A

,@R

W1

CM

PL

A

,@R

W2

CM

PL

A

,@R

W3

CM

PL

A,

@R

W0+

CM

PL

A,

@R

W1+

CM

PL

A,

@R

W2+

CM

PL

A,

@R

W3+

CM

PL

A,

@R

W0+

d8

CM

PL

A,

@R

W1+

d8

CM

PL

A,

@R

W2+

d8

CM

PL

A,

@R

W3+

d8

CM

PL

A,

@R

W4+

d8

CM

PL

A,

@R

W5+

d8

CM

PL

A,

@R

W6+

d8

CM

PL

A,

@R

W7+

d8

CM

PL

A,

@R

W0+

d16

CM

PL

A,

@R

W1+

d16

CM

PL

A,

@R

W2+

d16

CM

PL

A,

@R

W3+

d16

CM

PL

A,

@R

W0+

RW

7

CM

PL

A,

@R

W1+

RW

7

CM

PL

A,

@PC

+d16

CM

PL

A,

a

ddr1

6

AND

L

A,

RL0

AND

L

A,

RL0

AND

L

A

,RL1

AND

L

A,

RL1

AND

L

A,

RL2

AND

L

A,

RL2

AND

L

A,

RL3

AND

L

A,

RL3

AND

L

A

,@R

W0

AND

L

A

,@R

W1

AND

L

A

,@R

W2

AND

L

A

,@R

W3

AND

L

A,

@R

W0+

AND

L

A,

@R

W1+

AND

L

A,

@R

W2+

AND

L

A,

@R

W3+

AND

L

A,

@R

W0+

d8

AND

L

A,

@R

W1+

d8

AND

L

A,

@R

W2+

d8

AND

L

A,

@R

W3+

d8

AND

L

A,

@R

W4+

d8

AND

L

A,

@R

W5+

d8

AND

L

A,

@R

W6+

d8

AND

L

A,

@R

W7+

d8

AND

L

A,

@R

W0+

d16

AND

L

A,

@R

W1+

d16

AND

L

A,

@R

W2+

d16

AND

L

A,

@R

W3+

d16

AND

L

A,

@R

W0+

RW

7

AND

L

A,

@R

W1+

RW

7

AND

L

A,

@PC

+d16

AND

L

A,

a

ddr1

6

OR

L

A,

RL0

OR

L

A

,RL0

OR

L

A

,RL1

OR

L

A

,RL1

OR

L

A

,RL2

OR

L

A

,RL2

OR

L

A

,RL3

OR

L

A

,RL3

OR

L

A

,@R

W0

OR

L

A

,@R

W1

OR

L

A

,@R

W2

OR

L

A

,@R

W3

OR

L

A,

@R

W0+

OR

L

A,

@R

W1+

OR

L

A,

@R

W2+

OR

L

A,

@R

W3+

OR

L

A,

@R

W0+

d8

OR

L

A,

@R

W1+

d8

OR

L

A,

@R

W2+

d8

OR

L

A,

@R

W3+

d8

OR

L

A,

@R

W4+

d8

OR

L

A,

@R

W5+

d8

OR

L

A,

@R

W6+

d8

OR

L

A,

@R

W7+

d8

OR

L

A,

@R

W0+

d16

OR

L

A,

@R

W1+

d16

OR

L

A,

@R

W2+

d16

OR

L

A,

@R

W3+

d16

OR

L

A,

@R

W0+

RW

7

OR

L

A,

@R

W1+

RW

7

OR

L

A,

@PC

+d16

OR

L

A,

ad

dr16

XOR

L

A

,RL0

XOR

L

A

,RL0

XOR

L

A

,RL1

XOR

L

A

,RL1

XOR

L

A

,RL2

XOR

L

A

,RL2

XOR

L

A

,RL3

XOR

L

A

,RL3

XOR

L

A

,@R

W0

XOR

L

A

,@R

W1

XOR

L

A

,@R

W2

XOR

L

A

,@R

W3

XOR

L

A,

@R

W0+

XOR

L

A,

@R

W1+

XOR

L

A,

@R

W2+

XOR

L

A,

@R

W3+

XOR

L A

,

@R

W0+

d8

XOR

L A

,

@R

W1+

d8

XOR

L A

,

@R

W2+

d8

XOR

L A

,

@R

W3+

d8

XOR

L A

,

@R

W4+

d8

XOR

L A

,

@R

W5+

d8

XOR

L A

,

@R

W6+

d8

XOR

L A

,

@R

W7+

d8

XOR

L A

,

@R

W0+

d16

XOR

L A

,

@R

W1+

d16

XOR

L A

,

@R

W2+

d16

XOR

L A

,

@R

W3+

d16

XOR

L A

,

@R

W0+

RW

7

XOR

L A

,

@R

W1+

RW

7

XOR

L A

,

@PC

+d16

XOR

L A

,

add

r16

CBN

E

R

0,

#8,

rel

R

1,

#8,

rel

R

2,

#8,

rel

R

3,

#8,

rel

R

4,

#8,

rel

R

5,

#8,

rel

R

6,

#8,

rel

R

7,

#8,

rel

@

RW

0,

#8,

rel

@

RW

1,

#8,

rel

@

RW

2,

#8,

rel

@

RW

3,

#8,

rel

C

BNE

@R

W0+

d8,

#

8,re

l

@R

W1+

d8,

#

8,re

l

@R

W2+

d8,

#

8,re

l

@R

W3+

d8,

#

8,re

l

@R

W4+

d8,

#

8,re

l

@R

W5+

d8,

#

8,re

l

@R

W6+

d8,

#

8,re

l

@R

W7+

d8,

#

8,re

l

@R

W0+

d16

,#

8,re

l

@R

W1+

d16

,#

8,re

l

@R

W2+

d16

,#

8,re

l

@R

W3+

d16

,#

8,re

l

@R

W0+

RW

7

,#

8,re

l

@R

W1+

RW

7

,#

8,re

l

@PC

+d16

,

#

8,re

l

add

r16,

#

8,re

l

Use

pr

ohib

ited

Use

pr

ohib

ited

Use

pr

ohib

ited

Use

pr

ohib

ited

Use

pr

ohib

ited

Use

pr

ohib

ited

Use

pr

ohib

ited

Use

pr

ohib

ited

+

473



0010

2030

4050

6070

8090

A0

B0

C0

D0

E0

F0

+0

+1

+2

+3

+4

+5

+6

+7

+8

+9

+A

+B

+C

+D +E +F

JMPP

@

RL0

JMPP

@

RL0

JMPP

@

RL1

JMPP

@

RL1

JMPP

@

RL2

JMPP

@

RL2

JMPP

@

RL3

JMPP

@

RL3

JMPP

@@

RW

0

JMPP

@@

RW

1

JMPP

@@

RW

2

JMPP

@@

RW

3

JMPP

@

@R

W0+

JMPP

@

@R

W1+

JMPP

@

@R

W2+

JMPP

@

@R

W3+

JMPP

@@

RW

0+d8

JMPP

@@

RW

1+d8

JMPP

@@

RW

2+d8

JMPP

@@

RW

3+d8

JMPP

@@

RW

4+d8

JMPP

@@

RW

5+d8

JMPP

@@

RW

6+d8

JMPP

@@

RW

7+d8

JMPP

@@

RW0+

d16

JMPP

@@

RW1+

d16

JMPP

@@

RW2+

d16

JMPP

@@

RW3+

d16

JMPP

@@

RW0+

RW7

JMPP

@@

RW1+

RW7

JMPP

@@

PC+d

16

JMPP

@ad

dr16

CAL

LP

@

RL0

CAL

LP

@

RL0

CAL

LP

@

RL1

CAL

LP

@

RL1

CAL

LP

@

RL2

CAL

LP

@

RL2

CAL

LP

@

RL3

CAL

LP

@

RL3

CAL

LP

@

@R

W0

CAL

LP

@

@R

W1

CAL

LP

@

@R

W2

CAL

LP

@

@R

W3

CAL

LP

@@

RW

0+

CAL

LP

@@

RW

1+

CAL

LP

@@

RW

2+

CAL

LP

@@

RW

3+

CAL

LP

@@

RW

0+d8

CAL

LP

@@

RW

1+d8

CAL

LP

@@

RW

2+d8

CAL

LP

@@

RW

3+d8

CAL

LP

@@

RW

4+d8

CAL

LP

@@

RW

5+d8

CAL

LP

@@

RW

6+d8

CAL

LP

@@

RW

7+d8

CAL

LP

@

@R

W0+

d16

CAL

LP

@

@R

W1+

d16

CAL

LP

@

@R

W2+

d16

CAL

LP

@

@R

W3+

d16

CAL

LP

@

@R

W0+

RW

7

CAL

LP

@

@R

W1+

RW

7

CAL

LP

@@

PC+d

16

CAL

LP

@

addr

16

INC

L

RL0

INC

L

RL0

INC

L

RL1

INC

L

RL1

INC

L

RL2

INC

L

RL2

INC

L

RL3

INC

L

RL3

INC

L

@R

W0

INC

L

@R

W1

INC

L

@R

W2

INC

L

@R

W3

INC

L

@

RW

0+

INC

L

@

RW

1+

INC

L

@

RW

2+

INC

L

@

RW

3+

INC

L

@R

W0+

d8

INC

L

@R

W1+

d8

INC

L

@R

W2+

d8

INC

L

@R

W3+

d8

INC

L

@R

W4+

d8

INC

L

@R

W5+

d8

INC

L

@R

W6+

d8

INC

L

@R

W7+

d8

INC

L

@R

W0+

d16

INC

L

@R

W1+

d16

INC

L

@R

W2+

d16

INC

L

@R

W3+

d16

INC

L

@R

W0+

RW

7

INC

L

@R

W1+

RW

7

INC

L

@PC

+d16

INC

L

ad

dr16

DEC

L

RL0

DEC

L

RL0

DEC

L

RL1

DEC

L

RL1

DEC

L

RL2

DEC

L

RL2

DEC

L

RL3

DEC

L

RL3

DEC

L

@R

W0

DEC

L

@R

W1

DEC

L

@R

W2

DEC

L

@R

W3

DEC

L

@

RW

0+

DEC

L

@

RW

1+

DEC

L

@

RW

2+

DEC

L

@

RW

3+

DEC

L

@R

W0+

d8

DEC

L

@R

W1+

d8

DEC

L

@R

W2+

d8

DEC

L

@R

W3+

d8

DEC

L

@R

W4+

d8

DEC

L

@R

W5+

d8

DEC

L

@R

W6+

d8

DEC

L

@R

W7+

d8

DEC

L

@R

W0+

d16

DEC

L

@R

W1+

d16

DEC

L

@R

W2+

d16

DEC

L

@R

W3+

d16

DEC

L

@R

W0+

RW

7

DEC

L

@R

W1+

RW

7

DEC

L

@PC

+d16

DEC

L

ad

dr16

MO

VL

A,

RL0

MO

VL

A,

RL0

MO

VL

A,

RL1

MO

VL

A,

RL1

MO

VL

A,

RL2

MO

VL

A,

RL2

MO

VL

A,

RL3

MO

VL

A,

RL3

MO

VL

A

,@R

W0

MO

VL

A

,@R

W1

MO

VL

A

,@R

W2

MO

VL

A

,@R

W3

MO

VL

A,@

RW

0+

MO

VL

A,@

RW

1+

MO

VL

A,@

RW

2+

MO

VL

A,@

RW

3+

MO

VL

A,

@R

W0+

d8

MO

VL

A,

@R

W1+

d8

MO

VL

A,

@R

W2+

d8

MO

VL

A,

@R

W3+

d8

MO

VL

A,

@R

W4+

d8

MO

VL

A,

@R

W5+

d8

MO

VL

A,

@R

W6+

d8

MO

VL

A,

@R

W7+

d8

MO

VL

A,

@R

W0+

d16

MO

VL

A,

@R

W1+

d16

MO

VL

A,

@R

W2+

d16

MO

VL

A,

@R

W3+

d16

MO

VL

A,

@R

W0+

RW

7

MO

VL

A,

@R

W1+

RW

7

MO

VL

A,

@PC

+d16

MO

VL

A,

a

ddr1

6

MO

VL

R

L0,A

MO

VL

R

L0,A

MO

VL

R

L1,A

MO

VL

R

L1,A

MO

VL

R

L2,A

MO

VL

R

L2,A

MO

VL

R

L3,A

MO

VL

R

L3,A

MO

VL

@

RW

0,A

MO

VL

@

RW

1,A

MO

VL

@

RW

2,A

MO

VL

@

RW

3,A

MO

VL

@

RW

0+,A

MO

VL

@R

W1+

,A

MO

VL

@R

W2+

,A

MO

VL

@R

W3+

,A

MO

VL

@R

W0+

d8,A

MO

VL

@R

W1+

d8,A

MO

VL

@R

W2+

d8,A

MO

VL

@R

W3+

d8,A

MO

VL

@R

W4+

d8,A

MO

VL

@R

W5+

d8,A

MO

VL

@R

W6+

d8,A

MO

VL

@R

W7+

d8,A

MO

VL

@R

W0+

d16,

A

MO

VL

@R

W1+

d16,

A

MO

VL

@R

W2+

d16,

A

MO

VL

@R

W3+

d16,

A

MO

VL

@R

W0+

RW

7,A

MO

VL

@R

W1+

RW

7,A

MO

VL

@P

C+d

16,A

MO

VL

addr

16,A

MO

V

R

0,#8

MO

V

R

1,#8

MO

V

R

2,#8

MO

V

R

3,#8

MO

V

R

4,#8

MO

V

R

5,#8

MO

V

R

6,#8

MO

V

R

7,#8

MO

V

@R

W0,

#8

MO

V

@R

W1,

#8

MO

V

@R

W2,

#8

MO

V

@R

W3,

#8

MO

V

@R

W0+

,#8

MO

V

@R

W1+

,#8

MO

V

@R

W2+

,#8

MO

V

@R

W3+

,#8

MO

V

@R

W0+

d8,#

8

MO

V

@R

W1+

d8,#

8

MO

V

@R

W2+

d8,#

8

MO

V

@R

W3+

d8,#

8

MO

V

@R

W4+

d8,#

8

MO

V

@R

W5+

d8,#

8

MO

V

@R

W6+

d8,#

8

MO

V

@R

W7+

d8,#

8

MO

V @

RW

0+d1

6,#8

MO

V @

RW

1+d1

6,#8

MO

V @

RW

2+d1

6,#8

MO

V @

RW

3+d1

6,#8

MO

V @

RW

0+R

W7,

#8

MO

V @

RW

1+R

W7,

#8

MO

V

@P

C+d

16,#

8

MO

V

addr

16,#

8

MO

VEA

A,R

W0

MO

VEA

A,R

W1

MO

VEA

A,R

W2

MO

VEA

A,R

W3

MO

VEA

A,R

W4

MO

VEA

A,R

W5

MO

VEA

A,R

W6

MO

VEA

A,R

W7

MO

VEA

A,@

RW

0

MO

VEA

A,@

RW

1

MO

VEA

A

,@R

W2

MO

VEA

A

,@R

W3

MO

VEA

A,

@R

W0+

MO

VEA

A,

@R

W1+

MO

VEA

A,

@R

W2+

MO

VEA

A,

@R

W3+

MO

VEA

A,

@R

W0+

d8

MO

VEA

A,

@R

W1+

d8

MO

VEA

A,

@R

W2+

d8

MO

VEA

A,

@R

W3+

d8

MO

VEA

A,

@R

W4+

d8

MO

VEA

A,

@R

W5+

d8

MO

VEA

A,

@R

W6+

d8

MO

VEA

A,

@R

W7+

d8

MO

VEA

A,

@R

W0+

d16

MO

VEA

A,

@R

W1+

d16

MO

VEA

A,

@R

W2+

d16

MO

VEA

A,

@R

W3+

d16

MO

VEA

A,

@R

W0+

RW

7

MO

VEA

A,

@R

W1+

RW

7

MO

VEA

A,

@PC

+d16

MO

VEA

A,

ad

dr16

474



0010

2030

4050

6070

8090

A0

B0

C0

D0

E0

F0

ROLC

R

0

ROLC

R

1

ROLC

R

2

ROLC

R

3

ROLC

R

4

ROLC

R

5

ROLC

R

6

ROLC

R

7

ROLC

@

RW0

ROLC

@

RW1

ROLC

@

RW2

ROLC

@

RW3

ROLC

@RW

0+

ROLC

@RW

1+

ROLC

@RW

2+

ROLC

@RW

3+

ROLC

@RW

0+d8

ROLC

@RW

1+d8

ROLC

@RW

2+d8

ROLC

@RW

3+d8

ROLC

@RW

4+d8

ROLC

@RW

5+d8

ROLC

@RW

6+d8

ROLC

@RW

7+d8

ROLC

@RW

0+d1

6

ROLC

@RW

1+d1

6

ROLC

@RW

2+d1

6

ROLC

@RW

3+d1

6

ROLC

@RW

0+RW

7

ROLC

@RW

1+RW

7

ROLC

@PC

+d16

ROLC

a

ddr1

6

RORC

R

0

RORC

R

1

RORC

R

2

RORC

R

3

RORC

R

4

RORC

R

5

RORC

R

6

RORC

R

7

RORC

@RW

0

RORC

@RW

1

RORC

@RW

2

RORC

@RW

3

RORC

@RW

0+

RORC

@RW

1+

RORC

@RW

2+

RORC

@RW

3+

RORC

@RW

0+d8

RORC

@RW

1+d8

RORC

@RW

2+d8

RORC

@RW

3+d8

RORC

@RW

4+d8

RORC

@RW

5+d8

RORC

@RW

6+d8

RORC

@RW

7+d8

RORC

@RW

0+d1

6

RORC

@RW

1+d1

6

RORC

@RW

2+d1

6

RORC

@RW

3+d1

6

RORC

@RW

0+RW

7

RORC

@RW

1+RW

7

RORC

@PC

+d16

RORC

a

ddr1

6

INC

R

0

INC

R

1

INC

R

2

INC

R

3

INC

R

4

INC

R

5

INC

R

6

INC

R

7

INC

@

RW0

INC

@

RW1

INC

@

RW2

INC

@

RW3

INC

@RW

0+

INC

@RW

1+

INC

@RW

2+

INC

@RW

3+

INC

@RW

0+d8

INC

@RW

1+d8

INC

@RW

2+d8

INC

@RW

3+d8

INC

@RW

4+d8

INC

@RW

5+d8

INC

@RW

6+d8

INC

@RW

7+d8

INC

@RW

0+d1

6

INC

@RW

1+d1

6

INC

@RW

2+d1

6

INC

@RW

3+d1

6

INC

@RW

0+RW

7

INC

@RW

1+RW

7

INC

@PC

+d16

INC

a

ddr1

6

DEC

R

0

DEC

R

1

DEC

R

2

DEC

R

3

DEC

R

4

DEC

R

5

DEC

R

6

DEC

R

7

DEC

@

RW0

DEC

@

RW1

DEC

@

RW2

DEC

@

RW3

DEC

@RW

0+

DEC

@RW

1+

DEC

@RW

2+

DEC

@RW

3+

DEC

@RW

0+d8

DEC

@RW

1+d8

DEC

@RW

2+d8

DEC

@RW

3+d8

DEC

@RW

4+d8

DEC

@RW

5+d8

DEC

@RW

6+d8

DEC

@RW

7+d8

DEC

@RW

0+d1

6

DEC

@RW

1+d1

6

DEC

@RW

2+d1

6

DEC

@RW

3+d1

6

DEC

@RW

0+RW

7

DEC

@RW

1+RW

7

DEC

@PC

+d16

DEC

a

ddr1

6

MO

V

A,R0

MO

V

A,R1

MO

V

A,R2

MO

V

A,R3

MO

V

A,R4

MO

V

A,R5

MO

V

A,R6

MO

V

A,R7

MO

V

A

,@RW

0

MO

V

A

,@RW

1

MO

V

A

,@RW

2

MO

V

A

,@RW

3

MO

V

A,@

RW0+

MO

V

A,@

RW1+

MO

V

A,@

RW2+

MO

V

A,@

RW3+

MO

V

A,

@RW

0+d8

MO

V

A,

@RW

1+d8

MO

V

A,

@RW

2+d8

MO

V

A,

@RW

3+d8

MO

V

A,

@RW

4+d8

MO

V

A,

@RW

5+d8

MO

V

A,

@RW

6+d8

MO

V

A,

@RW

7+d8

MO

V

A,

@RW

0+d1

6

MO

V

A,

@RW

1+d1

6

MO

V

A,

@RW

2+d1

6

MO

V

A,

@RW

3+d1

6

MO

V

A,

@RW

0+RW

7

MO

V

A,

@RW

1+RW

7

MO

V

A,

@PC

+d16

MO

V

A,

a

ddr1

6

MO

V

R0,

A

MO

V

R1,

A

MO

V

R2,

A

MO

V

R3,

A

MO

V

R4,

A

MO

V

R5,

A

MO

V

R6,

A

MO

V

R7,

A

MO

V

@

RW0,

A

MO

V

@

RW1,

A

MO

V

@

RW2,

A

MO

V

@

RW3,

A

MO

V

@RW

0+,A

MO

V

@RW

1+,A

MO

V

@RW

2+,A

MO

V

@RW

3+,A

MO

V

@

R

W0+

d8,A

MO

V

@

R

W1+

d8,A

MO

V

@

R

W2+

d8,A

MO

V

@R

W3+

d8,A

MO

V

@R

W4+

d8,A

MO

V

@R

W5+

d8,A

MO

V

@R

W6+

d8,A

MO

V

@R

W7+

d8,A

MO

V

@R

W0+

d16,

A

MO

V

@R

W1+

d16,

A

MO

V

@R

W2+

d16,

A

MO

V

@R

W3+

d16,

A

MO

V

@R

W0+

RW7,

A

MO

V

@R

W1+

RW7,

A

MO

V

@P

C+d1

6,A

MO

V

addr

16,A

MO

VX

A,R

0

MO

VX

A,R

1

MO

VX

A,R

2

MO

VX

A,R

3

MO

VX

A,R

4

MO

VX

A,R

5

MO

VX

A,R

6

MO

VX

A,R

7

MO

VX

A,@

RW0

MO

VX

A,@

RW1

MO

VX

A,@

RW2

MO

VX

A,@

RW3

MO

VX

A

,@RW

0+

MO

VX

A

,@RW

1+

MO

VX

A

,@RW

2+

MO

VX

A

,@RW

3+

MO

VX

A,

@RW

0+d8

MO

VX

A,

@RW

1+d8

MO

VX

A,

@RW

2+d8

MO

VX

A,

@RW

3+d8

MO

VX

A,

@RW

4+d8

MO

VX

A,

@RW

5+d8

MO

VX

A,

@RW

6+d8

MO

VX

A,

@RW

7+d8

MO

VX

A,

@RW

0+d1

6

MO

VX

A,

@RW

1+d1

6

MO

VX

A,

@RW

2+d1

6

MO

VX

A,

@RW

3+d1

6

MO

VX

A,

@RW

0+RW

7

MO

VX

A,

@RW

1+RW

7

MO

VX

A,

@PC

+d16

MO

VX

A,

a

ddr1

6

XCH

A,R

0

XCH

A,R

1

XCH

A,R

2

XCH

A,R

3

XCH

A,R

4

XCH

A,R

5

XCH

A,R

6

XCH

A,R

7

XCH

A

,@RW

0

XCH

A

,@RW

1

XCH

A

,@RW

2

XCH

A

,@RW

3

XCH

A,

@RW

0+

XCH

A,

@RW

1+

XCH

A,

@RW

2+

XCH

A,

@RW

3+

XCH

A

,

@RW

0+d8

XCH

A

,

@RW

1+d8

XCH

A

,

@RW

2+d8

XCH

A

,

@RW

3+d8

XCH

A

,

@RW

4+d8

XCH

A

,

@RW

5+d8

XCH

A

,

@RW

6+d8

XCH

A

,

@RW

7+d8

XCH

A

,

@RW

0+d1

6

XCH

A

,

@RW

1+d1

6

XCH

A

,

@RW

2+d1

6

XCH

A

,

@RW

3+d1

6

XCH

A

,

@RW

0+RW

7

XCH

A

,

@RW

1+RW

7

XCH

A

,

@PC

+d16

XCH

A

,

ad

dr16

+0

+1

+2

+3

+4

+5

+6

+7

+8

+9

+A

+B

+C

+D +E +F

475



0010

2030

4050

6070

8090

A0

B0

C0

D0

E0

F0

JMP

@

RW0

JMP

@

RW1

JMP

@

RW2

JMP

@

RW3

JMP

@

RW4

JMP

@

RW5

JMP

@

RW6

JMP

@

RW7

JMP

@@

RW0

JMP

@@

RW1

JMP

@@

RW2

JMP

@@

RW3

JMP

@

@RW

0+

JMP

@

@RW

1+

JMP

@

@RW

2+

JMP

@

@RW

3+

JMP

@@

RW0+

d8

JMP

@@

RW1+

d8

JMP

@@

RW2+

d8

JMP

@@

RW3+

d8

JMP

@@

RW4+

d8

JMP

@@

RW5+

d8

JMP

@@

RW6+

d8

JMP

@@

RW7+

d8

JMP

@

@RW

0+d1

6

JMP

@

@RW

1+d1

6

JMP

@

@RW

2+d1

6

JMP

@

@RW

3+d1

6

JMP

@

@RW

0+RW

7

JMP

@

@RW

1+RW

7

JMP

@@

PC+d

16

JMP

@

addr

16

CALL

@

RW0

CALL

@

RW1

CALL

@

RW2

CALL

@

RW3

CALL

@

RW4

CALL

@

RW5

CALL

@

RW6

CALL

@

RW7

CALL

@@

RW0

CALL

@@

RW1

CALL

@@

RW2

CALL

@@

RW3

CALL

@

@RW

0+

CALL

@

@RW

1+

CALL

@

@RW

2+

CALL

@

@RW

3+

CALL

@@

RW0+

d8

CALL

@@

RW1+

d8

CALL

@@

RW2+

d8

CALL

@@

RW3+

d8

CALL

@@

RW4+

d8

CALL

@@

RW5+

d8

CALL

@@

RW6+

d8

CALL

@@

RW7+

d8

CALL

@

@RW

0+d1

6

CALL

@

@RW

1+d1

6

CALL

@

@RW

2+d1

6

CALL

@

@RW

3+d1

6

CALL

@

@RW

0+RW

7

CALL

@

@RW

1+RW

7

CALL

@@

PC+d

16

CALL

@ad

dr16

INCW

RW

0

INCW

RW

1

INCW

RW

2

INCW

RW

3

INCW

RW

4

INCW

RW

5

INCW

RW

6

INCW

RW

7

INCW

@

RW0

INCW

@

RW1

INCW

@

RW2

INCW

@

RW3

INCW

@RW

0+

INCW

@RW

1+

INCW

@RW

2+

INCW

@RW

3+

INCW

@RW

0+d8

INCW

@RW

1+d8

INCW

@RW

2+d8

INCW

@RW

3+d8

INCW

@RW

4+d8

INCW

@RW

5+d8

INCW

@RW

6+d8

INCW

@RW

7+d8

INCW

@RW

0+d1

6

INCW

@RW

1+d1

6

INCW

@RW

2+d1

6

INCW

@RW

3+d1

6

INCW

@RW

0+RW

7

INCW

@RW

1+RW

7

INCW

@PC

+d16

INCW

addr

16

DECW

RW0

DECW

RW1

DECW

RW2

DECW

RW3

DECW

RW4

DECW

RW5

DECW

RW6

DECW

RW7

DECW

@

RW0

DECW

@

RW1

DECW

@

RW2

DECW

@

RW3

DECW

@RW

0+

DECW

@RW

1+

DECW

@RW

2+

DECW

@RW

3+

DECW

@RW

0+d8

DECW

@RW

1+d8

DECW

@RW

2+d8

DECW

@RW

3+d8

DECW

@RW

4+d8

DECW

@RW

5+d8

DECW

@RW

6+d8

DECW

@RW

7+d8

DECW

@RW

0+d1

6

DECW

@RW

1+d1

6

DECW

@RW

2+d1

6

DECW

@RW

3+d1

6

DECW

@RW

0+RW

7

DECW

@RW

1+RW

7

DECW

@PC

+d16

DECW

a

ddr1

6

MO

VW

A

,RW

0

MO

VW

A

,RW

1

MO

VW

A

,RW

2

MO

VW

A

,RW

3

MO

VW

A

,RW

4

MO

VW

A

,RW

5

MO

VW

A

,RW

6

MO

VW

A

,RW

7

MO

VW

A,@

RW0

MO

VW

A,@

RW1

MO

VW

A,@

RW2

MO

VW

A,@

RW3

MO

VW

A,@

RW0+

MO

VW

A,@

RW1+

MO

VW

A,@

RW2+

MO

VW

A,@

RW3+

MO

VW

A,

@RW

0+d8

MO

VW

A,

@RW

1+d8

MO

VW

A,

@RW

2+d8

MO

VW

A,

@RW

3+d8

MO

VW

A,

@RW

4+d8

MO

VW

A,

@RW

5+d8

MO

VW

A,

@RW

6+d8

MO

VW

A,

@RW

7+d8

MO

VW

A,

@RW

0+d1

6

MO

VW

A,

@RW

1+d1

6

MO

VW

A,

@RW

2+d1

6

MO

VW

A,

@RW

3+d1

6

MO

VW

A,

@RW

0+RW

7

MO

VW

A,

@RW

1+RW

7

MO

VW

A,

@PC

+d16

MO

VW

A,

a

ddr1

6

MO

VW

R

W0,

A

MO

VW

R

W1,

A

MO

VW

R

W2,

A

MO

VW

R

W3,

A

MO

VW

R

W4,

A

MO

VW

R

W5,

A

MO

VW

R

W6,

A

MO

VW

R

W7,

A

MO

VW

@RW

0,A

MO

VW

@RW

1,A

MO

VW

@RW

2,A

MO

VW

@RW

3,A

MO

VW

@RW

0+,A

MO

VW

@RW

1+,A

MO

VW

@RW

2+,A

MO

VW

@RW

3+,A

MO

VW

@R

W0+

d8,A

MO

VW

@R

W1+

d8,A

MO

VW

@R

W2+

d8,A

MO

VW

@R

W3+

d8,A

MO

VW

@R

W4+

d8,A

MO

VW

@R

W5+

d8,A

MO

VW

@R

W6+

d8,A

MO

VW

@R

W7+

d8,A

MO

VW

@R

W0+

d16,

A

MO

VW

@R

W1+

d16,

A

MO

VW

@R

W2+

d16,

A

MO

VW

@R

W3+

d16,

A

MO

VW

@R

W0+

RW7,

A

MO

VW

@R

W1+

RW7,

A

MO

VW

@P

C+d1

6,A

MO

VW

addr

16,A

MO

VW

RW

0,#1

6

MO

VW

RW

1,#1

6

MO

VW

RW

2,#1

6

MO

VW

RW

3,#1

6

MO

VW

RW

4,#1

6

MO

VW

RW

5,#1

6

MO

VW

RW

6,#1

6

MO

VW

RW

7,#1

6

MO

VW

@RW

0,#1

6

MO

VW

@RW

1,#1

6

MO

VW

@RW

2,#1

6

MO

VW

@RW

3,#1

6

MO

VW

@

RW0+

,#16

MO

VW

@

RW1+

,#16

MO

VW

@

RW2+

,#16

MO

VW

@

RW3+

,#16

MO

VW @

RW

0+d8

,#16

MO

VW @

RW

1+d8

,#16

MO

VW @

RW

2+d8

,#16

MO

VW @

RW

3+d8

,#16

MO

VW @

RW

4+d8

,#16

MO

VW @

RW

5+d8

,#16

MO

VW @

RW

6+d8

,#16

MO

VW @

RW

7+d8

,#16

MO

VW@

RW0

+d16

,#16

MO

VW@

RW1

+d16

,#16

MO

VW@

RW2

+d16

,#16

MO

VW@

RW3

+d16

,#16

MO

VW@

RW0

+RW

7,#1

6

MO

VW@

RW1

+RW

7,#1

6

MO

VW @

PC

+d16

,#16

MO

VW

addr

16,#

16

XCHW

A,

RW0

XCHW

A,

RW1

XCHW

A,

RW2

XCHW

A,

RW3

XCHW

A,

RW4

XCHW

A,

RW5

XCHW

A,

RW6

XCHW

A,

RW7

XCHW

A

,@RW

0

XCHW

A

,@RW

1

XCHW

A

,@RW

2

XCHW

A

,@RW

3

XCHW

A

,@RW

0+

XCHW

A,

@RW

1+

XCHW

A,@

RW2+

XCHW

A,@

RW3+

XCHW

A,

@RW

0+d8

XCHW

A,

@RW

1+d8

XCHW

A,

@RW

2+d8

XCHW

A,

@RW

3+d8

XCHW

A,

@RW

4+d8

XCHW

A,

@RW

5+d8

XCHW

A,

@RW

6+d8

XCHW

A,

@RW

7+d8

XCHW

A,

@RW

0+d1

6

XCHW

A,

@RW

1+d1

6

XCHW

A,

@RW

2+d1

6

XCHW

A,

@RW

3+d1

6

XCHW

A,

@RW

0+RW

7

XCHW

A,

@RW

1+RW

7

XCHW

A,

@PC

+d16

XCHW

A,

a

ddr1

6

+0

+1

+2

+3

+4

+5

+6

+7

+8

+9

+A

+B

+C

+D +E +F

476



0010

2030

4050

6070

8090

A0

B0

C0

D0

E0

F0

ADD

A

,R0

ADD

A

,R1

ADD

A

,R2

ADD

A

,R3

ADD

A

,R4

ADD

A

,R5

ADD

A

,R6

ADD

A

,R7

ADD

A

,@R

W0

ADD

A

,@R

W1

ADD

A

,@R

W2

ADD

A

,@R

W3

ADD

A,@

RW

0+

ADD

A,@

RW

1+

ADD

A,@

RW

2+

ADD

A,@

RW

3+

ADD

A,

@R

W0+

d8

ADD

A,

@R

W1+

d8

ADD

A,

@R

W2+

d8

ADD

A,

@R

W3+

d8

ADD

A,

@R

W4+

d8

ADD

A,

@R

W5+

d8

ADD

A,

@R

W6+

d8

ADD

A,

@R

W7+

d8

ADD

A,

@R

W0+

d16

ADD

A,

@R

W1+

d16

ADD

A,

@R

W2+

d16

ADD

A,

@R

W3+

d16

ADD

A,

@R

W0+

RW

7

ADD

A,

@R

W1+

RW

7

ADD

A,

@PC

+d16

ADD

A,

add

r16

SUB

A

,R0

SUB

A

,R1

SUB

A

,R2

SUB

A

,R3

SUB

A

,R4

SUB

A

,R5

SUB

A

,R6

SUB

A

,R7

SUB

A

,@R

W0

SUB

A

,@R

W1

SUB

A

,@R

W2

SUB

A

,@R

W3

SUB

A,

@R

W0+

SUB

A,

@R

W1+

SUB

A,

@R

W2+

SUB

A,

@R

W3+

SUB

A,

@R

W0+

d8

SUB

A,

@R

W1+

d8

SUB

A,

@R

W2+

d8

SUB

A,

@R

W3+

d8

SUB

A,

@R

W4+

d8

SUB

A,

@R

W5+

d8

SUB

A,

@R

W6+

d8

SUB

A,

@R

W7+

d8

SUB

A,

@R

W0+

d16

SUB

A,

@R

W1+

d16

SUB

A,

@R

W2+

d16

SUB

A,

@R

W3+

d16

SUB

A,

@R

W0+

RW

7

SUB

A,

@R

W1+

RW

7

SUB

A,

@PC

+d16

SUB

A,

add

r16

ADD

C

A

,R0

ADD

C

A

,R1

ADD

C

A

,R2

ADD

C

A

,R3

ADD

C

A

,R4

ADD

C

A

,R5

ADD

C

A

,R6

ADD

C

A

,R7

ADD

C

A

,@R

W0

ADD

C

A

,@R

W1

ADD

C

A,

@R

W2

ADD

C

A

,@R

W3

ADD

C

A,@

RW

0+

ADD

C

A,@

RW

1+

ADD

C

A,@

RW

2+

ADD

C

A,@

RW

3+

ADD

C

A,

@R

W0+

d8

ADD

C

A,

@R

W1+

d8

ADD

C

A,

@R

W2+

d8

ADD

C

A,

@R

W3+

d8

ADD

C

A,

@R

W4+

d8

ADD

C

A,

@R

W5+

d8

ADD

C

A,

@R

W6+

d8

ADD

C

A,

@R

W7+

d8

ADD

C

A,

@R

W0+

d16

ADD

C

A,

@R

W1+

d16

ADD

C

A,

@R

W2+

d16

ADD

C

A,

@R

W3+

d16

ADD

C

A,

@R

W0+

RW

7

ADD

C

A,

@R

W1+

RW

7

ADD

C

A,

@PC

+d16

ADD

C

A,

ad

dr16

CM

P

A

,R0

CM

P

A

,R1

CM

P

A

,R2

CM

P

A

,R3

CM

P

A

,R4

CM

P

A

,R5

CM

P

A

,R6

CM

P

A

,R7

CM

P

A

,@R

W0

CM

P

A

,@R

W1

CM

P

A

,@R

W2

CM

P

A

,@R

W3

CM

P

A,@

RW

0+

CM

P

A,@

RW

1+

CM

P

A,@

RW

2+

CM

P

A,@

RW

3+

CM

P

A,

@R

W0+

d8

CM

P

A,

@R

W1+

d8

CM

P

A,

@R

W2+

d8

CM

P

A,

@R

W3+

d8

CM

P

A,

@R

W4+

d8

CM

P

A,

@R

W5+

d8

CM

P

A,

@R

W6+

d8

CM

P

A,

@R

W7+

d8

CM

P

A,

@R

W0+

d16

CM

P

A,

@R

W1+

d16

CM

P

A,

@R

W2+

d16

CM

P

A,

@R

W3+

d16

CM

P

A,

@R

W0+

RW

7

CM

P

A,

@R

W1+

RW

7

CM

P

A,

@PC

+d16

CM

P

A,

add

r16

AND

A

,R0

AND

A

,R1

AND

A

,R2

AND

A

,R3

AND

A

,R4

AND

A

,R5

AND

A

,R6

AND

A

,R7

AND

A

,@R

W0

AND

A

,@R

W1

AND

A

,@R

W2

AND

A

,@R

W3

AND

A,@

RW

0+

AND

A,@

RW

1+

AND

A,@

RW

2+

AND

A,@

RW

3+

AND

A,

@R

W0+

d8

AND

A,

@R

W1+

d8

AND

A,

@R

W2+

d8

AND

A,

@R

W3+

d8

AND

A,

@R

W4+

d8

AND

A,

@R

W5+

d8

AND

A,

@R

W6+

d8

AND

A,

@R

W7+

d8

AND

A,

@R

W0+

d16

AND

A,

@R

W1+

d16

AND

A,

@R

W2+

d16

AND

A,

@R

W3+

d16

AND

A,

@R

W0+

RW

7

AND

A,

@R

W1+

RW

7

AND

A,

@PC

+d16

AND

A,

ad

dr16

OR

A,R

0

OR

A,R

1

OR

A,R

2

OR

A,R

3

OR

A,R

4

OR

A,R

5

OR

A,R

6

OR

A,R

7

OR

A

,@R

W0

OR

A

,@R

W1

OR

A

,@R

W2

OR

A

,@R

W3

OR

A,@

RW

0+

OR

A,@

RW

1+

OR

A,@

RW

2+

OR

A,@

RW

3+

OR

A,

@R

W0+

d8

OR

A,

@R

W1+

d8

OR

A,

@R

W2+

d8

OR

A,

@R

W3+

d8

OR

A,

@R

W4+

d8

OR

A,

@R

W5+

d8

OR

A,

@R

W6+

d8

OR

A,

@R

W7+

d8

OR

A,

@R

W0+

d16

OR

A,

@R

W1+

d16

OR

A,

@R

W2+

d16

OR

A,

@R

W3+

d16

OR

A,

@R

W0+

RW

7

OR

A,

@R

W1+

RW

7

OR

A,

@PC

+d16

OR

A,

ad

dr16

XOR

A,R

0

XOR

A,R

1

XOR

A,R

2

XOR

A,R

3

XOR

A,R

4

XOR

A,R

5

XOR

A,R

6

XOR

A,R

7

XOR

A

,@R

W0

XOR

A

,@R

W1

XOR

A

,@R

W2

XOR

A

,@R

W3

XOR

A,@

RW

0+

XOR

A,@

RW

1+

XOR

A,@

RW

2+

XOR

A,@

RW

3+

XOR

A,

@R

W0+

d8

XOR

A,

@R

W1+

d8

XOR

A,

@R

W2+

d8

XOR

A,

@R

W3+

d8

XOR

A,

@R

W4+

d8

XOR

A,

@R

W5+

d8

XOR

A,

@R

W6+

d8

XOR

A,

@R

W7+

d8

XOR

A,

@R

W0+

d16

XOR

A,

@R

W1+

d16

XOR

A,

@R

W2+

d16

XOR

A,

@R

W3+

d16

XOR

A,

@R

W0+

RW

7

XOR

A,

@R

W1+

RW

7

XOR

A,

@PC

+d16

XOR

A,

ad

dr16

DBN

Z

R0,

r

DBN

Z

R1,

r

DBN

Z

R2,

r

DBN

Z

R3,

r

DBN

Z

R4,

r

DBN

Z

R5,

r

DBN

Z

R6,

r

DBN

Z

R7,

r

DBN

Z

@

RW

0,r

DBN

Z

@

RW

1,r

DBN

Z

@

RW

2,r

DBN

Z

@

RW

3,r

DBN

Z

@

RW

0+,r

DBN

Z

@

RW

1+,r

DBN

Z

@

RW

2+,r

DBN

Z

@

RW

3+,r

DBN

Z

@

RW

0+d8

,r

DBN

Z

@

RW

1+d8

,r

DBN

Z

@

RW

2+d8

,r

DBN

Z

@

RW

3+d8

,r

DBN

Z

@

RW

4+d8

,r

DBN

Z

@

RW

5+d8

,r

DBN

Z

@

RW

6+d8

,r

DBN

Z

@

RW

7+d8

,r

DBN

Z @

R

W0+

d16,

r

DBN

Z @

R

W1+

d16,

r

DBN

Z @

R

W2+

d16,

r

DBN

Z @

R

W3+

d16,

r

DBN

Z @

R

W0+

RW

7,r

DBN

Z @

R

W1+

RW

7,r

DBN

Z

@

PC

+d16

,r

DBN

Z

addr

16,r

+0

+1

+2

+3

+4

+5

+6

+7

+8

+9

+A

+B

+C

+D +E +F

477



0010

2030

4050

6070

8090

A0

B0

C0

D0

E0

F0

ADD

R

0,A

ADD

R

1,A

ADD

R

2,A

ADD

R

3,A

ADD

R

4,A

ADD

R

5,A

ADD

R

6,A

ADD

R

7,A

ADD

@

RW

0,A

ADD

@

RW

1,A

ADD

@

RW

2,A

ADD

@

RW

3,A

ADD

@R

W0+

,A

ADD

@R

W1+

,A

ADD

@R

W2+

,A

ADD

@R

W3+

,A

ADD

@

R

W0+

d8,A

ADD

@

R

W1+

d8,A

ADD

@

R

W2+

d8,A

ADD

@

R

W3+

d8,A

ADD

@

R

W4+

d8,A

ADD

@

R

W5+

d8,A

ADD

@

R

W6+

d8,A

ADD

@

R

W7+

d8,A

ADD

@

R

W0+

d16,

A

ADD

@

R

W1+

d16,

A

ADD

@

R

W2+

d16,

A

ADD

@

R

W3+

d16,

A

ADD

@

R

W0+

RW

7,A

ADD

@

R

W1+

RW

7,A

ADD

@

P

C+d

16,A

ADD

addr

16,A

SUB

R

0,A

SUB

R

1,A

SUB

R

2,A

SUB

R

3,A

SUB

R

4,A

SUB

R

5,A

SUB

R

6,A

SUB

R

7,A

SUB

@

RW

0,A

SUB

@

RW

1,A

SUB

@

RW

2,A

SUB

@

RW

3,A

SUB

@R

W0+

,A

SUB

@R

W1+

,A

SUB

@R

W2+

,A

SUB

@R

W3+

,A

SUB

@

R

W0+

d8,A

SUB

@

R

W1+

d8,A

SUB

@

R

W2+

d8,A

SUB

@

R

W3+

d8,A

SUB

@

R

W4+

d8,A

SUB

@

R

W5+

d8,A

SUB

@

R

W6+

d8,A

SUB

@

R

W7+

d8,A

SUB

@

R

W0+

d16,

A

SUB

@

R

W1+

d16,

A

SUB

@

R

W2+

d16,

A

SUB

@

R

W3+

d16,

A

SUB

@

R

W0+

RW

7,A

SUB

@

R

W1+

RW

7,A

SUB

@

P

C+d

16,A

SUB

addr

16,A

SUBC

A

,R0

SUBC

A

,R1

SUBC

A

,R2

SUBC

A

,R3

SUBC

A

,R4

SUBC

A

,R5

SUBC

A

,R6

SUBC

A

,R7

SUBC

A

,@R

W0

SUBC

A

,@R

W1

SUBC

A

,@R

W2

SUBC

A

,@R

W3

SUBC

A,

@R

W0+

SUBC

A,

@R

W1+

SUBC

A,

@R

W2+

SUBC

A,

@R

W3+

SUBC

A

,

@R

W0+

d8

SUBC

A

,

@R

W1+

d8

SUBC

A

,

@R

W2+

d8

SUBC

A

,

@R

W3+

d8

SUBC

A

,

@R

W4+

d8

SUBC

A

,

@R

W5+

d8

SUBC

A

,

@R

W6+

d8

SUBC

A

,

@R

W7+

d8

SUBC

A

,

@R

W0+

d16

SUBC

A

,

@R

W1+

d16

SUBC

A

,

@R

W2+

d16

SUBC

A

,

@R

W3+

d16

SUBC

A

,

@R

W0+

RW

7

SUBC

A

,

@R

W1+

RW

7

SUBC

A

,

@PC

+d16

SUBC

A,

a

ddr1

6

NEG

R0

NEG

R1

NEG

R2

NEG

R3

NEG

R4

NEG

R5

NEG

R6

NEG

R7

NEG

@R

W0

NEG

@R

W1

NEG

@R

W2

NEG

@R

W3

NEG

@R

W0+

NEG

@R

W1+

NEG

@R

W2+

NEG

@R

W3+

NEG

@R

W0+

d8

NEG

@R

W1+

d8

NEG

@R

W2+

d8

NEG

@R

W3+

d8

NEG

@R

W4+

d8

NEG

@R

W5+

d8

NEG

@R

W6+

d8

NEG

@R

W7+

d8

NEG

@R

W0+

d16

NEG

@R

W1+

d16

NEG

@R

W2+

d16

NEG

@R

W3+

d16

NEG

@R

W0+

RW

7

NEG

@R

W1+

RW

7

NEG

@PC

+d16

NEG

a

ddr1

6

AND

R

0,A

AND

R

1,A

AND

R

2,A

AND

R

3,A

AND

R

4,A

AND

R

5,A

AND

R

6,A

AND

R

7,A

AND

@

RW

0,A

AND

@

RW

1,A

AND

@

RW

2,A

AND

@

RW

3,A

AND

@R

W0+

,A

AND

@R

W1+

,A

AND

@R

W2+

,A

AND

@R

W3+

,A

AND

@

R

W0+

d8,A

AND

@

R

W1+

d8,A

AND

@

R

W2+

d8,A

AND

@

R

W3+

d8,A

AND

@

R

W4+

d8,A

AND

@

R

W5+

d8,A

AND

@

R

W6+

d8,A

AND

@

R

W7+

d8,A

AND

@

R

W0+

d16,

A

AND

@

R

W1+

d16,

A

AND

@

R

W2+

d16,

A

AND

@

R

W3+

d16,

A

AND

@

R

W0+

RW

7,A

AND

@

R

W1+

RW

7,A

AND

@

P

C+d

16,A

AND

addr

16,A

OR

R

0,A

OR

R

1,A

OR

R

2,A

OR

R

3,A

OR

R

4,A

OR

R

5,A

OR

R

6,A

OR

R

7,A

OR

@

RW

0,A

OR

@

RW

1,A

OR

@

RW

2,A

OR

@

RW

3,A

OR

@R

W0+

,A

OR

@R

W1+

,A

OR

@R

W2+

,A

OR

@R

W3+

,A

OR

@R

W0+

d8,A

OR

@R

W1+

d8,A

OR

@R

W2+

d8,A

OR

@R

W3+

d8,A

OR

@R

W4+

d8,A

OR

@R

W5+

d8,A

OR

@R

W6+

d8,A

OR

@R

W7+

d8,A

OR

@R

W0+

d16,

A

OR

@R

W1+

d16,

A

OR

@R

W2+

d16,

A

OR

@R

W3+

d16,

A

OR

@R

W0+

RW

7,A

OR

@R

W1+

RW

7,A

OR

@P

C+d

16,A

OR

addr

16,A

XOR

R

0,A

XOR

R

1,A

XOR

R

2,A

XOR

R

3,A

XOR

R

4,A

XOR

R

5,A

XOR

R

6,A

XOR

R

7,A

XOR

@

RW

0,A

XOR

@

RW

1,A

XOR

@

RW

2,A

XOR

@

RW

3,A

XOR

@R

W0+

,A

XOR

@R

W1+

,A

XOR

@R

W2+

,A

XOR

@R

W3+

,A

XOR

@

R

W0+

d8,A

XOR

@

R

W1+

d8,A

XOR

@

R

W2+

d8,A

XOR

@

R

W3+

d8,A

XOR

@

R

W4+

d8,A

XOR

@

R

W5+

d8,A

XOR

@

R

W6+

d8,A

XOR

@

R

W7+

d8,A

XOR

@

R

W0+

d16,

A

XOR

@

R

W1+

d16,

A

XOR

@

R

W2+

d16,

A

XOR

@

R

W3+

d16,

A

XOR

@

R

W0+

RW

7,A

XOR

@

R

W1+

RW

7,A

XOR

@

P

C+d

16,A

XOR

addr

16,A

NO

T

R0

NO

T

R1

NO

T

R2

NO

T

R3

NO

T

R4

NO

T

R5

NO

T

R6

NO

T

R7

NO

T

@R

W0

NO

T

@R

W1

NO

T

@R

W2

NO

T

@R

W3

NO

T

@

RW

0+

NO

T

@

RW

1+

NO

T

@

RW

2+

NO

T

@

RW

3+

NO

T

@R

W0+

d8

NO

T

@R

W1+

d8

NO

T

@R

W2+

d8

NO

T

@R

W3+

d8

NO

T

@R

W4+

d8

NO

T

@R

W5+

d8

NO

T

@R

W6+

d8

NO

T

@R

W7+

d8

NO

T

@R

W0+

d16

NO

T

@R

W1+

d16

NO

T

@R

W2+

d16

NO

T

@R

W3+

d16

NO

T

@R

W0+

RW

7

NO

T

@R

W1+

RW

7

NO

T

@PC

+d16

NO

T

ad

dr16

+0

+1

+2

+3

+4

+5

+6

+7

+8

+9

+A

+B

+C

+D +E +F

478



0010

2030

4050

6070

8090

A0

B0

C0

D0

E0

F0

ADD

W

A,R

W0

ADD

W

A,R

W1

ADD

W

A,R

W2

ADD

W

A,R

W3

ADD

W

A,R

W4

ADD

W

A,R

W5

ADD

W

A,R

W6

ADD

W

A,R

W7

ADD

W

A

,@R

W0

ADD

W

A

,@R

W1

ADD

W

A

,@R

W2

ADD

W

A

,@R

W3

ADD

W

A,

@R

W0+

ADD

W

A,

@R

W1+

ADD

W

A,

@R

W2+

ADD

W

A,

@R

W3+

ADD

W

A,

@R

W0+

d8

ADD

W

A,

@R

W1+

d8

ADD

W

A,

@R

W2+

d8

ADD

W

A,

@R

W3+

d8

ADD

W

A,

@R

W4+

d8

ADD

W

A,

@R

W5+

d8

ADD

W

A,

@R

W6+

d8

ADD

W

A,

@R

W7+

d8

ADD

W

A,

@R

W0+

d16

ADD

W

A,

@R

W1+

d16

ADD

W

A,

@R

W2+

d16

ADD

W

A,

@R

W3+

d16

ADD

W

A,

@R

W0+

RW

7

ADD

W

A,

@R

W1+

RW

7

ADD

W

A,

@PC

+d16

ADD

W A

,

ad

dr16

SUBW

A,R

W0

SUBW

A,R

W1

SUBW

A,R

W2

SUBW

A,R

W3

SUBW

A,R

W4

SUBW

A,R

W5

SUBW

A,R

W6

SUBW

A,R

W7

SUBW

A

,@R

W0

SUBW

A

,@R

W1

SUBW

A

,@R

W2

SUBW

A

,@R

W3

SUBW

A,

@R

W0+

SUBW

A,

@R

W1+

SUBW

A,

@R

W2+

SUBW

A,

@R

W3+

SUBW

A

,

@R

W0+

d8

SUBW

A

,

@R

W1+

d8

SUBW

A

,

@R

W2+

d8

SUBW

A

,

@R

W3+

d8

SUBW

A

,

@R

W4+

d8

SUBW

A

,

@R

W5+

d8

SUBW

A

,

@R

W6+

d8

SUBW

A

,

@R

W7+

d8

SUBW

A

,

@R

W0+

d16

SUBW

A

,

@R

W1+

d16

SUBW

A

,

@R

W2+

d16

SUBW

A

,

@R

W3+

d16

SUBW

A

,

@R

W0+

RW

7

SUBW

A

,

@R

W1+

RW

7

SUBW

A

,

@PC

+d16

SUBW

A

,

ad

dr16

ADD

CW

A,R

W0

ADD

CW

A,R

W1

ADD

CW

A,R

W2

ADD

CW

A,R

W3

ADD

CW

A,R

W4

ADD

CW

A,R

W5

ADD

CW

A,R

W6

ADD

CW

A,R

W7

ADD

CW

A

,@R

W0

ADD

CW

A

,@R

W1

ADD

CW

A

,@R

W2

ADD

CW

A

,@R

W3

ADD

CW

A,

@R

W0+

ADD

CW

A,

@R

W1+

ADD

CW

A,

@R

W2+

ADD

CW

A,

@R

W3+

ADD

CW

A,

@R

W0+

d8

ADD

CW

A,

@R

W1+

d8

ADD

CW

A,

@R

W2+

d8

ADD

CW

A,

@R

W3+

d8

ADD

CW

A,

@R

W4+

d8

ADD

CW

A,

@R

W5+

d8

ADD

CW

A,

@R

W6+

d8

ADD

CW

A,

@R

W7+

d8

ADD

CW

A,

@R

W0+

d16

ADD

CW

A,

@R

W1+

d16

ADD

CW

A,

@R

W2+

d16

ADD

CW

A,

@R

W3+

d16

ADD

CW

A,

@R

W0+

RW

7

ADD

CW

A,

@R

W1+

RW

7

ADD

CW

A,

@PC

+d16

ADD

CW

A,

ad

dr16

CM

PW

A,R

W0

CM

PW

A,R

W1

CM

PW

A,R

W2

CM

PW

A,R

W3

CM

PW

A,R

W4

CM

PW

A,R

W5

CM

PW

A,R

W6

CM

PW

A,R

W7

CM

PW

A

,@R

W0

CM

PW

A

,@R

W1

CM

PW

A

,@R

W2

CM

PW

A

,@R

W3

CM

PW

A,

@R

W0+

CM

PW

A,

@R

W1+

CM

PW

A,

@R

W2+

CM

PW

A,

@R

W3+

CM

PW

A,

@R

W0+

d8

CM

PW

A,

@R

W1+

d8

CM

PW

A,

@R

W2+

d8

CM

PW

A,

@R

W3+

d8

CM

PW

A,

@R

W4+

d8

CM

PW

A,

@R

W5+

d8

CM

PW

A,

@R

W6+

d8

CM

PW

A,

@R

W7+

d8

CM

PW

A,

@R

W0+

d16

CM

PW

A,

@R

W1+

d16

CM

PW

A,

@R

W2+

d16

CM

PW

A,

@R

W3+

d16

CM

PW

A,

@R

W0+

RW

7

CM

PW

A,

@R

W1+

RW

7

CM

PW

A,

@PC

+d16

CM

PW

A,

ad

dr16

AND

W

A,R

W0

AND

W

A,R

W1

AND

W

A,R

W2

AND

W

A,R

W3

AND

W

A,R

W4

AND

W

A,R

W5

AND

W

A,R

W6

AND

W

A,R

W7

AND

W

A

,@R

W0

AND

W

A

,@R

W1

AND

W

A

,@R

W2

AND

W

A

,@R

W3

AND

W

A,

@R

W0+

AND

W

A,

@R

W1+

AND

W

A,

@R

W2+

AND

W

A,

@R

W3+

AND

W

A,

@R

W0+

d8

AND

W

A,

@R

W1+

d8

AND

W

A,

@R

W2+

d8

AND

W

A,

@R

W3+

d8

AND

W

A,

@R

W4+

d8

AND

W

A,

@R

W5+

d8

AND

W

A,

@R

W6+

d8

AND

W

A,

@R

W7+

d8

AND

W

A,

@R

W0+

d16

AND

W

A,

@R

W1+

d16

AND

W

A,

@R

W2+

d16

AND

W

A,

@R

W3+

d16

AND

W

A,

@R

W0+

RW

7

AND

W

A,

@R

W1+

RW

7

AND

W

A,

@PC

+d16

AND

W

A,

ad

dr16

OR

W

A,R

W0

OR

W

A,R

W1

OR

W

A,R

W2

OR

W

A,R

W3

OR

W

A,R

W4

OR

W

A,R

W5

OR

W

A,R

W6

OR

W

A,R

W7

OR

W

A

,@R

W0

OR

W

A

,@R

W1

OR

W

A

,@R

W2

OR

W

A

,@R

W3

OR

W

A,

@R

W0+

OR

W

A,

@R

W1+

OR

W

A,

@R

W2+

OR

W

A,

@R

W3+

OR

W

A,

@R

W0+

d8

OR

W

A,

@R

W1+

d8

OR

W

A,

@R

W2+

d8

OR

W

A,

@R

W3+

d8

OR

W

A,

@R

W4+

d8

OR

W

A,

@R

W5+

d8

OR

W

A,

@R

W6+

d8

OR

W

A,

@R

W7+

d8

OR

W

A,

@R

W0+

d16

OR

W

A,

@R

W1+

d16

OR

W

A,

@R

W2+

d16

OR

W

A,

@R

W3+

d16

OR

W

A,

@R

W0+

RW

7

OR

W

A,

@R

W1+

RW

7

OR

W

A,

@PC

+d16

OR

W

A,

a

ddr1

6

XOR

W

A,R

W0

XOR

W

A,R

W1

XOR

W

A,R

W2

XOR

W

A,R

W3

XOR

W

A,R

W4

XOR

W

A,R

W5

XOR

W

A,R

W6

XOR

W

A,R

W7

XOR

W

A

,@R

W0

XOR

W

A

,@R

W1

XOR

W

A

,@R

W2

XOR

W

A

,@R

W3

XOR

W

A,

@R

W0+

XOR

W

A,

@R

W1+

XOR

W

A,

@R

W2+

XOR

W

A,

@R

W3+

XOR

W

A,

@R

W0+

d8

XOR

W

A,

@R

W1+

d8

XOR

W

A,

@R

W2+

d8

XOR

W

A,

@R

W3+

d8

XOR

W

A,

@R

W4+

d8

XOR

W

A,

@R

W5+

d8

XOR

W

A,

@R

W6+

d8

XOR

W

A,

@R

W7+

d8

XOR

W

A,

@R

W0+

d16

XOR

W

A,

@R

W1+

d16

XOR

W

A,

@R

W2+

d16

XOR

W

A,

@R

W3+

d16

XOR

W

A,

@R

W0+

RW

7

XOR

W

A,

@R

W1+

RW

7

XOR

W

A,

@PC

+d16

XOR

W

A,

ad

dr16

DW

BNZ

RW

0,r

DW

BNZ

RW

1,r

DW

BNZ

RW

2,r

DW

BNZ

RW

3,r

DW

BNZ

RW

4,r

DW

BNZ

RW

5,r

DW

BNZ

RW

6,r

DW

BNZ

RW

7,r

DW

BNZ

@

RW

0,r

DW

BNZ

@

RW

1,r

DW

BNZ

@

RW

2,r

DW

BNZ

@

RW

3,r

DW

BNZ

@

RW

0+,r

DW

BNZ

@R

W1+

,r

DW

BNZ

@R

W2+

,r

DW

BNZ

@R

W3+

,r

DW

BNZ

@

RW

0+d8

,r

DW

BNZ

@

RW

1+d8

,r

DW

BNZ

@

RW

2+d8

,r

DW

BNZ

@

RW

3+d8

,r

DW

BNZ

@

RW

4+d8

,r

DW

BNZ

@

RW

5+d8

,r

DW

BNZ

@

RW

6+d8

,r

DW

BNZ

@

RW

7+d8

,r

DW

BNZ

@R

W0+

d16,

r

DW

BNZ

@R

W1+

d16,

r

DW

BNZ

@R

W2+

d16,

r

DW

BNZ

@R

W3+

d16,

r

DW

BNZ

@R

W0+

RW

7,r

DW

BNZ

@R

W1+

RW

7,r

DW

BNZ

@

PC+d

16,r

DW

BNZ

addr

16,r

+0

+1

+2

+3

+4

+5

+6

+7

+8

+9

+A

+B

+C

+D +E +F

479



0010

2030

4050

6070

8090

A0

B0

C0

D0

E0

F0

ADD

W

R

W0,

A

ADD

W

R

W1,

A

ADD

W

R

W2,

A

ADD

W

R

W3,

A

ADD

W

R

W4,

A

ADD

W

R

W5,

A

ADD

W

R

W6,

A

ADD

W

R

W7,

A

ADD

W

@

RW

0,A

ADD

W

@

RW

1,A

ADD

W

@

RW

2,A

ADD

W

@

RW

3,A

ADD

W

@

RW

0+,A

ADD

W

@

RW

1+,A

ADD

W

@

RW

2+,A

ADD

W

@

RW

3+,A

ADD

W @

R

W0+

d8,A

ADD

W @

R

W1+

d8,A

ADD

W @

R

W2+

d8,A

ADD

W @

R

W3+

d8,A

ADD

W @

R

W4+

d8,A

ADD

W @

R

W5+

d8,A

ADD

W @

R

W6+

d8,A

ADD

W @

R

W7+

d8,A

ADD

W @

R

W0+

d16,

A

ADD

W @

R

W1+

d16,

A

ADD

W @

R

W2+

d16,

A

ADD

W @

R

W3+

d16,

A

ADD

W @

R

W0+

RW

7,A

ADD

W @

R

W1+

RW

7,A

ADD

W @

P

C+d

16,A

ADD

W

addr

16,A

SUBW

R

W0,

A

SUBW

R

W1,

A

SUBW

R

W2,

A

SUBW

R

W3,

A

SUBW

R

W4,

A

SUBW

R

W5,

A

SUBW

R

W6,

A

SUBW

R

W7,

A

SUBW

@

RW

0,A

SUBW

@

RW

1,A

SUBW

@

RW

2,A

SUBW

@

RW

3,A

SUBW

@

RW

0+,A

SUBW

@R

W1+

,A

SUBW

@R

W2+

,A

SUBW

@R

W3+

,A

SUBW

@R

W0+

d8,A

SUBW

@R

W1+

d8,A

SUBW

@R

W2+

d8,A

SUBW

@R

W3+

d8,A

SUBW

@R

W4+

d8,A

SUBW

@R

W5+

d8,A

SUBW

@R

W6+

d8,A

SUBW

@R

W7+

d8,A

SUBW

@R

W0+

d16,

A

SUBW

@R

W1+

d16,

A

SUBW

@R

W2+

d16,

A

SUBW

@R

W3+

d16,

A

SUBW

@R

W0+

RW

7,A

SUBW

@R

W1+

RW

7,A

SUBW

@P

C+d

16,A

SUBW

addr

16,A

SUBC

W

A,

RW

0

SUBC

W

A,

RW

1

SUBC

W

A,

RW

2

SUBC

W

A,

RW

3

SUBC

W

A,

RW

4

SUBC

W

A,

RW

5

SUBC

W

A,

RW

6

SUBC

W

A,

RW

7

SUBC

W

A

,@R

W0

SUBC

W

A

,@R

W1

SUBC

W

A

,@R

W2

SUBC

W

A

,@R

W3

SUBC

W

A,

@R

W0+

SUBC

W

A,

@R

W1+

SUBC

W

A,

@R

W2+

SUBC

W

A,

@R

W3+

SUBC

W A

,

@R

W0+

d8

SUBC

W A

,

@R

W1+

d8

SUBC

W A

,

@R

W2+

d8

SUBC

W A

,

@R

W3+

d8

SUBC

W A

,

@R

W4+

d8

SUBC

W A

,

@R

W5+

d8

SUBC

W A

,

@R

W6+

d8

SUBC

W A

,

@R

W7+

d8

SUBC

W A

,

@R

W0+

d16

SUBC

W A

,

@R

W1+

d16

SUBC

W A

,

@R

W2+

d16

SUBC

W A

,

@R

W3+

d16

SUBC

W A

,

@R

W0+

RW

7

SUBC

W A

,

@R

W1+

RW

7

SUBC

W A

,

@PC

+d16

SUBC

W A

,

ad

dr16

NEG

W

R

W0

NEG

W

R

W1

NEG

W

R

W2

NEG

W

R

W3

NEG

W

R

W4

NEG

W

R

W5

NEG

W

R

W6

NEG

W

R

W7

NEG

W

@R

W0

NEG

W

@R

W1

NEG

W

@R

W2

NEG

W

@R

W3

NEG

W

@

RW

0+

NEG

W

@

RW

1+

NEG

W

@

RW

2+

NEG

W

@

RW

3+

NEG

W

@R

W0+

d8

NEG

W

@R

W1+

d8

NEG

W

@R

W2+

d8

NEG

W

@R

W3+

d8

NEG

W

@R

W4+

d8

NEG

W

@R

W5+

d8

NEG

W

@R

W6+

d8

NEG

W

@R

W7+

d8

NEG

W

@R

W0+

d16

NEG

W

@R

W1+

d16

NEG

W

@R

W2+

d16

NEG

W

@R

W3+

d16

NEG

W

@R

W0+

RW

7

NEG

W

@R

W1+

RW

7

NEG

W

@PC

+d16

NEG

W

ad

dr16

AND

W

RW

0,A

AND

W

RW

1,A

AND

W

RW

2,A

AND

W

RW

3,A

AND

W

RW

4,A

AND

W

RW

5,A

AND

W

RW

6,A

AND

W

RW

7,A

AND

W

@

RW

0,A

AND

W

@

RW

1,A

AND

W

@

RW

2,A

AND

W

@

RW

3,A

AND

W

@R

W0+

,A

AND

W

@R

W1+

,A

AND

W

@R

W2+

,A

AND

W

@R

W3+

,A

AND

W @

R

W0+

d8,A

AND

W @

R

W1+

d8,A

AND

W @

R

W2+

d8,A

AND

W @

R

W3+

d8,A

AND

W @

R

W4+

d8,A

AND

W @

R

W5+

d8,A

AND

W @

R

W6+

d8,A

AND

W @

R

W7+

d8,A

AND

W @

R

W0+

d16,

A

AND

W @

R

W1+

d16,

A

AND

W @

R

W2+

d16,

A

AND

W @

R

W3+

d16,

A

AND

W @

R

W0+

RW

7,A

AND

W @

R

W1+

RW

7,A

AND

W @

P

C+d

16,A

AND

W

addr

16,A

OR

W

RW

0,A

OR

W

RW

1,A

OR

W

RW

2,A

OR

W

RW

3,A

OR

W

RW

4,A

OR

W

RW

5,A

OR

W

RW

6,A

OR

W

RW

7,A

OR

W

@

RW

0,A

OR

W

@

RW

1,A

OR

W

@

RW

2,A

OR

W

@

RW

3,A

OR

W

@R

W0+

,A

OR

W

@R

W1+

,A

OR

W

@R

W2+

,A

OR

W

@R

W3+

,A

OR

W

@R

W0+

d8,A

OR

W

@R

W1+

d8,A

OR

W

@R

W2+

d8,A

OR

W

@R

W3+

d8,A

OR

W

@R

W4+

d8,A

OR

W

@R

W5+

d8,A

OR

W

@R

W6+

d8,A

OR

W

@R

W7+

d8,A

OR

W

@R

W0+

d16,

A

OR

W

@R

W1+

d16,

A

OR

W

@R

W2+

d16,

A

OR

W

@R

W3+

d16,

A

OR

W

@R

W0+

RW

7,A

OR

W

@R

W1+

RW

7,A

OR

W

@P

C+d

16,A

OR

W

addr

16,A

XOR

W

RW

0,A

XOR

W

RW

1,A

XOR

W

RW

2,A

XOR

W

RW

3,A

XOR

W

RW

4,A

XOR

W

RW

5,A

XOR

W

RW

6,A

XOR

W

RW

7,A

XOR

W

@

RW

0,A

XOR

W

@

RW

1,A

XOR

W

@

RW

2,A

XOR

W

@

RW

3,A

XOR

W

@R

W0+

,A

XOR

W

@R

W1+

,A

XOR

W

@R

W2+

,A

XOR

W

@R

W3+

,A

XOR

W @

R

W0+

d8,A

XOR

W @

R

W1+

d8,A

XOR

W @

R

W2+

d8,A

XOR

W @

R

W3+

d8,A

XOR

W @

R

W4+

d8,A

XOR

W @

R

W5+

d8,A

XOR

W @

R

W6+

d8,A

XOR

W @

R

W7+

d8,A

XOR

W @

R

W0+

d16,

A

XOR

W @

R

W1+

d16,

A

XOR

W @

R

W2+

d16,

A

XOR

W @

R

W3+

d16,

A

XOR

W @

R

W0+

RW

7,A

XOR

W @

R

W1+

RW

7,A

XOR

W @

P

C+d

16,A

XOR

W

addr

16,A

NO

TW

R

W0

NO

TW

R

W1

NO

TW

R

W2

NO

TW

R

W3

NO

TW

R

W4

NO

TW

R

W5

NO

TW

R

W6

NO

TW

R

W7

NO

TW

@R

W0

NO

TW

@R

W1

NO

TW

@R

W2

NO

TW

@R

W3

NO

TW

@

RW

0+

NO

TW

@

RW

1+

NO

TW

@

RW

2+

NO

TW

@

RW

3+

NO

TW

@R

W0+

d8

NO

TW

@R

W1+

d8

NO

TW

@R

W2+

d8

NO

TW

@R

W3+

d8

NO

TW

@R

W4+

d8

NO

TW

@R

W5+

d8

NO

TW

@R

W6+

d8

NO

TW

@R

W7+

d8

NO

TW

@R

W0+

d16

NO

TW

@R

W1+

d16

NO

TW

@R

W2+

d16

NO

TW

@R

W3+

d16

NO

TW

@R

W0+

RW

7

NO

TW

@R

W1+

RW

7

NO

TW

@PC

+d16

NO

TW

ad

dr16

+0

+1

+2

+3

+4

+5

+6

+7

+8

+9

+A

+B

+C

+D +E +F

480



0010

2030

4050

6070

8090

A0

B0

C0

D0

E0

F0

MU

LU

A,R

0

MU

LU

A,R

1

MU

LU

A,R

2

MU

LU

A,R

3

MU

LU

A,R

4

MU

LU

A,R

5

MU

LU

A,R

6

MU

LU

A,R

7

MU

LU

A

,@R

W0

MU

LU

A

,@R

W1

MU

LU

A

,@R

W2

MU

LU

A

,@R

W3

MU

LU

A,@

RW

0+

MU

LU

A,@

RW

1+

MU

LU

A,@

RW

2+

MU

LU

A,@

RW

3+

MU

LU

A,

@R

W0+

d8

MU

LU

A,

@R

W1+

d8

MU

LU

A,

@R

W2+

d8

MU

LU

A,

@R

W3+

d8

MU

LU

A,

@R

W4+

d8

MU

LU

A,

@R

W5+

d8

MU

LU

A,

@R

W6+

d8

MU

LU

A,

@R

W7+

d8

MU

LU

A,

@R

W0+

d16

MU

LU

A,

@R

W1+

d16

MU

LU

A,

@R

W2+

d16

MU

LU

A,

@R

W3+

d16

MU

LU

A,

@R

W0+

RW

7

MU

LU

A,

@R

W1+

RW

7

MU

LU

A,

@PC

+d16

MU

LU

A,

a

ddr1

6

MU

LUW

A,

RW

0

MU

LUW

A,

RW

1

MU

LUW

A,

RW

2

MU

LUW

A,

RW

3

MU

LUW

A,

RW

4

MU

LUW

A,

RW

5

MU

LUW

A,

RW

6

MU

LUW

A,

RW

7

MU

LUW

A

,@R

W0

MU

LUW

A

,@R

W1

MU

LUW

A

,@R

W2

MU

LUW

A

,@R

W3

MU

LUW

A,

@R

W0+

MU

LUW

A,

@R

W1+

MU

LUW

A,

@R

W2+

MU

LUW

A,

@R

W3+

MU

LUW

A,

@R

W0+

d8

MU

LUW

A,

@R

W1+

d8

MU

LUW

A,

@R

W2+

d8

MU

LUW

A,

@R

W3+

d8

MU

LUW

A,

@R

W4+

d8

MU

LUW

A,

@R

W5+

d8

MU

LUW

A,

@R

W6+

d8

MU

LUW

A,

@R

W7+

d8

MU

LUW

A,

@R

W0+

d16

MU

LUW

A,

@R

W1+

d16

MU

LUW

A,

@R

W2+

d16

MU

LUW

A,

@R

W3+

d16

MU

LUW

A,

@R

W0+

RW

7

MU

LUW

A,

@R

W1+

RW

7

MU

LUW

A,

@PC

+d16

MU

LUW

A,

a

ddr1

6

DIV

U

A,R

0

DIV

U

A,R

1

DIV

U

A,R

2

DIV

U

A,R

3

DIV

U

A,R

4

DIV

U

A,R

5

DIV

U

A,R

6

DIV

U

A,R

7

DIV

U

A

,@R

W0

DIV

U

A

,@R

W1

DIV

U

A

,@R

W2

DIV

U

A

,@R

W3

DIV

U

A,@

RW

0+

DIV

U

A,@

RW

1+

DIV

U

A,@

RW

2+

DIV

U

A,@

RW

3+

DIV

U

A,

@R

W0+

d8

DIV

U

A,

@R

W1+

d8

DIV

U

A,

@R

W2+

d8

DIV

U

A,

@R

W3+

d8

DIV

U

A,

@R

W4+

d8

DIV

U

A,

@R

W5+

d8

DIV

U

A,

@R

W6+

d8

DIV

U

A,

@R

W7+

d8

DIV

U

A,

@R

W0+

d16

DIV

U

A,

@R

W1+

d16

DIV

U

A,

@R

W2+

d16

DIV

U

A,

@R

W3+

d16

DIV

U

A,

@R

W0+

RW

7

DIV

U

A,

@R

W1+

RW

7

DIV

U

A,

@PC

+d16

DIV

U

A,

ad

dr16

DIV

UW

A,R

W0

DIV

UW

A,R

W1

DIV

UW

A,R

W2

DIV

UW

A,R

W3

DIV

UW

A,R

W4

DIV

UW

A,R

W5

DIV

UW

A,R

W6

DIV

UW

A,R

W7

DIV

UW

A

,@R

W0

DIV

UW

A

,@R

W1

DIV

UW

A

,@R

W2

DIV

UW

A

,@R

W3

DIV

UW

A,@

RW

0+

DIV

UW

A,@

RW

1+

DIV

UW

A,@

RW

2+

DIV

UW

A,@

RW

3+

DIV

UW

A,

@R

W0+

d8

DIV

UW

A,

@R

W1+

d8

DIV

UW

A,

@R

W2+

d8

DIV

UW

A,

@R

W3+

d8

DIV

UW

A,

@R

W4+

d8

DIV

UW

A,

@R

W5+

d8

DIV

UW

A,

@R

W6+

d8

DIV

UW

A,

@R

W7+

d8

DIV

UW

A,

@R

W0+

d16

DIV

UW

A,

@R

W1+

d16

DIV

UW

A,

@R

W2+

d16

DIV

UW

A,

@R

W3+

d16

DIV

UW

A,

@R

W0+

RW

7

DIV

UW

A,

@R

W1+

RW

7

DIV

UW

A,

@PC

+d16

DIV

UW

A,

ad

dr16

+0

+1

+2

+3

+4

+5

+6

+7

+8

+9

+A

+B

+C

+D +E +F

481


Table D.9-15 MOVEA RWi, ea Instruction (First Byte = 79 H)

0010

2030

4050

6070

8090

A0

B0

C0

D0

E0

F0

MO

VEA

R

W0,

RW0

MO

VEA

R

W0,

RW1

MO

VEA

R

W0,

RW2

MO

VEA

R

W0,

RW3

MO

VEA

R

W0,

RW4

MO

VEA

R

W0,

RW5

MO

VEA

R

W0,

RW6

MO

VEA

R

W0,

RW7

MO

VEA

RW0,

@RW

0

MO

VEA

RW0,

@RW

1

MO

VEA

RW0,

@RW

2

MO

VEA

RW0,

@RW

3

MO

VEA

R

W0,

@RW

0+

MO

VEA

R

W0,

@RW

1+

MO

VEA

R

W0,

@RW

2+

MO

VEA

R

W0,

@RW

3+

MO

VEA

RW0

,@

RW0+

d8

MO

VEA

RW0

,@

RW1+

d8

MO

VEA

RW0

,@

RW2+

d8

MO

VEA

RW0

,@

RW3+

d8

MO

VEA

RW0

,@

RW4+

d8

MO

VEA

RW0

,@

RW5+

d8

MO

VEA

RW0

,@

RW6+

d8

MO

VEA

RW0

,@

RW7+

d8

MO

VEA

RW0

,@

RW0+

d16

MO

VEA

RW0

,@

RW1+

d16

MO

VEA

RW0

,@

RW2+

d16

MO

VEA

RW0

,@

RW3+

d16

MO

VEA

RW0

,@RW

0+RW

7

MO

VEA

RW0

,@RW

1+RW

7

MO

VEA

RW0

,@PC

+d16

MO

VEA

RW0

,

addr

16

MO

VEA

R

W1,

RW0

MO

VEA

R

W1,

RW1

MO

VEA

R

W1,

RW2

MO

VEA

R

W1,

RW3

MO

VEA

R

W1,

RW4

MO

VEA

R

W1,

RW5

MO

VEA

RW

1,RW

6

MO

VEA

RW

1,RW

7

MO

VEA

RW1,

@RW

0

MO

VEA

RW1,

@RW

1

MO

VEA

RW1,

@RW

2

MO

VEA

RW1,

@RW

3

MO

VEA

R

W1,

@RW

0+

MO

VEA

R

W1,

@RW

1+

MO

VEA

R

W1,

@RW

2+

MO

VEA

R

W1,

@RW

3+

MO

VEA

RW1

,@

RW0+

d8

MO

VEA

RW1

,@

RW1+

d8

MO

VEA

RW1

,@

RW2+

d8

MO

VEA

RW1

,@

RW3+

d8

MO

VEA

RW1

,@

RW4+

d8

MO

VEA

RW1

,@

RW5+

d8

MO

VEA

RW1

,@

RW6+

d8

MO

VEA

RW1

,@

RW7+

d8

MO

VEA

RW1

,@

RW0+

d16

MO

VEA

RW1

,@

RW1+

d16

MO

VEA

RW1

,@

RW2+

d16

MO

VEA

RW1

,@

RW3+

d16

MO

VEA

RW1

,@RW

0+RW

7

MO

VEA

RW1

,@RW

1+RW

7

MO

VEA

RW1

,

@PC

+d16

MO

VEA

RW1

,

addr

16

MO

VEA

R

W2,

RW0

MO

VEA

R

W2,

RW1

MO

VEA

R

W2,

RW2

MO

VEA

R

W2,

RW3

MO

VEA

R

W2,

RW4

MO

VEA

R

W2,

RW5

MO

VEA

R

W2,

RW6

MO

VEA

R

W2,

RW7

MO

VEA

RW2,

@RW

0

MO

VEA

RW2,

@RW

1

MO

VEA

RW2,

@RW

2

MO

VEA

RW2,

@RW

3

MO

VEA

R

W2,

@RW

0+

MO

VEA

R

W2,

@RW

1+

MO

VEA

R

W2,

@RW

2+

MO

VEA

R

W2,

@RW

3+

MO

VEA

RW2

,@

RW0+

d8

MO

VEA

RW2

,@

RW1+

d8

MO

VEA

RW2

,@

RW2+

d8

MO

VEA

RW2

,@

RW3+

d8

MO

VEA

RW2

,@

RW4+

d8

MO

VEA

RW2

,@

RW5+

d8

MO

VEA

RW2

,@

RW6+

d8

MO

VEA

RW2

,@

RW7+

d8

MO

VEA

RW2

,@

RW0+

d16

MO

VEA

RW2

,@

RW1+

d16

MO

VEA

RW2

,@

RW2+

d16

MO

VEA

RW2

,@

RW3+

d16

MO

VEA

RW2

,@RW

0+RW

7

MO

VEA

RW2

,@RW

1+RW

7

MO

VEA

RW2

,

@PC

+d16

MO

VEA

RW2

,

addr

16

MO

VEA

R

W3,

RW0

MO

VEA

R

W3,

RW1

MO

VEA

R

W3,

RW2

MO

VEA

R

W3,

RW3

MO

VEA

R

W3,

RW4

MO

VEA

R

W3,

RW5

MO

VEA

R

W3,

RW6

MO

VEA

R

W3,

RW7

MO

VEA

RW3,

@RW

0

MO

VEA

RW3,

@RW

1

MO

VEA

RW3,

@RW

2

MO

VEA

RW3,

@RW

3

MO

VEA

R

W3,

@RW

0+

MO

VEA

R

W3,

@RW

1+

MO

VEA

R

W3,

@RW

2+

MO

VEA

R

W3,

@RW

3+

MO

VEA

RW3

,@

RW0+

d8

MO

VEA

RW3

,@

RW1+

d8

MO

VEA

RW3

,@

RW2+

d8

MO

VEA

RW3

,@

RW3+

d8

MO

VEA

RW3

,@

RW4+

d8

MO

VEA

RW3

,@

RW5+

d8

MO

VEA

RW3

,@

RW6+

d8

MO

VEA

RW3

,@

RW7+

d8

MO

VEA

RW3

,@

RW0+

d16

MO

VEA

RW3

,@

RW1+

d16

MO

VEA

RW3

,@

RW2+

d16

MO

VEA

RW3

,@

RW3+

d16

MO

VEA

RW3

,@RW

0+RW

7

MO

VEA

RW3

,@RW

1+RW

7

MO

VEA

RW3

,

@PC

+d16

MO

VEA

RW3

,

addr

16

MO

VEA

R

W4,

RW0

MO

VEA

R

W4,

RW1

MO

VEA

R

W4,

RW2

MO

VEA

R

W4,

RW3

MO

VEA

R

W4,

RW4

MO

VEA

R

W4,

RW5

MO

VEA

R

W4,

RW6

MO

VEA

R

W4,

RW7

MO

VEA

RW4,

@RW

0

MO

VEA

RW4,

@RW

1

MO

VEA

RW4,

@RW

2

MO

VEA

RW4,

@RW

3

MO

VEA

R

W4,

@RW

0+

MO

VEA

R

W4,

@RW

1+

MO

VEA

R

W4,

@RW

2+

MO

VEA

R

W4,

@RW

3+

MO

VEA

RW4

,@

RW0+

d8

MO

VEA

RW4

,@

RW1+

d8

MO

VEA

RW4

,@

RW2+

d8

MO

VEA

RW4

,@

RW3+

d8

MO

VEA

RW4

,@

RW4+

d8

MO

VEA

RW4

,@

RW5+

d8

MO

VEA

RW4

,@

RW6+

d8

MO

VEA

RW4

,@

RW7+

d8

MO

VEA

RW4

,@

RW0+

d16

MO

VEA

RW4

,@

RW1+

d16

MO

VEA

RW4

,@

RW2+

d16

MO

VEA

RW4

,@

RW3+

d16

MO

VEA

RW4

,@RW

0+RW

7

MO

VEA

RW4

,@RW

1+RW

7

MO

VEA

RW4

,@PC

+d16

MO

VEA

RW4

,

addr

16

MO

VEA

R

W5,

RW0

MO

VEA

R

W5,

RW1

MO

VEA

R

W5,

RW2

MO

VEA

R

W5,

RW3

MO

VEA

R

W5,

RW4

MO

VEA

R

W5,

RW5

MO

VEA

R

W5,

RW6

MO

VEA

R

W5,

RW7

MO

VEA

RW5,

@RW

0

MO

VEA

RW5,

@RW

1

MO

VEA

RW5,

@RW

2

MO

VEA

RW5,

@RW

3

MO

VEA

R

W5,

@RW

0+

MO

VEA

R

W5,

@RW

1+

MO

VEA

R

W5,

@RW

2+

MO

VEA

R

W5,

@RW

3+

MO

VEA

RW5

,

@RW

0+d8

MO

VEA

RW5

,

@RW

1+d8

MO

VEA

RW5

,

@RW

2+d8

MO

VEA

RW5

,

@RW

3+d8

MO

VEA

RW5

,

@RW

4+d8

MO

VEA

RW5

,

@RW

5+d8

MO

VEA

RW5

,

@RW

6+d8

MO

VEA

RW5

,

@RW

7+d8

MO

VEA

RW5

,@

RW0+

d16

MO

VEA

RW5

,@

RW1+

d16

MO

VEA

RW5

,@

RW2+

d16

MO

VEA

RW5

,@

RW3+

d16

MO

VEA

RW5

,@RW

0+RW

7

MO

VEA

RW5

,@RW

1+RW

7

MO

VEA

RW5

,@PC

+d16

MO

VEA

RW5

,add

r16

MO

VEA

R

W6,

RW0

MO

VEA

R

W6,

RW1

MO

VEA

R

W6,

RW2

MO

VEA

R

W6,

RW3

MO

VEA

R

W6,

RW4

MO

VEA

R

W6,

RW5

MO

VEA

R

W6,

RW6

MO

VEA

R

W6,

RW7

MO

VEA

RW6,

@RW

0

MO

VEA

RW6,

@RW

1

MO

VEA

RW6,

@RW

2

MO

VEA

RW6,

@RW

3

MO

VEA

R

W6,

@RW

0+

MO

VEA

R

W6,

@RW

1+

MO

VEA

R

W6,

@RW

2+

MO

VEA

R

W6,

@RW

3+

MO

VEA

RW6

,@

RW0+

d8

MO

VEA

RW6

,@

RW1+

d8

MO

VEA

RW6

,@

RW2+

d8

MO

VEA

RW6

,@

RW3+

d8

MO

VEA

RW6

,@

RW4+

d8

MO

VEA

RW6

,@

RW5+

d8

MO

VEA

RW6

,@

RW6+

d8

MO

VEA

RW6

,@

RW7+

d8

MO

VEA

RW6

,@

RW0+

d16

MO

VEA

RW6

,@

RW1+

d16

MO

VEA

RW6

,@

RW2+

d16

MO

VEA

RW6

,@

RW3+

d16

MO

VEA

RW6

,@RW

0+RW

7

MO

VEA

RW6

,@RW

1+RW

7

MO

VEA

RW6

,

@PC

+d16

MO

VEA

RW6

,

addr

16

MO

VEA

R

W7,

RW0

MO

VEA

R

W7,

RW1

MO

VEA

R

W7,

RW2

MO

VEA

R

W7,

RW3

MO

VEA

R

W7,

RW4

MO

VEA

R

W7,

RW5

MO

VEA

R

W7,

RW6

MO

VEA

R

W7,

RW7

MO

VEA

RW7,

@RW

0

MO

VEA

RW7,

@RW

1

MO

VEA

RW7,

@RW

2

MO

VEA

RW7,

@RW

3

MO

VEA

R

W7,

@RW

0+

MO

VEA

R

W7,

@RW

1+

MO

VEA

R

W7,

@RW

2+

MO

VEA

R

W7,

@RW

3+

MO

VEA

RW7

,

@RW

0+d8

MO

VEA

RW7

,

@RW

1+d8

MO

VEA

RW7

,

@RW

2+d8

MO

VEA

RW7

,

@RW

3+d8

MO

VEA

RW7

,

@RW

4+d8

MO

VEA

RW7

,

@RW

5+d8

MO

VEA

RW7

,

@RW

6+d8

MO

VEA

RW7

,

@RW

7+d8

MO

VEA

RW7

,@

RW0+

d16

MO

VEA

RW7

,@

RW1+

d16

MO

VEA

RW7

,@

RW2+

d16

MO

VEA

RW7

,@

RW3+

d16

MO

VEA

RW7

,@RW

0+RW

7

MO

VEA

RW7

,@RW

1+RW

7

MO

VEA

RW7

,

@PC

+d16

MO

VEA

RW7

,

addr

16

+0

+1

+2

+3

+4

+5

+6

+7

+8

+9

+A

+B

+C

+D +E +F

482


Table D.9-16 MOV Ri, ea Instruction (First Byte = 7A H)

0010

2030

4050

6070

8090

A0

B0

C0

D0

E0

F0

MO

V

R

0,R

0

MO

V

R

0,R

1

MO

V

R

0,R

2

MO

V

R

0,R

3

MO

V

R

0,R

4

MO

V

R

0,R

5

MO

V

R

0,R

6

MO

V

R

0,R

7

MO

V

R

0,@

RW

0

MO

V

R

0,@

RW

1

MO

V

R

0,@

RW

2

MO

V

R

0,@

RW

3

MO

V

R

0,

@R

W0+

MO

V

R

0,

@R

W1+

MO

V

R

0,

@R

W2+

MO

V

R

0,

@R

W3+

MO

V

R0,

@R

W0+

d8

MO

V

R0,

@R

W1+

d8

MO

V

R0,

@R

W2+

d8

MO

V

R0,

@R

W3+

d8

MO

V

R0,

@R

W4+

d8

MO

V

R0,

@R

W5+

d8

MO

V

R0,

@R

W6+

d8

MO

V

R0,

@R

W7+

d8

MO

V

R0,

@R

W0+

d16

MO

V

R0,

@R

W1+

d16

MO

V

R0,

@R

W2+

d16

MO

V

R0,

@R

W3+

d16

MO

V

R0,

@R

W0+

RW

7

MO

V

R0,

@R

W1+

RW

7

MO

V

R0,

@

PC+d

16

MO

V

R0,

ad

dr16

MO

V

R

1,R

0

MO

V

R

1,R

1

MO

V

R

1,R

2

MO

V

R

1,R

3

MO

V

R

1,R

4

MO

V

R

1,R

5

MO

V

R

1,R

6

MO

V

R

1,R

7

MO

V

R

1,@

RW

0

MO

V

R

1,@

RW

1

MO

V

R

1,@

RW

2

MO

V

R

1,@

RW

3

MO

V

R

1,

@R

W0+

MO

V

R

1,

@R

W1+

MO

V

R

1,

@R

W2+

MO

V

R

1,

@R

W3+

MO

V

R1,

@R

W0+

d8

MO

V

R1,

@R

W1+

d8

MO

V

R1,

@R

W2+

d8

MO

V

R1,

@R

W3+

d8

MO

V

R1,

@R

W4+

d8

MO

V

R1,

@R

W5+

d8

MO

V

R1,

@R

W6+

d8

MO

V

R1,

@R

W7+

d8

MO

V

R1,

@R

W0+

d16

MO

V

R1,

@R

W1+

d16

MO

V

R1,

@R

W2+

d16

MO

V

R1,

@R

W3+

d16

MO

V

R1,

@R

W0+

RW

7

MO

V

R1,

@R

W1+

RW

7

MO

V

R1,

@

PC+d

16

MO

V

R1,

ad

dr16

MO

V

R

2,R

0

MO

V

R

2,R

1

MO

V

R

2,R

2

MO

V

R

2,R

3

MO

V

R

2,R

4

MO

V

R

2,R

5

MO

V

R

2,R

6

MO

V

R

2,R

7

MO

V

R

2,@

RW

0

MO

V

R

2,@

RW

1

MO

V

R

2,@

RW

2

MO

V

R

2,@

RW

3

MO

V

R

2,

@R

W0+

MO

V

R

2,

@R

W1+

MO

V

R

2,

@R

W2+

MO

V

R

2,

@R

W3+

MO

V

R2,

@R

W0+

d8

MO

V

R2,

@R

W1+

d8

MO

V

R2,

@R

W2+

d8

MO

V

R2,

@R

W3+

d8

MO

V

R2,

@R

W4+

d8

MO

V

R2,

@R

W5+

d8

MO

V

R2,

@R

W6+

d8

MO

V

R2,

@R

W7+

d8

MO

V

R2,

@R

W0+

d16

MO

V

R2,

@R

W1+

d16

MO

V

R2,

@R

W2+

d16

MO

V

R2,

@R

W3+

d16

MO

V

R2,

@R

W0+

RW

7

MO

V

R2,

@R

W1+

RW

7

MO

V

R2,

@

PC+d

16

MO

V

R2,

ad

dr16

MO

V

R

3,R

0

MO

V

R

3,R

1

MO

V

R

3,R

2

MO

V

R

3,R

3

MO

V

R

3,R

4

MO

V

R

3,R

5

MO

V

R

3,R

6

MO

V

R

3,R

7

MO

V

R3,

@R

W0

MO

V

R

3,@

RW

1

MO

V

R

3,@

RW

2

MO

V

R

3,@

RW

3

MO

V

R

3,

@R

W0+

MO

V

R

3,

@R

W1+

MO

V

R

3,

@R

W2+

MO

V

R

3,

@R

W3+

MO

V

R3,

@R

W0+

d8

MO

V

R3,

@R

W1+

d8

MO

V

R3,

@R

W2+

d8

MO

V

R3,

@R

W3+

d8

MO

V

R3,

@R

W4+

d8

MO

V

R3,

@R

W5+

d8

MO

V

R3,

@R

W6+

d8

MO

V

R3,

@R

W7+

d8

MO

V

R3,

@R

W0+

d16

MO

V

R3,

@R

W1+

d16

MO

V

R3,

@R

W2+

d16

MO

V

R3,

@R

W3+

d16

MO

V

R3,

@R

W0+

RW

7

MO

V

R3,

@R

W1+

RW

7

MO

V

R3,

@

PC+d

16

MO

V

R3,

ad

dr16

MO

V

R

4,R

0

MO

V

R

4,R

1

MO

V

R

4,R

2

MO

V

R

4,R

3

MO

V

R

4,R

4

MO

V

R

4,R

5

MO

V

R

4,R

6

MO

V

R

4,R

7

MO

V

R

4,@

RW

0

MO

V

R

4,@

RW

1

MO

V

R

4,@

RW

2

MO

V

R

4,@

RW

3

MO

V

R

4,

@R

W0+

MO

V

R

4,

@R

W1+

MO

V

R

4,

@R

W2+

MO

V

R

4,

@R

W3+

MO

V

R4,

@R

W0+

d8

MO

V

R4,

@R

W1+

d8

MO

V

R4,

@R

W2+

d8

MO

V

R4,

@R

W3+

d8

MO

V

R4,

@R

W4+

d8

MO

V

R4,

@R

W5+

d8

MO

V

R4,

@R

W6+

d8

MO

V

R4,

@R

W7+

d8

MO

V

R4,

@R

W0+

d16

MO

V

R4,

@R

W1+

d16

MO

V

R4,

@R

W2+

d16

MO

V

R4,

@R

W3+

d16

MO

V

R4,

@R

W0+

RW

7

MO

V

R4,

@R

W1+

RW

7

MO

V

R4,

@

PC+d

16

MO

V

R4,

ad

dr16

MO

V

R

5,R

0

MO

V

R

5,R

1

MO

V

R

5,R

2

MO

V

R

5,R

3

MO

V

R

5,R

4

MO

V

R

5,R

5

MO

V

R

5,R

6

MO

V

R

5,R

7

MO

V

R

5,@

RW

0

MO

V

R

5,@

RW

1

MO

V

R

5,@

RW

2

MO

V

R

5,@

RW

3

MO

V

R

5,

@R

W0+

MO

V

R

5,

@R

W1+

MO

V

R

5,

@R

W2+

MO

V

R

5,

@R

W3+

MO

V

R5,

@R

W0+

d8

MO

V

R5,

@R

W1+

d8

MO

V

R5,

@R

W2+

d8

MO

V

R5,

@R

W3+

d8

MO

V

R5,

@R

W4+

d8

MO

V

R5,

@R

W5+

d8

MO

V

R5,

@R

W6+

d8

MO

V

R5,

@R

W7+

d8

MO

V

R5,

@R

W0+

d16

MO

V

R5,

@R

W1+

d16

MO

V

R5,

@R

W2+

d16

MO

V

R5,

@R

W3+

d16

MO

V

R5,

@R

W0+

RW

7

MO

V

R5,

@R

W1+

RW

7

MO

V

R5,

@

PC+d

16

MO

V

R5,

ad

dr16

MO

V

R

6,R

0

MO

V

R

6,R

1

MO

V

R

6,R

2

MO

V

R

6,R

3

MO

V

R

6,R

4

MO

V

R

6,R

5

MO

V

R

6,R

6

MO

V

R

6,R

7

MO

V

R

6,@

RW

0

MO

V

R

6,@

RW

1

MO

V

R

6,@

RW

2

MO

V

R

6,@

RW

3

MO

V

R

6,

@R

W0+

MO

V

R

6,

@R

W1+

MO

V

R

6,

@R

W2+

MO

V

R

6,

@R

W3+

MO

V

R6,

@R

W0+

d8

MO

V

R6,

@R

W1+

d8

MO

V

R6,

@R

W2+

d8

MO

V

R6,

@R

W3+

d8

MO

V

R6,

@R

W4+

d8

MO

V

R6,

@R

W5+

d8

MO

V

R6,

@R

W6+

d8

MO

V

R6,

@R

W7+

d8

MO

V

R6,

@R

W0+

d16

MO

V

R6,

@R

W1+

d16

MO

V

R6,

@R

W2+

d16

MO

V

R6,

@R

W3+

d16

MO

V

R6,

@R

W0+

RW

7

MO

V

R6,

@R

W1+

RW

7

MO

V

R6,

@

PC+d

16

MO

V

R6,

a

ddr1

6

MO

V

R

7,R

0

MO

V

R

7,R

1

MO

V

R

7,R

2

MO

V

R

7,R

3

MO

V

R

7,R

4

MO

V

R

7,R

5

MO

V

R

7,R

6

MO

V

R

7,R

7

MO

V

R

7,@

RW

0

MO

V

R

7,@

RW

1

MO

V

R

7,@

RW

2

MO

V

R

7,@

RW

3

MO

V

R

7,

@R

W0+

MO

V

R

7,

@R

W1+

MO

V

R

7,

@R

W2+

MO

V

R

7,

@R

W3+

MO

V

R7,

@R

W0+

d8

MO

V

R7,

@R

W1+

d8

MO

V

R7,

@R

W2+

d8

MO

V

R7,

@R

W3+

d8

MO

V

R7,

@R

W4+

d8

MO

V

R7,

@R

W5+

d8

MO

V

R7,

@R

W6+

d8

MO

V

R7,

@R

W7+

d8

MO

V

R7,

@R

W0+

d16

MO

V

R7,

@R

W1+

d16

MO

V

R7,

@R

W2+

d16

MO

V

R7,

@R

W3+

d16

MO

V

R7,

@R

W0+

RW

7

MO

V

R7,

@R

W1+

RW

7

MO

V

R7,

@

PC+d

16

MO

V

R7,

ad

dr16

+0

+1

+2

+3

+4

+5

+6

+7

+8

+9

+A

+B

+C

+D +E +F

483


Table D.9-17 MOVW RWi, ea Instruction 4 (First Byte = 7B H)

0010

2030

4050

6070

8090

A0

B0

C0

D0

E0

F0

MO

VW

R

W0,

RW

0

MO

VW

R

W0,

RW

1

MO

VW

R

W0,

RW

2

MO

VW

R

W0,

RW

3

MO

VW

R

W0,

RW

4

MO

VW

R

W0,

RW

5

MO

VW

R

W0,

RW

6

MO

VW

R

W0,

RW

7

MO

VW

RW

O,@

RW

0

MO

VW

RW

O,@

RW

1

MO

VW

RW

O,@

RW

2

MO

VW

RW

O,@

RW

3

MO

VW

RW0,

@RW

0+

MO

VW

RW0,

@RW

1+

MO

VW

RW0,

@RW

2+

MO

VW

RW0,

@RW

3+

MO

VW R

W0

,@

RW

0+d8

MO

VW R

W0

,@

RW

1+d8

MO

VW R

W0

,@

RW

2+d8

MO

VW R

W0

,@

RW

3+d8

MO

VW R

W0

,@

RW

4+d8

MO

VW R

W0

,@

RW

5+d8

MO

VW R

W0

,@

RW

6+d8

MO

VW R

W0

,@

RW

7+d8

MO

VW R

WO

,

@R

W0+

d16

MO

VW R

WO

,

@R

W1+

d16

MO

VW R

WO

,

@R

W2+

d16

MO

VW R

WO

,

@R

W3+

d16

MO

VW R

WO

,

@R

W0+

RW

7

MO

VW R

WO

,

@R

W1+

RW

7

MO

VW

RW0,

@PC

+d16

MO

VW

RW

0,ad

dr16

MO

VW

R

W1,

RW

0

MO

VW

R

W1,

RW

1

MO

VW

R

W1,

RW

2

MO

VW

R

W1,

RW

3

MO

VW

R

W1,

RW

4

MO

VW

R

W1,

RW

5

MO

VW

R

W1,

RW

6

MO

VW

R

W1,

RW

7

MO

VW

RW

1,@

RW

0

MO

VW

RW

1,@

RW

1

MO

VW

RW

1,@

RW

2

MO

VW

RW

1,@

RW

3

MO

VW

RW1,

@RW

0+

MO

VW

RW1,

@RW

1+

MO

VW

RW1,

@RW

2+

MO

VW

RW1,

@RW

3+

MO

VW R

W1

,@

RW

0+d8

MO

VW R

W1

,@

RW

1+d8

MO

VW R

W1

,@

RW

2+d8

MO

VW R

W1

,@

RW

3+d8

MO

VW R

W1

,@

RW

4+d8

MO

VW R

W1

,@

RW

5+d8

MO

VW R

W1

,@

RW

6+d8

MO

VW R

W1

,@

RW

7+d8

MO

VW R

W1,

@R

W0+

d16

MO

VW R

W1,

@R

W1+

d16

MO

VW R

W1,

@R

W2+

d16

MO

VW R

W1,

@R

W3+

d16

MO

VW R

W1,

@R

W0+

RW

7

MO

VW R

W1,

@R

W1+

RW

7

MO

VW R

W1

,@

PC+d

16

MO

VW

RW

1,a

ddr1

6

MO

VW

R

W2,

RW

0

MO

VW

R

W2,

RW

1

MO

VW

R

W2,

RW

2

MO

VW

R

W2,

RW

3

MO

VW

R

W2,

RW

4

MO

VW

R

W2,

RW

5

MO

VW

R

W2,

RW

6

MO

VW

R

W2,

RW

7

MO

VW

RW

2,@

RW

0

MO

VW

RW

2,@

RW

1

MO

VW

RW

2,@

RW

2

MO

VW

RW

2,@

RW

3

MO

VW

R

W2,

@R

W0+

MO

VW

R

W2,

@R

W1+

MO

VW

R

W2,

@R

W2+

MO

VW

R

W2,

@R

W3+

MO

VW R

W2

,@

RW

0+d8

MO

VW R

W2

,@

RW

1+d8

MO

VW R

W2

,@

RW

2+d8

MO

VW R

W2

,@

RW

3+d8

MO

VW R

W2

,@

RW

4+d8

MO

VW R

W2

,@

RW

5+d8

MO

VW R

W2

,@

RW

6+d8

MO

VW R

W2

,@

RW

7+d8

MO

VW R

W2,

@R

W0+

d16

MO

VW R

W2,

@R

W1+

d16

MO

VW R

W2,

@R

W2+

d16

MO

VW R

W2,

@R

W3+

d16

MO

VW R

W2,

@R

W0+

RW

7

MO

VW R

W2,

@R

W1+

RW

7

MO

VW R

W2

,

@PC

+d16

MO

VW

RW

2,a

ddr1

6

MO

VW

R

W3,

RW

0

MO

VW

R

W3,

RW

1

MO

VW

R

W3,

RW

2

MO

VW

R

W3,

RW

3

MO

VW

R

W3,

RW

4

MO

VW

R

W3,

RW

5

MO

VW

R

W3,

RW

6

MO

VW

R

W3,

RW

7

MO

VW

RW

3,@

RW

0

MO

VW

RW

3,@

RW

1

MO

VW

RW

3,@

RW

2

MO

VW

RW

3,@

RW

3

MO

VW

R

W3,

@R

W0+

MO

VW

R

W3,

@R

W1+

MO

VW

R

W3,

@R

W2+

MO

VW

R

W3,

@R

W3+

MO

VW R

W3

,@

RW

0+d8

MO

VW R

W3

,@

RW

1+d8

MO

VW R

W3

,@

RW

2+d8

MO

VW R

W3

,@

RW

3+d8

MO

VW R

W3

,@

RW

4+d8

MO

VW R

W3

,@

RW

5+d8

MO

VW R

W3

,@

RW

6+d8

MO

VW R

W3

,@

RW

7+d8

MO

VW R

W3,

@R

W0+

d16

MO

VW R

W3,

@R

W1+

d16

MO

VW R

W3,

@R

W2+

d16

MO

VW R

W3,

@R

W3+

d16

MO

VW R

W3,

@R

W0+

RW

7

MO

VW R

W3,

@R

W1+

RW

7

MO

VW R

W3

,@

PC+d

16

MO

VW

RW

3,a

ddr1

6

MO

VW

R

W4,

RW

0

MO

VW

R

W4,

RW

1

MO

VW

R

W4,

RW

2

MO

VW

R

W4,

RW

3

MO

VW

R

W4,

RW

4

MO

VW

R

W4,

RW

5

MO

VW

R

W4,

RW

6

MO

VW

R

W4,

RW

7

MO

VW

RW

4,@

RW

0

MO

VW

RW

4,@

RW

1

MO

VW

RW

4,@

RW

2

MO

VW

RW

4,@

RW

3

MO

VW

R

W4,

@R

W0+

MO

VW

R

W4,

@R

W1+

MO

VW

R

W4,

@R

W2+

MO

VW

R

W4,

@R

W3+

MO

VW R

W4

,@

RW

0+d8

MO

VW R

W4

,@

RW

1+d8

MO

VW R

W4

,@

RW

2+d8

MO

VW R

W4

,@

RW

3+d8

MO

VW R

W4

,@

RW

4+d8

MO

VW R

W4

,@

RW

5+d8

MO

VW R

W4

,@

RW

6+d8

MO

VW R

W4

,@

RW

7+d8

MO

VW R

W4,

@R

W0+

d16

MO

VW R

W4,

@R

W1+

d16

MO

VW R

W4,

@R

W2+

d16

MO

VW R

W4,

@R

W3+

d16

MO

VW R

W4,

@R

W0+

RW

7

MO

VW R

W4,

@R

W1+

RW

7

MO

VW R

W4

,

@PC

+d16

MO

VW

RW

4,a

ddr1

6

MO

VW

R

W5,

RW

0

MO

VW

R

W5,

RW

1

MO

VW

R

W5,

RW

2

MO

VW

R

W5,

RW

3

MO

VW

R

W5,

RW

4

MO

VW

R

W5,

RW

5

MO

VW

R

W5,

RW

6

MO

VW

R

W5,

RW

7

MO

VW

RW

5,@

RW

0

MO

VW

RW

5,@

RW

1

MO

VW

RW

5,@

RW

2

MO

VW

RW

5,@

RW

3

MO

VW

R

W5,

@R

W0+

MO

VW

R

W5,

@R

W1+

MO

VW

R

W5,

@R

W2+

MO

VW

R

W5,

@R

W3+

MO

VW R

W5

,@

RW

0+d8

MO

VW R

W5

,@

RW

1+d8

MO

VW R

W5

,@

RW

2+d8

MO

VW R

W5

,@

RW

3+d8

MO

VW R

W5

,@

RW

4+d8

MO

VW R

W5

,@

RW

5+d8

MO

VW R

W5

,@

RW

6+d8

MO

VW R

W5

,@

RW

7+d8

MO

VW R

W5,

@R

W0+

d16

MO

VW R

W5,

@R

W1+

d16

MO

VW R

W5,

@R

W2+

d16

MO

VW R

W5,

@R

W3+

d16

MO

VW R

W5,

@R

W0+

RW

7

MO

VW R

W5,

@R

W1+

RW

7

MO

VW R

W5

,

@PC

+d16

MO

VW

RW

5,a

ddr1

6

MO

VW

R

W6,

RW

0

MO

VW

R

W6,

RW

1

MO

VW

R

W6,

RW

2

MO

VW

R

W6,

RW

3

MO

VW

R

W6,

RW

4

MO

VW

R

W6,

RW

5

MO

VW

R

W6,

RW

6

MO

VW

R

W6,

RW

7

MO

VW

RW

6,@

RW

0

MO

VW

RW

6,@

RW

1

MO

VW

RW

6,@

RW

2

MO

VW

RW

6,@

RW

3

MO

VW

R

W6,

@R

W0+

MO

VW

R

W6,

@R

W1+

MO

VW

R

W6,

@R

W2+

MO

VW

R

W6,

@R

W3+

MO

VW R

W6

,@

RW

0+d8

MO

VW R

W6

,@

RW

1+d8

MO

VW R

W6

,@

RW

2+d8

MO

VW R

W6

,@

RW

3+d8

MO

VW R

W6

,@

RW

4+d8

MO

VW R

W6

,@

RW

5+d8

MO

VW R

W6

,@

RW

6+d8

MO

VW R

W6

,@

RW

7+d8

MO

VW R

W6,

@R

W0+

d16

MO

VW R

W6,

@R

W1+

d16

MO

VW R

W6,

@R

W2+

d16

MO

VW R

W6,

@R

W3+

d16

MO

VW R

W6,

@R

W0+

RW

7

MO

VW R

W6,

@R

W1+

RW

7

MO

VW R

W6

,

@PC

+d16

MO

VW

RW

6,a

ddr1

6

MO

VW

R

W7,

RW

0

MO

VW

R

W7,

RW

1

MO

VW

R

W7,

RW

2

MO

VW

R

W7,

RW

3

MO

VW

R

W7,

RW

4

MO

VW

R

W7,

RW

5

MO

VW

R

W7,

RW

6

MO

VW

R

W7,

RW

7

MO

VW

RW

7,@

RW

0

MO

VW

RW

7,@

RW

1

MO

VW

RW

7,@

RW

2

MO

VW

RW

7,@

RW

3

MO

VW

R

W7,

@R

W0+

MO

VW

R

W7,

@R

W1+

MO

VW

R

W7,

@R

W2+

MO

VW

R

W7,

@R

W3+

MO

VW R

W7

,@

RW

0+d8

MO

VW R

W7

,@

RW

1+d8

MO

VW R

W7

,@

RW

2+d8

MO

VW R

W7

,@

RW

3+d8

MO

VW R

W7

,@

RW

4+d8

MO

VW R

W7

,@

RW

5+d8

MO

VW R

W7

,@

RW

6+d8

MO

VW R

W7

,@

RW

7+d8

MO

VW R

W7,

@R

W0+

d16

MO

VW R

W7,

@R

W1+

d16

MO

VW R

W7,

@R

W2+

d16

MO

VW R

W7,

@R

W3+

d16

MO

VW R

W7,

@R

W0+

RW

7

MO

VW R

W7,

@R

W1+

RW

7

MO

VW R

W7

,

@PC

+d16

MO

VW

RW

7,a

ddr1

6

+0

+1

+2

+3

+4

+5

+6

+7

+8

+9

+A

+B

+C

+D +E +F

484


Table D.9-18 BMOV ea, Ri Instruction (First Byte = 7C H)

0010

2030

4050

6070

8090

A0

B0

C0

D0

E0

F0

MO

V

R

0,R

0

MO

V

R

1,R

0

MO

V

R

2,R

0

MO

V

R

3,R

0

MO

V

R

4,R

0

MO

V

R

5,R

0

MO

V

R

6,R

0

MO

V

R

7,R

0

MO

V

@R

W0,

R0

MO

V

@R

W1,

R0

MO

V

@R

W2,

R0

MO

V

@R

W3,

R0

MO

V

@R

W0+

,R0

MO

V

@R

W1+

,R0

MO

V

@R

W2+

,R0

MO

V

@R

W3+

,R0

MO

V

@R

W0+

d8,R

0

MO

V

@R

W1+

d8,R

0

MO

V

@R

W2+

d8,R

0

MO

V

@R

W3+

d8,R

0

MO

V

@R

W4+

d8,R

0

MO

V

@R

W5+

d8,R

0

MO

V

@R

W6+

d8,R

0

MO

V

@R

W7+

d8,R

0

MO

V @

RW

0+d1

6,R

0

MO

V @

RW

1+d1

6,R

0

MO

V @

RW

2+d1

6,R

0

MO

V @

RW

3+d1

6,R

0

MO

V @

RW

0+R

W7,

R0

MO

V @

RW

1+R

W7,

R0

MO

V

P

C+d

16,R

0

MO

V

a

ddr1

6,R

0

MO

V

R

0,R

1

MO

V

R

1,R

1

MO

V

R

2,R

1

MO

V

R

3,R

1

MO

V

R

4,R

1

MO

V

R

5,R

1

MO

V

R

6,R

1

MO

V

R

7,R

1

MO

V

@R

W0,

R1

MO

V

@R

W1,

R1

MO

V

@R

W2,

R1

MO

V

@R

W3,

R1

MO

V

@R

W0+

,R1

MO

V

@R

W1+

,R1

MO

V

@R

W2+

,R1

MO

V

@R

W3+

,R1

MO

V

@R

W0+

d8,R

1

MO

V

@R

W1+

d8,R

1

MO

V

@R

W2+

d8,R

1

MO

V

@R

W3+

d8,R

1

MO

V

@R

W4+

d8,R

1

MO

V

@R

W5+

d8,R

1

MO

V

@R

W6+

d8,R

1

MO

V

@R

W7+

d8,R

1

MO

V @

RW

0+d1

6,R

1

MO

V @

RW

1+d1

6,R

1

MO

V @

RW

2+d1

6,R

1

MO

V @

RW

3+d1

6,R

1

MO

V @

RW

0+R

W7,

R1

MO

V @

RW

1+R

W7,

R1

MO

V

P

C+d

16,R

1

MO

V

a

ddr1

6,R

1

MO

V

R

0,R

2

MO

V

R

1,R

2

MO

V

R

2,R

2

MO

V

R

3,R

2

MO

V

R

4,R

2

MO

V

R

5,R

2

MO

V

R

6,R

2

MO

V

R

7,R

2

MO

V

@R

W0,

R2

MO

V

@R

W1,

R2

MO

V

@R

W2,

R2

MO

V

@R

W3,

R2

MO

V

@R

W0+

,R2

MO

V

@R

W1+

,R2

MO

V

@R

W2+

,R2

MO

V

@R

W3+

,R2

MO

V

@R

W0+

d8,R

2

MO

V

@R

W1+

d8,R

2

MO

V

@R

W2+

d8,R

2

MO

V

@R

W3+

d8,R

2

MO

V

@R

W4+

d8,R

2

MO

V

@R

W5+

d8,R

2

MO

V

@R

W6+

d8,R

2

MO

V

@R

W7+

d8,R

2

MO

V @

RW

0+d1

6,R

2

MO

V @

RW

1+d1

6,R

2

MO

V @

RW

2+d1

6,R

2

MO

V @

RW

3+d1

6,R

2

MO

V @

RW

0+R

W7,

R2

MO

V @

RW

1+R

W7,

R2

MO

V

P

C+d

16,R

2

MO

V

a

ddr1

6,R

2

MO

V

R

0,R

3

MO

V

R

1,R

3

MO

V

R

2,R

3

MO

V

R

3,R

3

MO

V

R

4,R

3

MO

V

R

5,R

3

MO

V

R

6,R

3

MO

V

R

7,R

3

MO

V

@R

W0,

R3

MO

V

@R

W1,

R3

MO

V

@R

W2,

R3

MO

V

@R

W3,

R3

MO

V

@R

W0+

,R3

MO

V

@R

W1+

,R3

MO

V

@R

W2+

,R3

MO

V

@R

W3+

,R3

MO

V

@R

W0+

d8,R

3

MO

V

@R

W1+

d8,R

3

MO

V

@R

W2+

d8,R

3

MO

V

@R

W3+

d8,R

3

MO

V

@R

W4+

d8,R

3

MO

V

@R

W5+

d8,R

3

MO

V

@R

W6+

d8,R

3

MO

V

@R

W7+

d8,R

3

MO

V @

RW

0+d1

6,R

3

MO

V @

RW

1+d1

6,R

3

MO

V @

RW

2+d1

6,R

3

MO

V @

RW

3+d1

6,R

3

MO

V @

RW

0+R

W7,

R3

MO

V @

RW

1+R

W7,

R3

MO

V

P

C+d

16,R

3

MO

V

a

ddr1

6,R

3

MO

V

R

0,R

4

MO

V

R

1,R

4

MO

V

R

2,R

4

MO

V

R

3,R

4

MO

V

R

4,R

4

MO

V

R

5,R

4

MO

V

R

6,R

4

MO

V

R

7,R

4

MO

V

@R

W0,

R4

MO

V

@R

W1,

R4

MO

V

@R

W2,

R4

MO

V

@R

W3,

R4

MO

V

@R

W0+

,R4

MO

V

@R

W1+

,R4

MO

V

@R

W2+

,R4

MO

V

@R

W3+

,R4

MO

V

@R

W0+

d8,R

4

MO

V

@R

W1+

d8,R

4

MO

V

@R

W2+

d8,R

4

MO

V

@R

W3+

d8,R

4

MO

V

@R

W4+

d8,R

4

MO

V

@R

W5+

d8,R

4

MO

V

@R

W6+

d8,R

4

MO

V

@R

W7+

d8,R

4

MO

V @

RW

0+d1

6,R

4

MO

V @

RW

1+d1

6,R

4

MO

V @

RW

2+d1

6,R

4

MO

V @

RW

3+d1

6,R

4

MO

V @

RW

0+R

W7,

R4

MO

V @

RW

1+R

W7,

R4

MO

V

P

C+d

16,R

4

MO

V

a

ddr1

6,R

4

MO

V

R

0,R

5

MO

V

R

1,R

5

MO

V

R

2,R

5

MO

V

R

3,R

5

MO

V

R

4,R

5

MO

V

R

5,R

5

MO

V

R

6,R

5

MO

V

R

7,R

5

MO

V

@R

W0,

R5

MO

V

@R

W1,

R5

MO

V

@R

W2,

R5

MO

V

@R

W3,

R5

MO

V

@R

W0+

,R5

MO

V

@R

W1+

,R5

MO

V

@R

W2+

,R5

MO

V

@R

W3+

,R5

MO

V

@R

W0+

d8,R

5

MO

V

@R

W1+

d8,R

5

MO

V

@R

W2+

d8,R

5

MO

V

@R

W3+

d8,R

5

MO

V

@R

W4+

d8,R

5

MO

V

@R

W5+

d8,R

5

MO

V

@R

W6+

d8,R

5

MO

V

@R

W7+

d8,R

5

MO

V @

RW

0+d1

6,R

5

MO

V @

RW

1+d1

6,R

5

MO

V @

RW

2+d1

6,R

5

MO

V @

RW

3+d1

6,R

5

MO

V @

RW

0+R

W7,

R5

MO

V @

RW

1+R

W7,

R5

MO

V

P

C+d

16,R

5

MO

V

a

ddr1

6,R

5

MO

V

R

0,R

6

MO

V

R

1,R

6

MO

V

R

2,R

6

MO

V

R

3,R

6

MO

V

R

4,R

6

MO

V

R

5,R

6

MO

V

R

6,R

6

MO

V

R

7,R

6

MO

V

@R

W0,

R6

MO

V

@R

W1,

R6

MO

V

@R

W2,

R6

MO

V

@R

W3,

R6

MO

V

@R

W0+

,R6

MO

V

@R

W1+

,R6

MO

V

@R

W2+

,R6

MO

V

@R

W3+

,R6

MO

V

@R

W0+

d8,R

6

MO

V

@R

W1+

d8,R

6

MO

V

@R

W2+

d8,R

6

MO

V

@R

W3+

d8,R

6

MO

V

@R

W4+

d8,R

6

MO

V

@R

W5+

d8,R

6

MO

V

@R

W6+

d8,R

6

MO

V

@R

W7+

d8,R

6

MO

V @

RW

0+d1

6,R

6

MO

V @

RW

1+d1

6,R

6

MO

V @

RW

2+d1

6,R

6

MO

V @

RW

3+d1

6,R

6

MO

V @

RW

0+R

W7,

R6

MO

V @

RW

1+R

W7,

R6

MO

V

P

C+d

16,R

6

MO

V

a

ddr1

6,R

6

MO

V

R

0,R

7

MO

V

R

1,R

7

MO

V

R

2,R

7

MO

V

R

3,R

7

MO

V

R

4,R

7

MO

V

R

5,R

7

MO

V

R

6,R

7

MO

V

R

7,R

7

MO

V

@R

W0,

R7

MO

V

@R

W1,

R7

MO

V

@R

W2,

R7

MO

V

@R

W3,

R7

MO

V

@R

W0+

,R7

MO

V

@R

W1+

,R7

MO

V

@R

W2+

,R7

MO

V

@R

W3+

,R7

MO

V

@R

W0+

d8,R

7

MO

V

@R

W1+

d8,R

7

MO

V

@R

W2+

d8,R

7

MO

V

@R

W3+

d8,R

7

MO

V

@R

W4+

d8,R

7

MO

V

@R

W5+

d8,R

7

MO

V

@R

W6+

d8,R

7

MO

V

@R

W7+

d8,R

7

MO

V

@R

W

0+d1

6,R

7

MO

V @

RW

1+d1

6,R

7

MO

V @

RW

2+d1

6,R

7

MO

V @

RW

3+d1

6,R

7

MO

V @

RW

0+R

W7,

R7

MO

V @

RW

1+R

W7,

R7

MO

V

P

C+d

16,R

7

MO

V

a

ddr1

6,R

7

+0

+1

+2

+3

+4

+5

+6

+7

+8

+9

+A

+B

+C

+D +E +F

485


Table D.9-19 MOVW ea, Rwi Instruction (First Byte = 7D H)

0010

2030

4050

6070

8090

A0

B0

C0

D0

E0

F0

MOV

W

RW

0,RW

0

MOV

W

RW

1,RW

0

MOV

W

RW

2,RW

0

MOV

W

RW

3,RW

0

MOV

W

RW

4,RW

0

MOV

W

RW

5,RW

0

MOV

W

RW

6,RW

0

MOV

W

RW

7,RW

0

MOV

W

@RW

0,RW

0

MOV

W

@RW

1,RW

0

MOV

W

@RW

2,RW

0

MOV

W

@RW

3,RW

0

MOV

W

@

RW0+

,RW

0

MOV

W

@

RW1+

,RW

0

MOV

W

@

RW2+

,RW

0

MOV

W

@

RW3+

,RW

0

MOV

W

@RW

0+d

8,RW

0

MOV

W

@RW

1+d

8,RW

0

MOV

W

@RW

2+d

8,RW

0

MOV

W

@RW

3+d

8,RW

0

MOV

W

@RW

4+d

8,RW

0

MOV

W

@RW

5+d

8,RW

0

MOV

W

@RW

6+d

8,RW

0

MOV

W

@RW

7+d

8,RW

0

MOV

W @

RW0

+d1

6,RW

0

MOV

W @

RW1

+d1

6,RW

0

MOV

W @

RW2

+d1

6,RW

0

MOV

W @

RW3

+d1

6,RW

0

MOV

W @

RW0

+RW

7,RW

0

MOV

W @

RW1

+RW

7,RW

0

MOV

W @

PC+

d1

6,RW

0

MOV

W

add

r

16,R

W0

MOV

W

RW

0,RW

1

MOV

W

RW

1,RW

1

MOV

W

RW

2,RW

1

MOV

W

RW

3,RW

1

MOV

W

RW

4,RW

1

MOV

W

RW

5,RW

1

MOV

W

RW

6,RW

1

MOV

W

RW

7,RW

1

MOV

W

@RW

0,RW

1

MOV

W

@RW

1,RW

1

MOV

W

@RW

2,RW

1

MOV

W

@RW

3,RW

1

MOV

W

@

RW0+

,RW

1

MOV

W

@

RW1+

,RW

1

MOV

W

@

RW2+

,RW

1

MOV

W

@

RW3+

,RW

1

MOV

W @

RW

0+d

8,RW

1

MOV

W @

RW

1+d

8,RW

1

MOV

W @

RW

2+d

8,RW

1

MOV

W @

RW

3+d

8,RW

1

MOV

W @

RW

4+d

8,RW

1

MOV

W @

RW

5+d

8,RW

1

MOV

W @

RW

6+d

8,RW

1

MOV

W @

RW

7+d

8,RW

1

MOV

W @

RW0

+d1

6,RW

1

MOV

W @

RW1

+d1

6,RW

1

MOV

W @

RW2

+d1

6,RW

1

MOV

W @

RW3

+d1

6,RW

1

MOV

W @

RW0

+RW

7,RW

1

MOV

W @

RW1

+RW

7,RW

1

MOV

W @

PC+

d

16,R

W1

MOV

W

add

r

16,R

W1

MOV

W

RW

0,RW

2

MOV

W

RW

1,RW

2

MOV

W

RW

2,RW

2

MOV

W

RW

3,RW

2

MOV

W

RW

4,RW

2

MOV

W

RW

5,RW

2

MOV

W

RW

6,RW

2

MOV

W

RW

7,RW

2

MOV

W

@RW

0,RW

2

MOV

W

@RW

1,RW

2

MOV

W

@RW

2,RW

2

MOV

W

@RW

3,RW

2

MOV

W

@

RW0+

,RW

2

MOV

W

@

RW1+

,RW

2

MOV

W

@

RW2+

,RW

2

MOV

W

@

RW3+

,RW

2

MOV

W @

RW

0+d

8,RW

2

MOV

W @

RW

1+d

8,RW

2

MOV

W @

RW

2+d

8,RW

2

MOV

W @

RW

3+d

8,RW

2

MOV

W @

RW

4+d

8,RW

2

MOV

W @

RW

5+d

8,RW

2

MOV

W @

RW

6+d

8,RW

2

MOV

W @

RW

7+d

8,RW

2

MOV

W @

RW0

+d1

6,RW

2

MOV

W @

RW1

+d1

6,RW

2

MOV

W @

RW2

+d1

6,RW

2

MOV

W @

RW3

+d1

6,RW

2

MOV

W @

RW0

+RW

7,RW

2

MOV

W @

RW1

+RW

7,RW

2

MOV

W @

PC+

d

16,R

W2

MOV

W

add

r

1

6,RW

2

MOV

W

RW

0,RW

3

MOV

W

RW

1,RW

3

MOV

W

RW

2,RW

3

MOV

W

RW

3,RW

3

MOV

W

RW

4,RW

3

MOV

W

RW

5,RW

3

MOV

W

RW

6,RW

3

MOV

W

RW

7,RW

3

MOV

W

@RW

0,RW

3

MOV

W

@RW

1,RW

3

MOV

W

@RW

2,RW

3

MOV

W

@RW

3,RW

3

MOV

W

@

RW0+

,RW

3

MOV

W

@

RW1+

,RW

3

MOV

W

@

RW2+

,RW

3

MOV

W

@

RW3+

,RW

3

MOV

W @

RW

0+d

8,RW

3

MOV

W @

RW

1+d

8,RW

3

MOV

W @

RW

2+d

8,RW

3

MOV

W @

RW

3+d

8,RW

3

MOV

W @

RW

4+d

8,RW

3

MOV

W @

RW

5+d

8,RW

3

MOV

W @

RW

6+d

8,RW

3

MOV

W @

RW

7+d

8,RW

3

MOV

W @

RW0

+d1

6,RW

3

MOV

W @

RW1

+d1

6,RW

3

MOV

W @

RW2

+d1

6,RW

3

MOV

W @

RW3

+d1

6,RW

3

MOV

W @

RW0

+RW

7,RW

3

MOV

W @

RW1

+RW

7,RW

3

MOV

W @

PC+

d1

6,RW

3

MOV

W

add

r

1

6,RW

3

MOV

W

RW

0,RW

4

MOV

W

RW1,

RW4

MOV

W

RW2,

RW4

MOV

W

RW3,

RW4

MOV

W

RW4,

RW4

MOV

W

RW5,

RW4

MOV

W

RW6,

RW4

WOV

W

RW7,

RW4

MOV

W

@RW

0,RW

4

MOV

W

@RW

1,RW

4

MOV

W

@RW

2,RW

4

MOV

W

@RW

3,RW

4

MOV

W

@

RW0+

,RW

4

MOV

W

@

RW1+

,RW

4

MOV

W

@

RW2+

,RW

4

MOV

W

@

RW3+

,RW

4

MOV

W @

RW

0+d

8,RW

4

MOV

W @

RW

1+d

8,RW

4

MOV

W @

RW

2+d

8,RW

4

MOV

W @

RW

3+d

8,RW

4

MOV

W @

RW

4+d

8,RW

4

MOV

W @

RW

5+d

8,RW

4

MOV

W @

RW

6+d

8,RW

4

MOV

W @

RW

7+d

8,RW

4

MOV

W @

RW0

+d1

6,RW

4

MOV

W @

RW1

+d1

6,RW

4

MOV

W @

RW2

+d1

6,RW

4

MOV

W @

RW3

+d1

6,RW

4

MOV

W @

RW0

+RW

7,RW

4

MOV

W @

RW1

+RW

7,RW

4

MOV

W @

PC+

d1

6,RW

4

MOV

W

add

r

1

6,RW

4

MOV

W

RW

0,RW

5

MOV

W

RW

1,RW

5

MOV

W

RW

2,RW

5

MOV

W

RW

3,RW

5

MOV

W

RW

4,RW

5

MOV

W

RW

5,RW

5

MOV

W

RW

6,RW

5

WOV

W

RW

7,RW

5

MOV

W

@RW

0,RW

5

MOV

W

@RW

1,RW

5

MOV

W

@RW

2,RW

5

MOV

W

@RW

3,RW

5

MOV

W

@

RW0+

,RW

5

MOV

W

@

RW1+

,RW

5

MOV

W

@

RW2+

,RW

5

MOV

W

@

RW3+

,RW

5

MOV

W @

RW

0+d

8,RW

5

MOV

W @

RW

1+d

8,RW

5

MOV

W @

RW

2+d

8,RW

5

MOV

W @

RW

3+d

8,RW

5

MOV

W @

RW

4+d

8,RW

5

MOV

W @

RW

5+d

8,RW

5

MOV

W @

RW

6+d

8,RW

5

MOV

W @

RW

7+d

8,RW

5

MOV

W @

RW0

+d1

6,RW

5

MOV

W @

RW1

+d1

6,RW

5

MOV

W @

RW2

+d1

6,RW

5

MOV

W @

RW3

+d1

6,RW

5

MOV

W @

RW0

+RW

7,RW

5

MOV

W @

RW1

+RW

7,RW

5

MOV

W @

PC+

d1

6,RW

5

MOV

W

add

r

16,

RW5

MOV

W

RW

0,RW

6

MOV

W

RW

1,RW

6

MOV

W

RW

2,RW

6

MOV

W

RW

3,RW

6

MOV

W

RW

4,RW

6

MOV

W

RW

5,RW

6

MOV

W

RW

6,RW

6

WOV

W

RW

7,RW

6

MOV

W

@RW

0,RW

6

MOV

W

@RW

1,RW

6

MOV

W

@RW

2,RW

6

MOV

W

@RW

3,RW

6

MOV

W

@

RW0+

,RW

6

MOV

W

@

RW1+

,RW

6

MOV

W

@

RW2+

,RW

6

MOV

W

@

RW3+

,RW

6

MOV

W @

RW

0+d

8,RW

6

MOV

W @

RW

1+d

8,RW

6

MOV

W @

RW

2+d

8,RW

6

MOV

W @

RW

3+d

8,RW

6

MOV

W @

RW

4+d

8,RW

6

MOV

W @

RW

5+d

8,RW

6

MOV

W @

RW

6+d

8,RW

6

MOV

W @

RW

7+d

8,RW

6

MOV

W @

RW0

+d1

6,RW

6

MOV

W @

RW1

+d1

6,RW

6

MOV

W @

RW2

+d1

6,RW

6

MOV

W @

RW3

+d1

6,RW

6

MOV

W @

RW0

+

RW7,

RW6

MOV

W @

RW1

+

RW7,

RW6

MOV

W @

PC+

d1

6,RW

6

MOV

W

add

r

1

6,RW

6

MOV

W

RW0,

RW7

MOV

W

RW1,

RW7

MOV

W

RW2,

RW7

MOV

W

RW3,

RW7

MOV

W

RW4,

RW7

MOV

W

RW5,

RW7

MOV

W

RW6,

RW7

WOV

W

RW7,

RW7

MOV

W

@RW

0,RW

7

MOV

W

@RW

1,RW

7

MOV

W

@RW

2,RW

7

MOV

W

@RW

3,RW

7

MOV

W

@

RW0+

,RW

7

MOV

W

@

RW1+

,RW

7

MOV

W

@

RW2+

,RW

7

MOV

W

@

RW3+

,RW

7

MOV

W @

RW

0+d

8,RW

7

MOV

W @

RW

1+d

8,RW

7

MOV

W @

RW

2+d

8,RW

7

MOV

W @

RW

3+d

8,RW

7

MOV

W @

RW

4+d

8,RW

7

MOV

W @

RW

5+d

8,RW

7

MOV

W @

RW

6+d

8,RW

7

MOV

W @

RW

7+d

8,RW

7

MOV

W @

RW0

+d1

6,RW

7

MOV

W @

RW1

+d1

6,RW

7

MOV

W @

RW2

+d1

6,RW

7

MOV

W @

RW3

+d1

6,RW

7

MOV

W @

RW0

+RW

7,RW

7

MOV

W @

RW1

+RW

7,RW

7

MOV

W @

PC+

d

16,R

W7

MOV

W

add

r

1

6,RW

7

+0

+1

+2

+3

+4

+5

+6

+7

+8

+9

+A

+B

+C

+D +E +F

486


Table D.9-20 XCH Ri, ea Instruction (First Byte = 7E H)

0010

2030

4050

6070

8090

A0

B0

C0

D0

E0

F0

XCH

R

0,R

0

XCH

R

0,R

1

XCH

R

0,R

2

XCH

R

0,R

3

XCH

R

0,R

4

XCH

R

0,R

5

XCH

R

0,R

6

XCH

R

0,R

7

XCH

R

0,@

RW

0

XCH

R

0,@

RW

1

XCH

R

0,@

RW

2

XCH

R

0,@

RW

3

XCH

R0,

@R

W0+

XCH

R0,

@R

W1+

XCH

R0,

@R

W2+

XCH

R0,

@R

W3+

XCH

R0,

@R

W0+

d8

XCH

R0,

@R

W1+

d8

XCH

R0,

@R

W2+

d8

XCH

R0,

@R

W3+

d8

XCH

R0,

@R

W4+

d8

XCH

R0,

@R

W5+

d8

XCH

R0,

@R

W6+

d8

XCH

R0,

@R

W7+

d8

XCH

R0,

@R

W0+

d16

XCH

R0,

@R

W1+

d16

XCH

R0,

W2+

d16,

A

XCH

R0,

@R

W3+

d16

XCH

R0,

@R

W0+

RW

7

XCH

R0,

@R

W1+

RW

7

XCH

R0,

@PC

+d16

XCH

R0,

ad

dr16

XCH

R

1,R

0

XCH

R

1,R

1

XCH

R

1,R

2

XCH

R

1,R

3

XCH

R

1,R

4

XCH

R

1,R

5

XCH

R

1,R

6

XCH

R

1,R

7

XCH

R

1,@

RW

0

XCH

R

1,@

RW

1

XCH

R

1,@

RW

2

XCH

R

1,@

RW

3

XCH

R1,

@R

W0+

XCH

R1,

@R

W1+

XCH

R1,

@R

W2+

XCH

R1,

@R

W3+

XCH

R1,

@R

W0+

d8

XCH

R1,

@R

W1+

d8

XCH

R1,

@R

W2+

d8

XCH

R1,

@R

W3+

d8

XCH

R1,

@R

W4+

d8

XCH

R1,

@R

W5+

d8

XCH

R1,

@R

W6+

d8

XCH

R1,

@R

W7+

d8

XCH

R1,

@R

W0+

d16

XCH

R1,

@R

W1+

d16

XCH

R1,

W2+

d16,

A

XCH

R1,

@R

W3+

d16

XCH

R1,

@R

W0+

RW

7

XCH

R1,

@R

W1+

RW

7

XCH

R1,

@PC

+d16

XCH

R1,

ad

dr16

XCH

R

2,R

0

XCH

R

2,R

1

XCH

R

2,R

2

XCH

R

2,R

3

XCH

R

2,R

4

XCH

R

2,R

5

XCH

R

2,R

6

XCH

R

2,R

7

XCH

R

2,@

RW

0

XCH

R

2,@

RW

1

XCH

R

2,@

RW

2

XCH

R

2,@

RW

3

XCH

R2,

@R

W0+

XCH

R2,

@R

W1+

XCH

R2,

@R

W2+

XCH

R2,

@R

W3+

XCH

R2,

@R

W0+

d8

XCH

R2,

@R

W1+

d8

XCH

R2,

@R

W2+

d8

XCH

R2,

@R

W3+

d8

XCH

R2,

@R

W4+

d8

XCH

R2,

@R

W5+

d8

XCH

R2,

@R

W6+

d8

XCH

R2,

@R

W7+

d8

XCH

R2,

@R

W0+

d16

XCH

R2,

@R

W1+

d16

XCH

R2,

W2+

d16,

A

XCH

R2,

@R

W3+

d16

XCH

R2,

@R

W0+

RW

7

XCH

R2,

@R

W1+

RW

7

XCH

R2,

@PC

+d16

XCH

R2,

ad

dr16

XCH

R

3,R

0

XCH

R

3,R

1

XCH

R

3,R

2

XCH

R

3,R

3

XCH

R

3,R

4

XCH

R

3,R

5

XCH

R

3,R

6

XCH

R

3,R

7

XCH

R

3,@

RW

0

XCH

R

3,@

RW

1

XCH

R

3,@

RW

2

XCH

R

3,@

RW

3

XCH

R3,

@R

W0+

XCH

R3,

@R

W1+

XCH

R3,

@R

W2+

XCH

R3,

@R

W3+

XCH

R3,

@R

W0+

d8

XCH

R3,

@R

W1+

d8

XCH

R3,

@R

W2+

d8

XCH

R3,

@R

W3+

d8

XCH

R3,

@R

W4+

d8

XCH

R3,

@R

W5+

d8

XCH

R3,

@R

W6+

d8

XCH

R3,

@R

W7+

d8

XCH

R3,

@R

W0+

d16

XCH

R3,

@R

W1+

d16

XCH

R3,

W2+

d16,

A

XCH

R3,

@R

W3+

d16

XCH

R3,

@R

W0+

RW

7

XCH

R3,

@R

W1+

RW

7

XCH

R3,

@PC

+d16

XCH

R3,

ad

dr16

XCH

R

4,R

0

XCH

R

4,R

1

XCH

R

4,R

2

XCH

R

4,R

3

XCH

R

4,R

4

XCH

R

4,R

5

XCH

R

4,R

6

XCH

R

4,R

7

XCH

R

4,@

RW

0

XCH

R

4,@

RW

1

XCH

R

4,@

RW

2

XCH

R

4,@

RW

3

XCH

R4,

@R

W0+

XCH

R4,

@R

W1+

XCH

R4,

@R

W2+

XCH

R4,

@R

W3+

XCH

R4,

@R

W0+

d8

XCH

R4,

@R

W1+

d8

XCH

R4,

@R

W2+

d8

XCH

R4,

@R

W3+

d8

XCH

R4,

@R

W4+

d8

XCH

R4,

@R

W5+

d8

XCH

R4,

@R

W6+

d8

XCH

R4,

@R

W7+

d8

XCH

R4,

@R

W0+

d16

XCH

R4,

@R

W1+

d16

XCH

R4,

W2+

d16,

A

XCH

R4,

@R

W3+

d16

XCH

R4,

@R

W0+

RW

7

XCH

R4,

@R

W1+

RW

7

XCH

R4,

@PC

+d16

XCH

R4,

add

r16

XCH

R

5,R

0

XCH

R

5,R

1

XCH

R

5,R

2

XCH

R

5,R

3

XCH

R

5,R

4

XCH

R

5,R

5

XCH

R

5,R

6

XCH

R

5,R

7

XCH

R

5,@

RW

0

XCH

R

5,@

RW

1

XCH

R

5,@

RW

2

XCH

R

5,@

RW

3

XCH

R5,

@R

W0+

XCH

R5,

@R

W1+

XCH

R5,

@R

W2+

XCH

R5,

@R

W3+

XCH

R5,

@R

W0+

d8

XCH

R5,

@R

W1+

d8

XCH

R5,

@R

W2+

d8

XCH

R5,

@R

W3+

d8

XCH

R5,

@R

W4+

d8

XCH

R5,

@R

W5+

d8

XCH

R5,

@R

W6+

d8

XCH

R5,

@R

W7+

d8

XCH

R5,

@R

W0+

d16

XCH

R5,

@R

W1+

d16

XCH

R5,

W2+

d16,

A

XCH

R5,

@R

W3+

d16

XCH

R5,

@R

W0+

RW

7

XCH

R5,

@R

W1+

RW

7

XCH

R5,

@PC

+d16

XCH

R5,

ad

dr16

XCH

R

6,R

0

XCH

R

6,R

1

XCH

R

6,R

2

XCH

R

6,R

3

XCH

R

6,R

4

XCH

R

6,R

5

XCH

R

6,R

6

XCH

R

6,R

7

XCH

R

6,@

RW

0

XCH

R

6,@

RW

1

XCH

R

6,@

RW

2

XCH

R

6,@

RW

3

XCH

R6,

@R

W0+

XCH

R6,

@R

W1+

XCH

R6,

@R

W2+

XCH

R6,

@R

W3+

XCH

R6,

@R

W0+

d8

XCH

R6,

@R

W1+

d8

XCH

R6,

@R

W2+

d8

XCH

R6,

@R

W3+

d8

XCH

R6,

@R

W4+

d8

XCH

R6,

@R

W5+

d8

XCH

R6,

@R

W6+

d8

XCH

R6,

@R

W7+

d8

XCH

R6,

@R

W0+

d16

XCH

R6,

@R

W1+

d16

XCH

R6,

W2+

d16,

A

XCH

R6,

@R

W3+

d16

XCH

R6,

@R

W0+

RW

7

XCH

R6,

@R

W1+

RW

7

XCH

R6,

@PC

+d16

XCH

R6,

add

r16

XCH

R

7,R

0

XCH

R

7,R

1

XCH

R

7,R

2

XCH

R

7,R

3

XCH

R

7,R

4

XCH

R

7,R

5

XCH

R

7,R

6

XCH

R

7,R

7

XCH

R

7,@

RW

0

XCH

R

7,@

RW

1

XCH

R

7,@

RW

2

XCH

R

7,@

RW

3

XCH

R7,

@R

W0+

XCH

R7,

@R

W1+

XCH

R7,

@R

W2+

XCH

R7,

@R

W3+

XCH

R7,

@R

W0+

d8

NO

TW

R7,

@R

W1+

d8

XCH

R7,

@R

W2+

d8

NO

TW

R7,

@R

W3+

d8

NO

TW

R7,

@R

W4+

d8

XCH

R7,

@R

W5+

d8

XCH

R7,

@R

W6+

d8

XCH

R7,

@R

W7+

d8

XCH

R7,

@R

W0+

d16

XCH

R7,

@R

W1+

d16

XCH

R7,

W2+

d16,

A

XCH

R7,

@R

W3+

d16

XCH

R7,

@R

W0+

RW

7

XCH

R7,

@R

W1+

RW

7

XCH

R7,

@PC

+d16

XCH

R7,

ad

dr16

+0

+1

+2

+3

+4

+5

+6

+7

+8

+9

+A

+B

+C

+D +E +F

487


Table D.9-21 XCHW RWi, ea Instruction 4 (First Byte = 7F H)

0010

2030

4050

6070

8090

A0

B0

C0

D0

E0

F0

XCHW

R

W0,

RW0

XCHW

R

W0,

RW1

XCHW

R

W0,

RW2

XCHW

R

W0,

RW3

XCHW

R

W0,

RW4

XCHW

R

W0,

RW5

XCHW

R

W0,

RW6

XCHW

R

W0,

RW7

XCHW

RW0,

@RW

0

XCHW

RW0,

@RW

1

XCHW

RW0,

@RW

2

XCHW

RW0,

@RW

3

XCHW

R

W0,

@RW

0+

XCHW

R

WO

,@RW

1+

XCHW

R

WO

,@RW

2+

XCHW

R

WO

,@RW

3+

XCHW

RW

0,

@RW

0+d8

XCHW

RW

0,

@RW

1+d8

XCHW

RW

0,

@RW

2+d8

XCHW

RW

0,

@RW

3+d8

XCHW

RW

0,

@RW

4+d8

XCHW

RW

0,

@RW

5+d8

XCHW

RW

0,

@RW

6+d8

XCHW

RW

0,

@RW

7+d8

XCHW

RW

0,

@RW

0+d1

6

XCHW

RW

0,

@RW

1+d1

6

XCHW

RW

0,

@RW

2+d1

6

XCHW

RW

0,

@RW

3+d1

6

XCHW

RW

0,

@RW

0+RW

7

XCHW

RW

0,

@RW

1+RW

7

XCHW

RW

0,

@PC

+d16

XCHW

RW

0,

a

ddr1

6

XCHW

R

W1,

RW0

XCHW

R

W1,

RW1

XCHW

R

W1,

RW2

XCHW

R

W1,

RW3

XCHW

R

W1,

RW4

XCHW

R

W1,

RW5

XCHW

R

W1,

RW6

XCHW

R

W1,

RW7

XCHW

RW1,

@RW

0

XCHW

RW1,

@RW

1

XCHW

RW1,

@RW

2

XCHW

RW1,

@RW

3

XCHW

R

W1,

@RW

0+

XCHW

R

W1,

@RW

1+

XCHW

R

W1,

@RW

2+

XCHW

R

W1,

@RW

3+

XCHW

RW

1,

@RW

0+d8

XCHW

RW

1,

@RW

1+d8

XCHW

RW

1,

@RW

2+d8

XCHW

RW

1,

@RW

3+d8

XCHW

RW

1,

@RW

4+d8

XCHW

RW

1,

@RW

5+d8

XCHW

RW

1,

@RW

6+d8

XCHW

RW

1,

@RW

7+d8

XCHW

RW

1,

@RW

0+d1

6

XCHW

RW

1,

@RW

1+d1

6

XCHW

RW

1,

@RW

2+d1

6

XCHW

RW

1,

@RW

3+d1

6

XCHW

RW

1,

@RW

0+RW

7

XCHW

RW

1,

@RW

1+RW

7

XCHW

RW

1,

@PC

+d16

XCHW

RW

1,

a

ddr1

6

XCHW

R

W2,

RW0

XCHW

R

W2,

RW1

XCHW

R

W2,

RW2

XCHW

R

W2,

RW3

XCHW

R

W2,

RW4

XCHW

R

W2,

RW5

XCHW

R

W2,

RW6

XCHW

R

W2,

RW7

XCHW

RW2,

@RW

0

XCHW

RW2,

@RW

1

XCHW

RW2,

@RW

2

XCHW

RW2,

@RW

3

XCHW

R

W2,

@RW

0+

XCHW

R

W2,

@RW

1+

XCHW

R

W2,

@RW

2+

XCHW

R

W2,

@RW

3+

XCHW

RW

2,

@RW

0+d8

XCHW

RW

2,

@RW

1+d8

XCHW

RW

2,

@RW

2+d8

XCHW

RW

2,

@RW

3+d8

XCHW

RW

2,

@RW

4+d8

XCHW

RW

2,

@RW

5+d8

XCHW

RW

2,

@RW

6+d8

XCHW

RW

2,

@RW

7+d8

XCHW

RW

2,

@RW

0+d1

6

XCHW

RW

2,

@RW

1+d1

6

XCHW

RW

2,

@RW

2+d1

6

XCHW

RW

2,

@RW

3+d1

6

XCHW

RW

2,

@RW

0+RW

7

XCHW

RW

2,

@RW

1+RW

7

XCHW

RW

2,

@PC

+d16

XCHW

RW

2,

a

ddr1

6

XCHW

R

W3,

RW0

XCHW

R

W3,

RW1

XCHW

R

W3,

RW2

XCHW

R

W3,

RW3

XCHW

R

W3,

RW4

XCHW

R

W3,

RW5

XCHW

R

W3,

RW6

XCHW

R

W3,

RW7

XCHW

RW3,

@RW

0

XCHW

RW3,

@RW

1

XCHW

RW3,

@RW

2

XCHW

RW3,

@RW

3

XCHW

R

W3,

@RW

0+

XCHW

R

W3,

@RW

1+

XCHW

R

W3,

@RW

2+

XCHW

R

W3,

@RW

3+

XCHW

RW

3,

@RW

0+d8

XCHW

RW

3,

@RW

1+d8

XCHW

RW

3,

@RW

2+d8

XCHW

RW

3,

@RW

3+d8

XCHW

RW

3,

@RW

4+d8

XCHW

RW

3,

@RW

5+d8

XCHW

RW

3,

@RW

6+d8

XCHW

RW

3,

@RW

7+d8

XCHW

RW

3,

@RW

0+d1

6

XCHW

RW

3,

@RW

1+d1

6

XCHW

RW

3,

@RW

2+d1

6

XCHW

RW

3,

@RW

3+d1

6

XCHW

RW

3,

@RW

0+RW

7

XCHW

RW

3,

@RW

1+RW

7

XCHW

RW

3,

@PC

+d16

XCHW

RW

3,

addr

16

XCHW

R

W4,

RW0

XCHW

R

W4,

RW1

XCHW

R

W4,

RW2

XCHW

R

W4,

RW3

XCHW

R

W4,

RW4

XCHW

R

W4,

RW5

XCHW

R

W4,

RW6

XCHW

R

W4,

RW7

XCHW

RW4,

@RW

0

XCHW

RW4,

@RW

1

XCHW

RW4,

@RW

2

XCHW

RW4,

@RW

3

XCHW

R

W4,

@RW

0+

XCHW

R

W4,

@RW

1+

XCHW

R

W4,

@RW

2+

XCHW

R

W4,

@RW

3+

XCHW

RW

4,

@RW

0+d8

XCHW

RW

4,

@RW

1+d8

XCHW

RW

4,

@RW

2+d8

XCHW

RW

4,

@RW

3+d8

XCHW

RW

4,

@RW

4+d8

XCHW

RW

4,

@RW

5+d8

XCHW

RW

4,

@RW

6+d8

XCHW

RW

4,

@RW

7+d8

XCHW

RW

4,

@RW

0+d1

6

XCHW

RW

4,

@RW

1+d1

6

XCHW

RW

4,

@RW

2+d1

6

XCHW

RW

4,

@RW

3+d1

6

XCHW

RW

4,

@RW

0+RW

7

XCHW

RW

4,

@RW

1+RW

7

XCHW

RW

4,

@PC

+d16

XCHW

RW

4,

addr

16

XCHW

R

W5,

RW0

XCHW

R

W5,

RW1

XCHW

R

W5,

RW2

XCHW

R

W5,

RW3

XCHW

R

W5,

RW4

XCHW

R

W5,

RW5

XCHW

R

W5,

RW6

XCHW

R

W5,

RW7

XCHW

RW5,

@RW

0

XCHW

RW5,

@RW

1

XCHW

RW5,

@RW

2

XCHW

RW5,

@RW

3

XCHW

R

W5,

@RW

0+

XCHW

R

W5,

@RW

1+

XCHW

R

W5,

@RW

2+

XCHW

R

W5,

@RW

3+

XCHW

RW

5,

@RW

0+d8

XCHW

RW

5,

@RW

1+d8

XCHW

RW

5,

@RW

2+d8

XCHW

RW

5,

@RW

3+d8

XCHW

RW

5,

@RW

4+d8

XCHW

RW

5,

@RW

5+d8

XCHW

RW

5,

@RW

6+d8

XCHW

RW

5,

@RW

7+d8

XCHW

RW

5,

@RW

0+d1

6

XCHW

RW

5,

@RW

1+d1

6

XCHW

RW

5,

@RW

2+d1

6

XCHW

RW

5,

@RW

3+d1

6

XCHW

RW

5,

@RW

0+RW

7

XCHW

RW

5,

@RW

1+RW

7

XCHW

RW

5,

@PC

+d16

XCHW

RW

5,

addr

16

XCHW

R

W6,

RW0

XCHW

R

W6,

RW1

XCHW

R

W6,

RW2

XCHW

R

W6,

RW3

XCHW

R

W6,

RW4

XCHW

R

W6,

RW5

XCHW

R

W6,

RW6

XCHW

R

W6,

RW7

XCHW

RW6,

@RW

0

XCHW

RW6,

@RW

1

XCHW

RW6,

@RW

2

XCHW

RW6,

@RW

3

XCHW

R

W6,

@RW

0+

XCHW

R

W6,

@RW

1+

XCHW

R

W6,

@RW

2+

XCHW

R

W6,

@RW

3+

XCHW

RW

6,

@RW

0+d8

XCHW

RW

6,

@RW

1+d8

XCHW

RW

6,

@RW

2+d8

XCHW

RW

6,

@RW

3+d8

XCHW

RW

6,

@RW

4+d8

XCHW

RW

6,

@RW

5+d8

XCHW

RW

6,

@RW

6+d8

XCHW

RW

6,

@RW

7+d8

XCHW

RW

6,

@RW

0+d1

6

XCHW

RW

6,

@RW

1+d1

6

XCHW

RW

6,

@RW

2+d1

6

XCHW

RW

6,

@RW

3+d1

6

XCHW

RW

6,

@RW

0+RW

7

XCHW

RW

6,

@RW

1+RW

7

XCHW

RW

6,

@PC

+d16

XCHW

RW

6,

addr

16

XCHW

R

W7,

RW0

XCHW

R

W7,

RW1

XCHW

R

W7,

RW2

XCHW

R

W7,

RW3

XCHW

R

W7,

RW4

XCHW

R

W7,

RW5

XCHW

R

W7,

RW6

XCHW

R

W7,

RW7

XCHW

RW7,

@RW

0

XCHW

RW7,

@RW

1

XCHW

RW7,

@RW

2

XCHW

RW7,

@RW

3

XCHW

R

W7,

@RW

0+

XCHW

R

W7,

@RW

1+

XCHW

R

W7,

@RW

2+

XCHW

R

W7,

@RW

3+

XCHW

RW

7,

@RW

0+d8

XCHW

RW

7,

@RW

1+d8

XCHW

RW

7,

@RW

2+d8

XCHW

RW

7,

@RW

3+d8

XCHW

RW

7,

@RW

4+d8

XCHW

RW

7,

@RW

5+d8

XCHW

RW

7,

@RW

6+d8

XCHW

RW

7,

@RW

7+d8

XCHW

RW

7,

@RW

0+d1

6

XCHW

RW

7,

@RW

1+d1

6

XCHW

RW

7,

@RW

2+d1

6

XCHW

RW

7,

@RW

3+d1

6

XCHW

RW

7,

@RW

0+RW

7

XCHW

RW

7,

@RW

1+RW

7

XCHW

RW

7,

@PC

+d16

XCHW

RW

7,

addr

16

+0

+1

+2

+3

+4

+5

+6

+7

+8

+9

+A

+B

+C

+D +E +F

488

INDEX

INDEX

The index follows on the next page.This is listed in alphabetic order.

489

INDEX

Index

Numerics

16-bit free-run timer..............................................17916-bit free-run timer (x 1)......................................17416-bit free-run timer count timing .........................19616-bit free-run timer register.................................17916-bit free-run timer, block diagram of .................17916-bit free-run timer, operation of.........................19516-bit I/O timer register ................................175, 17716-bit I/O timer, block diagram of .........................17616-bit input capture, operation of .........................20016-bit output compare timing................................19816-bit output compare, operation of .....................1972M-bit flash memory, feature of............................3782M-bit flash memory, sector configuration of .......3798/16-bit PPG count clock, selecting .....................2208/16-bit PPG interrupt ..........................................2238/16-bit PPG operation mode...............................2178/16-bit PPG output operation..............................2188/16-bit PPG pulse output on pin, controlling.......2218/16-bit PPG register............................................2078/16-bit PPG, block diagram of ............................2058/16-bit PPG, operation of....................................2168/16-bit PPG, overview of ....................................2048/16-bit up/down counter/timer, block

diagram of ..................................................2288/16-bit up/down counter/timer, function of ..........2268/16-bit up/down counter/timer, register of...........2308/16-bit up/down counter/timer, reload and

compare function of ...................................2458/16-bit up/down counter/timer, selecting count

mode of ......................................................2428/16-bit up/down counter/timer, simultaneous

activation of reload and compare function of ..................................................247

8-bit x 2-channel operation and 16-bit x 1-channel operation ....................................................251

A

A/D converter operation, continuous mode..........279A/D converter operation, single mode..................279A/D converter operation, stop mode ....................280A/D converter register ..........................................272A/D converter, block diagram of...........................271A/D converter, note on using................................288A/D converter, outline of.......................................270

accumulator (A)...................................................... 37ADCR1 and ADCR2............................................. 278ADCS1 and ADCS2............................................. 273address register (IADR) ....................................... 357addressing ........................................................... 431addressing method, flash memory data write ...... 393allocation of multibyte data in memory space........ 33analog input enable register (ADER) ................... 153automatic algorithm execution status confimation,

hardware sequence flag ............................ 384automatic ready function selection register

(ARSR) ...................................................... 132

B

bank addressing..................................................... 31bank register .......................................................... 45bank select prefix ................................................... 48baud rate generator, dedicated............................ 312buffer address pointer (BAP) ................................. 74bus control register (IBCR) .................................. 352bus control signal selection register (ECSR) ....... 135bus status register (IBSR).................................... 349

C

CCRH0................................................................. 236CCRH1................................................................. 238CCRL0 and CCRL1 ............................................. 240chip/sector erase operation, data polling flag

(DQ7) ......................................................... 386clock control register (ICCR)................................ 355clock generation block, note on ............................. 82clock monitor function, block diagram of.............. 374clock output allowed register (CLKR)................... 375clock section register (CKSCR) ............................. 96clock selection register (CKSCR)......................... 104clock selection, status transition for ....................... 98clock supply map ................................................... 83command sequence table.................................... 383common register bank prefix (CMR)...................... 49communication in CLK synchronous mode,

start of........................................................ 318communication in CLK synchronous mode,

termination of ............................................. 318communication prescaler control register

(CDCR) ...................................................... 310

490

INDEX

communication prescaler control register, setting of .................................................... 311

compare detection flag......................................... 251condition code register (CCR)................................ 40consecutive prefix code ......................................... 52control register value when CLK synchronous

mode is used, setting................................. 318control status register (ADCS1 and ADCS2) ....... 273conversion data protection function ..................... 289conversion using I2OS......................................... 281count clear/gate function...................................... 249count direction flag and count direction

change flag ................................................ 250count mode of 8/16-bit up/down counter/timer,

selecting..................................................... 242counter control register 0 higher (CCRH0) .......... 236counter control register 1 higher (CCRH1) .......... 238counter control registers 0 and 1 lower

(CCRL0 and CCRL1)................................. 240counter status registers 0 and 1

(CSR0 and CSR1) ..................................... 233CPU intermittent operation function ............... 90, 110CPU, feature of ...................................................... 28CSR0 and CSR1.................................................. 233

D

D/A control register (DADR0 and DADR1) .......... 295D/A converter data register

(DADR0 and DADR1) ................................ 294D/A converter operation ....................................... 296D/A converter register .......................................... 292D/A converter, block diagram of........................... 293data counter (DCT) ................................................ 72data polling flag (DQ7), chip/sector erase

operation.................................................... 386data polling flag (DQ7), sector erase temporary

stop operation ............................................ 386data polling flag (DQ7), write operation ............... 386data polling flag status transition.......................... 386data register (ADCR1 and ADCR2) ..................... 278data register (IDAR) ............................................. 358dedicated baud rate generator............................. 312dedicated register .................................................. 35delayed interrupt generation module, block

diagram of.................................................. 266delayed interrupt generation module,

operation of................................................ 267delayed interrupt generation module,

precaution on using ................................... 267

delayed interrupt generation module, register of ...................................................266

device handling, note on.........................................21direct addressing ..................................................433direct page register (DPR)......................................44DTMF control register (DTMC) .............................368DTMF data register (DTMD).................................370DTMF generator feature .......................................366DTMF generator operation ...................................371DTMF generator register ......................................367DTMF generator, block diagram of.......................366DTP operation ......................................................259DTP/external interrupt function.............................254DTP/external interrupt register .............................255DTP/external interrupt unit, block diagram of .......254DTP/external interrupt unit, operation of...............259DTP/interrupt cause register (EIRR).....................257DTP/interrupt enable register (ENIR) ...................256

E

effective address field...................................432, 450EIRR .....................................................................257ELVR ....................................................................258ENIR .....................................................................256execution cycle count ...........................................447execution cycle count, calculating ........................447extended intelligent I/O service (EI2OS)

status register (ISCS) ...................................73extended intelligent I/O service (EI2OS) structure .67extended intelligent I/O service (EI2OS),

one transfer time ..........................................77extended intelligent I/O service (EI2OS),

operation of ..................................................66extended intelligent I/O service (EI2OS),

overview of ...................................................65extended intelligent I/O service (EI2OS),

procedure for using ......................................76extended intelligent I/O service (EI2OS),

processing procedure of...............................75extended intelligent I/O service (EI2OS),

processing time for .......................................77extended intelligent I/O service descriptor (ISD) ....71external bus pin control circuit ..............................130external bus pin control circuit register .................131external bus pin control circuit, block

diagram of ..................................................130external clock........................................................314external interrupt request and DTP request,

switching between ......................................261external interrupt request level .............................262

491

INDEX

external memory access ......................................130external memory access control signal ................138external memory access register .........................131external memory access, block diagram of ..........130external shift clock mode......................................336

F

F2MC-16L instruction table ..................................454flag change suppression prefix (NCC) ...................49flash memory arbitrary data erase

(sector erase).............................................396flash memory arbitrary data erase (sector erase),

sector specification method .......................396flash memory arbitrator data, sector erase

procedure ...................................................396flash memory automatic algorithm activation,

command sequence table..........................383flash memory control status register (FMCS).......380flash memory data write .......................................393flash memory data write, note on writing data......393flash memory program example...........................400flash memory read/reset status............................392flash memory register...........................................378flash memory sector erase temporary restart.......399flash memory sector erase temporary stop..........398flash memory total data erase (chip erase)..........395flash memory write procedure..............................393flash memory write/erase, detailed

explanation of.............................................391flash memory writing and erasure method ...........378FPT-100P-M05 package dimension.........................7FPT-100P-M05, pin assignment...............................9FPT-100P-M06 package dimension.........................8FPT-100P-M06, pin assignment.............................10

G

general-purpose register ........................................46generation of exception due to attempt to execute

undefined instruction....................................80

H

hardware interrupt configuration ............................61hardware interrupt, overview of..............................61higher address control register (HACR) ...............134hold function.........................................................142

I

I/O circuit type ........................................................18I/O extended serial interface interrupt function.....343

I/O extended serial interface register ................... 329I/O extended serial interface, block diagram of.... 328I/O extended serial interface, operation of ........... 335I/O extended serial interface, outline of ............... 328I/O extended serial interface, serial data

register (SDR) R/W standby status............ 337I/O extended serial interface, STOP status.......... 337I/O extended serial interface, stopped status....... 337I/O extended serial interface, transfer status ....... 337I/O map ................................................................ 418I/O port register .................................................... 145I/O port, overview of............................................. 144I/O register address pointer (IOA).......................... 72I2C interface feature ............................................ 346I2C interface mode transition............................... 363I2C interface operation, acknowledge.................. 360I2C interface operation, addressing ..................... 359I2C interface operation, arbitration....................... 359I2C interface operation, bus error ........................ 360I2C interface operation, start condition ................ 359I2C interface operation, stop condition ................ 359I2C interface register............................................ 348I2C interface transfer flow.................................... 361I2C interface, block diagram of ............................ 347I2OS activation in continuous mode,

example of ................................................. 284I2OS activation in single mode, example of......... 282I2OS activation in stop mode, example of ........... 286I2OS, conversion using........................................ 281IBCR .................................................................... 352IBSR..................................................................... 349indirect addressing............................................... 440initial value of each 8/16-bit hardware ................. 224input capture ........................................................ 190input capture (x 2) ................................................ 174input capture control status register (ICS01) ....... 193input capture data register (IPCP0 and IPCP1) ... 192input capture input timing..................................... 201input capture register ........................................... 190input capture, block diagram of............................ 191input resistor register (RDR) ................................ 151input resistor register (RDR), block diagram of.... 151input resistor register (RDR), note on .................. 152instruction map structure...................................... 467instruction table, description of item in................. 451instuction type...................................................... 430intelligent I/O service (I2OS)................................ 325internal shift clock mode ...................................... 336internal timer ........................................................ 314

492

INDEX

interrupt cause ....................................................... 57interrupt control register (ICR) ............................... 68interrupt level mask register (ILM) ......................... 41interrupt processing time........................................ 79interrupt suppression instruction ............................ 61interrupt vector ............................................... 59, 424interrupt, overview of.............................................. 56interval interrupt function for timebase timer........ 160interval interrupt function for watch timer ............. 172ISCS....................................................................... 73

L

linear addressing.................................................... 30low power control circuit register............................ 93low power control circuit, block diagram of ............ 92low power control circuit, operation mode of.......... 90low power mode................................................... 102low power mode control register (LPMCR) .... 94, 104low power mode control register, access to... 95, 104low power mode operating state .......................... 103low power mode, status transition diagram for .... 117low power mode, transition condition for.............. 113

M

machine clock initialization................................... 112machine clock switching ........................................ 91main clock and PLL clock, switching between ..... 112main clock and subclock, switching between....... 112main clock oscillation stabilization wait

interval setting...................................... 90, 111MB90650A series, block diagram of device in ......... 6MB90650A series, feature of ................................... 2MB90650A series, model available in...................... 5MB90650A series, package dimension

(FPT-100P-M05)............................................ 7MB90650A series, package dimension

(FPT-100P-M06)............................................ 8MB90F654A serial programming connection,

basic configuration of................................. 406memory access mode, overview of...................... 124memory space ....................................................... 29memory space for each bus mode....................... 127memory space in each bus mode, example of

recommended setting for ........................... 129memory space of MB90650A................................. 53minimum connection configuration of flash

microcomputer programmer (when power is supplied from programmer power supply), example of ................................................. 414

minimum connection configuration of flash microcomputer programmer (when user power supply is used), example of .............412

mode data.............................................................126mode pin...............................................................125multibyte data access .............................................34multibyte data in memory space, allocation of........33multiple interrupt .....................................................62multiple sectors, note on specifying......................396

O

operation after reset being cleared.........................87OTPROM programming..........................................23output compare.....................................................184output compare (x 4) ............................................174output compare control status register

(OCS0 to OCS3) ........................................187output compare register........................................184output compare, block diagram of ........................185output compare, register (OCCP0 to OCCP3) .....186output pin register (ODR) .....................................150output pin register (ODR), block diagram of .........150output pin register (ODR), note on .......................150

P

peripheral connected externally when DTP is used, condition of ...........................262

pin function, explanation of.....................................11pin state in single chip mode ................................426port data register (PDR) .......................................146port direction register (DDR).................................148PPG0 operation mode control register (PPGC0)..208PPG0/PPG1 output pin control register

(PPGOE) ....................................................213PPG1 operation mode control register

(PPGC1).....................................................210prefix code and interrupt/hold suppression

instruction .....................................................51procedure for DTP/external interrupt unit,

operation of ................................................262processing procedure of extended intelligent I/O

service (EI2OS) ............................................75processing time for extended intelligent I/O

service (EI2OS) ............................................77processor status (PS) .............................................40program counter (PC).............................................43pseudo watch mode, release of............................106pseudo watch mode, switching to.........................106

493

INDEX

R

RCR0 and RCR1..................................................232ready function.......................................................140receive operation..................................................316recommended setting for memory space in

each bus mode, example of .......................129register bank ..........................................................47register bank pointer (RP) ......................................41register saved onto stack .......................................62relationship between reloaded value and

pulse width .................................................219reload and compare function of 8/16-bit up/down

counter/timer ..............................................245reload register (PRLL and PRLH) ........................215reload/compare registers 0 and 1

(RCR0 and RCR1) .....................................232reloaded value and pulse width,

relationship between ..................................219request level setting register (ELVR)....................258reset cause.............................................................84

S

saving register onto stack at interrupt ....................62SCC, MSS and INT bit conflict, note on ...............354SCR......................................................................303sector configuration of 2M-bit flash memory ........379sector erase operation, sector erase timer

flag (DQ3) ..................................................390sector erase procedure, flash memory

arbitrator data.............................................396sector erase temporary stop operation,

data polling flag (DQ7) ...............................386sector erase temporary stop operation,

toggle bit flag (DQ6) ...................................388sector erase timer flag (DQ3), sector erase

operation ....................................................390sector erase timer flag status transition................390sector specification method, flash memory

arbitrary data erase (sector erase).............396send operation .....................................................316serial control register (SCR).................................303serial data I/O timing ............................................342serial data register (SDR) R/W standby status.....337serial input data register (SIDR)/serial output

data register (SODR) .................................306serial mode control status register (SMCS)..........330serial mode register (SMR) ..................................301serial programming connection example (when

power is supplied from programmer power supply).............................................410

serial programming connection example (when user power supply is used) ............. 408

serial shift data register (SDR)............................. 334serial status register (SSR).................................. 307shift operation, start/stop timing of ....................... 339simultaneous activation of reload and compare

function of 8/16-bit up/down counter/timer.............................................. 247

sleep mode, release of......................................... 105sleep mode, switching to...................................... 105SMR..................................................................... 301software interrupt configuration.............................. 63software interrupt operation ................................... 64software interrupt, note on ..................................... 64software interrupt, overview of ............................... 63standby status, return from .................................. 262start/stop timing of shift operation........................ 339status transition diagram for low power mode ..... 117status transition for clock selection ........................ 98stop mode, release of .......................................... 108stop mode, switching to ....................................... 108

T

time chart for 8/16-bit PPG reload register, writing ........................................................ 222

timebase counter ................................................. 160timebase timer control register (TBTC)................ 158timebase timer register ........................................ 156timebase timer register, block diagram of ............ 157timer counter control status register (TCCS) ....... 181timer counter data register (TCDT)...................... 180timing limit exceed flag (DQ5), write and

chip/sector erase operation ....................... 389timing limit exceed flag status transition .............. 389toggle bit flag (DQ6), sector erase temporary

stop operation ............................................ 388toggle bit flag (DQ6), write and chip/sector

erase operation.......................................... 388toggle bit flag status transition ............................. 388transfer data format.............................................. 316transfer data format in CLK synchronous mode .. 317transition condition for low power mode............... 113

U

UART application example (sample system configuration when mode 1 is used) .......... 323

UART communication flowchart........................... 324UART feature....................................................... 298UART flag (PE, ORE, FRE, RDRF and TDRE) ... 319UART interrupt and flag, set timing of.................. 320

494

INDEX

UART interrupt generation source ....................... 319UART operation ................................................... 315UART register ...................................................... 300UART, block diagram of....................................... 299UART, note on using............................................ 325UDCR register, writing data to ............................. 249UDCR0 and UDCR1 ............................................ 231undefined instruction, generation of exception

due to attempt to execute ............................ 80up/down counter registers 0 and 1

(UDCR0 and UDCR1)................................ 231user stack pointer (USP) and system stack

pointer (SSP) ............................................... 39USP and SSP ........................................................ 39

W

watch counter....................................................... 172watch mode, release of........................................ 107

watch mode, switching to .....................................107watch timer control register (WTC).......................170watch timer register ..............................................168watch timer, block diagram of...............................169watchdog timer control register (WDTC) ..............164watchdog timer register ........................................162watchdog timer register, block diagram of............163watchdog timer, activating ....................................166watchdog timer, clearing.......................................166watchdog timer, reset preventing .........................166watchdog timer, stopping......................................166write and chip/sector erase operation,

timing limit exceed flag (DQ5) ....................389write and chip/sector erase operation,

toggle bit flag (DQ6) ...................................388write operation, data polling flag (DQ7) ................386writing time chart for 8/16-bit PPG reload

register .......................................................222

495

INDEX

496

CM43-10110-3E

FUJITSU SEMICONDUCTOR • CONTROLLER MANUAL

F2MC-16L

16-BIT MICROCONTROLLER

MB90650A Series

HARDWARE MANUAL

June 2001 the third edition

Published FUJITSU LIMITED Electronic Devices

Edited Technical Information Dept.

Documents

16-BIT MICROCONTROLLER MB90650A Series HARDWARE … · i PREFACE Objectives and Intended Reader Thank you for purchasing Fujitsu semiconductor products. The MB90650A series is a 16-bit