150 mA, 16V, High-Performance LDO - Microchip Technologyww1.microchip.com/downloads/en/DeviceDoc/20002276C.pdf · for four to six primary cell battery-powered applications, 12V mobile

MCP1754/MCP1754S150 mA, 16V, High-Performance LDO

Features:

• High PSRR: >70 dB @ 1 kHz, Typical

• 56.0 µA Typical Quiescent Current

• Input Operating Voltage Range: 3.6V to16.0V

• 150 mA Output Current for All Output Voltages

• Low-Dropout Voltage, 300 mV Typical @ 150 mA

• 0.4% Typical Output Voltage Tolerance

• Standard Output Voltage Options (1.8V, 2.5V, 2.8V, 3.0V, 3.3V, 4.0V, 5.0V)

• Output Voltage Range 1.8V to 5.5V in 0.1V Increments (tighter increments also possible per design)

• Output Voltage Tolerances of ±2.0% Over Entire Temperature Range

• Stable with Minimum 1.0 µF Output Capacitance

• Power Good Output

• Shutdown Input

• True Current Foldback Protection

• Short-Circuit Protection

• Overtemperature Protection

Applications:

• Battery-Powered Devices

• Battery-Powered Alarm Circuits

• Smoke Detectors

• CO2 Detectors

• Pagers and Cellular Phones

• Smart Battery Packs

• PDAs

• Digital Cameras

• Microcontroller Power

• Consumer Products

• Battery-Powered Data Loggers

Related Literature:

• AN765, “Using Microchip’s Micropower LDOs” (DS00765), Microchip Technology Inc., 2007

• AN766, “Pin-Compatible CMOS Upgrades to BiPolar LDOs” (DS00766), Microchip Technology Inc., 2003

• AN792, “A Method to Determine How Much Power a SOT23 Can Dissipate in an Application” (DS00792), Microchip Technology Inc., 2001

Description:

The MCP1754/MCP1754S is a family of CMOS lowdropout (LDO) voltage regulators that can deliver up to150 mA of current while consuming only 56.0 µA ofquiescent current (typical). The input operating range isspecified from 3.6V to 16.0V, making it an ideal choicefor four to six primary cell battery-powered applications,12V mobile applications and one to three-cell Li-Ion-powered applications.

The MCP1754/MCP1754S is capable of delivering150 mA with only 300 mV (typical) of input to outputvoltage differential. The output voltage tolerance of theMCP1754/MCP1754S is typically ±0.2% at +25°C and±2.0% maximum over the operating junctiontemperature range of -40°C to +125°C. Line regulationis ±0.01% typical at +25°C.

Output voltages available for the MCP1754/MCP1754Srange from 1.8V to 5.5V. The LDO output is stable whenusing only 1 µF of output capacitance. Ceramic,tantalum or aluminum electrolytic capacitors may all beused for input and output. Overcurrent limit andovertemperature shutdown provide a robust solution forany application.

The MCP1754/MCP1754S family introduces a truecurrent foldback feature. When the load impedancedecreases beyond the MCP1754/MCP1754S loadrating, the output current and voltage will gracefullyfoldback towards 30 mA at about 0V output. When theload impedance decreases and returns to the ratedload, the MCP1754/MCP1754S follows the samefoldback curve as the device comes out of currentfoldback.

Package options for the MCP1754S include theSOT-23A, SOT-89-3, SOT-223-3 and 2x3 DFN-8.

Package options for the MCP1754 include theSOT-23-5, SOT-223-5, and 2x3 DFN-8.

2011-2013 Microchip Technology Inc. DS20002276C-page 1

MCP1754/MCP1754S

Package Types – MCP1754S

Package Types – MCP1754

1

3

2

VIN

GND VOUT

1 2 3

VIN GND VOUT

3-Pin SOT-23A 3-Pin SOT-89

GND

Tab is connected to GND

8-Lead 2X3 DFN(*)

1 2 3

SOT-223-3

4

GNDVIN VOUT

GND

2

NC

NC

GND

NC

NC

1

2

3

4

8

7

6

5 NC

VINVOUT

EP9

* Includes Exposed Thermal Pad (EP); see Table 3-2.

(Note: The 3-lead SOT-223 (DB) isnot a standard package for outputvoltages below 3.0V)

1 2

SOT23-5

1 2 3

SOT-223-5

4 5

PIN FUNCTION

1 SHDN

5 PWRGD

3 GND 4 VOUT

2 VIN

4

3

5

PIN FUNCTION

4 PWRGD

2 GND

1 VIN

5 VOUT

3 SHDN

Tab is connected to GND

8-Lead 2X3 DFN(*)

3

NC

PWRGD

GND

NC

NC

1

2

3

4

8

7

6

5 SHDN

VINVOUT

EP9

* Includes Exposed Thermal Pad (EP); see Table 3-1.

DS20002276C-page 2 2011-2013 Microchip Technology Inc.

MCP1754/MCP1754S

Functional Block Diagram – MCP1754S

+-

MCP1754S

VIN VOUT

GND

+VIN

Error Amplifier

VoltageReference

OvercurrentOvertemperature


MCP1754/MCP1754S

Functional Block Diagram – MCP1754

Typical Application Circuits

EA

+

–

VOUT

PMOS

RfCfISNS

Overtemperature

VREF

Comp

92% of VREF

TDELAY

VIN

Driver w/limitand SHDN

GND

Soft-Start

SenseUndervoltage Lock Out

VIN

Reference

SHDN

SHDN

SHDNSensing

(UVLO)

PWRGD

MCP1754

MCP1754S

CIN1 µF Ceramic

COUT1 µF Ceramic

VOUT5.0V

IOUT30 mA

VIN

VO

UT

12V+

GN

D


MCP1754/MCP1754S

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings †

Input Voltage, VIN..................................................................+17.6VVIN, PWRGD, SHDN ..................... (GND-0.3V) to (VIN+0.3V)VOUT .................................................. (GND-0.3V) to (+5.5V)Internal Power Dissipation ............ Internally-Limited (Note 6)Output Short Circuit Current .................................ContinuousStorage temperature .....................................-55°C to +150°CMaximum Junction Temperature.....................165°C (Note 7)Operating Junction Temperature...................-40°C to +150°CESD protection on all pins kV HBM and 200V MM

† Notice: Stresses above those listed under “MaximumRatings” may cause permanent damage to the device. This isa stress rating only and functional operation of the device atthose or any other conditions above those indicated in theoperational listings of this specification is not implied.Exposure to maximum rating conditions for extended periodsmay affect device reliability.

AC/DC CHARACTERISTICSElectrical Specifications: Unless otherwise specified, all limits are established for VIN = VR + 1V, Note 1, ILOAD = 1 mA, COUT = 1 µF (X7R), CIN = 1 µF (X7R), TA = +25°C, tr(VIN) = 0.5V/µs, SHDN = VIN, PWRGD = 10K to VOUT.Boldface type applies for junction temperatures, TJ (Note 7) of -40°C to +125°C.

Parameters Sym. Min. Typ. Max. Units Conditions

Input/Output Characteristics

Input Operating Voltage VIN 3.6 — 16.0 V

Output Voltage Operating Range

VOUT-RANGE 1.8 — 5.5 V

Input Quiescent Current Iq — 56 90 µA IL = 0 mA

Input Quiescent Current for SHDN mode

ISHDN — 0.1 5 µA SHDN = GND

Ground Current IGND — 150 250 µA ILOAD = 150 mA

Maximum Output Current IOUT 150 — — mA

Output Soft Current Limit

IOUT_SCL — 250 — mA VIN = VIN(MIN), VOUT 0.1V, Current measured 10 ms after load is applied

Output Pulse Current Limit

IOUT_PCL — 250 — mA Pulse Duration < 100 ms, Duty Cycle < 50%, VOUT 0.1V, Note 6

Output Short Circuit Foldback Current

IOUT_SC — 30 — mA VIN = VIN(MIN), VOUT = GND

Output Voltage Overshoot on Startup

VOVER — 0.5 — %VOUT VIN = 0 to 16V, ILOAD = 150 mA

Output Voltage Regulation VOUT VR-2.0% VR±0.2% VR+2.0% V Note 2

VOUT TemperatureCoefficient

TCVOUT — 22 ppm/°C Note 3

Note 1: The minimum VIN must meet two conditions: VIN3.6V and VIN VR + VDROPOUT(MAX).2: VR is the nominal regulator output voltage when the input voltage VIN = VRated + VDROPOUT(MAX) or VIN = 3.6V

(whichever is greater); IOUT = 1 mA. 3: TCVOUT = (VOUT-HIGH – VOUT-LOW) *106/(VR * Temperature), VOUT-HIGH = highest voltage measured over the

temperature range. VOUT-LOW = lowest voltage measured over the temperature range.4: Load regulation is measured at a constant junction temperature using low duty cycle pulse testing. Changes in output

voltage due to heating effects are determined using thermal regulation specification TCVOUT.5: Dropout voltage is defined as the input to output differential at which the output voltage drops 2% below the output

voltage value that was measured with an applied input voltage of VIN = VR + 1V or VIN = 3.6V (whichever is greater).6: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction

temperature and the thermal resistance from junction to air (i.e., TA, TJ, JA). Exceeding the maximum allowable power dissipation causes the device operating junction temperature to exceed the maximum 150°C rating. Sustained junction temperatures above +150°C can impact the device reliability.

7: The junction temperature is approximated by soaking the device under test at an ambient temperature equal to the desired junction temperature. The test time is small enough such that the rise in the junction temperature over the ambient temperature is not significant.


MCP1754/MCP1754S

Line Regulation VOUT/(VOUT x VIN)

-0.05 ±0.01 +0.05 %/V VR + 1V VIN 16V

Load Regulation VOUT/VOUT -1.1 -0.4 0 % IL = 1.0 mA to 150 mA, Note 4

Dropout Voltage (Note 5) VDROPOUT — 300 500 mV IL = 150 mA

Dropout Current IDO — 50 85 µA VIN = 0.95VR, IOUT = 0 mA

Undervoltage Lockout

Undervoltage Lockout UVLO — 2.95 — V Rising VIN

Undervoltage Lockout Hysteresis

UVLOHYS — 285 — mV Falling VIN

Shutdown Input

Logic High Input VSHDN-HIGH 2.4 — VIN(MAX) V

Logic Low Input VSHDN-LOW 0.0 — 0.8 V

Shutdown Input Leakage Current

SHDNILK — 0.100 0.500 µA SHDN = GND

— 0.500 2.0 SHDN = 16V

Power Good Output

PWRGD Input Voltage Operating Range

VPWRGD_VIN 1.7 — VIN V ISINK = 1 mA

PWRGD Threshold Voltage (Referenced to VOUT)

VPWRGD_TH 90 92 94 %VOUT Falling Edge of VOUT

PWRGD Threshold Hysteresis

VPWRGD_HYS — 2.0 — %VOUT Rising Edge of VOUT

PWRGD Output Voltage Low VPWRGD_L — 0.2 0.6 V IPWRGD_SINK = 5.0 mA, VOUT = 0V

PWRGD Output Sink Current

IPWRGD_L 5.0 — — mA VPWRGD 0.4V

PWRGD Leakage Current IPWRGD_LK — 40 700 nA VPWRGD Pullup = 10 k to VIN, VIN = 16V

PWRGD Time Delay TPG — 100 — µs Rising Edge of VOUT, RPULLUP = 10 k

Detect Threshold to PWRGD Active Time Delay

TVDET_PWRGD — 200 — µs Falling Edge of VOUT after Transition from VOUT = VPRWRGD_TH + 50 mV, to VPWRGD_TH - 50 mV,RPULLUP = 10k to VIN

AC/DC CHARACTERISTICS (CONTINUED)Electrical Specifications: Unless otherwise specified, all limits are established for VIN = VR + 1V, Note 1, ILOAD = 1 mA, COUT = 1 µF (X7R), CIN = 1 µF (X7R), TA = +25°C, tr(VIN) = 0.5V/µs, SHDN = VIN, PWRGD = 10K to VOUT.Boldface type applies for junction temperatures, TJ (Note 7) of -40°C to +125°C.










MCP1754/MCP1754S

AC Performance

Output Delay From VIN To VOUT = 90% VREG

TDELAY — 240 — µs VIN = 0V to 16V, VOUT = 90% VR, tr (VIN)= 5V/µs,COUT = 1 µF, SHDN = VIN

Output Delay From VIN To VOUT > 0.1V

TDELAY_START — 80 — µs VIN = 0V to 16V, VOUT 0.1V, tr (VIN)= 5V/µs,COUT = 1 µF, SHDN = VIN

Output Delay From SHDN to VOUT = 90% VREG

TDELAY_SHDN — 160 — µs VIN = 16V, VOUT = 90% VR,COUT = 1 µF, SHDN = GND to VIN

Output Noise eN — 3 — µV/(Hz)1/2 IL = 50 mA, f = 1 kHz, COUT = 1 µF

Power Supply Ripple Rejection Ratio

PSRR — 72 — dB VR = 5V, f = 1 kHz, IL = 150 mA, VINAC = 1V pk-pk, CIN = 0 µF, VIN = VR + 1.5V

Thermal Shutdown Temperature

TSD — 150 — °C Note 6

Thermal Shutdown Hysteresis

TSD — 10 — °C

AC/DC CHARACTERISTICS (CONTINUED)Electrical Specifications: Unless otherwise specified, all limits are established for VIN = VR + 1V, Note 1, ILOAD = 1 mA, COUT = 1 µF (X7R), CIN = 1 µF (X7R), TA = +25°C, tr(VIN) = 0.5V/µs, SHDN = VIN, PWRGD = 10K to VOUT.Boldface type applies for junction temperatures, TJ (Note 7) of -40°C to +125°C.










MCP1754/MCP1754S

TEMPERATURE SPECIFICATIONS (Note 1)


Temperature Ranges

Specified Temperature Range TA -40 +125 °C

Operating Temperature Range TJ -40 +150 °C

Storage Temperature Range TA -55 +150 °C

Thermal Package Resistance

Thermal Resistance, SOT-223-3 JAJC

——

6215

——

°C/W

Thermal Resistance, SOT-23A-3 JAJC

——

336110

——

°C/W


——

153.3100

——

°C/W


——

6215

——

°C/W

Thermal Resistance, 2X3 DFN JAJC

——

9326

——

°C/W

Note 1: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air (i.e., TA, TJ, JA). Exceeding the maximum allowable power dissipation causes the device operating junction temperature to exceed the maximum +150°C rating. Sustained junction temperatures above +150°C can impact the device reliability.


MCP1754/MCP1754S

2.0 TYPICAL PERFORMANCE CURVES

Note 1: Unless otherwise indicated VR = 3.3V, COUT = 1 µF Ceramic (X7R), CIN = 1 µF Ceramic (X7R), IL = 1 mA, TA = +25°C,VIN = VR + 1V or VIN = 3.6V (whichever is greater), SHDN = VIN, package = SOT-223.

2: Junction Temperature (TJ) is approximated by soaking the device under test to an ambient temperature equal to thedesired junction temperature. The test time is small enough such that the rise in junction temperature over the ambienttemperature is not significant.

FIGURE 2-1: Quiescent Current vs. Input Voltage.



FIGURE 2-4: Ground Current vs. Load Current.

FIGURE 2-5: Quiescent Current vs. Junction Temperature.


Note: The graphs and tables provided following this note are a statistical summary based on a limited number ofsamples and are provided for informational purposes only. The performance characteristics listed hereinare not tested or guaranteed. In some graphs or tables, the data presented may be outside the specifiedoperating range (e.g., outside specified power supply range) and therefore outside the warranted range.

40

50

60

70

80

3 4 5 6 7 8 9 10 11 12 13 14 15 16

Qui

esce

nt C

urre

nt (µ

A)

Input Voltage (V)

VOUT = 1.8VIOUT = 0 µA

+25°C+130°C

-45°C0°C

+90°C

40

45

50

55

60

65

70

3 5 7 9 11 13 15

Qui

esce

nt C

urre

nt (µ

A)

Input Voltage (V)


+25°C

+130°C

-45°C

0°C

+90°C

01020304050607080

1.0 3.0 5.0 7.0 9.0 11.0 13.0 15.0 17.0

Qui

esce

nt C

urre

nt (µ

A)

Input Voltage (V)


+25°C

+130°C

-45°C0°C

+90°C

40

60

80

100

120

140

160

180

0 20 40 60 80 100 120 140 160

GN

D C

urre

nt (µ

A)

Load Current (mA)

VOUT = 5.0V

VOUT = 3.3V

VOUT = 1.8V

01020304050607080

-45 -20 5 30 55 80 105 130

Qui

esce

nt C

urre

nt (µ

A)

Junction Temperature (°C)

VOUT = 5.0V VOUT = 1.8V

VOUT = 3.3V

01020304050607080

024681012141618

Qui

esce

nt C

urre

nt (µ

A)

Input Voltage (V)

VOUT = 5.0V

+25°C


MCP1754/MCP1754S

Note 1: Unless otherwise indicated VR = 3.3V, COUT = 1 µF Ceramic (X7R), CIN = 1 µF Ceramic (X7R), IL = 1 mA,TA = +25°C, VIN = VR + 1V or VIN = 3.6V (whichever is greater), SHDN = VIN, package = SOT-223.

2: Junction Temperature (TJ) is approximated by soaking the device under test to an ambient temperatureequal to the desired junction temperature. The test time is small enough such that the rise in junctiontemperature over the ambient temperature is not significant.

FIGURE 2-7: Output Voltage vs. Input Voltage.



FIGURE 2-10: Output Voltage vs. Load Current.



1.800

1.802

1.804

1.806

1.808

1.810

1.812

1.814

3 4 5 6 7 8 9 10 11 12 13 14 15 16

Out

put V

olta

ge (V

)

Input Voltage (V)

VOUT = 1.8V+25°C

+130°C

-45°C

0°C

+90°C

3.2903.2923.2943.2963.2983.3003.3023.3043.3063.3083.310

4 5 6 7 8 9 10 11 12 13 14 15 16

Out

put V

olta

ge (V

)

Input Voltage (V)

VOUT = 3.3V

+25°C

+130°C

-45°C

0°C

+90°C

5.000

5.004

5.008

5.012

5.016

5.020

6 7 8 9 10 11 12 13 14 15 16

Out

put V

olta

ge (V

)

Input Voltage (V)

VOUT = 5.0V

+25°C

+130°C

-45°C

0°C

+90°C

1.790

1.795

1.800

1.805

1.810

1.815

0 25 50 75 100 125 150

Out

put V

olta

ge (V

)

Load Current (mA)

VOUT = 1.8V25°C

90°C

130°C

0°C

-45°C

3.280

3.285

3.290

3.295

3.300

3.305

3.310

0 25 50 75 100 125 150

Out

put V

olta

ge (V

)

Load Current (mA)

VOUT = 3.3V

25°C 90°C

0°C-45°C

130°C

4.9804.9854.9904.9955.0005.0055.0105.0155.020

0 25 50 75 100 125 150

Out

put V

olta

ge (V

)

Load Current (mA)

VOUT = 5.0V

25°C

90°C

0°C-45°C

130°C


MCP1754/MCP1754S

Note 1: Unless otherwise indicated VR = 3.3V, COUT = 1 µF Ceramic (X7R), CIN = 1 µF Ceramic (X7R), IL = 1 mA,TA = +25 °C, VIN = VR + 1V or VIN = 3.6V (whichever is greater), SHDN = VIN, package = SOT-223.


FIGURE 2-13: Dropout Voltage vs. Load Current.

FIGURE 2-14: Dropout Voltage vs. Load Current.

FIGURE 2-15: Dynamic Line Response.

FIGURE 2-16: Dynamic Line Response.

FIGURE 2-17: Short Circuit Current vs. Input Voltage.

0.000

0.100

0.200

0.300

0.400

0.500

0 15 30 45 60 75 90 105 120 135 150

Dro

pout

Vol

tage

(V)

Load Current (mA)

VOUT = 3.3V

+25°C

+130°C

-45°C0°C

+90°C

0.0000.0500.1000.1500.2000.2500.3000.3500.400

0 15 30 45 60 75 90 105 120 135 150

Dro

pout

Vol

tage

(V)

Load Current (mA)

VOUT = 3.3V

+25°C

+130°C

-45°C

0°C

+90°C

0

10

20

30

40

50

4 6 8 10 12 14 16

Shor

t Circ

uit C

urre

nt (m

A)

Input Voltage (V)

VOUT = 3.3V25°C90°C

130°C

0°C

-45°C


MCP1754/MCP1754S



FIGURE 2-18: Load Regulation vs. Temperature.



FIGURE 2-21: Line Regulation vs. Temperature.



-1.50-1.40-1.30-1.20-1.10-1.00-0.90-0.80-0.70-0.60-0.50

-45 -20 5 30 55 80 105 130

Load

Reg

ulat

ion

(%)

Temperature (°C)

VOUT=1.8VIout = 1 mA to 150 mA

VIN = 12V

VIN = 16V

VIN = 10V

VIN =

VIN = 3.6V

-1.00

-0.80

-0.60

-0.40

-0.20

0.00

-45 -20 5 30 55 80 105 130

Load

Reg

ulat

ion

(%)

Temperature (°C)

VOUT=3.3VIout = 1 mA to 150 mA

VIN = 16V

VIN = 5V VIN = 10V

VIN = 12V

VIN = 4.3V

-1.00

-0.80

-0.60

-0.40

-0.20

0.00

-45 -20 5 30 55 80 105 130

Load

Reg

ulat

ion

(%)

Temperature (°C)

VOUT= 5VIout = 1 mA to 150 mA

VIN = 16V

VIN = 6VVIN = 10V

VIN = 12V

-0.03

-0.02

-0.01

0.00

0.01

-45 -20 5 30 55 80 105 130

Line

Reg

ulat

ion

(%/V

)

Temperature (°C)

VOUT=1.8V

150 mA

0 mA

50 mA

100 mA

10 mA

-0.03

-0.02

-0.01

0.00

0.01

-45 -20 5 30 55 80 105 130

Line

Reg

ulat

ion

(%/V

)

Temperature (°C)

VOUT=3.3V

150 mA

0 mA

50 mA

100 mA

10 mA

-0.03

-0.02

-0.01

0.00

0.01

-45 -20 5 30 55 80 105 130

Line

Reg

ulat

ion

(%/V

)

Temperature (°C)

VOUT=5V

150 mA

0 mA

50 mA

100 mA

10 mA


MCP1754/MCP1754S



FIGURE 2-24: Power Supply Ripple Rejection vs. Frequency.

FIGURE 2-25: Power Supply Ripple Rejection vs. Frequency.

FIGURE 2-26: Output Noise vs. Frequency (3 lines, VR = 1.2V, 3.3V, 5.0V).

FIGURE 2-27: Power Up Timing.

FIGURE 2-28: Startup From Shutdown.

FIGURE 2-29: Short Circuit Current Foldback.

-110-100-90-80-70-60-50-40-30-20-10

0

0.01 0.1 1 10 100 1000

PSR

R (d

B)

Frequency ( Hz)

VOUT = 1.8VVIN = 6.5VVINAC = 1 Vp-pCIN = 0 F

IOUT = 10 mA

IOUT = 150 mA

-100-90-80-70-60-50-40-30-20-10

0

0.01 0.1 1 10 100 1000

PSR

R (d

B)

Frequency ( Hz)

VOUT = 5.0VVIN = 6.5VVINAC = 1V p-pCIN = 0 F IOUT = 160 mA

IOUT = 40 mA

0.001

0.010

0.100

1.000

10.000

0.01 0.1 1 10 100 1000Frequency ( Hz)

VOUT=5.0V, VIN=6.0V IOUT=50mA

VOUT=3.3V, VIN=4.3V

VOUT=1.8V, VIN=3.6V

0.000.250.500.751.001.251.501.752.00

0.00 0.05 0.10 0.15 0.20 0.25 0.30

Out

put V

olta

ge (V

)

Output Current (A)

Increasing Load

Decreasing Load

VIN = 3.6VVOUT = 1.8V


MCP1754/MCP1754S





FIGURE 2-32: Dynamic Load Response.

FIGURE 2-33: Dynamic Load Response.

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0.00 0.05 0.10 0.15 0.20 0.25 0.30

Out

put V

olta

ge (V

)

Output Current (A)

Increasing Load

Decreasing Load

VIN = 4.3VVOUT = 3.3V

0.00.51.01.52.02.53.03.54.04.55.05.5

0.00 0.05 0.10 0.15 0.20 0.25 0.30

Out

put V

olta

ge (V

)

Output Current (A)

Increasing Load

Decreasing Load

VIN = 6VVOUT = 5V


MCP1754/MCP1754S

3.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1 and Table 3-2.

3.1 Regulated Output Voltage (VOUT)

Connect VOUT to the positive side of the load and thepositive terminal of the output capacitor. The positiveside of the output capacitor should be physicallylocated as close to the LDO VOUT pin as is practical.The current flowing out of this pin is equal to the DCload current.

3.2 Power Good Output (PWRGD)

The PWRGD output is an open-drain output used toindicate when the LDO output voltage is within 92%(typically) of its nominal regulation value. The PWRGDthreshold has a typical hysteresis value of 2%. ThePWRGD output is delayed by 100 µs (typical) from thetime the LDO output is within 92% + 2% (typicalhysteresis) of the regulated output value on power-up.This delay time is internally fixed. The PWRGD pin maybe pulled up to VIN or VOUT. Pulling up to VOUTconserves power when the device is in shutdown(SHDN = 0V) mode.

3.3 Ground Terminal (GND)

Regulator ground. Tie GND to the negative side of theoutput and the negative side of the input capacitor.Only the LDO bias current flows out of this pin; there isno high current. The LDO output regulation isreferenced to this pin. Minimize the voltage dropsbetween this pin and the negative side of the load.

3.4 Shutdown Input (SHDN)

The SHDN input is used to turn the LDO output voltageon and off. When the SHDN input is at a logic highlevel, the LDO output voltage is enabled. When theSHDN input is pulled to a logic low level, the LDOoutput voltage is disabled. When the SHDN input ispulled low, the PWRGD output also goes low and theLDO enters a low quiescent current shutdown state.

3.5 Unregulated Input Voltage (VIN)

Connect VIN to the input unregulated source voltage.Like all low dropout linear regulators, low-sourceimpedance is necessary for the stable operation of theLDO. The amount of capacitance required to ensurelow-source impedance depends on the proximity of theinput source capacitors or battery type. For mostapplications, 1 µF of capacitance ensures stableoperation of the LDO circuit. The input capacitor shouldhave a capacitance value equal to or larger than theoutput capacitor for performance applications. Theinput capacitor supplies the load current duringtransients and improves performance. For applicationsthat have load currents below 10 mA, the inputcapacitance requirement can be lowered. The type ofcapacitor used may be ceramic, tantalum or aluminumelectrolytic. The low ESR characteristics of the ceramicyields better noise and PSRR performance at highfrequency.

TABLE 3-1: MCP1754 PIN FUNCTION TABLE

Pin No.SOT223-5

Pin No.SOT23-5

Pin No.2X3 DFN

Name Function

4 5 1 VOUT Regulated Voltage Output

5 4 2 PWRGD Open-Drain Power Good Output

— — 3,6,7 NC No Connection

3 2 4 GND Ground Terminal

1 3 5 SHDN Shutdown Input

2 1 8 VIN Unregulated Supply Voltage

EP — EP GND Exposed Pad, Connected to GND

TABLE 3-2: MCP1754S PIN FUNCTION TABLE

Pin No.SOT223-3

Pin No.SOT23A

Pin No.SOT89

Pin No.2X3 DFN

Name Function

3 2 3 1 VOUT Regulated Voltage Output

— — — 2,3,5,6,7 NC No Connection

2 1 2 4 GND Ground Terminal

1 3 1 8 VIN Unregulated Supply Voltage

EP — EP EP GND Exposed Pad, Connected to GND


MCP1754/MCP1754S

3.6 Exposed Pad (EP)

Some of the packages have an exposed metal pad onthe bottom of the package. The exposed metal padgives the device better thermal characteristics byproviding a good thermal path to either the PCB or heatsink to remove heat from the device. The exposed padof the package is internally connected to GND.


MCP1754/MCP1754S

4.0 DEVICE OVERVIEW

The MCP1754/MCP1754S is a 150 mA output current,Low Dropout (LDO) voltage regulator. The low dropoutvoltage of 300 mV typical at 150 mA of current makesit ideal for battery-powered applications. The inputvoltage range is 3.6V to 16.0V. Unlike other high outputcurrent LDOs, the MCP1754/MCP1754S typicallydraws only 150 µA of quiescent current for a 150 mAload. The MCP1754 adds a shutdown control input pinand a power good output pin. The output voltageoptions are fixed.

4.1 LDO Output Voltage

The MCP1754/MCP1754S LDO has a fixed outputvoltage. The output voltage range is 1.8V to 5.5V.

4.2 Output Current and Current Limiting

The MCP1754/MCP1754S LDO is tested and ensuredto supply a minimum of 150 mA of output current. TheMCP1754/MCP1754S has no minimum output load, sothe output load current can go to 0 mA and the LDO willcontinue to regulate the output voltage to withintolerance.

The MCP1754/MCP1754S also incorporates a trueoutput current foldback. If the output load presents anexcessive load due to a low-impedance short circuitcondition, the output current and voltage will fold backtowards 30 mA and 0V, respectively.

The output voltage and current resume normal levelswhen the excessive load is removed. If the overloadcondition is a soft overload, the MCP1754/MCP1754S

supplies higher load currents of up to typically 250 mA.This allows for device usage in applications that havepulsed load currents having an average output currentvalue of 150 mA or less.

Output overload conditions may also result in anovertemperature shutdown of the device. If the junctiontemperature rises above +150°C (typical), the LDOshuts down the output. See Section 4.8“Overtemperature Protection” for more informationon overtemperature shutdown.

4.3 Output Capacitor

The MCP1754/MCP1754S requires a minimum outputcapacitance of 1 µF for output voltage stability. Ceramiccapacitors are recommended because of their size,cost and environmentally robust qualities.

Aluminum-electrolytic and tantalum capacitors can beused on the LDO output as well. The Equivalent SeriesResistance (ESR) of the electrolytic output capacitorshould be no greater than 2.0. The output capacitorshould be located as close to the LDO output as ispractical. Ceramic materials X7R and X5R have lowtemperature coefficients and are well within theacceptable ESR range required. A typical 1 µF X7R0805 capacitor has an ESR of 50 milliohms.

Larger LDO output capacitors are used with theMCP1754/MCP1754S to improve dynamicperformance and power supply ripple rejectionperformance. A maximum of 1000 µF isrecommended. Aluminum-electrolytic capacitors arenot recommended for low temperature applications of<-25°C.

FIGURE 4-1: Typical Current Foldback.

0

1

2

3

4

5

6

0.000 0.050 0.100 0.150 0.200 0.250

V OU

T(V

)

IOUT (A)

Typical Current FoldBack - 5V Output

Increasing Load Decreasing Load


MCP1754/MCP1754S

4.4 Input Capacitor

Low input source impedance is necessary for the LDOoutput to operate properly. When operating frombatteries or in applications with long lead length(>10 inches) between the input source and the LDO,some input capacitance is recommended. A minimumof 1.0 µF to 4.7 µF is recommended for mostapplications.

For applications that have output step loadrequirements, the input capacitance of the LDO is veryimportant. The input capacitance provides the LDOwith a good local low-impedance source to pull thetransient currents from in order to respond quickly tothe output load step. For good step responseperformance, the input capacitor should be ofequivalent or higher value than the output capacitor.The capacitor should be placed as close to the input ofthe LDO as is practical. Larger input capacitors alsohelp reduce any high-frequency noise on the input andoutput of the LDO and reduce the effects of anyinductance that exists between the input sourcevoltage and the input capacitance of the LDO.

4.5 Power Good Output (PWRGD)

The open-drain PWRGD output is used to indicatewhen the output voltage of the LDO is within 94%(typical value, see Section 1.0 “ElectricalCharacteristics” for minimum and maximumspecifications) of its nominal regulation value.

As the output voltage of the LDO rises, the open-drainPWRGD output is actively held low until the outputvoltage has exceeded the power good threshold plusthe hysteresis value. Once this threshold has beenexceeded, the power good time delay is started (shownas TPG in the Electrical Characteristics table). Thepower good time delay is fixed at 100 µs (typical). Afterthe time delay period, the PWRGD open-drain outputbecomes inactive and may be pulled high by anexternal pull-up resistor, indicating that the outputvoltage is stable and within regulation limits. The powergood output is typically pulled up to VIN or VOUT. Pullingthe signal up to VOUT conserves power duringShutdown mode.

If the output voltage of the LDO falls below the powergood threshold, the power good output will transitionlow. The power good circuitry has a 200 µs delay whendetecting a falling output voltage, which helps toincrease noise immunity and avoid false triggering ofthe power good output during fast output transients.See Figure 4-2 for power good timing characteristics.

When the LDO is put into Shutdown mode using theSHDN input, the power good output is pulled lowimmediately, indicating that the output voltage is out ofregulation. The timing diagram for the power goodoutput when using the shutdown input is shown inFigure 4-3.

The power good output is an open-drain output that canbe pulled up to any voltage equal to or less than theLDO input voltage. This output is capable of sinking5 mA (VPWRGD < 0.4V).

FIGURE 4-2: Power Good Timing.

FIGURE 4-3: Power Good Timing from Shutdown.

4.6 Shutdown Input (SHDN)

The SHDN input is an active-low input signal that turnsthe LDO on and off. The SHDN threshold is a fixedvoltage level. The minimum value of this shutdownthreshold required to turn the output ON is 2.4V. Themaximum value required to turn the output OFF is 0.8V.

TPG

TVDET_PWRGD

VPWRGD_TH

VOUT

PWRGD

VOL

VOH

VIN

SHDN

VOUT

TDELAY_SHDN

PWRGD

TPG


MCP1754/MCP1754S

The SHDN input ignores low going pulses (pulsesmeant to shut down the LDO) that are up to 400 ns inpulse width. If the shutdown input is pulled low for morethan 400 ns, the LDO enters Shutdown mode. Thissmall bit of filtering helps to reject any system noisespikes on the shutdown input signal.

On the rising edge of the SHDN input, the shutdowncircuitry has a 70 µs delay before allowing the LDOoutput to turn on. This delay helps to reject any falseturn-on signals or noise on the SHDN input signal. Afterthe 70 µs delay, the LDO output enters its soft-startperiod as it rises from 0V to its final regulation value. Ifthe SHDN input signal is pulled low during the 70 µsdelay period, the timer resets and the delay time startsover again on the next rising edge of the SHDN input.The total time from the SHDN input going high (turn-on)to the LDO output being in regulation is typically160 µs. See Figure 4-4 for a timing diagram of theSHDN input.

FIGURE 4-4: Shutdown Input Timing Diagram.

4.7 Dropout Voltage and Undervoltage Lockout

Dropout voltage is defined as the input-to-outputvoltage differential at which the output voltage drops2% below the nominal value that was measured with aVR + 1.0V differential applied. The MCP1754/MCP1754S LDO has a very low dropout voltagespecification of 300 mV (typical) at 150 mA of outputcurrent. See Section 1.0 “Electrical Characteristics”for maximum dropout voltage specifications.

The MCP1754/MCP1754S LDO operates across aninput voltage range of 3.6V to 16.0V and incorporatesinput Undervoltage Lockout (UVLO) circuitry that keepsthe LDO output voltage off until the input voltagereaches a minimum of 2.95V (typical) on the risingedge of the input voltage. As the input voltage falls, theLDO output remains on until the input voltage levelreaches 2.70V (typical).

For high-current applications, voltage drops across thePCB traces must be taken into account. The traceresistances can cause significant voltage dropsbetween the input voltage source and the LDO. Forapplications with input voltages near 3.0V, these PCBtrace voltage drops can sometimes lower the inputvoltage enough to trigger a shutdown due toundervoltage lockout.

4.8 Overtemperature Protection

The MCP1754/MCP1754S LDO has temperature-sensing circuitry to prevent the junction temperaturefrom exceeding approximately +150°C. If the LDOjunction temperature does reach +150°C, the LDOoutput is turned off until the junction temperature coolsto approximately +137°C, at which point the LDOoutput automatically resumes normal operation. If theinternal power dissipation continues to be excessive,the device will again shut off. The junction temperatureof the die is a function of power dissipation, ambienttemperature and package thermal resistance. SeeSection 5.0 “Application Circuits and Issues” formore information on LDO power dissipation andjunction temperature.

SHDN

VOUT

70 µs90 µs

TDELAY_SHDN400 ns (typical)


MCP1754/MCP1754S

NOTES:


MCP1754/MCP1754S

5.0 APPLICATION CIRCUITS AND ISSUES

5.1 Typical Application

The MCP1754/MCP1754S is most commonly used asa voltage regulator. Its low quiescent current and lowdropout voltage make it ideal for many battery-poweredapplications.

FIGURE 5-1: Typical Application Circuit.

5.1.1 APPLICATION INPUT CONDITIONS

5.2 Power Calculations

5.2.1 POWER DISSIPATION

The internal power dissipation of the MCP1754/MCP1754S is a function of input voltage, outputvoltage and output current. The power dissipation, as aresult of the quiescent current draw, is so low that it isinsignificant (56.0 µA x VIN). The following equationcan be used to calculate the internal power dissipationof the LDO.

EQUATION

The maximum continuous operating junctiontemperature specified for the MCP1754/MCP1754S is+150°C. To estimate the internal junction temperatureof the MCP1754/MCP1754S, the total internal powerdissipation is multiplied by the thermal resistance fromjunction to ambient (RJA). The thermal resistance fromjunction to ambient for the SOT23A pin package isestimated at 336 °C/W.

EQUATION

The maximum power dissipation capability of apackage is calculated given the junction-to-ambientthermal resistance and the maximum ambienttemperature for the application. The following equationcan be used to determine the package maximuminternal power dissipation.

EQUATION

EQUATION

EQUATION

Package Type = SOT23

Input Voltage Range = 3.6V to 4.8V

VIN maximum = 4.8V

VOUT typical = 1.8V

IOUT = 50 mA maximum

MCP1754S

GND

VOUT

VINCIN1 µF Ceramic

COUT1 µF Ceramic

VOUT

VIN3.6V to 4.8V

1.8V

IOUT50 mA

PLDO VIN MAX VOUT MIN – IOUT MAX =

PLDO = LDO Pass device internal power dissipation

VIN(MAX) = Maximum input voltage

VOUT(MIN) = LDO minimum output voltage

TJ MAX PTOTAL RJA TA MAX +=

TJ(MAX) = Maximum continuous junctiontemperature

PTOTAL = Total device power dissipation

RJA = Thermal resistance from junction to ambient

TA(MAX) = Maximum ambient temperature

PD MAX TJ MAX TA MAX –

RJA---------------------------------------------------=

PD(MAX) = Maximum device power dissipation

TJ(MAX) = Maximum continuous junction temperature

TA(MAX) = Maximum ambient temperature


TJ RISE PD MAX RJA=

TJ(RISE) = Rise in device junction temperature over the ambient temperature

PD(MAX = Maximum device power dissipation


TJ TJ RISE TA+=

TJ = Junction Temperature

TJ(RISE) = Rise in device junction temperature over the ambient temperature

TA = Ambient temperature


MCP1754/MCP1754S

5.3 Voltage Regulator

Internal power dissipation, junction temperature rise,junction temperature and maximum power dissipationare calculated in the following example. The powerdissipation, as a result of ground current, is smallenough to be neglected.

5.3.1 POWER DISSIPATION EXAMPLE

5.3.1.1 Device Junction Temperature Rise

The internal junction temperature rise is a function ofinternal power dissipation and the thermal resistancefrom junction to ambient for the application. The thermalresistance from junction to ambient (RJA) is derivedfrom an EIA/JEDEC® standard for measuring thermalresistance for small surface mount packages. The EIA/JEDEC specification is JESD51-7, “High EffectiveThermal Conductivity Test Board for Leaded SurfaceMount Packages”. The standard describes the testmethod and board specifications for measuring thethermal resistance from junction to ambient. The actualthermal resistance for a particular application can varydepending on many factors, such as copper area andthickness. Refer to AN792, “A Method to DetermineHow Much Power a SOT23 Can Dissipate in anApplication” (DS00792), for more information regardingthis subject.

5.3.1.2 Junction Temperature Estimate

To estimate the internal junction temperature, thecalculated temperature rise is added to the ambient oroffset temperature. For this example, the worst-casejunction temperature is estimated as follows:

Maximum Package Power Dissipation Examples at+40°C Ambient Temperature

5.4 Voltage Reference

The MCP1754/MCP1754S can be used not only as aregulator, but also as a low quiescent current voltagereference. In many microcontroller applications, theinitial accuracy of the reference can be calibrated usingproduction test equipment or by using a ratiomeasurement. When the initial accuracy is calibrated,the thermal stability and line regulation tolerance arethe only errors introduced by the MCP1754/MCP1754S LDO. The low-cost, low quiescent currentand small ceramic output capacitor are all advantageswhen using the MCP1754/MCP1754S as a voltagereference.

FIGURE 5-2: Using the MCP1754/MCP1754S as a Voltage Reference.

Package

Package Type = SOT-23

Input Voltage

VIN = 3.6V to 4.8V

LDO Output Voltages and Currents

VOUT = 1.8V

IOUT = 50 mA

Maximum Ambient Temperature

TA(MAX) = +40°C

Internal Power Dissipation

Internal Power dissipation is the product of the LDO output current multiplied by the voltage across the LDO (VIN to VOUT).

PLDO(MAX) = (VIN(MAX) - VOUT(MIN)) x IOUT(MAX)

PLDO = (4.8V - (0.97 x 1.8V)) x 50 mA

PLDO = 152.7 milliwatts

TJ(RISE) = PTOTAL x RJA

TJ(RISE) = 152.7 milliwatts x 336.0°C/Watt

TJ(RISE) = 51.3°C

TJ = TJ(RISE) + TA(MAX)

TJ = 91.3°C

SOT-23 (336.0°C/Watt = RJA)

PD(MAX) = (125°C – 40°C)/336°C/W

PD(MAX) = 253 milliwatts

SOT-89 (153.3°C/Watt = RJA)

PD(MAX) = (125°C – 40°C)/153.3°C/W

PD(MAX) = 554 milliwatts

PIC®MCP1754S

GND

VINCIN1 µF COUT

1 µF

Bridge Sensor

VOUTVREF

ADO AD1

Ratio Metric Reference

56 µA Bias Microcontroller


MCP1754/MCP1754S

5.5 Pulsed Load Applications

For some applications, there are pulsed load currentevents that may exceed the specified 150 mAmaximum specification of the MCP1754/MCP1754S.The internal current limit of the MCP1754/MCP1754Sprevents high peak load demands from causing non-recoverable damage. The 150 mA rating is a maximumaverage continuous rating. As long as the averagecurrent does not exceed 150 mA, pulsed higher loadcurrents can be applied to the MCP1754/MCP1754S.The typical current limit for the MCP1754/MCP1754S is250 mA (TA +25°C).


MCP1754/MCP1754S

NOTES:


MCP1754/MCP1754S

6.0 PACKAGING INFORMATION

6.1 Package Marking Information

Legend: XX...X Customer-specific informationY Year code (last digit of calendar year)YY Year code (last 2 digits of calendar year)WW Week code (week of January 1 is week ‘01’)NNN Alphanumeric traceability code Pb-free JEDEC® designator for Matte Tin (Sn)* This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it willbe carried over to the next line, thus limiting the number of available charactersfor customer-specific information.

3e

3e

XXXXXXX

NNNXXXYYWW

3-Lead SOT-223 (MCP1754S only) Example:

1754S18EDB1335

256

Part Number Code

MCP1754S-1802E/DB 1754S18

MCP1754ST-1802E/DB 1754S18

MCP1754S-3302E/DB 1754S33

MCP1754ST-3302E/DB 1754S33

MCP1754S-5002E/DB 1754S50

MCP1754ST-5002E/DB 1754S50

3-Lead SOT-23A (MCP1754S only) Example:

XXNN

NNN

3-Lead SOT-89 (MCP1754S only) Example:

JC25

MT1335256

Part Number Code

MCP1754ST-1802E/CB JCNN

MCP1754ST-3302E/CB JDNN

MCP1754ST-5002E/CB JENN

Part Number Code

MCP1754ST-1802E/MB MTYYWW

MCP1754ST-3302E/MB MUYYWW

MCP1754ST-5002E/MB MVYYWW


MCP1754/MCP1754S

Package Marking Information (Continued)

XXNN

5-Lead SOT-23A (2x3) (MCP1754 only) Example:

YQ25

XXXYYWWNNN

XXXXXXX

5-Lead SOT-223 (MCP1754 only) Example:

175418EDC1335

256

Part Number Code

MCP1754T-1802E/OT YQNN

MCP1754T-3302E/OT YRNN

MCP1754T-5002E/OT YSNN

Part Number Code

MCP1754T-1802E/DC 175418

MCP1754T-3302E/DC 175433

MCP1754T-5002E/DC 175450

8-Lead DFN (2x3) Example:

Part Number Code Part Number Code

MCP1754-1802E/MC AKG MCP1754S-1802E/MC ALN

MCP1754-3302E/MC AKH MCP1754S-3302E/MC ALM

MCP1754-5002E/MC AKJ MCP1754S-5002E/MC ALL

MCP1754T-1802E/MC AKG MCP1754ST-1802E/MC ALN

MCP1754T-3302E/MC AKH MCP1754ST-3302E/MC ALM

MCP1754T-5002E/MC AKJ MCP1754ST-5002E/MC ALL

AKJ33525


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APPENDIX A: REVISION HISTORY

Revision C (September 2013)

The following is the list of modifications:

1. Corrected Product Identification Systemexamples.

2. Minor editorial corrections.

Revision B (April 2013)

The following is the list of modifications:

1. Updated Note 5 in the AC/DC Characteristicstable.

2. Updated Figure 2-20.

3. Minor grammatical and spelling corrections.

Revision A (August 2011)

4. Original data sheet for the MCP1754/MCP1754S family of devices.


MCP1754/MCP1754S

NOTES:


MCP1754/MCP1754S

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Device: MCP1754: 150 mA, 16V High-Performance LDOMCP1754T: 150 mA, 16V High-Performance LDO

(Tape and Reel) (SOT)MCP1754S: 150 mA, 16V High-Performance LDOMCP1754ST: 150 mA, 16V High-Performance LDO

(Tape and Reel) (SOT)

Tape and Reel: T = Tape and Reel

Output Voltage*: 18 = 1.8V “Standard”

33 = 3.3V “Standard”

50 = 5.0V “Standard”

*Contact factory for other voltage options

Extra Feature Code: 0 = Fixed

Tolerance: 2 = 2% (Standard)

Temperature Range: E = -40°C to +125°C

Package: CB = Plastic Small Outline, (SOT-23A), 3-leadDB* = Plastic Small Outline, (SOT-223), 3-leadDC = Plastic Small Outline, (SOT223), 5-leadMB = Plastic Small Outline, (SOT-89), 3-leadMC = Plastic Dual Flat, No Lead, (2x3 DFN), 8-leadOT = Plastic Small Outline, (SOT-23), 5-lead

*Note: The 3-lead SOT-223 (DB) is not a standard package for output voltages below 3.0V

PART NO. X- XX

PackageTapeand Reel

Device

Examples:

a) MCP1754T-1802E/DC: 1.8V, 5LD SOT-223,Tape and Reel

b) MCP1754T-3302E/DC: 3.3V, 5LD SOT-223,Tape and Reel

c) MCP1754T-5002E/DC: 5.0V, 5LD SOT-223,Tape and Reel

a) MCP1754T-1802E/OT: 1.8V, 5LD SOT-23,Tape and Reel

b) MCP1754T-3302E/OT: 3.3V, 5LD SOT-23,Tape and Reel

c) MCP1754T-5002E/OT: 5.0V, 5LD SOT-23,Tape and Reel

a) MCP1754T-1802E/MC: 1.8V, 8LD DFN,Tape and Reel

b) MCP1754T-3302E/MC: 3.3V, 8LD DFN,Tape and Reel

c) MCP1754T-5002E/MC: 5.0V, 8LD DFN,Tape and Reel

a) MCP1754ST-3302E/DB: 3.3V, 3LD SOT-223,Tape and Reel

b) MCP1754ST-5002E/DB: 5.0V, 3LD SOT-223,Tape and Reel

a) MCP1754ST-1802E/CB: 1.8V, 3LD SOT-23A,Tape and Reel

b) MCP1754ST-3302E/CB: 3.3V, 3LD SOT-23A,Tape and Reel

c) MCP1754ST-5002E/CB: 5.0V, 3LD SOT-23A,Tape and Reel

a) MCP1754ST-1802E/MB: 1.8V, 3LD SOT-89,Tape and Reel

b) MCP1754ST-3302E/MB: 3.3V, 3LD SOT-89,Tape and Reel

c) MCP1754ST-5002E/MB: 5.0V, 3LD SOT-89,Tape and Reel

a) MCP1754ST-1802E/MC: 1.8V, 8LD DFN,Tape and Reel

b) MCP1754ST-3302E/MC: 3.3V, 8LD DFN,Tape and Reel

c) MCP1754ST-5002E/MC: 5.0V, 8LD DFN,Tape and Reel

X/

Temp.

X

Tolerance

X

FeatureCode

XX

OutputVoltage


MCP1754/MCP1754S

NOTES:


Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of ourproducts. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such actsallow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding deviceapplications and the like is provided only for your convenienceand may be superseded by updates. It is your responsibility toensure that your application meets with your specifications.MICROCHIP MAKES NO REPRESENTATIONS ORWARRANTIES OF ANY KIND WHETHER EXPRESS ORIMPLIED, WRITTEN OR ORAL, STATUTORY OROTHERWISE, RELATED TO THE INFORMATION,INCLUDING BUT NOT LIMITED TO ITS CONDITION,QUALITY, PERFORMANCE, MERCHANTABILITY ORFITNESS FOR PURPOSE. Microchip disclaims all liabilityarising from this information and its use. Use of Microchipdevices in life support and/or safety applications is entirely atthe buyer’s risk, and the buyer agrees to defend, indemnify andhold harmless Microchip from any and all damages, claims,suits, or expenses resulting from such use. No licenses areconveyed, implicitly or otherwise, under any Microchipintellectual property rights.

2011-2013 Microchip Technology Inc.

QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV

== ISO/TS 16949 ==

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MTP, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.

Analog-for-the-Digital Age, Application Maestro, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O, Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA and Z-Scale are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

GestIC and ULPP are registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries.

All other trademarks mentioned herein are property of their respective companies.

© 2011-2013, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.

Printed on recycled paper.

ISBN: 978-1-62077-473-1

Microchip received ISO/TS-16949:2009 certification for its worldwide

DS20002276C-page 43

headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

DS20002276C-page 44 2013 Microchip Technology Inc.

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Documents

150 mA, 16V, High-Performance LDO - Microchip Technologyww1.microchip.com/downloads/en/DeviceDoc/20002276C.pdf · for four to six primary cell battery-powered applications, 12V mobile