400 Advanced Digital Design with the Verilog HDL

M2.M2~SRAM.memory[3] = 8'b0101_00_11;M2.M2_SRAM.memory[4] = 131'; .

M2.M2_SRAM.memory[5] = 8'b0101_00_01;M2.M2_SRAM.memory[6] = 128;

M2.M2_SRAM:memory[7] =8'b0101_00_00;M2.M2_SRAM.memory[8] =129;

M2.M2_SRAM.memory[9J =8'b0010_00_01;

M2.M2_SRAM.memory[10] =8'b1000_00_00;M2.M2_SRAM.memory[11] =134;

M2.M2_SRAM.memory[12] =8'bOO01_10_11;M2.M2_SRAM.memory[13]=8'b0111_00_11;M2.M2_SRAM.memory[14] =140;II Load data

M2.M2_SRAM.memory[128]=6;M2.M2_SRAM.memory[129] =1;M2.M2_SRAM.memory[130] =2;M2.M2_SRAM.memory[131] =0;M2.M2_SRAM.memory[134] =139;I/M2.M2_SRAM.memory[135] =0;M2.M2_SRAM.memory[139] =8'b1111_00_00;M2.M2_SRAM.memory[140]=9;

endendmodule

7.4 DesigJiExample: UART

IIRead 131 to R3

/I Read 128to R1~

/I Read 129 to RO

II Sub R1-RO to R1

II BRZII Holdsaddress for BRZ

/IAdd R2+R3 to R3II BR

~..

./

/

II HALT/I Recycle

Systemsthat exchange information and interact via serial data channels use modemsas interfaces between the host machinesldevicesand the channel, as shown in Figure7-14.For example,a modem allowsa computer to conneCtto a telephone line and com-municate with a receivingcomputer thr~ugh its modem [2,5].The host ma~hinestoresinformation in a parallel word format, but transmits and receives data in a serial, sin-gle-bit, format. If\.modem is also called a DART, or universal asynchronous receiver and

SerialDataChannel

trt It~

Modem ~'£i"Pr~ortn,

.' ~

FIGURE 7-14 Processor/modem communication {)ver a serial channel.

0'>

/~'

~ and Synthesisof Datapath ControUers 401

-I-

FIGURE 7.15 Data format for ASCII text transmitted by a UART.-'

transmitter, indicating that the device has the capability to both receive and transmitserial data. This design example Willaddress the modeling and synthesis of a UART'stransmitter and receiver.

For this discussion, a UART exchanges text data in an American Standard Codefor Information Interchange (ASCII) format in which each alphabetical character isencoded by 7 bits and augmented by a parity bit that can be used for error detection.For transmission, the modem wraps this 8-bit subword with a start-bit in the least sig-nificant bit (LSB), and a stop-bit in the most significant bit (MSB), resulting in the to-bitword format shown in Figure 7-15. The first 9 data bits are transmitted in sequence, be-ginning with the start-bit, with each bit being asserted at the serial line for one cycle ofthe modemclock.Thestop-bitmayassertformorethanoneclock. t.

7.4.1 UART Operation

The UART transmitter is always part of larger environment in which a host processorcontrols transmission by fetching a data word in parallel format and directing theUART to transtnit it in a'serial format. Likewise, the receiver must detect transmission,receive the data in serial format, strip off the start- and stop-bits, and store the dataword in a parallel format. The receiver's job is more complex, because the clock used tosend the iqbound data is not available at the remote receiver. The receiver must regen-erate the clock locally, using the receiving machine's clock rather than the clock of thetransmitting machine.

The simplified architecture of a UART presen5ea in Figure 7-16 shows the signalsused by a host processor to control the UART and to move data to and from a data busin the host machine. Details, of the host machine are not shown.

7.4.2 UART Thansmitter

The input-output signalsof the transmitter are shown in the high-levelblock diagramin Figure 7-17.The input signalsare provided by the host processor,and the output sig-nais control the movement of data in the UART.The architecture of the transmitterwill consist of a controller, a data register (XMT_datareg), a data shift register(XMT_shftreg), and a status register (biccount) to count the bits that are transmitted.The status register willbe included with the datapath unit.

It

402

SeriaUn

readJlocready _inread_nocready _out

Error!Erro1'2

'"

ByteJea4yT _byte

Serial_oui

Load.J{MT _datareg

Advanced Digital, Design with the Verilog HDL

.

~ .

...

UART_Receiver

Sys_Clock

Sample_elk

Clock

resec

UART_TransmittecArch

FIGURE 7-16 -Block diagram of aU ART. -

~~I3~

o/FromHost

~... and SynthesisofData path Controllers 403

ByteJeady

Load...J(MT _datareg

biccount

T_byte

Load...J(lt1TJhftreg-I-

start

shift

clear

FIGURE 7-17 Interface signals of a state machine controller for a DART transmitter.

The controller has the following inputs. For simplicity,Load_XMT_datareg isshown connected directly-toXMT_datareg:

Bytcready

Load_XMT _datareg

T_byte

biCcount

asserted by host machine to indicate that Dpta_Bus hasvalid dataassertion transfers Data_Bus to the transmitter datastorage register, XMT _dataregassertion initiates transmission of a byte of data,including the stop, start, andparity bitscounts bits in the word during transmission

The state'machine of the controller forms the followingoutput signals that control thedatapath of the transmitter:

. Load_XMT _shftreg

startshift

cleaf

assertion loads the contents of XMT_dataJegintoXMT_shftregsignals the start of transmissiondirects XMT _shftreg to shift by one bit towards the LSBand to backfill with a stop bit (1). .;clears biCcount

The ASM chart of the state machine controlling the transmitter ~ shown inFigure 7.18. The machine has three states: idle, waiting, and sending. When reseC is as-serted, the machine asynchronously enters idle, biccount is flush~d, XMT _shftreg isloaded with Is, and the control signals clear, Load_XMT _shftreg, shift, and start are dri-ven to O.In idle, if an active edge of Clock oCcurs while Load_XMT _dataJeg is assert-ed by the external host; the contents of Data_Bus will transfer to XMT _dataJeg. (Thisaction is not part of the ASM chart because it occurs independently of the state of themachine.) The machine remains in idle until start is asserted.

'\

,"

404-

Advan«:edDigital Design with the VerilogHDL

reseC .,

...

1

LoadJ{MT Jhftreg

Note: Only tbe brancb corresponding to a true decision isanootated at a decision diamond; signals tbat are not sbownexpiJcitlyasserted are de-asserted. Conditional assertions areindicatedbytbe nameof tbe assertedsignal

FIGURE '-18 ASM chart for the state machine controller for the DART transmitter.

- When ByteJeady is asserted, Load_XMT_shftreg is asserted and nexCstate is dri-ven to waiting. The assertion of Load_XMT _shftreg indicates that XMT _datareg nowcontains data that can be transferred to the internal shift register. At the next activeedge of Clock, with Load_XMT _shftreg asserted, three activities occur: (1) state trans-fers from idle to waiting, (2) the contents of XMT_datareg are loaded into the leftmostbits ofXMT_shftreg, a (word_size + 1)-bit shift register whose LSB signals the stanand stop of transmission, and (3) the LSB of XMT_shftreg is reloaded with 1, the stop-bit. The machine remains in waiting until the external processor asserts T_byte.

At the ne:xt active edge of Clock, with T_byte asserted, state enters sending, andthe LSB of XMT _shftreg is set to 0 to signal the start of transmission. At the same time.

Design and Synthesis of Datapath Controllers 405 ,shift is driven to 1, and nexCstate retains the state code corresponding to sending.Atsubsequent active edges of Clock,with shift asserted, state remains in sending and thecontents of XMT _shftreg are shifted toward the LSB, which drives the external serialchannel. As the data shifts occur, is are back-filled in XMT _shf!!eg, andbiCcount is in-cremented. With state in sending,shift asserts while biccountis less than 9. The ma-chine increments biccount after each movement of data, and when biccount reaches 9clear asserts, indicating that all of the bits of the augmented word have been shifted tothe serial output. At the next active edge of Clock, the machine returns to idle.

The control signals produce<! by the state machine induce state-dependent regis-ter transfers i~ t}]"edata path. The activity of the primary inputs (ByteJeady,Load_XMLdatareg, and T_byte), and the signals from the controner (Load_XMT_shftreg,start,shift, clear) are shown in Figure 7-19, along with the movement of data in the data-path registers. The contents of the registers are shown at successive edges of clock, witha time axis going from the top ofthe figure toward the bottom. Transitions of the activeedge of clock occur between the successive rows displaying contents of XMT _datareg.The bits of the transmitted signal are shown in the sequence in which they are trans-mitted, with the rightmost cell of XMLshftreg holding the bit that is transmitted at the

serial interface at each step. The state of the machine is shown, and the stat~transitionsand datapath register transitions that occur on the rising edges of clock are shown inthe register boxes. The values of the control signals that cause the register trapsitionsare also shown. The~displayed values of the control signals are those they held immedi-

- ately before the active edge of-Clock; and which cause the register transfers that areshown. The sequence of output bits is also $ttown, with is being-pushed into the MSBof XMT _shftrt:g under the action of shift. The sequence of output bits of the transmit-ted signal are shown as a word at each time step, with the 1lllderstanding thatJhe LSBof the word is the first bit that was.transmitted, and the MSB of the word is the most re-cent bit that was,transmitted at the serial interface.

The Verilog description, UARLTransmitter _Arch, of the architecture for thetransmitter has three cyclic behaviors-a level-sensitive behavior describing the com-binational logic for next state and.outputs of the controller, an edge-sensitive behaviorto synchronize the state transitions of the controller, and another edge-sensitive be-havior to synchronize the register transfers of thejdatapath registers. For simplicity, weinclude the entire description in a single Verilo{module, rather than impose architec-tural boundaries around the datapath and the controller (see Figure 7-20). The modulecan be partitioned and synthesized into the individual functional units.

Some simulation results are shown in Figure 7-21 and Figure 7-22 for an 8-bitdata word. The waveforms produced by the simulator h~ve been annotated to indicatesignificant features of the transmitter's behavior. Fll"st,observe the values of the signalsimmediately after reseC is asserted. The state is idle. Note that Data_Bus initially con-tains the value a7h (1O10_01112),a value specified by the testbench used for simulation.With ByteJeady' not yet asserted" and with LoadjCMT ~datareg asserted, theData_Bus is loaded into XMT_datareg. The machine remains in idle until ByteJeady isasserted. When ByteJeady asserts, then Load_XMT_shftreg asserts. This causes the

406 AdvancedpigitaIDesignwiththeVerilogHDL

;....

Inputs and controls

Load..J(MT_datareg "

j

ByteJeady ,

Load_XMT_shftreg

Tbyte. .

j

- start Datapath~~gistersj ,hiI' (OIl"'='" data)

rQl0 j 1 1[:':-'~ Dma_Bw[1<1J C", " 'L;J '+ t clock edges t ~. ';/

~1Ql1Ql00000J= XML"""'~g[7<1,,

]~~~ ~ ~: ,',".', ~~~1Ql t /Stopbit

0110~~~~J - XMTJhftreg[8:0] t0000

,

°",

0,','",

000 J fAmIII,

' "

,

1,

1,

.

,

,1,

'

,

11,

'

,

' 1~,,

~,

~;Z~ ;- --1", 000 ~ ,/: / I"- ,',' ° 0 ° J ~:", ".; '>:""- '" ''''', '.", / , I000" ,~IIi\mj.iJIlIhl ~ :

00000100 J 1 -i i

0000010,1 r 1 -iEl' i

. ~~a I"".w,..,.",:00000r11!1L<!J1I!1iI J 1 -:~ :

lR~g I I

00000~~fj J. 1 -!- Transmitt:d:. al 1~~~~fi1')rQl!iil J I~ Sign 1

0~~~~~~g. 11111 -:~ :, 1

0000 01f1J0!t11J [iJIIiliIilimmj!!H~ i00m01'

J '---'" ..' 1" ° ,',,' " I.""'" -", ,.' ,.. ",' , 1000 0 0 c, "~-:t:! .,d.""",-" :

00000~01J ~-i ===:

""", OB' J ': ,",,', ,""f", ," "."""" ,,',,'..,. ",":000.00101fJ ~-:l~~E_,~~~~:~:-----000000m1W J " ' / [StOPbiiiA-..Signal value at serial interface

,"

'.""

nGURE 7-19 Control signals andtlataflow in an 8-bit DART transmitter.

t.

Design and Synthesis of Datapath Controllers 407 ..

module UART_Transmitter_Arch(SeriaLout, Data_Bus,Byte_ready,Load_XMT_datareg,T_byte.Clock,reseU;parameter word-,-size= 8; . /I Size of data word, e.g., 8 bitsparameter one_hoCcount=.3; I/Number of one-hot statesparameter state_count';; one_hoCcount; /I Number of bits in state registerparameter size_biCcount = 3; . /I Size of the bit"counrer, e.g., 4

II Must count to word_size + 1/I one-hot state encodingparameter

parameterparameterparameter

idle = 3'b001;waiting = 3'b010;sending = 3'b100;all_ones = 9'b1~1111_1111;

outputinput [word size - 1:0]inputinputinput

- inputinput

SeriaLoutData_Bus;Byte_ready;Load_XMT_datareg;T_~e; .Clock;reseC;

reg [word_size - 1:0]reg [word_size:O]regreg [state_count - 1:0]reg [size_biCcountO]regregreg

XMT _datareg;XMT _shftreg;Load_XMT _shftreg;state, nexCstate;biCcount;clear;shift;start;

assign SeriaLout = XMT _shftreg[O];

/I Word + 1 extra bit

/I Serial output to data channel/I Host data bus containing data word/I Used by host to signal readyII Used by host to load the data register/I Usedby host to signal the start of transmissionII Bit clock of the transmitter

/I Resets internal registers, loads the/I XMT _shftreg with ones

I/Transmit Data Register/I Transmit Shift Register: {data, start bit}

/I Flag to load the XMT _shftreg \/I State machine controller/I Counts the bits that are transmitted/I Clears biC count after last bit is sentII Causes shift of data in XMT _shftreg/I Signals start of transmission

/I LSB of shift register

always @ (state or Byte_ready or biCcount or T_byte) begin: OutpuCand_next_stateLoad_XMT_shftreg = 0; .

clear = 0; -.shift = 0;start = 0;next_state = state;case (state)

idle:

waiting:

sending:

default:endcase

end

if (Byte_ready == 1) beginLoad_XMT_shftreg = 1;next_state = waiting;

end

if (T.:o:byte= = 1) beginstart ==1;neXCstate = sending;

end

if (bit_count!= word_size + 1)shift = 1;

else beginclear = 1;next_state = idle;

end

next_state = idle;

/

FIGURE 7-20 Verilog Description of the DART transmitter.

408 Advanced Digital Design with the Verilog HDL

always@ (posedge Clockor negedge reseU begin: State_Transitionsif (reseL == 0) state <= idle;else. state <= nexLstate; end

always @'(posedge Clockor negedgereseU begin: Registec Transfersif (reseL==0) begin .

XMT_shftreg<= all_ones;biLcount <= 0;

endelse begin

if (Load_XMT- datareg = = 1)XMT_datareg <= Data_Bus;

; ,

-I-

II Get the data bus'

if (Load_XMT_shftreg. == 1)XMT_shftreg <= {XMT_datareg, 1'b1};

if (start == 1)XMT_shftreg[O]<= 0;

/I Load shift reg,/I insert stop bit

/I Signal start of transmission

if (clear ="= 1) bit.count <= 0;else if (shift == 1) biLcount <= biLcount + 1;

if (shift == 1)XMT_shftreg <= {1'b1, XMT_shftreg[word_size:1]};

end "end

endmodule

II Shift right, fill with 1 's\

FlGURE 7.20 Continued

load_XI,ILdataregData-BusXMLdatareg[7:0]

---"'- a

ByteJeadyload-XMT_shflregXMT_shflreg[8:0]T_byte

I/ .

.,.~-eXninli:13¥fe9¥n fa .e

"

startshiftSerial_outclearblLcount(3:0]

nexLstate[2:0]state[2:0] ,

""

2"'2 waitin

FlGURE 7.21 Annotated simulation results for the 8-bit DART transmitter.

409 ,Design and Synthesis of Datapath Controllers

,

I

i

Load_XMT _dataregData_BusXMT_datareg[7:0]

ByteJeadyLoacLXMT_shftregXMT_Shftreg[8:0]XMT_shftreg[8]XMLshftreg[7)XMT_shftreg[6]XMT_shftreg[5]XMT_shftr~9[4]XMT_shftreg[3]XMT_shftreg[2]XMT_shftreg[l]XML5hftreg[O]T_byte

startshift

141

64a

14e X 1a7 Xld3TfeITTf4Y1fclTlfd X 1fe 1ft

FIGURE 7.22 'Data movement through XMT_shftreg.

-

state to change to waiting at the next active edge of Clock. The 9-blt XMT_shftreg isnow loaded with the value {a7h,1f= 1_°100_11112= 14fh. Note that the LSB ofXMT_shftreg is loaded with a 1.The machine remains in waiting until T_byte is assert-ed. The assertion of T_byteassertl'start."%e machine enters sending at the active edgeof Clq,ck immediately after the host processor's assertion of T_byte, and theLSB of XMT _shftreg is loadeg with, a 0. TheJ9-~it word in XMT _shftreg becomes1_°100 :11102= 14eh' The ° in the LSB signals the start of transmission. Figure 7-21 hasbeen annotated to showthe !J1ovementotdata through XMT_shftreg. Note thatls arefilled behind, as the word shifts to the right. At the active edge of the clock afterbiCcount reaches 9 (for an 8~bit word), clear asserts, biCcount is flushed, and the machine~~~~ ~ .. .

For diagnostic purposes,..the testl2ench includes a lO-bit shift register that receivesSeriaCout (by hierarchical dereferencing). The eight innermost bits of this register aredisplayed in Figure 7-21 as sencwofd[7: 0] (skipping the start-bit and the stop-bit) toreveal the correct transmissio~ of data, a7h.The bit sequence of SeriaCout likewise hasthis value. This is evident at the active edge of the clock after the assertion of clear. Themovement of datalhrougb~XMT_shftregis shown in Figure 7-22.