1/30/20151 The ARM Programmers Model Jacob Huerta, Ryan Crell,
and Veronica Hohe
Slide 2
Outline ARM Registers Von Neumann Cycle Sequence CPSR Memory
Standard ARM vs. Thumb ARM Instructions ARM Instructions Supervisor
Mode/Kernel Mode Exceptions 1/30/20152
Slide 3
ARM Registers 1/30/20153
Slide 4
4 ARM Registers Instruction set = operations to change system
state State = data items in processors visible registers/systems
memory Multiple invisible registers in a processor
Slide 5
1/30/20155 ARM Registers User-level programming 15 general
purpose registers PC CPSR System-level programming/exceptions
Remaining registers
Slide 6
Von Neumann Cycle Sequence 1/30/20156
Slide 7
Von Neumann Cycle Sequence 1/30/20157
Slide 8
CPSR 1/30/20158
Slide 9
9 ARM CPSR Control Bits Protected from user-level programs Mode
Control the processor mode Bits 0-4 (must be a valid mode) T
Control the instruction set State bit IF Enables control interrupt
Bit 6 is FIQ disable and Bit 7 is IRQ disable
Slide 10
1/30/201510 ARM CPSR Flag Bits Condition Code Flags NZCV N
(Negative flag) 0/1 = value is positive/negative Z (Zero flag) 0/1
= result is non-zero/zero C (Carry flag) 0/1 = extends for
shift/borrows for subtraction V (Overflow flag) 0/1 = no
overflow/overflow caused by last arithmetic operation
Slide 11
1/30/201511 ARM CPSR Unused Bits Unused bits Reserved State
preserved when changing the flag or control bits Should not be
altered by programs Should not rely on them when checking the PSR
status Might read as 1s or 0s in future processors
Slide 12
ARM Memory Organization 1/30/201512
Slide 13
1/30/201513 ARM Memory Organization View memory as linear array
of bytes numbered from 0 to 2 32 -1 Store data items in Byte (8
bits) Half-word (16 bits) Word (32 bits) Align words on 4 bytes
Organize in little-endian style
Slide 14
ARM Instructions 1/30/201514
Slide 15
ARM vs. THUMB Instructions ARM 32-bit instruction set 3-data
address instructions 16 general purpose registers THUMB 16-bit
instruction set 2-data address instructions 8 general purpose
registers Less regular instructions Higher code density High
performance 1/30/201515
Slide 16
ARM vs. THUMB Instructions Not a complete architecture Supports
ARM architecture The T bit in CPSR toggles the interpretation
1/30/201516
Slide 17
ARM vs. THUMB Instructions 1/30/201517
Slide 18
1/30/201518 ARM Instructions Load-store architecture Processes
only values stored in registers and instructions Performs
operations on these values Stores results in register Affects
memory using only load and store instructions Inability to perform
memory-to-memory operations Instructions Data processing: between
registers (add, sub, etc.) Data transfer: between registers and
memory (load, store) Control flow: execution of instructions
(branches, link, supervisor calls)
Slide 19
Supervisor Mode/Kernel Mode 1/30/201519
Slide 20
Supervisor Mode/Kernel Mode Kernel code Device drivers
Privileged code User program with IO access permissions
Unprivileged code User programs 1/30/201520 User with supervisor
privileges can use system calls to affect
Slide 21
Exceptions 1/30/201521
Slide 22
1/30/201522 Exceptions Normal execution is paused to handle
events like Systems calls Interrupts generated by external sources
Undefined instructions Traps
Slide 23
Exception Handling Save current state is Copy PC into register
rl4_exc Copy CPSR into register SPSR_exc Register r13_exc = pointer
to memory stack to store user registers Set processor operating
mode to exception mode 1/30/201523
Slide 24
Exception Handling Set PC to value between 0x00 and 0x1C
depending on exception type Restore user registers from memory
stack Restore (adjusted) PC and CPSR 1/30/201524
Slide 25
Input/Output (I/O) System 1/30/201525
Slide 26
Input/Output (I/O) System I/O peripheral Device mapped to
memory Device registers treated as memory locations by system Given
interrupt support (make interrupt requests) Normal interrupt (IRQ)
= most requests Fast interrupt (FIQ) = time-sensitive/critical
requests Direct Memory Access (DMA) External to ARM processor
Handles high-bandwidth I/O traffic 1/30/201526
Slide 27
References (2001). The Thumb Instruction Set. Web. 2001.
January 28, 2015. http://paulkilloran.com/arm/Lecture_7.pdf (2014).
About processor exceptions. ARM. Web.
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0471g/BABGCFHB.html.
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0471g/BABGCFHB.html
(2014). Exception handling process. ARM. Web.
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0471g/BABGCFHB.html.
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0471g/BABGCFHB.html
(2014). Load/store architecture. Wikipedia. Web. August 4, 2014.
http://en.wikipedia.org/wiki/Load/store_architecture.
http://en.wikipedia.org/wiki/Load/store_architecture (2014).
Protection ring. Wikipedia. Web. December 30, 2014.
http://en.wikipedia.org/wiki/Protection_ring.
http://en.wikipedia.org/wiki/Protection_ring (2014). Reserved bits.
ARM. Web. August 4, 2014.
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0229c/ch02s07s03.html
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0229c/ch02s07s03.html
(2014). Trap (computing). Wikipedia. Web. April 30, 2014.
http://en.wikipedia.org/wiki/Trap_(computing).
http://en.wikipedia.org/wiki/Trap_(computing) Furber, S. (2000).
ARM system-on-chip architecture. Harlow, England: Addison-Wesley.
(2014). Gibson, J. (2011). ARM assembly language: An Introduction
(2nd ed.). Lexington, KY: The Author. 1/30/201527
