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Cu 1 (2,5 im): cho on chng trnh vit bng VHDL sau:
a, Tm li v sa li bng cch vit li chng trnh
Cc li c lm ni bt thnh mu vng
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity RSFF is
port ( R;S;RST;CLK : in STD_LOGIC; -- Dng du phy ngn cch khai
bo cc chn vo/ra ch khng dng chm phy
Q : out STD_LOGIC; -- Khai bo cc chn vo/ra cui cng ca
entity khng dng chm phy y (tha du chm phy)
) -- Thiu du chm phy y
end RSFF;
--}} End of automatically maintained section
architecture RSFF of RSFF is
signal q0: std_logic;
begin
process (CLK,RST,R,S); -- Tha du chm phy y
variable RS:std_logic_vector (1 downto 0);
begin
RS
when "00"=>q0=>q0; -- Dng lnh gn bin
when "01"=>q0=>'1'; ; -- Dng lnh gn bin
when "10"=>q0=>'0'; -- Dng lnh gn bin
when others=>q0=>'X'; -- Dng lnh gn bin
end case;
end if; end if;
end process;
Q=q0; -- Dng lnh gn bin
begin
process (CLK,RST,R,S)
variable RS:std_logic_vector (1 downto 0);
begin
RS:=R&S;
if (RST=1) then
q0
Hnh 1: M hnh RSFF v bng s tht
Cu 2 (2,5 im): Vit m VHDL m t mch nh hnh bn di:
Hnh 2: Mch logic s
4
Chng trnh VHDL:
------------ Mo ta hoat dong cua component JKFF--------------
library ieee;
use ieee.std_logic_1164.all;
entity JKFF is
port (J, K,CLK,RST: in std_logic;
y,ynot : out std_logic
);
end JKFF;
architecture JKFF of JKFF is
signal state: std_logic;
begin
process(CLK, RST)
variable JK: std_logic_vector(1 downto 0);
begin
JK:=J&K;
if (RST='1') then
state
when "01" => state null;
end case;
end if;
end process;
y
port ( x,y: in std_logic;
z: out std_logic
);
end OR_2;
architecture OR_2 of OR_2 is
begin
z
port ( x,y: in std_logic;
z: out std_logic
);
end AND_2;
architecture AND_2 of AND_2 is
begin
z
component inverter -- Khai bo khi component cng NOT cp thp
port( x: in std_logic;
y: out std_logic
);
end component;
--------------cong OR_2----------------
component OR_2 -- Khai bo khi component cng OR_2 cp thp
port( x,y: in std_logic;
z: out std_logic
);
end component;
--------------cong NOR_2----------------
component NOR_2 -- Khai bo khi component cng NOR_2 cp thp
port( x,y: in std_logic;
z: out std_logic
);
end component;
--------------cong AND_2----------------
component AND_2 -- Khai bo khi component cng AND_2 cp thp
port( x,y: in std_logic;
z: out std_logic
);
end component;
signal S1,S2,S3,S4,S5,S6,S7,S8: std_logic; -- Khai bo cc tn hiu lu tr tm thi
cc gi tr trung gian (xem hnh bn di)
begin
Cong_not: inverter port map(x1,S1); -- Kt ni cc khi component cp thp li
vi nhau port_name => signal_name
Cong_OR : OR_2 port map(x2,S8,S2);
JKFF_1 : JKFF port map(S1,S2,CLK,RST,S3,S4);
Cong_NOR: NOR_2 port map(S1,S3,S5);
JKFF_2 : JKFF port map(S5,S6,CLK,RST,S7,S8);
Cong_AND: AND_2 port map(S7,S4,z);
end bai_2;
Hnh 3: Cc tn hiu tm (Temp) S0 S8
Cu 3 (5 im): V s chuyn trng thi, s khi, vit m t VHDL, cho
OTOMAT c nh vi mt u vo X v mt u ra Z hot ng theo yu cu sau:
- Z = 1 nu nh gp dy s vo l 0100- Z = 0 trong mi trng hp khc
Phn tch bi ton ( Phn ny khng vit vo bi thi, ch c hiu vn
dng lm nhng bi khc):
- Theo bi ra th y l thit k my trng thi hu hn FSM, y u ra Z ch ph
thuc vo trng thi hin ti nn l FSM kiu MOORE.
- Theo bi ra ta xy dng c bng trng thi ng ra theo ng vo:
Trng thi hin ti(pr_state)
Trng thi tip theo(nx_state) Ng ra
(Z)X = 0 X = 1S0 S1 S0 0S1 S1 S2 0S2 S3 S0 0S3 S4 S2 0S4 S1 S2 1
Trng thi S0 l trng thi ch 0 u tin.Trng thi S1 l trng thi c 0 v ch 1.Trng thi S2 l trng thi c 01 v ang ch 0 th 2.Trng thi S3 l trng thi c 010 v ch 0 th 3.Trng thi S4 l trng thi thu c chui 0100.
Phn bi lm (vit vo bi thi):- V s chuyn trng thi:
- S khi mch:
- Vit m VHDL m t mch:
--------------------------------------------------------------------- phat hien chuoi "0100" FSM VHDL-- by Khanh Hung, 08/06/2014--------------------Khai bao thu vien------------------------------library ieee;use ieee.std_logic_1164.all;--------------------Khai bao thuc the------------------------------entity FSM is
port ( X :in std_logic; -- Input X CLK :in std_logic; -- Input clock RST :in std_logic; -- Input reset
Z :out std_logic -- Output );end FSM;-------------------------------------------------------------------architecture FSM of FSM is
type state is (S0,S1,S2,S3,S4); -- Khai bo state l d liu kiu lit k cc trng
thisignal pr_state, nx_state: state; --Pr_state(trang thai hien tai), nx_state(trang thai
tiep theo)begin--------------------Phan mach tuan tu ben duoi---------------------
process(RST,CLK)begin
if (RST='1') thenpr_state
end if;when S2 => -- Khi trng thi hin ti l S2
Z
M Code
Bi 1
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity RSFF is
port ( R,S,RST,CLK : in STD_LOGIC;Q : out STD_LOGIC
);
end RSFF;
--}}
End of automatically maintained section
architecture RSFF of RSFF is
signal q0: std_logic;
begin
process (CLK,RST,R,S)
variable RS:std_logic_vector (1 downto 0);
begin
RS:=R&S;
if (RST='1') then
q0
when "00"=>q0q0q0q0
process(CLK, RST)
variable JK: std_logic_vector(1 downto 0);
begin
JK:=J&K;
if (RST='1') then
state
use ieee.std_logic_1164.all;
entity AND_2 is
port ( x,y: in std_logic;
z: out std_logic
);
end AND_2;
architecture AND_2 of AND_2 is
begin
z
y: out std_logic
);
end component;
---------------------------------------
component OR_2
port( x,y: in std_logic;
z: out std_logic
);
end component;
---------------------------------------
component NOR_2
port( x,y: in std_logic;
z: out std_logic
);
end component;
---------------------------------------
component AND_2
port( x,y: in std_logic;
z: out std_logic
);
end component;
---------------------------------------
signal S1,S2,S3,S4,S5,S6,S7,S8: std_logic;
begin
Cong_not: inverter port map(x1,S1);
Cong_OR : OR_2 port map(x2,S8,S2);
JKFF_1 : JKFF port map(S1,S2,CLK,RST,S3,S4);
Cong_NOR: NOR_2 port map(S1,S3,S5);
JKFF_2 : JKFF port map(S5,S6,CLK,RST,S7,S8);
Cong_AND: AND_2 port map(S7,S4,z);
end bai_2;
Cch 2
library ieee; -- khai bo th vin
use ieee.std_logic_1164.all;
entity bai_2 is
port ( x1,x2,CLK,RST: in std_logic; -- Khai bo cc chn vo
z: out std_logic -- Khai bo cc chn ra
);
end bai_2;
architecture bai_2 of bai_2 is
--------------khoi JKFF----------------
component JKFF is -- Khai bo khi component JKFF cp thp
port( J,K,CLK,RST: in std_logic;
y,ynot : out std_logic
);
end component;
--------------cong NOT----------------
component inverter is -- Khai bo khi component cng NOT cp thp
port( x: in std_logic;
y: out std_logic
);
end component;
--------------cong OR_2----------------
component OR_2 is -- Khai bo khi component cng OR_2 cp thp
port( x,y: in std_logic;
z: out std_logic
);
end component;
--------------cong NOR_2----------------
component NOR_2 is -- Khai bo khi component cng NOR_2 cp thp
port( x,y: in std_logic;
z: out std_logic
);
end component;
--------------cong AND_2----------------
component AND_2 is -- Khai bo khi component cng AND_2 cp thp
port( x,y: in std_logic;
z: out std_logic
);
end component;
signal S1,S2,S3,S4,S5,S6,S7,S8: std_logic; -- Khai bo cc tn hiu lu tr tm thi cc gi tr trung gian
begin
Cong_not: inverter port map(x1,S1); -- Kt ni cc khi component cp thp li vi nhau port_name => signal_name
Cong_OR : OR_2 port map(x2,S8,S2);
JKFF_1 : JKFF port map(S1,S2,CLK,RST,S3,S4);
Cong_NOR: NOR_2 port map(S1,S3,S5);
JKFF_2 : JKFF port map(S5,S6,CLK,RST,S7,S8);
Cong_AND: AND_2 port map(S7,S4,z);
end bai_2;
Bi 3
-------------------------------------------------------------------
-- phat hien chuoi "0100" FSM VHDL
--------------------Khai bao thu vien------------------------------
library ieee;
use ieee.std_logic_1164.all;
--------------------Khai bao thuc the------------------------------
entity FSM is
port (
X :in std_logic; -- Input X
CLK :in std_logic; -- Input clock
RST :in std_logic; -- Input reset
Z :out std_logic -- Output
);
end FSM;
-------------------------------------------------------------------
architecture FSM of FSM is
type state is (S0,S1,S2,S3,S4); -- Khai bo state l d liu kiu lit k cc trng thi
signal pr_state, nx_state: state; --Pr_state(trang thai hien tai), nx_state(trang thai tiep theo)
begin
--------------------Phan mach tuan tu ben duoi---------------------
process(RST,CLK)
begin
if (RST='1') then
pr_state
--------------------Phan mach to hop ben duoi----------------------
process(X,pr_state) -- Danh sch cm nhn l trng thi hin ti v u vo X
begin
case pr_state is -- Vi trng thi hin ti l:
when S0 => -- Khi trng thi hin ti l S0
Z
end if;
when S4 => -- Khi trng thi hin ti l S4
Z