12.2 Silicon Solar Cells

12.2.1. High Efficiency Crystalline Solar Cells

Fabrication of large area (5 inch X 5 inch) crystalline silicon solar cells (Dr. Saravanan):

Boron doped silicon wafers (p-type) of thickness 180±20 m with bulk resistivity of 0.5-3 cm and the carrier life time in the range of 0.6 – 1.9 s were used for fabricating silicon solar

cells. As per the conventional screen printed aluminum back surface field silicon solar cellprocess flow, first these wafers were subjected to the saw damage removal (SDR) and alkalitexturization processes by using the required composition of potassium hydroxide andisopropyl alcohol with deionized water. The scanning electron microscope and Zeta 3Dmicroscope studies on these wafers reveal that the texture is uniform with average pyramid

size and height of 2.6 and 2.3 respectively. The SEM images are as shown in Fig 1.

Fig. 1: Surface Morphology of the SDR and Textured Wafer

The textured wafers were cleaned by RCA cleaning processes to remove the organic andmetallic contaminants. Subsequently, the wafers were subjected to diffusion of phosphorus intube furnace using POCl3 as precursor. Sheet resistance of the deposited/diffused n layer isaround ~ 100 Ω/. The phosphosilicate glass (PSG) formed at the edges and also at thesurface of the silicon wafers, were removed by plasma edge isolation (PEI) and with 2% HFwash respectively. In order to make use of the maximum incident light and for the hydrogenpassivation, SiNx of thickness ~ 78 nm and refractive index ~ 1.96 was deposited byemploying plasma enhanced chemical vapour deposition (PECVD) technique. The backaluminum of about 850 mgm was deposited using conventional screen printing techniquefollowed by the drying of printed aluminum at 250 C around 4 minutes. Consequently thefront silver contacts were made with paste lay down of 105 mgms. The FC printed cells wereagain dried at 250 C around 4 minutes. The completed cells were cured by employing rapidthermal annealing process to realize the contacts. The temperature profile of rapid thermalannealing process was designed in such a way that the burn out and firing processeshappened in a single route. The burn out process was done in the temperature range of 300-400 C to drive out the organic binders and it was carried out in the nitrogen and oxygen

1

ambient. The firing process was carried out in the temperature range of 800-860 C so thatthe front silver contacts diffused through the silicon nitride layer and adheres to theunderlying silicon. The images of the completed cell are as shown in Fig. 2.

Fig. 2: Images of the completed solar cells.

The electrical characterization of the fabricated cells is underway. Further processoptimization will be carried out based on the characterization results.

Monocrystalline silicon solar cells on n-type substrates (Bandana Singha):

Previous work: Boron diffusion was optimized for sheet resistance values 55±5 Ω/sq andsolar cell was formed, without any optics improving techniques, with front side Al and backside Ti-Pd- Ag contacts. The obtained cell efficiency was >10% and PC1D simulatedefficiency of the same cell was 14%.Work carried during the reporting period: (TMAH and IPA) texturing was done prior to RCAcleaning to increase the absorption of incident radiation. In addition to that Al2O3 (10nm) andSiNx (60nm) respectively were deposited at the front side as passivating layer. Lift offlithography was done to make the front contact with evaporated Al, and Ti-Pd-Ag contactwas used to cover the whole back surface. The process flow diagram of the complete processis shown in Fig. 3.

2

Texturing with TMAH + IPARCA cleaningWet oxidationBack surface oxide removal and phosphorus n+ diffusion for BSFPSG removal and front side B- diffusion

Removal of BSG and BRLLift off for front contact formation with evaporated AlNative oxide removal from back with 2% HF and Ti-Pd- Ag deposition

IV characteri-zationAl2O3 (10nm) followed by SiNx(60nm) deposition at front

Fig. 3: Schematic of the process steps used in fabricating n- type c- Si solar cell with BSOD and boric acid diffusion (separately) at the front surface with Al2O3+SiNx front passivation.The illuminated IV of one of the solar cells for cell area 1.5cm x 1.5cm is shown in Fig. 4.

0.0 0.1 0.2 0.3 0.4 0.5

-0.10

-0.08

-0.06

-0.04

-0.02

0.00

0.02

0.04

Curr

ent (A

)

Voltage (V)

illuminated

Fig. 4: IV characteristics of the solar cell with textured surface (with TMAH+IPA solution)

and Al2O3 (10nm) + SiNx (60nm) front passivating layer

From the IV of the solar cell it can be concluded that the solar has significant shunt and needsimprovement.

Different output parameters of the cell are given below:

Isc: 23.71 mA

Jsc: 10.54 mA/cm2

Voc: 91.895 mV

3

Impp: 11.43 mA

Vmpp: 46.596 mV

Pmpp: 532.463 µW

Fill factor: 24.4 %

Efficiency: 0.2 %

Texturing (Mallikarjunachari):

Texturing the surfaces of silicon wafer is one of the most important ways of increasing theirefficiencies. The texturing process reduces the surface reflection loss through photontrapping, thereby increasing the short circuit current of the solar cell. The texturing ofcrystalline silicon was carried out using alkaline solutions. Such solutions resulted inanisotropic etching that leads to the formation of random pyramids. Before the texturingprocess was carried out, saw-damage etching was performed in order to remove the surfacedefects and damage caused by wire sawing.Temperature Effect: One of the most important parameter in texturing process is bathtemperature, its effect on the pyramid structure, uniformity of pyramids and reflectance. Thescheme of the experiment is that the concentration of the solution of NaOH and alcohol isfixed with changing bath Temperature at constant time; the optimum surface texturingconditions for mono crystalline silicon will be obtained by measurement of reflection andSEM.

Fig. 5(a) SEM images of textured samples by NaOH (2.5wt %) and IPA (8WT %)at different temperatures. (b) Reflectance curves of textured samples at different temperaturesand constant time 20minutes.

70oC60oC50oC

A80oC

4

In texturing process, rate of reaction and etching velocity are strongly dependent ontemperature of the solution. From figure1 at lower temperature 50oc, rate of reaction is verylow so pyramids are not formed. When bath temperature is increased from 50 oc to 70 oc, thepyramids becomes more uniform. Due to this uniformity of pyramids, surface reflectanceshows minimum valve at 70 oc.

Fig. 6: SEM images of textured samples at different temperatures with constant concentration(NaOH-1.5wt%, and time1minutes)

Fig. 5 shows the SEM images (at same magnification 10000X)of textured samples by usingNaOH (1.5wt %) and IPA(5wt%) at different temperatures 50 oC &60 oC. Textured sample at60 oC shows more uniform and lower pyramid sizes than textured sample at 80 oC, so thereflectance of textured samples at 60 oC shows minimum value.

Fig. 7(a): Reflectance curves of samples textured by NaOH (1.5wt %) solution and IPA (5wt%) at different temperatures. Fig. 7(b): Average Reflectance (400nm-1100nm) VsTemperature for different samples.

In fig. 7(b) highest average reflectance was found for textured samples at 50 oC &80 oC. Atlower temperature, average reflectance was very high due to low reaction rate. At 50oCtextured sample with small concentration of NaOH (1.5wt%) shows the average reflectancelow value than high concentration of NaOH (2.5wt%). At higher temperature also averagereflectance was very high for all textured samples due to very high reaction rate and etchingvelocity.

Al2O3 deposited by reactive sputtering for surface passivation (Meenakshi Bhaisare):

60oC 80oC

5

In this report we present the effect of deposition power density (PD) on the quality of p - typesilicon surface passivation by pulsed – DC (p - DC) reactive sputtered Aluminum oxide(AlOx) films. The high quality surface passivation is related to the activation of both fieldeffect and chemical passivation, i. e. high fixed oxide charges (Qf) in the dielectric and lowinterface state density (Dit). The process is carried out at PD in the range of 0.13 - 1.3 W cm-2.The films were subjected to post - deposition annealing (PDA) in N2 + O2 ambient in 79:21ratios to mimic dry air at 520 °C. Fig. 8(a) shows the deposition rate for different PD. The deposition rate increases withincrease in PD. High deposition rate ~ 5 nm. min-1 is observed at PD of 1.3 W. cm-2. A RI of1.6 is measured for all the films after annealing. Film thickness (tox) of 16 nm and 20 nm weremeasured for PD of 0.13 W. cm-2 and 1.3 W. cm-2 respectively.

Fig. 8: (a) Deposition rate for as - deposited films and (b) negative fixed oxide charges (Q f)and (c) interface state density (Dit) for as - deposited and annealed films at different PDconditions.

Fig. 8 (b) and (c) shows the extracted negative Qf from capacitance – voltage (CV) and Dit

from conductance - voltage (GV) measured plot, respectively. A consistent increase in Qf isobserved with increasing power for as - deposited films. The films show high negative Qf of 6× 1012 cm-2 after annealing. Almost similar values of negative Qf is observed for all the PDconditions. The Dit is independent of deposition power for both as - deposited and annealedsamples. The Dit decreases by an order of magnitude to about 2 × 1011 cm-2.eV-1 afterannealing. Fig. 9 (a) shows the measured τeff and Fig. 9 (b) shows the calculated value of Seff at the twoextreme PD of 0.13 and 1.3 W. cm-2 conditions, measured on p - type FZ wafers. AlOx filmsare deposited on both sides of the FZ wafers. We have used τbulk ~ 30 ms, which is the upperlimit of τbulk calculated using the generalized parameterization by Kerr et al. (J. Appl. Phys.,vol. 91, pp. 399, 2002).

6

Fig. 9(a) τeff and (b) Seff for different excess minority carrier concentration (∆n) measured onas-deposited and annealed films for PD of 0.13 and 1.3 W.cm-2.

A significant improvement in Seff is observed after annealing. Very low Seff of 30 cm. s-1 isobtained for AlOx film deposited at high PD of 1.3 W. cm-2, whereas at low PD of 0.13 W. cm-

2 the surface passivation degrades to Seff of 107 cm. s-1. We have observed an increase ineffective lifetime with increase in process power, while Zhang et al. (IEEE Journal ofPhotovoltaics, vol. 3, pp. 183-186, 2013) reported a contrary effect in the case of RFsputtered AlOx films. The Seff values are different at two PD conditions, in spite similarnegative Qf and Dit values after PDA as shown using electrical characterization. The onlydifference is the large distribution of Dit at low PD of 0.13 W. cm-2. Thus from the electricalcharacterization we were not be able to draw any conclusion for difference in Seff. In thisreport we have demonstrated that the process throughput in p-DC reactive sputtered of AlOx

can be increased without sacrificing the surface passivation quality.

Low Temperature Oxy-nitride for Surface Passivation of Silicon Solar Cells (Sandeep S S)

Impact of Addition of Ammonia to Plasma Oxidation Process:

The role of ammonia on the interface properties of the grown plasma oxide was studied.Silicon oxy-nitride film was grown at 320oC in an inductively coupled plasma chamber. Amixture of ammonia (NH3) and nitrous oxide (N2O) was used for the growth of the oxy-nitride. N2O flow was kept constant at 50 sccm, while ammonia flow was varied from 10 to50 sccm. The chamber pressure was kept at 25mT, while substrate power was kept at 10W.The evolution of plasma characteristics upon addition of ammonia was investigated usingoptical emission spectrograph, while chemical composition of the grown oxy-nitride wasstudied using FTIR measurements. Thickness measurements were carried out using anellipsometer. The electrical properties of the films were studied using MOS capacitorsfabricated on p-type silicon wafers, with aluminium as the gate electrode. The electricalproperties of the films were investigated before and after capping it with a silicon nitridelayer deposited in ICP-CVD. The electrical properties of the stack were also investigatedafter a 400oC anneal.

From the optical emission spectroscopy (OES) studies, as shown in fig. 10, it was observedthat the emission from the oxygen atomic lines at 777 nm and 844 nm corresponding to the

atomic transitions 3p5P – 3s5S and 3p3P – 3s3S respectively, the intensity of which camedown upon addition of ammonia. Additionally a H emission line could be seen at 656nm. The

7

study focussed on understanding the role of the atomic hydrogen on the surface passivationproperties of the as grown oxy-nitride film.

Fig. 10: Optical emission spectrum for N2O+NH3 mixture for varying NH3 flow rates.

From the ellipsometry measurements it was observed that the thickness of the as grown oxy-nitride came down upon introducing ammonia, as can be seen from fig 11. FTIRmeasurements revealed the presence of Si-O-Si stretching mode vibrations in the range of1065 cm-1 to 1107 cm-1. A trough corresponding to Si-Si unsaturated bonds was also observedat 640 cm-1. The intensity of the trough increased with an increase in ammonia flow rate.Additionally a broader trough was observed at 464cm-1. This trough corresponds to N-Hwagging mode vibrations. The broad trough may also indicate the presence of SiO4 phases at510cm-1.

Fig. 11: Ellipsometry data showing thicknessvariation with varying ammonia flow rate.

Fig. 12: FTIR spectra for the as grown oxy-nitride films with varying ammonia flow rate.

As can be seen from fig. 13, for the as grown oxy-nitride film, the interface state density (D it)decreases marginally with an increasing ammonia flow rate, but remains above 1012ev-1cm-2.Upon capping the same with silicon nitride film, Dit comes down less than 1012ev-1cm-2, butremains same for all ammonia flow rates. Upon annealing at 400oC, Dit decreases further, andminimal Dit is exhibited by the stack comprising oxy-nitride film grown at ammonia flow of50 sccm. This decrease in interface state density maybe due to the increased hydrogen contentwithin the as-grown film. However, Dit remained above 1011ev-1cm-2 for all cases. The high Dit

can be attributed to the surface damage that may have been caused by the higher substrate

8

power used during the growth of oxy-nitride. However, the fixed oxide charge densitydecreases from 1012cm-2 to ~5x1011cm-2 for the as grown oxy-nitride. Upon capping with asilicon nitride layer, it improves further to 1012cm-2, with no clear difference seen for varyingammonia flow rates. Qox increases marginally upon annealing, and the maximum value wasshown for the stack comprising oxy-nitride film grown using an ammonia flow rate of 50sccm, as shown in Fig. 13.

Fig. 13: Variation in Dit for (a) oxy-nitride (b) stack of oxy-nitride/silicon nitride (c) after annealingstack.

Fig. 14: Variation in Qox for (a) Oxy-nitride (b) stack of Oxy-nitride/Silicon nitride (c) after annealing stack.

From this set of experiments, it was observed, that addition of 50 sccm of ammonia duringthe oxy-nitride growth process can decrease the Dit, and improves the Qox, upon annealing at400oC. Further efforts are being directed at lowering the interface state density to the order of1010ev-1cm-2 . The effect of high temperature annealing (>800oC) is also being investigated.

Contact optimizaton (Karthick Murukesan, Shashwata Chattopadhyaya):

The experiments in this quarter were part of our effort to make solar cells from n type siliconbase. During this quarter, we continued work on TLM (transmission line model) basedmeasurements of Ohmic contacts to p-type silicon. Fair progress has been made. Weunderstood the reason behind poor results (contact resistivity and semiconductor sheetresistance values) reported in the previous quarter. It was a process step (oxygen plasma ashafter the lift off lithography prior to the evaporation of Al) which produced a thin oxide layer

9

and led to poor contact between Al and p type silicon. A brief etch in dilute HF removes theoxide layer and the contact quality improves. A typical measurement is shown in the Fig. 15.

Fig. 15: TLM measurements for contact resistivity of Al over Boron (P) doped emitters

The values obtained from the figure1 are as follows:Transfer length =6.5 micron; Rsh extracted from graph= 40 Ohm/square;Contact resistance (Rc) = 0.1274 ohm; Contact resistivity = 3.3 E-5 ohm-cm;Another important aspect is the quality of contact to p type emitter formed by diffusion ofboron into n type base. We have reported previously that a silicon boride layer is formedwhile diffusing boron into silicon. This boron rich layer (BRL) is impervious to HF and maynot be desirable for good contact to the p emitter. We are currently studying the methods ofremoval of BRL and corresponding effect on the contact resistance.

12.2.2. 3D Junctions (Student: Som Mondal):

Salient features:

The current research direction in this work is to estimate the junction depth using HF/HNO3solution due to differential etch mechanism in p and n-type surface.

Detailed progress report:

In the earlier stage of this work, an alternate characterization method based on wet chemicaletching has been used to estimate the junction depth formed after laser doping. The presentwork focuses on the analysis of defects introduced by the laser doping process. Lifetimemeasurement was done on bare and diffused samples before and after laser doping. Table 1

10

gives the different annealing conditions used for different types of samples. Fig. 16consolidates the data of lifetime before and after laser process on a bare p-type wafer. Thedata is given for laser processed side as well as of the rear side.

Table 1: Condition used for studying the effect of laser annealing

Condition Tag Effect

Scan speed=40mm/s, Duty = 24% A Low

Scan speed=5mm/s, Duty = 24% B Medium

Scan speed=40mm/s, Duty = 25% C Medium

Scan speed=5mm/s, Duty = 24% D High

Fig. 16: Lifetime degradation after annealing with different condition. All values are taken atminority carrier density of 1 x 1014 cm3.

Fig. 17: Lifetime degradation after laser doping with different condition on P diffusedsamples. All values are taken at micority carrier density of 1 x 1014 cm3.

Fig. 17 depicts the lifetime change in P diffused samples before and after laser doping. Afterlaser annealing on bare p-type substrate, the lifetime on both laser processed side and on rearside degrades. Hence it is expected that laser processing has incorporated some defects in thesubstrate. However, as presented in Fig. 17, the lifetime of both laser processed side and back

11

side improves significantly on diffused samples. This result is not fully understood andfurther experiments will be carried out to understand such change in lifetime.

12.2.3. Novel technology for contact formation using temperature sensitive paste (Sastry):

Objective:

To open ARC selectively using chemical etching paste in finger- bus bar grid pattern. The finger width should be less than 100 µm and should process industrial solar cells.

Experimental:

To remove ARC, chemical etching method by electro-discharge machine (EDM) wire ispreformed on half-finished solar cells. Finger opening width of 47 µm mare achieved using a30 µm and 87 µm are achieved using a 50 µm EDM wires. Since the EDM wire patterning manual method has limitations in continuity and finer fingerwidths, the experimental procedure is slightly modified. The experiment is conducted on a3d- stage. Using 50 µm EDM wires, variation range started from 70-200 µm (opening of afinger) and 50-150 in the case of 30 µm wire with the 3d- stage. These are the results from 3dstage experiments.

Fig. 18: 3d stage and cell holder

Experiment:Using the EDM wires, a set up has been made for patterning. The wire is fixed between theacrylic discs to create sufficient tension. This is fixed to the 3d stage so that to move in zdirection (up and down). Single fingers are patterned on the solar cells. The experiment isdesigned for 60, 80 and 100 µm wires.

To obtain full potential of this method, alternatively screen print of etch paste is suggested.Screen count with 60, 80 and 100 µm are planned. Same etching paste is used for thismethod. Screen with different mesh counts (60 – 100 µm) for the solar cell size 4 x 4 sq. Cm

12

were made. The screens are placed under the screen printer. Once the etch paste is kept on thescreen at screen printer, the printing job is done. Using flood and squeeze, the etch paste istransferred to the solar cell placed under the screen. Etch paste printed solar cells are heatedto 3900 C – 90 s at hot oven. At this temperature, the etch paste will remove anti reflectivecoatings on the solar cell. The chemical residues are cleaned with DI water. The experiment is repeted with three different screens (60, 80 & 100 µm). For each screen,the grid design is optimized.

Future work: EDM wire using 3d stage with single fingers are metalized using two steps- Ni and

Cu. The experiment is repeated with 40, 60, 80 µm EDM wires. With bus bar design, the

metallization is done for obtaining I-V Characteristics. Screen printed with etch paste solar cells are also processed for metallization – two

step Ni & Cu and characterized. These two steps are compared with standard solar cell of same size (commercial silver

paste- solar cell).

12.2.4 Ni/Cu metallization for front contact (Mehul Raval):

Salient Features: Characterization of contact resistivity (ρc) variation and silicide formationfor different annealing conditions for Ni seed layer in Ni-Cu based contacts.Deatiled progress Report: Deposition of Ni seed layer of 50-100nm thickness with TLMsamples fabrication for ρc measurements and cross-sectional studies for observing silicideformation.Electroless Ni alkaline bath was used for Ni deposition. Typically for an alkaline bath, a highbath temperature is required and hence bath temperature was maintained in the range of 90-95°C. Plating time intervals were in the range of 30-45s to obtain thickness in the range of50-100nm. Constant bath pH was maintained during the experiments by addition ofammonium hydroxide (NH4OH). Temperature and pH were constantly monitored during theplating process.Samples with 50nm and 100nm Ni seed layer were annealed at 500°C and 550°C respectivelyfor 30s to 90s. Contact Resistivity measurements were done using the conventional TLMapproach. Current of 20 mA was maintained during the measurements. A set of 3 to 5 sampleswere fabricated for each specific annealing condition. For observing silicide formation,samples with Ni deposited on textured Si (100) were prepared for SEM measurements.Fig. 19 and 20 show ρc data for Ni seed layer annealed at different conditions. A minimumvalue of 4.58 mΩ-cm2 was obtained for a 50nm Ni seed layer, while 2.76 mΩ-cm2 wasobtained for annealing at 550°C.Silicide formation for different conditions as observed are represented in Fig. 21 and 22. Itcan be observed that silicide formation is pretty uniform for both cases, though towards thebottom of pyramids, silicidation seems to have not taken place in either case. It can beinferred that along with a low ρc , the respective annealing conditions lead to a uniformsilicide formation which is suitable from metallization perspective.

13

Fig. 19: Contact Resistivity variation for 50nm Ni seed layer with different annealingconditions.

Fig. 20: Contact Resistivity variation for 100nm Ni seed layer with different annealing conditions

14

Fig. 21: Silicide formation for 50nm Ni seed layer annealed at 500°C for 90s.

Fig. 22: Silicide formation for 100nm Ni seed layer annealed at 550°C for 90s.

12.2.6. Plasmonics for Photovoltaic Application (Hemant Kumar Singh):

In the process of optimizing (minimization) the reflectance from the front surface we areexploring the plasmonics technology by using silver nanoparticles on the front of thesubstrate in order to utilize the plasmonics assisted enhanced forward scattering. We explored

15

initially many device structure suitable for such condition and then we started theoptimization of nanoparticles fabrication. In this report we present some of the goodexperimental results by adding one more optimization i.e. space layers thickness. For this, wedid series of experiments for various spacer layer thickness and different recipes optimizedfor nanoparticles fabrication. Fig. 23 shows some of the images of the surface of varioussamples after silicon nitride (SiNx) deposition and subsequent silver nanoparticles (AgNP)fabricated on it. Fig. 23 (b), (d) closely shows the plasmonics effect of AgNP on samples asgiving changed reflecting colour from samples. It can be noticed that only 60 nm of SiNx isequivalent to 80 nm of SiNx if AgNP is fabricated on it. Fig. 24 shows the measured totalreflectance of such samples. Table 2 shows the corresponding weighted reflectance for thesesamples weighed with respect to AM 1.5 G spectrum. It can be clearly seen that sampleSi/SiNx(60nm)/AgNP gives better weighted reflectance than Si/SiNx (60nm) and even betterthan Si/SiNx(80nm) which is generally used as standard ARC thickness. Also it can be notedthat there is trade off between optimizing the reflectance for visible and IR wavelengthregion. Minimizing the reflection in IR region results in higher reflection in visiblewavelength region and vice versa. Fig. 25 shows the SEM images and the particle size andshape distribution obtained by image processing of the SEM images of these samples. It canbe seen that the average particle size is 60 nm-80 nm for both but much better shapeanisotropy is seen for nanoparticles for the later. Table 3 shows the surface coverage andaverage shape anisotropy for these samples.

Fig. 23: Zeta microscope image of sample surface for different samples (a). SiNx (60nm) deposited on Si, (b). AgNP fabricated on Si/SiNx (60nm), (c). SiNx (80nm) deposited on Si, (d). AgNP fabricated on Si/SiNx (80nm).

Fig. 24: Total reflectance measured of various samples discussed here.

16

From above results, we can see that we are able to minimize the reflection from plasmonicsbased samples as compared to standard 80 nm silicon nitride based samples (Si/SiNx (80nm))by varying the recipes for NP formation and spacer layer thickness. In this report, we haveshown the weighed total reflectance better than standard 80 nm antireflection coating (siliconnitride) based samples. However, as we are still getting the higher reflection in visiblewavelength region for which experiments are going on to improve it further.

17

Table 2: Weighed total and specular reflectance for these samples

Sample Name

Weighted Total Reflectance(with respect to AM 1.5 G)

WeightedSpecular

Reflectance

300nmto

1200 nm

300nmto

700 nm

700nmto

1200 nm

300nmto

1200 nm

Si 42.55 % 45.49 % 38.67 % 41.63 %

Si/SiNx(60nm) 14.73 % 9.31 % 21.88 % 13.67 %

Si/SiNx(80nm) 13.75 % 13.04 % 14.65 % 12.60 %

Si/SiNx(60nm) /AgNP

(ID:1NPFab-1)

12.90 % 12.13 % 13.88 % 8.79 %

Si/SiNx(80nm)/AgNP

(ID: 1NPFab-2)

21.23 % 31.94 % 7.03 % 19.34 %

Fig. 25: SEM image of Si/SiNx(60nm)/AgNP (inset shows the processed image), (b). Particledistribution of AgNPs of Si/SiNx(60nm)/AgNP sample (inset shows the shape anisotropy ofnanoparticles. (c). SEM image of Si/SiNx(80nm)/AgNP (inset shows the processed image),(d). Particle distribution of AgNPs of Si/SiNx(80nm)/AgNP sample (inset shows the shapeanisotropy of nanoparticles).

Table 3: Image J analysed results for above samples

12.2.7 Slicing of silicon wafers for PV applications using Wire Electric Discharge Machining (We-EDM) (G. Dongre, Kamesh Joshi, Gaurav Sharma):

Modeling of wire-EDM slicing process for Silicon ingots

Salient features: Literature review suggests that the so much work has been done to modelsilicon ingot slicing by EDM but in case of wire-EDM, there are not so many models. Even ifthere are, they have mainly modeled the wire, not the ingot. Plasma features, pulse timings,multi-discharges phenomena haven’t been taken into account into a single model. Fractions

18

of total energy going to plasma, wire and work-piece have been assumed in all the models,they have not calculated any fraction.

Detail report (Report is based on the modeling and simulation work carried in this quarter):In this work, a mathematical model has been developed using dielectric properties, heattransfer equations, ingot material properties, and steady state heat source characteristics topredict temperature profile, crater radius and erosion rate for the work-piece in wire-EDMprocess and its dependence on voltage, current, wire diameter and ‘pulse on-time’ has beenshown. Parts of total energy getting transferred to wire, work-piece and plasma have beencalculated through heat transfer equations and some concepts of quantum physics (see Fig.26).

Fig. 26: Approach to the model

Single discharge model for EDM process

The single discharge model obtained in this work has been validated by performing singledischarge experiments on steel work-pieces. The Fig. 27 shows the SEM micro-micrographsfor single discharge on steel workpiece. The single discharge model has been extended toevaluate the cathode and anode energy partitioning in a steady-state multi-discharge wire-EDM process. The erosion rate obtained using the model has been compared withexperimental values. The erosion rate obtained using the model is always greater thanexperimental values (see Fig. 28). However, with a consideration of ‘plasma flushingefficiency’, corrected erosion rate matched well with experimental values.

Fig. 27: SEM micro-graphs for single discharge model

19

Fig. 28: Experimental validation of single discharge model

Multiple discharge model for wire-EDM of silicon ingot slicing

For multi-discharge model same equations were used but no. of sparks along the wire lengthwere also considered. Using cluster model for sparks and also considering ‘field enhancementfactor’, wire was divided into 16 parts so that 2D temperature profile for work-piece wasobtained which gave temperature profile, crater depth and erosion rate for each part. As thevoltage, current and ‘pulse-on time’ increase individually (keeping other parametersconstant), both plasma temperature and interface temperature increase. Power input to thewire increases with increase in all these parameters which increase energy generated inplasma so plasma temperature increases. Energy is getting transferred from plasma to work-piece through radiation and particle bombardment so due to increase in plasma energyinterface temperature will also increase. Plasma temperature is always more than interfacetemperature in all the cases, as only a part of plasma energy is getting transferred to work-piece. Also, the gradient of ‘plasma temperature’ graph is much higher than that of ‘interfacetemperature’ graph. This is because ions and electrons properties don’t increase significantlywith plasma temperature to give very large change in interface temperature. Crater depth isthe depth of the circular contour having temperature equals to 1783 K, so only the volumehaving depth equal to crater depth will get eroded. After getting the temperature profile ofwork-piece, crater depth can easily be found out. In multi-discharge model, crater depth willbe different for all the parts of work-piece and will decrease from top to bottom. Erosion ratecan be determined by considering the volume removed in unit cycle time ( T on+T off ¿ . Inmulti-discharge model, erosion rate will be different for all the parts of work-piece and willdecrease from top to bottom. With respect to voltage, current, ‘pulse on-time’ and wirediameter, erosion rate will have same trends as crater depth as it is directly proportional tosquare of crater depth.In this section, multiple discharge modeling will be considered for wire-EDM process withMolybdenum as wire and silicon as work-piece. Banerjee and Prasad say that the sparks areproduced on the wire in clusters. Kildemoe et al. say that the number of sparks at differentlocation on the wire depend on the field enhancement factor ( β ) of the wire at differentlocation, which is dependent on micro-peak radius and inter electrode gap according toEquation below, so the value of β will be different at different locations. In this model, asmolybdenum wire has been considered, value of micro-peak radius can be assumed to be a

20

constant (0.23 μm ) throughout the wire. For the gap of 10 μm, the value of β comesout to be 44.50.

_

(1 / )

dgeometric

a a d

From Fig 4, for β = 44.50, taking maximum value for no. of sparks no. of sparks i.e. 90.At the top of the wire, the no. of sparks will be maximum and will decrease along the wirelength from top to bottom. Energy of each spark will be assumed same as each spark willhave same plasma radius. In Fig. 29(b), the number of sparks at the top of the wire has beentaken 20 % more than the bottom. The wire of length 75 mm has been divided in 16 parts oflength 4.7 mm each. At the bottom the number of sparks has been taken as the average valueof sparks, which are 75 and at the top, number of sparks are 90. Now the modeling of multispark wire EDM process will be done.

Fig. 29: (a) Relation between β and number of sparks (b) Number of sparks along the wirelength (from the top).

As the wire has been divided in 16 parts of 4.7 mm each, different crater radius and depthswill occur. Interface Temperature will decrease down the length of wire. So crate radius/depthwill also decrease. Total erosion rate will be sum of erosion rates of all the 16 parts. Hereerosion rate has been considered in (mm2 /min). ER (i )=π r ( i)1687

2/(T on+T off )

Total ER = ∑i=1

16

ER

Multi discharge model has been verified with experiments done on wire-EDM machine withsilicon as ingot and molybdenum as wire. The value of crater depth for model andexperiments is comparable but erosion rate for model is higher than experiments. It is due tore-deposition of some part of eroded material on the work-piece. So net eroded materialbecomes lesser and experimental value of erosion rate becomes smaller than theoretical one.Plasma Flushing Efficiency is considered which is ratio of experimental erosion rate andtheoretical erosion rate. It gives a general idea of ability of plasma channel for ejecting themolten material from melted ingot. Corrected erosion rate which is PFE times model erosionrate, matched well with experimental values (see Fig. 30).

21

Fig. 30: Experimental validation of multi-discharge model

Concluding remarks

In wire-EDM, breakdown of liquid dielectric leads to the formation of a plasmachannel between the electrodes. In case of anode and cathode the contribution ofparticle bombardment to the heat transfer by plasma is comparable with that ofradiation.

As the voltage, current and ‘pulse on-time’ increase (keeping other parametersconstant), plasma temperature and interface temperature increase.

Crater radius will increase with increase in voltage, current and ‘pulse on-time’. Byincreasing wire diameter (keeping other parameters constant), interface temperaturedecreases. Consequently crater radius decreases.

Erosion rate will increase with increase in voltage, current and ‘pulse on-time’. Withincrease in wire diameter, crater radius will decrease so erosion rate will decrease.

Due to re-deposition of some part of eroded material on the ingot, experimental valueof erosion rate becomes smaller than theoretical one.

22