120W Dual-Stage Matrix Compatible Automotive Headlight …

TPS92682-Q1

2 Phase Boost

Controller

Transient

ProtectionEMI Filter

TPS92520-Q1

Dual Synchronous

Buck Current

Regulator

TPS92520-Q1

Dual Synchronous

Buck Current

Regulator

GND

MSP432E401Y

Micro Controller

TPS57060 + LM26420

5V and 3V3 Supplies

VBOOST

SP

I

UARTCAN

Battery

TPS9266EVM6-900

TCAN1042

CAN Transciever

TCAN1042

CAN Transciever

TPS92662-Q1

TPS92662-Q1

TPS92662-Q1

TPS92662-Q1

GNDTCAN1042

CAN Transciever

MASTER

CAN

TIDA-050030

GND

1TIDUEU1A–October 2019–Revised November 2019Submit Documentation Feedback

Copyright © 2019, Texas Instruments Incorporated

120W Dual-Stage Matrix Compatible Automotive Headlight ECU ReferenceDesign

Design Guide: TIDA-050030120W Dual-Stage Matrix Compatible Automotive HeadlightECU Reference Design

DescriptionThis reference design details a headlight ECU usingan interleaved boost in voltage regulation modefeeding four synchronous buck channels. This designis also capable of matrix headlight control and ismounted to a heatsink and enclosed to emulate anautomotive headlight ECU.

The TPS92682-Q1 is setup as a two phase interleavedboost controller set in voltage regulation mode capableof 130W output power. The boost output drives twoTPS92520-Q1 dual channel synchronous buck driversfor a total of four buck channels at 120W total output.The design is mounted to a heatsink and enclosed toemulate an automotive headlight ECU. A MSP432processor controls the TPS92682-Q1 and the twoTPS92520-Q1 devices by the SPI interface. TheMSP432 communicates to the master via CAN andalso communicates to the lighting matrix module usingUART communications via a CAN transceiver.

Several bench-test results are available for the designincluding an efficiency data, thermal measurements,pixel-controlled load data, and EMC measurementsaccording to the CISPR 25 Class 5 conductedspecification.

Resources

TIDA-050030 Design FolderTSP92682-Q1 Product FolderTPS92520-Q1 Product Folder

Search Our E2E™ support forums

Features• Interleaved voltage output boost using one

TPS92682• Four synchronous-buck channels capable of pixel

controlled loads using two TPS92520s• Supports dynamic loads, matrix controllers for LED

pixel control• Buck channels capable for 1.5A maximum, 55W

limited to a total of 120W• 9 V to 24 V full power operating range, power de-

rate down to 6V inputs• Fully enclosed headlight ECU example CISPR 25

Class 5 conducted test data from 0.15 to 108 MHz.• Reverse battery protection circuit included in this

reference design

Applications• Automotive Lighting:

– Dynamic and static headlights– Rear light

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http://www.ti.com/product/TPS92682-Q1


http://www.ti.com/tool/TIDA-050030



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http://e2e.ti.com/support/applications/ti_designs/

http://www.ti.com/applications/automotive/body-lighting/overview.html

http://www.ti.com/solution/automotive-headlight

http://www.ti.com/solution/automotive-rear-light

System Description www.ti.com

2 TIDUEU1A–October 2019–Revised November 2019Submit Documentation Feedback



An IMPORTANT NOTICE at the end of this TI reference design addresses authorized use, intellectual property matters and otherimportant disclaimers and information.

1 System DescriptionThis reference design demonstrates a self-contained headlight ECU with four output channels that can bepixel controlled for a complete headlight solution including low beam, high beam, turn, and DRL (daytimerunning lights). The design is a two stage boost into multiple buck configuration. The boost, using oneTPS92682 in voltage regulation mode, is an interleaved 130W output with adjustable voltage output. Thefour-buck outputs are delivered by two dual-channel TPS92520 synchronous buck converters. The systemcan operate during cold crank and load dump conditions when the battery voltage varies. A two-stageECU is needed due to the dynamic nature of a matrix load where the LED current regulation is done by alow output capacitor topology such as a buck at the second stage, and the wide input voltage variability ofan automotive battery system requires a boost first stage to ensure a consistent input voltage for the bucksecond stage. The buck converter outputs are capable of pixel control using TPS9266x lighting matrixmanager devices.

The reference design also includes reverse battery protection, bias supplies, a heat sinking enclosure, anda MSP432 micro controller with self-contained software enabling a headlight ECU with CAN interface.

This reference design considers the following as part of the design requirements:• Each channel capable of 55W max, total for all channels is 120W• Each channel capable of 1.5-A LED current maximum• Operation during cold cranking, warm crank, power is derated• Tested via SPI communications, self-contained ECU via CAN communications• Enclosure and heatsink to provide EMC and thermal test data• Reverse battery connection protection

1.1 Key System Specifications

Table 1. Key System Specifications

PARAMETER TEST CONDITIONS MIN TYP MAX UNITINPUT CHARACTERISTICSInput voltage range of operating

DC (continuous) Full output power 9 13 24 V

Input voltage range of operatingDC (power derated) Power de-rated which covers cold and warm crank conditions 6 - 44 V

OUTPUT CHARACTERISTICSInterleaved Boost output Output power at Vout = 50V 130 W

Maximum string length perchannel LEDs at forward voltage of 3V 14

VLED output voltage 4 42 VILED output current 1.5 ABucks Output power 120 W

SYSTEM CHARACTERISTICSfSW switching frequency -

Boost400 kHz

fSW switching frequency - Buck 400 kHz

Total System Efficiency@ 5 LEDs 86 %@10 LEDs 89 %

EMI (conducted)BASE BOARD CHARACTERISTICS

PCB Form Factor 3.610" (W) x 4.280" (L) x 0.062" (T) - - in.ECU Fort Factor 4.5" (W) x 5.0" (L) x 1.425" (T) in.

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Output Power (W)

Eff

icie

ncy (

%)

10 20 30 40 50 60 70 80 90 100 110 12074%

76%

78%

80%

82%

84%

86%

88%

90%

92%

94%

10 LED5 LED

www.ti.com System Description




Table 1. Key System Specifications (continued)PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Number of layers and Stackup Layer 1:1 oz. cu., Layer 2:2 oz. cu., Layer 3:2 oz. cu., Layer 4:2 oz.cu., Layer 5:2 oz. cu., Layer 5:and 1 oz. cu.

- 6 - Layers

Figure 1. Output Power vs. Efficiency at VIN = 13 V

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TPS92682-Q1

2 Phase Boost

Controller

Transient

ProtectionEMI Filter

TPS92520-Q1

Dual Synchronous

Buck Current

Regulator

TPS92520-Q1

Dual Synchronous

Buck Current

Regulator

GND

MSP432E401Y

Micro Controller

TPS57060 + LM26420

5V and 3V3 Supplies

VBOOST

SP

I

UARTCAN

Battery

TPS9266EVM6-900

TCAN1042

CAN Transciever

TCAN1042

CAN Transciever

TPS92662-Q1

TPS92662-Q1

TPS92662-Q1

TPS92662-Q1

GNDTCAN1042

CAN Transciever

MASTER

CAN

TIDA-050030

GND

System Overview www.ti.com




2 System Overview

2.1 Block Diagram

Figure 2. Block Diagram of TIDA-01520

2.2 Design ConsiderationsThis reference design implements a high density, high efficiency, two stage boost into multiple buck LEDdrivers that supports four channels into a LED matrix manager with a total of 120 watts of output power.The design was implemented considering the following automotive requirements and design goals:• Small form factor that is approximately a 100 cm2 with high power density• Enclosure to provide EMC shielding and heat sinking for thermal dissipation• Reverse battery connection protection• Operation during cold cranking, warm crank, power is derated• Each channel capable of 55W max, total for all channels is 120W• Each channel capable of 1.5-A LED current maximum• CISPER25 Class 5 compliant

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2.3 Highlighted Products

2.3.1 TPS92682-Q1The TPS92682-Q1 is a dual-channel, peak current-mode controller with SPI communication interface. Thedevice is programmable to operate in constant-voltage (CV) or constant-current (CC) modes. In CV mode,TPS92682-Q1 can be programmed to operate as two independent or dual-phase Boost voltage regulators.The output voltage can be programmed using an external resistor voltage divider, and a SPI-programmable 8-bit DAC.

In CC mode, the device is designed to support dual channel step-up or step-down LED driver topologies.LED current can be independently modulated using analog or PWM dimming techniques. Analog dimmingwith over 28:1 range is obtained using a programmable 8-bit DAC. PWM dimming of LED current isachieved either by directly modulating the PWM input pins with the desired duty cycle, or using a SPI-programmable 10-bit PWM counter. The optional PDRV gate driver output can be used to drive anexternal P-Channel series MOSFET.

The TPS92682-Q1 incorporates an advanced SPI-programmable diagnostic and fault protectionmechanism including: cycle-by-cycle current limit, output overvoltage and undervoltage protection, LEDovercurrent protection, and thermal warning. The device also includes an open-drain fault indicator outputper channel.

The TPS92682-Q1 includes an LH pin, when pulled high, initiates the limp home (LH) condition. In LHmode, the device uses a separate set of SPI-programmed registers.

Figure 3 shows the functional block diagram of the TPS92682-Q1 boost controller. The TPS92682-Q1 isused in constant-voltage (CV) mode for the design of this headlight ECU reference design.

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S

R

Q GATE1

PGND

OSCILLATOR Clk_M

Slope Gen. &

MAX Duty

CHx_Islope

PWM1

+±CH1_UV FB1/OV1

+

±

CH1_VFB

CH1_Isense

CH1_CV

CSP1

CSN1

COMP1

CH2_comp

2PH

DAC

SS1

x14 0

1

OC/UC

SENSE

(150%/50%)

CH1_OC

CH1_UC

PDRV1

CSP1

PWM1

RT

DAC

Dither

FMDAC

RT_Open

CH1_PD_comp

R

Dominant

CH1_EN

7.5V LDO

5V LDO

VIN

EN

VCC

VDD

EN

+

±

CH1_complow100mV

CH

1_

FB

O_

EN

10Ps

Filter

DAC1

IADJ

PWM1

0

1

0

1

CH1_MAXD_EN

CH1_Clk100p

CH1_Clk100p

CH1_Clk10p

CH1_MAXD

CH1_s

CH1_s

CH1&2_Clk100p

CH1&2_Clk10p

SYNC

CH1_HG

POR

+

±

50mV

CH1_OV

DAC

OV0

1

0

1

1.23V

ref

CH1_CV

VDD

CH1_OV_EN

VDD

CH1_EAref

+

±

ISP1

ISN1

CH1_ILIMIT

CH1_Islope

CH1_LBSEL

CH1_Gate

VDD

CH1ILIM20PA

CH1_FILT1

VDD

+

±

CH1_comp

CH1_Gate

CH1_IS_OPEN

CH1_Duty

INT_PWM

0

1

S

R QR

DominantCH1_Duty

CH1_PWM_O

PWM1PWM1

CH1_EAref

CH1_VFB

SYNC_EN

1

0

FLT1

SYNC/FLT2 SYNC

CH1_EA_FB

CH1&2_ISLP

CH1_OVDAC

CH1_SSDAC

CH1&2_DIV

CH1&2_CLK

CH1_nPDRV

CH1_FAULT

CH2_FAULT

UVLOUVLO

Thermal

Limit

TSDPOR

POR

TW

100%

10%

Clk10p

Clk100p

Power_FLT

Power_FLT

Power_FLT

CH1_close_comp

TSD

BG_NOK

UVLO

POR

Power_FLT

CH1_comp

5Ps

Delay

CH1_PD_O

CH1_PD_O

Dither_EN

RT OPEN

CH1_MAXD

LEB

CH1_close_comp_n

CH1_close_comp_n

CH1_close_comp

CH1_close_comp

CH1_close_comp

CH1_close_comp

CH1_IADJ

+

±

gM





Figure 3. Functional Block Diagram of TPS92682-Q1 Boost Controller

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2.3.2 TPS92520-Q1The high-performance LED driver can independently modulate LED current using both analog or PWMdimming techniques. The TPS92520-Q1 is a dual synchronous monolithic device that incorporates fourMOSFETs into a high density package that provides superior thermal performance. Linear analogdimming response with over 20:1 range is obtained by programming the 10-bit IADJ value via SPI. PWMdimming of LED current is achieved by directly modulating the corresponding UDIM input pin with thedesired duty cycle or by enabling the internal PWM generator circuit. The PWM generator translates the10-bit PWM register value to a corresponding duty cycle by comparing it to an internal digital counter.

The TPS92520-Q1 incorporates an advanced SPI programmable diagnostic and fault protection featuring:cycle-by-cycle switch current limit, BOOT undervoltage, LED open, LED short, thermal warning andthermal shutdown. An on-board 10-bit ADC samples critical input parameters required for system healthmonitoring and diagnostics.

The TPS92520-Q1 is available in 6.2 mm x 11 mm thermally enhanced 32-pin HTSSOP package with a3.86mm x 3.9 mm top exposed pad.

Figure 4 shows a block diagram of the TPS92520-Q1 buck LED driver.

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V5D

UVLO

Rising: 4.1 V

Falling: 4.0 V

Hys: 100 mV

BandgapVBG

BST1

LEB

Control

and

Switch

Fault

Logic

VIN1

SW1

PGND

DAC

IADJ1

UDIM1

V5A

+

VBG pwm1

+

+±

3 V

CSP1

CSN1

COMP1

VIN1

ADC

iadj1

ton1

MISO

MOSI

SCK

SSN

10MHz

Oscillator

clk_m

V5A

GND

2VBG

Digital Supply

V5A

LHIVLHI

+

Thermal

Sensor

adc_sel

adcout

Current

Limit

Circuit

LEB

Current

Limit

Circuit

ch1_en

Analog Supply

2VBG

VIADJ1

VCSN1

Valley Current

Control

udim1

Digital Logic

5 V

Logic

IO

bstuv1

lsilim1

hsilim1

Channel 1

V5D

On Time

Control

BST2

VIN2

SW2

PGND

CSP2

CSN2

COMP2DAC

IADJ2

iadj2

ch2_en

udim2

bstuv2

lsilim2

hsilim2

VIN1

Sleep Enable

ton1

Channel 2

ton2

toffmin1

toffmin1

toffmin2

ch1_en

bstuv1

lsilim1

hsilim1

VIADJ2

por

uvlo

open1

short1VIN1

VIN2

VCSN1

VCSN2

V5D

VLHI

VTMP

LED Fault

Detection

open2

short2open1

short1

open2

short2

uvlo

por

slp

ts1

ts2

UDIM2

FLT

fpin

UVLO &

PWM

INPUT

pwm1

Rail-to-Rail

Error Amplifer

Current

Reference

slp_o

slp_o

slp_o





Figure 4. Functional Block Diagram of TPS92520-Q1 Buck LED Driver

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ArmCortex-M4F

(120 MHz)

NVIC MPU

FPUETM Flash

(1024KB)

Bootloader

DriverLib

AES and CRC

Ethernet Bootloater

ROM

DCode bus

ICode bus

JTAG, SWD

SystemControl and

Clocks(with Precision

Oscillator)

Bus Matrix

System Bus

SRAM(256KB)

SYSTEM PERIPHERALS

WatchdogTimer

(2 Units)DMA

HibernationModule

Tamper

EEPROM(6K)

General-Purpose

Timer (8 Units)

GPIOs(90)

ExternalPeripheralInterface

CRCModule

AESModule

DESModule

SHA/MD5Module

SERIAL PERIPHERALS

UART(8 Units)

USB OTG(FS PHYor ULPI)

I2C(10 Units)

SSI(4 Units)

CANController(2 Units)

EthernetMAC, PHY, MII

ANALOG PERIPHERALS

12-Bit ADC(2 Units,

20 Channels)

AnalogComparator

(3 Units)

MOTION CONTROL PERIPHERALS

QEI(1 Unit)

PWM(1 Unit,

8 Signals)

Advanced

Periphera

lB

us

(AP

B)

Advanced

Hig

h-P

erf

orm

ance

Bus

(AH

B)





2.3.3 MSP432E401YThe SimpleLink MSP432E401Y Arm® Cortex® -M4F microcontrollers provide top performance andadvanced integration. The product family is positioned for cost-effective applications requiring significantcontrol processing and connectivity capabilities. The MSP432E401Y microcontrollers integrate a largevariety of rich communication features to enable a new class of highly connected designs with the ability toallow critical real-time control between performance and power. The microcontrollers feature integratedcommunication peripherals along with other high-performance analog and digital functions to offer a strongfoundation for many different target uses, spanning from human-machine interface (HMI) to networkedsystem management controllers

Figure 5 shows a block diagram of the MSP432E401Y microcontroller.

Figure 5. Functional Block Diagram of MSP432E401Y Microcontroller

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TPS92682-Q1





2.4 System Design Theory

2.4.1 PCB and Form FactorThis reference design uses a six-layer printed circuit board (PCB) where components are placed on bothsides and a machined enclosure interfaces to the bottom of the board to provide heat sinking. Thermalvias are used to conduct heat from the top side of the PCB to the bottom for thermal management. Theenclosure is machined to allow for direct thermal connection to the TPS92520s on the bottom of the boardalong with other components that need heasinking directly to the enclosure. Placing components on bothsides of the board ensures a high density design. The PCB has a dimension of 109 mm × 92 mm. Theprimary objective of the design with regards to the PCB is to make a solution that is compact while stilladequate heat sinking. The enclosure was also designed to provide shielding for EMI/EMC compliancerequired by each automotive company. In a final-production version of this reference design, the size ofthe solution can be further reduced. Figure 6 shows a 3D rendering of the PCB.

Figure 6. 3D Render of TIDA-050030 PCB–Top Side

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TPS92520-Q1





Figure 7. 3D Render of TIDA-050030 PCB–Bottom Side

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VIN+

VIN+VBAT+

VBAT-

3

1

2

60 V

Q2

60V

D3

60V

D4

60V

D5

GND

VBOOST

4.7uF

C5

VIN 6-44VDC

150W MAX

100k

R3

100k

R2

100k

R4

50V

0.01uF

C1

50V

0.1uF

C4

50V

0.1uF

C6

50V

0.1uF

C11

5

4

1

2

3

Q1

two holes each, 0.1"

VBAT+

VBAT-

100k

R1

Vin

GND

50V

0.01uF

C2

8.2V

D2

1µH

L1

10uF

C7

GND

10uF

C8 50V

220µF

C3

10uF

C9

10uF

C10

10uF

C1226V

D1

GND





2.4.2 Input ProtectionIn this reference design, reverse polarity protection is implemented by using the body diode of an N-channel MOSFET, Q1, in conjunction with the VBOOST to turn on the MOSFET when the system is activeand thus reducing the power dissipation that would otherwise be dissipated using a schottky. Q2, D3, andD4 work together to ensure fast turn off of the Q1 FET during fault conditions, D2 is a zener that protectthe gate of the Q1 by clamping it to less than 10 V, and D5 ensures that Q1 doesn't turn on until thesystem is fully up and running and VBOOST has been raised to greater than +VBAT, see Figure 8. D1 isa transient voltage suppressor (TVS) that protections against over voltage conditions during faults andprovides reverse battery protection.

Figure 8. Schematic of Input Protection + EMI Filter

2.4.3 EMI FilterA LC low-pass filter is placed on the input of the boost controller to attenuate conducted differential modenoise generated by the system. The filter consists of C3, C7, C8, C9, C10, C11, and L1 as shown inFigure 8. Additional localized filtering, which includes C1, C2, C4, C5 and C12, is added close to theconnector J2 to further help reduce conducted EMI. For more details, see Simple Success WithConducted EMI From DC-DC Converters.

2.4.4 TPS92682-Q1 Boost ControllerTable 2 shows the default design parameters for the boost controller.

Table 2. Design Parameters of Default Boost Controller

DESIGN PARAMETERS VALUEOutput voltage range 18 V to 55 V

Output power 130 WMinimum input voltage (DC) 6 VTypical input voltage (DC) 13.5 V

Maximum input voltage (DC) 24 VSwitching frequency 260 kHz

For the maximum boost ratio (6 V to 45 V), the switching frequency of the TPS92682-Q1 is limited by aforced off-time. Based on Equation 1, the internal clock frequency, FCLKM, is set by R23. In conjunction withthe SWDIV register (address 0x03h) setting (in this case set to divide by four (0x01h), the switchingfrequency, FSW, is set following to CHxCLK = fCLKM/4, where CHxCLK is the channel clocks (switchingfrequency).

NOTE: The TPS92682 is setup as a two phase constant voltage controller and the effective FSW istwice the channel frequency.

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http://www.ti.com/lit/pdf/SNVA489


GND

GND

GND

BS

TC

OM

P

GNDGND

GND

100k

R9

GND

GND

VBOOST

GND

GND

1uF

50V

C24

2.2uF

C37

2.2uF

C39 GND

470pF

100V

C36

7.5

R21

GND

GND

GND

MAX POWER = 140W (2-PHASE)BOOST LED VOLTAGE REGULATOR

VBST_FB

SCK

MOSI

TP1

GND

GND

GND

50V

100pF

C27

VIN1

EN2

PWM13

PWM24

SSN5

SCK6

MISO7

MOSI8

ISN124

ISP123

GATE122

VCC21

PGND20

GATE219

ISP218

ISN217

LH9

FLT110

FLT2/SYNC11

COMP212

PDRV213

CSN214

CSP215

FB2/OV216

RT32

VDD31

AGND30

COMP129

PDRV128

CSN127

CSP126

FB1/OV125

PAD33

TPS92682QRHMQ1

U1

GND

GND

GND

50V

0.033uF

C18

50V

10pF

C23

20.0k

R10

4.12k

R15

50V

10pF

C40

80V

33uF

C14

VIN+

MOSI

MISO

SCK

SSN_BOOSTSSN0

BnFLT2

BnFLT1

MISO

80V

33uF

C28

GND

2X PCE4126TR-ND

2X PCE4126TR-ND

4.7uF

C16

4.7uF

C17

4.7uF

C30

4.7uF

C31

L6 multiple footprint

50V

1000pF

C38

50V

1000pF

C26

10.0

R24

1

3

2

D6

PDS5100HQ-13

1

3

2

D7

PDS5100HQ-13

5

4

1 2 3

Q4

SQJA90EP-T1_GE3

5

4

1 2 3

Q3

SQJA90EP-T1_GE3

10.0

R14

BSTnFLT1

V_BOOST

Vin

GND

7.5

R6

GND

470pF

100V

C25VBST_FB

VDD

BS

TC

OM

P

Vin

BSTnFLT2

10.0k

R16

10.0k

R17

MCU_3V3D

10.0k

R7

GND

10.0k

R13

GND

10.0k

R20

100k

t° RT1

NCP18WF104J03RB

MCU_3V3D

GND

0.02

R26DNP

0.02

R19DNP

A_BST

A_VIN

A_NTC1

1.00

R11

221k

R5

221k

R8

15µH

L3

15µH

L2

4.99

R22

4.99

R12

0.01

R18

0.01

R25

100V

4.7uF

C19

100V

4.7uF

C20

100V

4.7uF

C21

100V

4.7uF

C22

100V

4.7uF

C32

100V

4.7uF

C33

100V

4.7uF

C34

100V

4.7uF

C35

143k

R23

u

12

CLKM

T

10f

12.5 R





(1)

Figure 9 shows the default TPS92682-Q1 boost controller schematic of this reference design.

Figure 9. Schematic of TPS92682-Q1 Boost Controller

The main components of the boost stage are selected by following the Detailed Design Procedure sectionin the data sheet TPS92682-Q1 Dual -Channel Constatnt-Voltage and Constant-Current Controller withSPI Interface.

R23, same as RT, sets the switching frequency. The inductor L2 and L3 has a value of 15 µH with asaturation current rating above the maximum expected inductor current of 10.6 A at a minimum inputvoltage of 9 V. Based on this input current capability, a value of 10 mΩ is selected for the current senseresistor R18 and R25. R14, R26, C26, and C38 form a filter for the current sensing for each phase.

The output capacitors smooth the output voltage ripple and provide a source of charge during transientloading conditions. Also the output capacitors reduce the output voltage overshoot when the load isdisconnected suddenly. Ripple current rating of output capacitor must be carefully selected. In a boostregulator, the output is supplied by discontinuous current and the ripple current requirement is usuallyhigh, which makes ceramic capacitors a perfect fit. The output voltage ripple is dominated by ESR of theoutput capacitors. Paralleling the output capacitor is a good choice to minimize effective ESR and split theoutput ripple current into capacitors. This example uses four 4.7-µF ceramic capacitors and one 0.1-µFceramic capacitor with a voltage rating of 100 V per phase. Additional bulk capacitance was added via two33-µF electrolytic capacitors for added ripple reduction and greater energy storage. A higher outputvoltage ripple in this reference design is not a concern for the buck LED drivers, which are connected tothe boost output voltage. Input capacitors C16, C17, C30, and C31 smooth the input voltage ripple. Thisreference design uses small-sized 4.7-µF ceramic capacitors with a voltage rating of 50 V.

The low-side power switches Q3 and Q4 are 80-V rated N-channel MOSFETs in a PowerPAK® package.100-V Schottky diodes D6 and D7 are used as the catch diode to improve efficiency. R12 and R22 aregate resistors that can limit the rise and fall times of the switch node voltage. A resistor-capacitor snubbernetwork (R6, R21, C25, and C36) across the N-channel MOSFETs, Q3 and Q4, reduces ringing andspikes at the switching node. For how to calculate these values, see Power Tips: Calculate an R-Csnubber in seven steps.

R10, C18, C23 and C40 configure the error amplifier gain and phase characteristics to produce a stablevoltage loop. For more details, see How to Measure the Loop Transfer Function of Power Supplies.

See Section 4.3 for layout guidelines for the boost controller in this reference design.

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http://www.ti.com/lit/pdf/SLUSCX8A

http://www.ti.com/lit/pdf/SLUSCX8A

https://e2e.ti.com/blogs_/b/powerhouse/archive/2016/05/05/calculate-an-r-c-snubber-in-seven-steps



100V

0.1uF

C55

GND

100V

0.1uF

C41

GND

CSN1

CSP1

CSN2

CSP2

BST2

SCK

BUCK2

BUCK1

SSN_1-2

GND

100k

R36

MISO

MOSI

SCK

SSN_BUCK_1-2

BUCK1-2_nFLT

SSN_1-2a

BUCK_nFLT_1-2

GND

GND

GND

GND

0R32

0R34

BKPWM_11

BUCK1-2_V5D

BUCK1-2_V5A

COMP1

5V

BKPWM_12

V_BUCK2

V_BUCK1

25V

0.1uF

C43

25V

0.1uF

C52

1.5uF

C45

100V

1.5uF

C51

16V

1uF

C46

16V

1uF

C48

COMP2

16V

2200pF

C42

16V

2200pF

C54

0.1µF

16V

C47

0.1µF

16V

C500.1µF

16V

C49

1000pF

C44

100V

1000pF

C53

V_BUCK_2

V_BUCK_1

BCKPWM_11

BCKPWM_12

SW2

SW1

BST1

3

1

2

Q5

SI2323DS

3

1

2

Q6

MMBT3904LT1G

10.0k

R35

10.0k

R40

GND

5V_EN

5V

5V

COMP216

UDIM215

PGND14

PGND13

VIN212

VIN211

GND10

V5A9

V5D8

GND7

VIN16

VIN15

PGND4

PGND3

UDIM12

COMP11

CSN132

CSP131

BST130

SW129

SW128

FLT27

LHI26

SSN25

SCK24

MISO23

MOSI22

SW221

SW220

BST219

CSP218

CSN217

TPS92520QDADQ1

U2

LHI_1-2

15.8k

R27

15.8k

R39

30.1k

R43

30.1k

R31

V_BOOST

V_BOOST

1.00kR33

1.00k

R29

1.00k

R41

10.0k

R37

0R30

0R38

47µH

L4

47µH

L5

D9

PD3S160Q-7

GND

D8

PD3S160Q-7

GND

0.22uF

C74

0.22uF

C75

0.22uF

C76

0.22uF

C77

0.1

R28

0.1

R42

GND





2.4.5 TPS92520-Q1 Buck LED DriverTable 3 shows the default design parameters for the buck LED drivers.

Table 3. Design Parameters of Default Buck LED Driver

DESIGN PARAMETER RANGE DEFAULT VALUEInput voltage 18 V to 55 V 50 V

LED forward voltage 3 VNumber of LEDs in series 1 to 14 8

Output current range 0.2 A to 1.5 A 1 AOutput voltage 3 V to 42 V 24 V

Output power per channel 30 W max 24 WSwitching frequency 440 kHz

Figure 10 and Figure 11 shows the default TPS92520-Q1 LED driver schematic of this reference design.

Figure 10. Schematic of TPS92520-Q1 Buck LED Driver–Channels 1 and 2

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OUT

IN

VD

V

GND

GND

GND

COMP3

GND

PGND

COMP4

0R49

0R51

UDIM-3

GND

BUCK3-4_V5D

BUCK3-4_V5A

100V

0.1uF

C70

GND

100V

0.1uF

C56

GND

CSN3

CSP3

CSN4

CSP4

BST4

SCK

BUCK4

BUCK3

SSN_3-4

GND

100k

R53

MISO

MOSI

SCK

SSN_BUCK_3-4

BUCK3-4_nFLT

SSN_3-4a

BUCK_nFLT_3-4

UDIM-4

V_BUCK4

V_BUCK3

25V

0.1uF

C59

25V

0.1uF

C67

1.5uF

C60

100V

1.5uF

C66

16V

1uF

C61

16V

1uF

C63

BKPWM_22

BKPWM_21

16V

2200pF

C69

16V

2200pF

C57

0.1µF

16V

C64

0.1µF

16V

C62

0.1µF

16V

C65

1000pF

C58

100V

1000pF

C68

V_BUCK_3

V_BUCK_4

BCKPWM_22

BCKPWM_21

SW3

BST3

SW4

5V

3

1

2

Q7

SI2323DS

3

1

2

Q8

MMBT3904LT1G

10.0k

R52

10.0k

R56

GND

5V

5V

COMP216

UDIM215

PGND14

PGND13

VIN212

VIN211

GND10

V5A9

V5D8

GND7

VIN16

VIN15

PGND4

PGND3

UDIM12

COMP11

CSN132

CSP131

BST130

SW129

SW128

FLT27

LHI26

SSN25

SCK24

MISO23

MOSI22

SW221

SW220

BST219

CSP218

CSN217

TPS92520QDADQ1

U3

LHI_3-4

15.8k

R44

15.8k

R57

30.1k

R47

30.1k

R60

V_BOOST

V_BOOST

1.00kR50

1.00k

R46

1.00k

R58

10.0k

R54

47µH

L6

47µH

L7

0R48

0R55

5V_EN

D11

PD3S160Q-7

D10

PD3S160Q-7

GND

GND

0.22uF

C80

0.22uF

C81

0.22uF

C82

0.22uF

C83

GND

0.1

R45

0.1

R59

GND





Figure 11. Schematic of TPS92520-Q1 Buck LED Driver–Channels 3 and 4.

The main components of the buck LED drivers are selected by following the Detailed Design Proceduresection in TPS92520-Q1 4.5V to 65V Input Dual 1.6-A Synchronous Buck LED Driver with SPI Control.

Components R22, R35, C26, and C39 are used to program the off-time of the hysteretic LED drivers to0.2 µs. With the default configuration, the LED current is set to 1 A with a inductor ripple current of 0.1 A.When selecting an inductor, ensure the ratings for both peak and average current are adequate. For theinductors L3 and L4, a value of 47 µH is selected. Based on the output current capability, a value of 220mΩ is selected for the current sense resistors R21 and R34. R23, R24, R36, and R37 program the startupand UVLO level. C28 and C40 at the UVLO pin are placed for noise immunity. Capacitors C20 and C33tied to the switch node (SW pin) and the diodes D6 and D10 connected to the VCC supply power theBOOT pin to ensure proper operation of the internal MOSFET. The 10-µF VCC capacitors C19 and C31supply current for the device operation as well as additional power for external circuitry. The low-siderectifier diodes D7 and D12 are 3-A rated, low-leakage, Schottky diodes in a PowerDI5 package. DiodesD8 and D13 provide reverse polarity protection to the PWM pin because the signal is coming from theinput voltage. With a voltage higher than 1 V on the PWM, the device starts operation.

The input capacitors C21, C22, C23, C34, C35, and C36 provide a low impedance source for thediscontinuous input current of the buck LED drivers. The output capacitors C24, C25, C37, and C38 inparallel with the LED load reduce the ripple current on the LEDs. The TPS9250-Q1 has a rail to rail, fastoutput current sense that allows true average current regulation all the way down to fully shunted output toallow for current regulation accuracy as well as dynamic load operation.

2.4.6 Duty Cycle ConsiderationThe switch duty cycle, D, defines the converter operation and is a function of the input and outputvoltages. In steady state, the duty cycle is derived using Equation 2:

(2)

There is no limitation for small duty cycles, since at low duty cycles, the switching frequency is reduced asneeded to always ensure current regulation. The maximum duty cycle attainable is limited by the minimumoff-time duration and is a function of switching frequency.

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L(MAX)OUT

SW D LED

iC

8 f r i

'

u u u '

L(MAX)L(PK) LED(MAX)

ii I

2

'

2L(MAX)2

L(RMS) LED(MAX)

ii I

12

§ ·'¨ ¸ ¨ ¸© ¹

IN(TYP)

L SW

VL

4 i f

u ' u

DAC(FS)CS

LED(MAX)

0.9 VR

14 I

u

u





2.4.7 Switching Frequency SelectionNominal switching frequency (tON > tON(MIN)) is set by programming the CHxTON register. The switchingvaries slightly over operating range and temperature based on converter efficiency. Table 4 showscommon switching frequencies and corresponding CHxTON register values.

Table 4. Frequency Setting

FREQUENCY CHxTON REGISTER VALUE (DECIMAL) CHxTON REGISTER VALUE (BINARY)200 kHz 3 000011400 kHz 7 0001111 MHz 19 010011

1.6 MHz 31 0111112.2 MHz 43 101011

2.4.8 LED Current Set PointThe LED current is set by the external resistor, RCS, and the CHxIADJ register value. The current senseresistor, RCS, is selected to meet the maximum LED current specification and 90% of the full-scale rangeof CHxIADJ-DAC.

(3)

The LED current can be varied between minimum and maximum specified limits by writing to the CHxIADJregister.

2.4.9 Inductor SelectionThe inductor is sized to meet the ripple specification at 50% duty cycle. TI recommends a minimum of30% peak-to-peak inductor ripple to ensure periodic switching operation. Use Equation 4 to calculate theinductor value.

(4)

Use Equation 5 and Equation 6 to calculate the RMS and peak currents through the inductor. It isimportant that the inductor is rated to handle these currents.

(5)

(6)

2.4.10 Output Capacitor SelectionThe output capacitor value depends on the total series resistance of the LED string, rD, and the switchingfrequency, fSW. The capacitance required for the target LED ripple current is calculated using the .

(7)

For applications where the converter supports pixel beam or matrix LED loads, additional designconsiderations influence the selection of output capacitor. The size of the output capacitor depends on theslew-rate setting of the LED bypass switches and must be selected after consulting the lighting matrixmanager.

When choosing the output capacitors, it is important to consider the ESR and the ESL characteristicssince they directly impact the LED current ripple. Ceramic capacitors are the best choice due to thefollowing:

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BWCOMP

SW

0.0055C

f

uV

Q(BST)

BST

5D BST(HYS) BST(UV) FREQ

IC

V V V PWM

u





• Low ESR• High ripple current rating• Long lifetime• Good temperature performance

With ceramic capacitor technoloy, it is important to consider the derating factors associated with highertemperature and DC bias operating conditions. TI recommends an X7R dielectric with a voltage ratinggreater than maximum LED stack voltage.

2.4.11 Input Capacitor SelectionThe input capacitor buffers the input voltage for transient events and decouples the converter from thesupply. TI recommends a 2.2 µF input capacitor across the VIN pin and PGND placed close to the device,and connected using wide traces. X7R-rated ceramic capacitors are the best choice due to the low ESR,high ripple current rating, and good temperature performance. Additional capacitance can be required tofurther limit the input voltage deviation during PWM dimming operation.

2.4.12 Bootstrap Capacitor SelectionThe bootstrap capacitor biases the high-side gate driver during the high-side FET on-time. The requiredcapacitance depends on the PWM dimming frequency, PWMFREQ, and is sized to avoid boot undervoltageand fault during PWM dimming operation. The bootstrap capacitance, CBST, is calculated using .

(8)

Table 5 summarizes the TI recommended bootstrap capacitor value for different PWM dimmingfrequencies.

Table 5. Bootstrap Capacitor Value

PWM DIMMING FREQUENCY (Hz) BOOTSTRAP CAPACITOR (µF)1395 0.11221 0.1977 0.15814 0.15610 0.22407 0.33199 0.56100 1

2.4.13 Compensation Capacitor SelectionA simple integral compensator is recommended to achieve stable operation across the wide operatingrange. Use to calculate the compensation capacitor needed to achieve stable response.

(9)

The factor, σBW, determines the bandwidth of the loop and is usually set between 50 and 100 isrecommended. A larger σBW value results in lower loop bandwidth and over-damped response.

2.4.14 Input Undervoltage ProtectionFigure 10 and Figure 11 shows that the undervoltage protection threshold is programmed using a resistordivider, RUV1 and RUV2, from the input voltage, VIN, to ground. Use Equation 10 and Equation 11 tocalculate the resistor values.

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UDIM(RISE)UVx1 UVx2

INx(RISE) UDIM(RISE)

VR R

V V u

HYSUVx2

UDIM(UVLO)

VR

I





(10)

(11)

See Section 4.3 for layout guidelines for the TPS92520-Q1 in this reference design.

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0.10

-

VIN

+

0+ -VI_IN

DC Power Supply

0-50V / 20A

0.10

0+ -VI_1LED load - 1

1-16 LEDs

0.10


1-16 LEDs

0.10


1-16 LEDs

0.10


1-16 LEDs

+

VLED1

-

+

VLED2

-

+

VLED3

-

+

VLED4

-

-

VBOOST

+

www.ti.com Hardware, Testing Requirements, and Test Results




3 Hardware, Testing Requirements, and Test Results

3.1 Required HardwareFigure 12 shows the default test setup for taking efficiency measurements, startup/shutdown, and steadystate waveforms of this reference design. Voltage measurements were taken using kelvin connections.The currents were measured using a one percent, 0.1 Ω shunt resistor in conjunction with a precisionmulti meter for all current measurements. Voltage and current waveforms were taken using voltage andcurrent probes with an oscilloscope. Inductor currents were measured by putting a loop in series with theinductor and using the current probe attached to the oscilloscope.

Figure 12. Efficiency, Startup/Shutdown, and Steady State Test Setup

Connect a DC power supply to each input terminal (J2, pin 11 (+BAT) and 12 (-BAT)) and the LED stringsto the output terminals (J2, pin 1-4, 13, and 1 4).

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Hardware, Testing Requirements, and Test Results www.ti.com




3.2 Testing and ResultsAll tests in this section are performed in the default configuration where the input voltage is 13.5 V and theLED current is adjusted to generate 30W per channel up to 1.5A. Testing was done with 10 and 5 LEDs.

3.2.1 Startup/ShutdownFigure 13 through Figure 16 show the startup and shutdown behavior of the reference design. Duringstartup, the adaptive pre-boost control starts acting and regulates the boost output voltage to the set level.

Figure 13. Startup, 12 LEDs at 0.75A Figure 14. Startup, 6 LEDs at 1.5A

CH1: VIN, CH2: VOUT LED driver, CH3: LED current, CH4:VBOOST


Figure 15. Shutdown, 12 LEDs at 1.5A Figure 16. Shutdown, 12 LEDs at 0.75A



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3.2.2 Steady State OperationFigure 17 through Figure 20 show the steady state operation of the TPS92682-Q1 boost controller. With10 LEDs connected, the boost controller operates with nearly a 50 percent duty cycle.

Figure 17. Boost Operation at 120W output Figure 18. Boost Operation at 60W output

CH1: SW boost, CH2: VIN, CH3: IL boost, CH4: VBOOST(NOTE: only one of two phases)

CH1: SW boost, CH2: VIN, CH3: IL boost, CH4: VBOOST(NOTE: only one of two phases)

Figure 19 and Figure 20 show the steady state operation of the TPS92520-Q1 buck LED driver.

Figure 19. LED Driver Operation at 12 LEDs and 1A Figure 20. LED Driver Operation at 6LEDs at 1A

CH1: SW LED driver, CH2: VOUT LED driver, CH3: IL LED,CH4: VBOOST

CH1: SW LED driver, CH2: VOUT LED driver, CH3: IL LED,CH4: VBOOST

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Output Power (W)

Eff

icie

ncy (

%)

10 20 30 40 50 60 70 80 90 100 110 12074%

76%

78%

80%

82%

84%

86%

88%

90%

92%

94%

10 LED5 LED





3.2.3 EfficiencyFigure 21 shows the efficiency of the design in different conditions. To achieve a total efficiency of 89percent, each stage (boost and buck) operates with an efficiency of ≈ 94 percent.

Figure 21. Output Power vs. Efficiency at VIN = 13 V

3.2.4 Thermal PerformanceFigure 22 through Figure 25 show the thermal behavior for different conditions. To improve the thermalperformance of the whole board, consider implementing the following items:• Add more layers on the PCB• Increase the PCB size• Increase the copper thickness to 2 oz• Add a heat sink• Select larger and more expensive components

The design was run at 120 watts of output power at input voltage of 13.5 V and allowed to thermallystabilize. The TPS92520-Q1 has an internal temp sense to allow for the measurement of the junctiontemperature of the device via register TEMPL/H (0x1B/1C). The internal junction temperatures of U2 andU3 where read via the SPI bus to confirm the rise in junction temperature (TJ) of the two TPS92520'scompared to the ambient air temp of 25°C. The junction temperatures, TJ, are listed in each figure asTPS92520_1-2 and TPS92520_3-4.

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TPS92520_1-2: TJ = 34°C

TPS92520_3-4: TJ = 33°C





Figure 22. Thermal Image with respect to TIDA-050030 PCB.

Figure 23 shows temperatures at various sample points (Sp). Figure A shows that most of the powerdissipation is contained within the boost converter section of the design. Sp1 is the case temperature ofthe TPS92682-Q1. Sp2 and Sp3 are temperatures at the current sense resistors (R25 and R18). Sp5 isthe temperature for the current sense resistor of for VBUCK1 (R42). Sp4 and Sp6 are the temperaturesnext to Q3, D6, Q4, and D7.

Figure 23. Thermal Image of Top Side PCB at ≈120W Output and at 13.5 V Input. Sample Points 1-6Shown

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TPS92520_1-2: TJ = 34°C

TPS92520_3-4: TJ = 33°C





Figure 24 shows a close up of the boost converters surface temperatures. Sp1 shows the temperature atU1 (TPS92682-Q1). Sp2 and Sp3 show the temperatures of the current sense resistors R18 and R23.Sp4 shows the temp at schottky diode D7 and Sp5 shows the temperature at Q4. We are seeing no morethan a 30°C rise worst case at the sense resistors. The other parts that are seeing significant powerdissipation are seeing less than 20°C rise.

Figure 24. Thermal Image: Closeup of Boost Converter Circuitry at ≈ 120 W Output

Figure 25 shows a close up of the two buck LED driver's (TPS92520-Q1) surface temperatures. Sp1, Sp2,Sp3, and Sp4 shows the temperature at all four current sense resistors (R28, R42, R45, and R59) for thefour channels (VBUCK1/2/3/4). Sp5 shows the temperatures at the PCB above the TPS92520. We areseeing no more than a 12°C rise worst case at the sense resistors. The TPS92520's are seeing less than10°C rise given 120W of output power. The enhanced 32-pin HTSSOP package with the 3.86mm x 3.9mm top exposed pad when mated with heat sink enclosure in conjunction with thermal potting compoundperforms very well.

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TPS92520_1-2: TJ = 34°C

TPS92520_3-4: TJ = 33°C





Figure 25. Thermal Image: Closeup of Buck Converter Circuitry at ≈ 120 W Output

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CANO ± Master

CAN

DC Power Supply

0-50V / 20A

(BATTERY)

TPS92663-Q1 Six Channel Matrix Evaluation Module

TIDA-050030

Matrix Module Harness





3.2.5 LED Matrix ManagerFigure 26 shows the setup of the design operating with a full light matrix manager solution, specifically theTPS92662/3-Q1 EVM. The matrix evaluation module was controlled via CAN and registers were modifiedto adjust phase, pulse width, and slew rate, see TPS92662/3-Q1 datasheet for specific register details.

Figure 26. TIDA 050030 Setup for Lighting Matrix Module Testing

Figure 27 shows the connection points for the TIDA-050030 connector to the TPS92663-Q1 six channelmatrix evaluation module.

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Figure 27. Schematic of TIDA-050030 Connector Connections

Channel 2 of the oscilloscope was setup on V_BUCK2 (teal) to measure the LED voltage of the TIDA-050030 board, while channel 3 of the oscilloscope (magenta) was a current probe measuring the outputcurrent of V_BUCK2. The worst case phase and pulse width settings were selected to demonstrateperformance. Figure 27 shows the connection points for the TIDA-050030 connector to the TPS92663-Q1six channel matrix evaluation module. TheTPS92662-Q1's registers were setup for phase, pulse width,and slew rate. It is important to note that Figure 28, Figure 29, and Figure 30 show how the TPS92520-Q1's maintains current regulation with minimal over/undershoot with fast settling to the regulation setpoint. See the TPS92662-Q1 data sheet for details about registers and settings.

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Figure 28. Waveforms of 0 Phase Shift, 20/1024 Pulse Width, SLEWRATE=01, at 350mA Using LightingMatrix Module EVM


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3.2.6 Electromagnetic Compatibility (EMC)All tests in this section are performed according to the CISPR 25 standard. Figure 31 shows the setup.Note that the test setup for conducted emissions is a worst case scenario where the LED driver PCB isplaced 5 cm above the reference ground plane. In a real application housing, the distance from the LEDdriver PCB to the reference ground plane will be higher; thus, the common-mode noise coupling will belower.

Figure 31. CISPR 25 Conducted Emissions Setup

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Figure 32. CISPR 25 Conducted Emissions Connections

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CISPER 25 Class 5

PK detector

AVG detector





3.2.6.1 Conducted EmissionsFigure 33 shows the conducted emissions at a power level of approximately 68 W with all four channelswith 10 LEDs per channel. From 150 kHz to 30 MHz, the design is passing class 5.

Figure 33. Conducted Emissions: 0.15 MHz to 30 MHz, BUCK1, BUCK2, BUCK3, and BUCK4 on Ten LEDs(≈ 86 W)

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D7

Q4

C32C33C35C34

R25R26

Q3

D6

R19R18

C19C20C21C22

L2

BOTTOM

L3

BOTTOM

U1

C3

0

C3

1

C1

6

C1

7

SW

SW

VBOOST

VBOOST

VIN+

VIN+

GND

GND

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4 Design Files

4.1 SchematicsTo download the schematics, see the design files at TIDA-050030.

4.2 Bill of MaterialsTo download the bill of materials (BOM), see the design files at TIDA-050030.

4.3 PCB Layout RecommendationsThe layout of the boost controller as shown in Figure 34 is created by following the layout example andguidelines in the Layout section of TPS92682-Q1 Dual Channel Constant-Voltage and Constant-CurrentController with SPI Interface.

Figure 34. TPS92682-Q1 Boost Controller Layout (Top Layer)

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http://www.ti.com/lit/pdf/SLUSCX8

http://www.ti.com/lit/pdf/SLUSCX8

L4

C8

0

L5

L6

L7

U2

U3

C8

1

C8

3

C8

2

C7

7

C7

6

C7

5

C7

4

C28

C14

VBOOST

VBOOST

VBOOST

VBOOST

SW

SW

SW

SW

GND

GND

CSP1

CSP2

CSP3

CSP4

Design Files www.ti.com




The layout of the buck converters as shown in Figure 35 is created by following the layout examples andguidelines in the application note: TPS92520-Q1 4.5V to 65V Input Dual 1.6-A Synchronous Buck LEDDriver with SPI Control or AN-1229 SIMPLE SWITCHER PCB Layout Guidelines.

Figure 35. TPS92520-Q1 Buck LED Drivers Layout (Bottom Layer)

4.3.1 Layout PrintsTo download the layer plots, see the design files at TIDA-050030.

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http://www.ti.com/lit/pdf/SNVA054C


www.ti.com Design Files




4.4 Altium ProjectTo download the Altium project files, see the design files at TIDA-050030.

4.5 Gerber FilesTo download the Gerber files, see the design files at TIDA-050030.

4.6 Assembly DrawingsTo download the assembly drawings, see the design files at TIDA-050030.

5 Related Documentation1. Texas Instruments, AN-2162 Simple Success With Conducted EMI From DC-DC Converters

Application Report2. Texas Instruments, LM5122 Wide-Input Synchronous Boost Controller With Multiple Phase Capability

Data Sheet3. TI E2E Community, Power Tips: Calculate an R-C snubber in seven steps4. Texas Instruments, AN-1889 How to Measure the Loop Transfer Function of Power Supplies

Application Report5. Texas Instruments, TPS92520-Q1 4.5V to 65V Input Dual 1.6-A Synchronous Buck LED Driver with

SPI Control6. Texas Instruments, PMP9796 - 5V Low-Power TEC Driver Reference Design

5.1 TrademarksE2E is a trademark of Texas Instruments.

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http://www.ti.com/lit/pdf/SNVS954

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Revision History

Revision HistoryNOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Original (October 2019) to A Revision .................................................................................................... Page

• Changed figure 28 title "Phase Margin" to "Phase Shift" ........................................................................... 28• Changed figure 29 title "Phase Margin" to "Phase Shift" ........................................................................... 28• Changed figure 30 title "Phase Margin" to "Phase Shift" ........................................................................... 29

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